Semiconductor equipment

Abstract

This semiconductor device includes: a first and a second power supply line and a first and a second ground line that are disposed on a first surface of a substrate; a third power supply line that is disposed on a second surface of the substrate and is connected with the first power supply line through a via; and a fourth power supply line. The semiconductor device includes: a first region that includes the second power supply line, the first ground line and the third power supply line; a second region that includes the fourth power supply line and the second ground line; a third region that is located, in a plan view, between the first region and the second region; and a power supply switch circuit that includes a switch transistor connected between the first and the second power supply lines. Due to the foregoing, a power supply switch can be appropriately arranged in a semiconductor device that includes a substrate having a power supply wiring network disposed on the second surface side thereof.

Description

Technical Field

[0001] The present invention relates to a semiconductor device.

[0002] The present application claims priority based on U.S. Provisional Application No. 63 / 261,846 filed on September 30, 2021, and incorporates all contents described in the above application by reference. Background Art

[0003] In an SRAM (Static Random Access Memory), when the arrangement of power supply wirings differs between a bit cell region and a peripheral circuit region, an isolation region may be provided to secure a gap between the bit cell region and the peripheral circuit region in a plan view. A technique called BPR (Buried Power Rail), in which a power supply wiring is embedded in a semiconductor substrate, is known. A technique is known in which a power switch circuit is provided between a power supply line and a virtual power supply line to switch between supplying and cutting off a power supply voltage to an internal circuit. A technique called BS-PDN (Backside-Power Delivery Network), in which a power supply wiring network is provided on a back surface of a semiconductor substrate and a power supply voltage is supplied through a via penetrating the back surface and a front surface of the semiconductor substrate, is known. Prior Art Documents Patent Documents

[0004] Patent Document 1 U.S. Patent No. 10446224 Specification Patent Document 2 U.S. Patent No. 8670265 Specification Patent Document 3 U.S. Patent Application Publication No. 2020 / 0135718 Specification Patent Document 4 U.S. Patent Application Publication No. 2018 / 0151494 Specification Patent Document 5 U.S. Patent Publication No. 2005 / 0212018 Specification Patent Document 6 U.S. Patent No. 10170413 [Patent Document 7] International Publication No. 2020 / 065916 [Patent Document 8] International Publication No. 2021 / 070366 [Patent Document 9] International Publication No. 2021 / 070367 [Patent Document 10] International Publication No. 2021 / 079511 [Patent Document 11] International Publication No. 2021 / 111604 [Overview of the project] [Problems that the invention aims to solve]

[0005] Detailed technical considerations have not been made regarding how to arrange the power switch circuit when the BS-PDN is located on the back of the circuit board.

[0006] The present invention has been made in view of the above points, and aims to appropriately arrange a power switch in a semiconductor device having a substrate on which a power wiring network is provided on the back surface. [Means for solving the problem]

[0007] In one aspect of the present invention, the semiconductor device comprises a substrate having a first surface and a second surface facing the first surface; a first power line provided on the first surface; a second power line provided on the first surface; a first ground line provided on the first surface; a third power line provided on the second surface; a via provided on the substrate that electrically connects the first power line and the third power line; a fourth power line electrically connected to the second power line; a second ground line provided on the first surface; a first region having the second power line, the first ground line, the third power line, and the via; a second region having the fourth power line and the second ground line; a third region located between the first region and the second region in a plan view; and a power switch circuit having a switch transistor electrically connected between the first power line and the second power line. [Effects of the Invention]

[0008] According to the disclosed technology, a power switch can be appropriately positioned on a semiconductor device having a substrate on which a power wiring network is provided on the back surface. [Brief explanation of the drawing]

[0009] [Figure 1] This is a plan view showing an overview of the layout of the semiconductor device in the first embodiment. [Figure 2] This is a circuit block diagram showing an overview of the power switch circuit located in the bit cell area of ​​Figure 1. [Figure 3] This is a plan view showing an example of the layout of power wiring in the area where the power switch circuit in Figure 1 is located. [Figure 4] This is a plan view showing another example of the power wiring layout in the area where the power switch circuit in Figure 1 is located. [Figure 5] This figure shows an example of a bit cell placed in the bit cell area of ​​Figure 1. [Figure 6] This figure shows another example of a bit cell placed in the bit cell area of ​​Figure 1. [Figure 7]It is a plan view showing an example of the layout of the power switch circuit, bit cell region and peripheral circuit region of FIG. 3. [Figure 8] It is a cross-sectional view showing a cross-section along line Y1-Y1' of FIG. 7. [Figure 9] It is a cross-sectional view showing a cross-section along line Y2-Y2' of FIG. 7. [Figure 10] It is a plan view showing a modification of the layout shown in FIG. 7. [Figure 11] It is a plan view showing an example of the layout of power supply wiring in a region where a power switch circuit of a semiconductor device according to a second embodiment is arranged. [Figure 12] It is a plan view showing an example of a power switch circuit arranged in the peripheral circuit region of FIG. 11. [Figure 13] It is a plan view showing a modification of the power switch circuit of FIG. 11. [Figure 14] It is a circuit block diagram showing an outline of a power switch circuit arranged in a standard cell region of a semiconductor device according to a third embodiment. [Figure 15] It is a plan view showing an outline of the layout of the standard cell region of FIG. 14. [Figure 16] It is a plan view showing an example of the layout of power supply wiring in a region where the power switch circuit of FIG. 15 is arranged. [Figure 17] It is a plan view showing an example of the power switch circuit of FIG. 16. [Figure 18] It is a plan view showing an example of the end cap cell PSW-EN2 of FIG. 15. [Figure 19] It is a plan view showing an example of a case where the end cap cell of FIG. 18 is arranged adjacent to the power switch circuit of FIG. 17. [Figure 20] It is a plan view showing an example of the end cap cell PSW-EN1 of FIG. 15. DETAILED DESCRIPTION OF THE INVENTION

[0010] Embodiments will be described below with reference to the drawings. In the following, symbols indicating signals may also be used to indicate signal values, signal lines, or signal terminals. Symbols indicating power supplies may also be used to indicate power supply voltage, power supply lines, or power supply terminals to which the power supply voltage is supplied.

[0011] (First Embodiment) Figure 1 is a plan view showing an overview of the layout of a semiconductor device in a first embodiment. The semiconductor device 100 shown in Figure 1 is, for example, an SRAM. The semiconductor device 100 has a bit cell area BCA and a peripheral circuit area PCA and a decoder area DECA arranged around the bit cell area BCA. The peripheral circuit area PCA and the decoder area DECA are examples of a first area. The bit cell area BCA is an example of a second area.

[0012] For example, the peripheral circuit region PCA and the bit cell region BCA are arranged side by side in the X direction, and the decoder region DECA and the bit cell region BCA are arranged side by side in the Y direction. The X direction is an example of a first direction. The Y direction is an example of a second direction different from the first direction. In a plan view, an isolation region SPA is placed between the bit cell region BCA, the peripheral circuit region PCA, and the decoder region DECA. The isolation region SPA is an example of a third region.

[0013] For example, different power supply voltages are supplied to the bit cell area BCA, the peripheral circuit area PCA, and the decoder area DECA. For example, multiple power lines extending in the X direction and arranged in the Y direction are provided to the bit cell area BCA, the peripheral circuit area PCA, and the decoder area DECA. The positions and spacing of the power lines in the bit cell area BCA, the peripheral circuit area PCA, and the decoder area DECA may differ. Alternatively, a common power supply voltage may be supplied to the bit cell area BCA and the peripheral circuit area PCA.

[0014] Furthermore, a predetermined number of power switch circuits PSW1 are provided in the peripheral circuit area PCA and the decoder area DECA, respectively. A predetermined number of power switch circuits PSW2 are provided in the bit cell area BCA. Note that one or both of the power switch circuits PSW1 and PSW2 may be located in the isolation area SPA. Power switch circuit PSW1 is an example of a first power switch circuit. Power switch circuit PSW2 is an example of a second power switch circuit. Hereafter, when power switch circuits PSW1 and PSW2 are not distinguished, they will also be referred to as power switch circuit PSW.

[0015] Figure 2 is a circuit block diagram showing an overview of the power switch circuit PSW2 located in the bit cell area BCA of Figure 1. Note that the power switch circuit PSW1 located in the peripheral circuit area PCA and the decoder area DECA has a similar circuit configuration to that shown in Figure 2. The bit cell area BCA contains multiple bit cells BC (i.e., memory cells). Each bit cell BC is electrically connected to the virtual power line VVDD and the ground line VSS, and operates by receiving power from the virtual power line VVDD.

[0016] The power switch circuit PSW2 includes a switch transistor SWT and a control circuit CNTL. The switch transistor SWT is, for example, a p-channel transistor and operates by receiving a switch control signal SWCNT from the control circuit CNTL at its gate. In Figure 2, for simplicity, only one switch transistor SWT is shown, but multiple switch transistors SWT may be arranged between the power line VDD and the virtual power line VVDD.

[0017] While the switch transistor SWT is ON, the power line VDD and the virtual power line VVDD are electrically connected, and the power supply voltage VDD is supplied to the virtual power line VVDD. While the switch transistor SWT is OFF, the electrical connection between the power line VDD and the virtual power line VVDD is broken, and the virtual power line VVDD is set to a floating state.

[0018] The control circuit CNTL is, for example, a buffer circuit. When the control circuit CNTL operates the SRAM, it sets the switch control signal SWCNT to a low level to supply power voltage from the power line VDD to the virtual power line VVDD. When the control circuit CNTL stops the operation of the SRAM, it sets the switch control signal SWCNT to a high level to stop supplying power voltage from the power line VDD to the virtual power line VVDD.

[0019] Figure 3 is a plan view showing an example of the power wiring layout in the area where the power switch circuit PSW in Figure 1 is located. Figure 3 is an enlarged view of the area where the peripheral circuit area PCA and the bit cell area BCA are arranged with the isolation area SPA in between, and the power switch circuits PSW1 and PSW2 in Figure 1 are arranged in the isolation area SPA as a common power switch circuit PSW. Note that, as shown in Figure 1, the power switch circuits PSW1 and PSW2 may be provided in the peripheral circuit area PCA and the bit cell area BCA respectively.

[0020] In the example shown in Figure 3, the wiring of the Mint layer and the BPR wiring are provided extending in the X direction, while the local wiring LI and the wiring on the back surface BS of the semiconductor substrate SUB (Figure 9) are provided extending in the Y direction. For example, the Mint layer is provided on the surface of the semiconductor substrate SUB and is the metal wiring layer closest to the semiconductor substrate SUB. The local wiring LI is provided on the semiconductor substrate SUB on the semiconductor substrate SUB side of the Mint layer. The semiconductor substrate SUB is an example of a substrate. The surface of the semiconductor substrate SUB is an example of a first surface, and the back surface of the semiconductor substrate SUB is an example of a second surface facing the surface of the semiconductor substrate SUB.

[0021] In the following, power lines, virtual power lines, and ground lines wired to the peripheral circuit area PCA and decoder area DECA are denoted by the codes VDD1, VVDD1, and VSS1, respectively. Power lines, virtual power lines, and ground lines wired to the bit cell area BCA are denoted by the codes VDD2, VVDD2, and VSS2, respectively. In the following, the codes BPR, LI, Mint, and BS, shown in parentheses after the power line or ground line name, indicate the layer on which the power line or ground line is located. Note that in Figure 3, the virtual power line VVDD2 (Mint) extends to the peripheral circuit area PCA.

[0022] Circuits located in the peripheral circuit area PCA and the decoder area DECA are electrically connected to the virtual power line VVDD1 and the ground line VSS1. Bit cells located in the bit cell area BCA are electrically connected to the virtual power line VVDD2 and the ground line VSS2. In the example shown in Figure 3, the power switch circuit PSW is electrically connected to the power line VDD1, the virtual power line VVDD2, and the ground line VSS1.

[0023] The isolated region SPA is provided with a power switch circuit PSW having a switch transistor (not shown) electrically connected to the power line VDD1 (Mint) and the virtual power line VVDD2 (Mint). The power switch circuit PSW is electrically connected to the ground line VSS1 (Mint).

[0024] In the isolated region SPA, power line VDD1(Mint) is connected to power line VDD1(BPR) located in the peripheral circuit region PCA. Ground line VSS1(Mint) is connected to ground line VSS1(BPR) located in the peripheral circuit region PCA. The power supply voltage supplied to the virtual power line VVDD2(Mint) via the power switch circuit PSW is supplied to the bit cell region BCA, and then supplied to the peripheral circuit region PCA via the virtual power lines VVDD1(LI) and VVDD1(BPR).

[0025] In the bit cell region (BCA), the ground wire VSS2(BPR) on the surface of the semiconductor substrate (SUB) and the ground wire VSS2(BS) on the back surface (BS) of the semiconductor substrate (SUB) are connected to each other via a TSV (Through Silicon Via). A TSV is an example of a via. In the peripheral circuit region (PCA), the ground wire VSS1(BPR) on the surface of the semiconductor substrate (SUB) and the ground wire VSS1(BS) on the back surface (BS) are connected to each other via a TSV. Also in the peripheral circuit region (PCA), the power line VDD1(BPR) and the ground wire VDD1(BS) on the back surface (BS) are connected to each other via a TSV.

[0026] The grounding wires VSS1 and VSS2 may be connected to each other via wiring provided on the back surface BS or the front surface of the semiconductor substrate SUB. Hereafter, the back surface BS of the semiconductor substrate SUB will also be simply referred to as the back surface BS.

[0027] Furthermore, in Figure 3, the virtual power line VVDD2 of the bit cell region BCA is provided in the Mint layer, but as shown in Figure 10 later, it may also be provided using a BPR. In this case, the virtual power line VVDD2(BPR) and the virtual power line VVDD2(BS) provided on the back surface BS may be connected to each other via a TSV. Alternatively, the virtual power line VVDD2(BS) provided on the back surface BS may be connected to the virtual power line VVDD2(Mint) via a TSV.

[0028] Power line VDD1(BPR) is an example of a first power line. Virtual power line VVDD1(BPR) is an example of a second power line. Power line VDD1(BS) is an example of a third power line. Power line VDD1(Mint) is an example of a fifth power line. Virtual power line VVDD2(Mint) is an example of a fourth or sixth power line. Ground line VSS1(BPR) is an example of a first ground line. Ground line VSS2(BPR) is an example of a second ground line. Ground line VSS1(BS) is an example of a third ground line. Ground line VSS2(BS) is an example of a fourth ground line. For example, power line VDD1(BS), ground line VSS1(BS), virtual power line VVDD2(BS), and ground line VSS2(BS) may be provided as BS-PDN.

[0029] For example, the layout shown in Figure 3 is repeated in the Y direction. In the bit cell region BCA, where many bit cells BC (Figures 5 and 6) are arranged, elements such as transistors may be arranged at a higher density compared to the peripheral circuit region PCA. For this reason, the spacing of the grounding wires VSS2 (BPR) in the Y direction may be set smaller than the spacing of the grounding wires VSS1 (BPR) in the peripheral circuit region PCA to accommodate the densely arranged elements.

[0030] Therefore, in the peripheral circuit area PCA and the bit cell area BCA, the types of power supply wiring for BPRs aligned in the X direction may not be the same. To account for cases where the power supply types of BPRs aligned in the X direction are different (e.g., VDD1 and VSS2), the spacing of the BPR wiring in the X direction is set, for example, by layout rules, to a distance that minimizes mutual influence of the power supplies.

[0031] Figure 4 is a plan view showing another example of the power wiring layout in the area where the power switch circuit of Figure 1 is located. Elements similar to those in Figure 3 are given the same reference numerals or patterns, and detailed descriptions are omitted.

[0032] In Figure 4, the Y-direction positions of the BPR wiring provided in the peripheral circuit region PCA and the BPR wiring provided in the bit cell region BCA are different from each other. Also, the Y-direction positions of the virtual power line VVDD1(Mint) provided in the peripheral circuit region PCA and the isolation region SPA and the virtual power line VVDD2(Mint) provided in the bit cell region BCA are different from each other.

[0033] In this case, the virtual power line VVDD1(Mint) is electrically connected to the virtual power line VVDD2(Mint) via a local wiring LI that extends in the Y direction in the bit cell area BCA. This allows the virtual power lines VVDD1(Mint) and VVDD2(Mint), which are located at different positions in the Y direction, to be connected to each other, and the power switch circuit PSW provided in the isolation area SPA can be shared between the peripheral circuit area PCA and the bit cell area BCA. The virtual power line VVDD1(Mint) is an example of the first wiring. Note that the wiring extending in the Y direction that electrically connects the virtual power lines VVDD1(Mint) and VVDD2(Mint) may be wiring provided in a layer above the Mint layer.

[0034] Figure 5 shows an example of a bit cell BC located in the bit cell region BCA of Figure 1. To make the wiring layout easier to understand, Figure 5(A) shows the wiring of the Mint layer and the layout of vias connected to the Mint layer, and Figure 5(B) shows the wiring, gates, fins, and vias of the layers below the Mint layer (on the semiconductor substrate SUB side). Figure 5(C) shows the circuit of bit cell BC. The layouts shown in Figures 5(A) and 5(B) overlap each other in a plan view. In Figure 5, the power line name, ground line name, signal line name, or node name is indicated in parentheses after the wiring layer name or gate name.

[0035] Via 1, indicated by a square, connects the wiring of the Mint layer to each gate. Via 2, indicated by a circle, connects the wiring of the Mint layer to the local wiring LI. Via 3, indicated by a diamond, connects the local wiring LI to the wiring of the BPR. The local wiring LI and fin FIN are connected at a position where they overlap in a plan view.

[0036] The dashed rectangles in Figure 5(B) represent p-channel transistors P1 and P2, n-channel transistors N1 and N2, and transfer transistors T1 and T2. Transfer transistors T1 and T2 are n-channel transistors. The symbols Q and QB shown in Figures 5(A) to 5(C) represent complementary storage nodes of bit cell BC. Storage node Q is connected to bit line BL via transfer transistor T1. Storage node QB is connected to bit line BLB via transfer transistor T2.

[0037] Two word lines WL on the Mint layer are connected to gates GT4 and GT1 of transfer transistors T1 and T2, respectively, via VIA1. A virtual power line VVDD2 on the Mint layer is connected to local wirings LI2 and LI7 via VIA2. Local wiring LI2 is connected to the source of p-channel transistor P1. Local wiring LI7 is connected to the source of p-channel transistor P2.

[0038] The wiring Q in the Mint layer is connected to local wiring LI5 and fins FIN3 and FIN4 via via VIA2, and to gate GT3 via via VIA1. Fin FIN3 functions as the source and drain of p-channel transistor P1, and fin FIN4 functions as the source and drain of transfer transistor T1 and n-channel transistor N1.

[0039] The wiring QB on the Mint layer is connected to local wiring LI4 and fins FIN2 and FIN1 via via VIA2, and to gate GT2 via via VIA1. Fin FIN2 functions as the source and drain of p-channel transistor P2, and fin FIN1 functions as the source and drain of transfer transistor T2 and n-channel transistor N2.

[0040] The bit line BLB, located in the Mint layer, is connected to local wiring LI1 and fin FIN1 via via VIA2. The bit line BL, also located in the Mint layer, is connected to local wiring LI8 and fin FIN4 via via VIA2. The ground wires VSS2 of the two BPRs located on either side in the Y direction in Figure 6(B) are connected to local wirings LI3 and LI6, respectively, via via VIA3. Local wiring LI3 is connected to the source of n-channel transistor N1. Local wiring LI6 is connected to the source of n-channel transistor N2.

[0041] Figure 6 shows another example of bit cell BC located in bit cell region BCA of Figure 1. Elements similar to those in Figure 5 are given the same reference numerals or patterns, and detailed explanations are omitted. Figure 6 has the same layout as Figure 5, except that the virtual power line VVDD2 is also provided in BPR.

[0042] The virtual power line VVDD2 of local wiring LI2 and LI7 is connected to the virtual power line VVDD2 of the BPR via via VIA3. The virtual power line VVDD2 of the BPR is located between the ground lines VSS2 of the two BPRs and extends in the X direction, as is the ground line VSS2 of the two BPRs.

[0043] Figure 7 is a plan view showing an example of the layout of the power switch circuit (PSW), bit cell area (BCA), and peripheral circuit area (PCA) shown in Figure 3. Of the legends showing the correspondence between wiring patterns and wiring types shown in Figure 7, those not shown in Figure 7 are the same as the legends showing the correspondence between wiring patterns and wiring types shown in Figures 5 and 6.

[0044] In the bit cell region BCA, for example, bit cells BC, as shown in Figure 5, are arranged side by side in the Y direction. In this case, two bit cells BC aligned in the Y direction are arranged mirror-symmetrically with respect to the X direction. Note that in Figure 7, some of the wiring and vias of the bit cell region BC are omitted from the illustration.

[0045] The power switch circuit PSW located in the isolated region SPA includes the switch transistor SWT and the control circuit CNTL shown in Figure 2. The control circuit CNTL has inverters IV1 and IV2 connected to the power line VDD1 (Mint) and the ground line VSS (Mint). Inverters IV1 and IV2 operate as buffers. Inverter IV1 inverts the level of the signal received at the input terminal IN and outputs it as a switch control signal SWCNT to the switch control signal line SWCNT (Mint). For example, the ground line VSS (Mint) wired to the isolated region SPA is connected to the ground line VSS1 (BPR) of the peripheral circuit region PCA and the ground line VSS2 (BPR) of the bit cell region BCA.

[0046] The switch control signal SWCNT is supplied to the gate of the p-channel transistor P of the switch transistor SWT and to the input terminal of inverter IV2. Inverter IV2 inverts the level of the signal received at the input terminal and outputs it from the output terminal OUT. For example, the signal output from output terminal OUT2 is supplied to input terminal IN2 of the control circuit CNTL of another power switch circuit PSW (not shown) which is located adjacent to the power switch circuit PSW shown in Figure 7 in the Y direction. The switch control signal SWCNT controls the on and off state of the p-channel transistor P of the switch transistor SWT, thereby controlling the supply of power voltage to the virtual power line VVDD.

[0047] The switch transistor SWT has multiple p-channel transistors P, each with a source connected to the power line VDD1 (Mint), a drain connected to the virtual power line VVDD (Mint), and a gate connected to the switch control signal line SWCNT (Mint). Here, the source of the p-channel transistors P is provided on one of the fins FIN facing each other across the gate. The drain of the p-channel transistors P is provided on the other fin FIN facing the source across the gate.

[0048] One end of fin FIN is electrically connected to power line VDD1(Mint) via local wiring LI, and the other end of fin FIN is electrically connected to virtual power line VVDD(Mint) via local wiring LI. The virtual power line VVDD(Mint), connected to the switch transistor SWT, extends along the X direction to the peripheral circuit region PCA and connects to virtual power line VVDD1(BPR) via local wiring LI in the peripheral circuit region PCA. Furthermore, the virtual power line VVDD(Mint) extends along the X direction to bit cell BC and connects to bit cell BC.

[0049] In the peripheral circuit area PCA, multiple power lines VDD1(BPR) are provided, connected to power line VDD1(Mint). These multiple power lines VDD1(BPR) are connected to each other via TSV to power line VDD1(BS) on the back surface BS. By electrically connecting power line VDD1(BS) to multiple power lines VDD1(BPR) in common and arranging the power lines VDD1 in a mesh pattern, the power supply capacity can be increased.

[0050] Furthermore, the peripheral circuit area PCA is provided with multiple grounding wires VSS1(BPR) connected to the grounding wire VSS1(Mint). The multiple grounding wires VSS1(BPR) are connected to each other via the TSV and the grounding wire VSS1(BS) on the back surface BS. By electrically connecting the grounding wire VSS1(BS) to the multiple grounding wires VSS1(BPR) in common, the grounding wires VSS1 can be arranged in a mesh pattern, reducing grounding resistance and thus reducing power supply noise.

[0051] By extending the virtual power supply line VVDD(Mint) along the X direction, the power supply voltage output from the drain of the switch transistor SWT can be supplied to the peripheral circuit area PCA and the bit cell area BCA. Here, the virtual power supply line VVDD(Mint) can be routed without bending in a plan view.

[0052] By extending the grounding wire VSS(Mint) along the X direction, the grounding wire VSS can be connected to the grounding wires VSS1(BPR) and VSS1(BS) of the peripheral area PCA, and to the grounding wire VSS2(BPR) of the bit cell BC. This allows for lower grounding resistance compared to connecting the grounding wire VSS(Mint), which is connected to the power switch circuit PSW, to only one of the peripheral circuit area PCA or the bit cell area BCA.

[0053] Furthermore, the wiring of the BPR in the bit cell area BCA and the wiring of the BPR in the peripheral circuit area PCA may be offset in the Y direction, as shown in Figure 4. Also, as shown in Figure 4, multiple grounding lines VSS2(BPR) in the bit cell area BCA may be connected to each other via grounding lines VSS2(BS) provided on the back surface BS. In addition, multiple virtual power lines VVDD1(BPR) in the peripheral circuit area PCA may be connected to each other via virtual power lines VVDD1(BS) (not shown) provided on the back surface BS. Furthermore, in other embodiments and modifications, the wiring of multiple BPRs may be connected to each other via wiring provided on the back surface BS.

[0054] Figure 8 is a cross-sectional view showing a section along the line Y1-Y1' in Figure 7. The wiring in the Mint layer is connected to the local wiring LI via via VIA2. For example, the power line VDD1(Mint) is connected to the power line VDD1(LI) via via VIA2, and further connected to the fin FIN, which is part of the switch transistor SWT. The fin FIN is provided on the semiconductor substrate SUB.

[0055] Figure 9 is a cross-sectional view showing a section along the line Y2-Y2' in Figure 7. For example, power line VDD1(Mint) is connected to power line VDD1(BS) provided on the back surface BS of the semiconductor substrate SUB via via VIA2, local wiring LI, via VIA3, BPR, and TSV. Similarly, ground line VSS(Mint) is connected to ground line VSS(BPR) via via VIA2, local wiring LI, and via VIA3. Note that power line VDD1(Mint) and power line VDD1(BPR) may be connected via via VIA instead of local wiring LI. Likewise, ground line VSS(Mint) and ground line VSS(BPR) may be connected via via VIA instead of local wiring LI.

[0056] Figure 10 is a plan view showing a modified version of the layout shown in Figure 7. Elements similar to those in Figure 7 are given the same reference numerals or patterns, and detailed explanations are omitted. Figure 10 has the same layout as Figure 7, except that the virtual power line VVDD2 of the bit cell area BCA is provided using a BPR.

[0057] In the isolated SPA region, the virtual power line VVDD(Mint) connected to the drain of the p-channel transistor P is connected to the virtual power line VVDD1(BPR) of the peripheral circuit region PCA and the virtual power line VVDD2(BPR) of the bit cell region BCA. The virtual power line VVDD2(BPR) is an example of a fourth power line.

[0058] For example, in the peripheral circuit area PCA, virtual power line VVDD(Mint) is connected to virtual power line VVDD1(LI) via via VIA2 and to virtual power line VVDD1(BPR) via via VIA3. Furthermore, in the bit cell area BCA, virtual power line VVDD(Mint) is connected to virtual power line VVDD2(BPR) via via VIA2, local wiring LI, and via VIA3. Note that in the bit cell area BCA, virtual power line VVDD(Mint) may also be connected to virtual power line VVDD2(BPR) via via VIA without going through local wiring LI.

[0059] In Figure 10, the multiple virtual power lines VVDD2(BPR) provided in the bit cell region BCA may be connected to each other via a virtual power line VVDD(BS) (not shown) provided on the back surface BS of the semiconductor substrate SUB. Also, in Figures 3, 4, 7, and 10, a power switch circuit PSW1 that supplies power voltage to the virtual power line VVDD1 of the peripheral circuit region PCA may be provided in the peripheral circuit region PCA. In this case, the power switch circuit PSW provided in the isolation region SPA may supply power voltage only to the virtual power line VVDD2 of the bit cell region BCA.

[0060] Furthermore, the Y-direction position of the virtual power line VVDD1(BPR) in the peripheral circuit area PCA may be set to be the same as the Y-direction position of the virtual power line VVDD2(BPR) in the bit cell area BCR. Also, the wiring of the BPR in the bit cell area BCA and the wiring of the BPR in the peripheral circuit area PCA may be offset in the Y-direction, as shown in Figure 4.

[0061] In this embodiment, a power switch circuit PSW (or PSW1, PSW2) can be placed in an SRAM on the back surface BS of a semiconductor substrate SUB, where grounding lines VSS (e.g., VSS1, VSS2) and power lines VDD (e.g., VDD1) are wired.

[0062] By placing the power switch circuit (PSW) in the isolated area (SPA), the layout size of the peripheral circuit area (PCA) and the bit cell area (BCA) can be reduced. As a result, the chip size or layout size of the semiconductor device 100 can be reduced. By routing the power line VDD, virtual power line VVDD, and ground line VSS of the power switch circuit (PSW) in the isolated area (SPA) using a Mint layer, the power switch circuit (PSW) can be placed in the isolated area (SPA) without violating the routing layout rules of the BPR.

[0063] By supplying the power supply voltage VDD used in the power switch circuit PSW from wiring provided on the back surface BS, it is possible to suppress the increase in the power supply wiring area on the front surface of the semiconductor substrate SUB.

[0064] As shown in Figure 10, by using a BPR to route the virtual power line VVDD2, the wiring resistance can be reduced, and the ability to supply the virtual power voltage VVDD2 to the bit cell BC can be increased.

[0065] As shown in Figures 3 and 7, the virtual power line VVDD1 (BPR) and the power line VDD1 (BPR) are arranged at a distance in the X direction. As shown in Figures 3 and 7, the power line VDD1 (BPR) and the ground line VSS2 (BPR) are arranged at a distance in the X direction, separated by the isolation area SPA. This allows for the installation of BPR wiring without violating the BPR wiring layout rules.

[0066] In the peripheral circuit area PCA, power supply capacity can be increased by electrically connecting power line VDD1(BS) to multiple power lines VDD1(BPR) in common, thereby arranging power lines VDD1 in a mesh pattern. In the peripheral circuit area PCA, ground line VSS1(BS) can be electrically connected to multiple ground lines VSS1(BPR) in common, thereby arranging ground lines VSS1 in a mesh pattern, reducing grounding resistance and thus reducing power supply noise.

[0067] In the bit cell region BCA, by electrically connecting the grounding wire VSS2(BS) to multiple grounding wires VSS2(BPR) in common, the grounding wires VSS2 can be arranged in a mesh pattern, reducing grounding resistance and thus reducing power supply noise. Assume that multiple virtual power lines VVDD2(BPR) and virtual power lines VVDD2(BS) are provided in the bit cell region BCA. In this case, by electrically connecting the virtual power line VVDD2(BS) to multiple virtual power lines VVDD2(BPR) in common and arranging the virtual power lines VVDD2 in a mesh pattern, the power supply capacity can be increased.

[0068] (Second embodiment) Figure 11 is a plan view showing an example of the power wiring layout in the area where the power switch circuit of the semiconductor device is located in the second embodiment. Elements similar to those in Figure 3 are given the same reference numerals or patterns. Figure 11 is an enlarged view of the area where the peripheral circuit area PCA and the bit cell area BCA are located separated by the isolation area SPA, and the power switch circuits PSW1 and PSW2 from Figure 1 are located in the peripheral circuit area PCA as a common power switch circuit PSW.

[0069] For example, in Figure 11, a power switch circuit PSW common to both the peripheral circuit area PCA and the bit cell area BCA is located in the peripheral circuit area PCA, while no power switch circuit PSW is located in the isolated area SPA. Alternatively, as shown in Figure 1, power switch circuits PSW1 and PSW2 may be provided in the peripheral circuit area PCA and the bit cell area BCA, respectively. The virtual power line VVDD1(Mint) of the power switch circuit PSW located in the peripheral circuit area PCA extends to the bit cell area BCA.

[0070] Figure 12 is a plan view showing an example of a power switch circuit PSW located in the peripheral circuit region PCA of Figure 11. The virtual power line VVDD1(Mint), which extends from the power switch circuit PSW to the bit cell region BCA, is connected to the sources of the p-channel transistors P1 and P2 (Figure 5) of each bit cell BC via the virtual power line VVDD2(LI), similar to Figure 7 described above.

[0071] In addition, in the bit cell area BCA, the virtual power line VVDD1 (Mint) may be connected to the virtual power line VVDD2 (BPR) as shown in Figure 10, and then connected to the local wiring LI (VVDD2) via the virtual power line VVDD2 (BPR).

[0072] Figure 13 is a plan view showing a modified example of the power switch circuit PSW of Figure 11. Elements similar to those in Figure 3 are given the same reference numerals or patterns. Figure 13 is similar to the layout shown in Figures 11 and 12, except that the power switch circuit PSW is located across the peripheral circuit area PCA and the isolated area SPA.

[0073] Power line VDD1 is routed using BPR in the peripheral circuit area (PCA) and using the Mint layer in the isolated area (SPA). Power line VDD1 (BPR) and power line VDD1 (Mint) are located at the same position in the Y direction and are connected at a position where they overlap in a plan view. In Figure 13, via VIA3, local routing LI, and via VIA2, which connect the BPR routing and the Mint layer routing to each other, are omitted.

[0074] In addition, in the bit cell area BCA, the virtual power line VVDD1 (Mint) may be connected to the virtual power line VVDD2 (BPR) as shown in Figure 10, and then connected to the local wiring LI (VVDD2) via the virtual power line VVDD2 (BPR).

[0075] As described above, the same effects as in the embodiments described can be obtained in this embodiment as well. For example, a power switch circuit PSW can be placed in an SRAM on the back surface BS of a semiconductor substrate SUB, on which grounding lines VSS (e.g., VSS1, VSS2) and power line VDD (e.g., VDD1) are wired. By supplying the power supply voltage VDD used by the power switch circuit PSW from the wiring provided on the back surface BS, the increase in the power supply wiring area on the front surface side of the semiconductor substrate SUB can be suppressed.

[0076] Furthermore, in this embodiment, by placing a portion of the power switch circuit PSW in the isolated region SPA, the layout size of the peripheral circuit region PCA can be reduced compared to the case where the power switch circuit PSW is placed only in the peripheral circuit region PCA. As a result, the chip size of the semiconductor device can be reduced.

[0077] (Third embodiment) Figure 14 is a circuit block diagram showing an overview of the power switch circuit PSW located in the standard cell block SCB of the semiconductor device in the third embodiment. Elements similar to those in Figure 2 are denoted by the same reference numerals, and detailed explanations are omitted. Figure 14 is the same as Figure 2, except that a standard cell area SCA is provided between the virtual power line VVDD and the ground line VSS instead of SRAM.

[0078] Figure 15 is a plan view showing an overview of the layout of the standard cell block (SCB) in Figure 14. The standard cell block (SCB) has a standard cell area (SCA) where the circuits that will become standard cells are arranged, and an end cap area (ECAP) that surrounds the standard cell area (SCA). For example, the end cap area (ECAP) is provided to suppress variations in electrical characteristics that occur when the arrangement density of wiring or elements differs between the standard cell area (SCA) and the circuits arranged around the standard cell area (SCA).

[0079] In the standard cell area SCA, multiple power switch circuits PSW are arranged in the Y direction. A dummy power switch circuit PSW-EN1 is placed at the end of the Y-arranged power switch circuits PSW on the end cap area ECAP side. A dummy power switch circuit PSW-EN2 is placed at the end of the Y-arranged power switch circuits PSW on the standard cell area SCA side. Hereafter, the dummy power switch circuit PSW-EN1 will also be referred to as end cap cell PSW-EN1, and the dummy power switch circuit PSW-EN2 will also be referred to as end cap cell PSW-EN2.

[0080] Figure 16 is a plan view showing an example of the power wiring layout in the area where the power switch circuit PSW of Figure 15 is located. Elements similar to those in Figure 3 are given the same reference numerals or patterns. In the standard cell area SCA, the virtual power line VVDD (BPR) and the ground line VSS (PBR), provided using BPR, are arranged extending in the X direction.

[0081] In the region where the power switch circuit PSW is located, the virtual power line VVDD(BPR) is disconnected and the power line VDD(BPR) is established. The disconnected virtual power lines VVDD(BPR) on both sides in the X direction of the power switch circuit PSW are connected to each other via the virtual power line VVDD(Mint). The power switch circuit PSW has a switch transistor SWT (Figure 14) that connects the power line VDD(BPR) to the virtual power line VVDD(Mint).

[0082] In the region where the power switch circuit PSW is located, multiple power lines VDD(BPR) arranged at intervals in the Y direction are connected via a TSV to a power line VDD(BS) provided on the back surface BS of the semiconductor substrate SUB. In the standard cell region SCA, the ground line VSS(BPR) is connected via a TSV to a ground line VSS(BS) provided on the back surface BS. In addition, in the standard cell region SCA, the virtual power line VVDD(BPR) may be connected via a TSV to a virtual power line VVDD(BS) provided on the back surface BS.

[0083] Furthermore, multiple power lines VDD (BPR) may be connected to each other via wiring in the Mint layer or above the Mint layer, rather than via wiring on the back BS. The ground line VSS (BPR) may be connected to wiring in the Mint layer or above the Mint layer, rather than via wiring on the back BS. Multiple virtual power lines VVVD (BPR) may be connected to each other via wiring in the Mint layer or above the Mint layer, rather than via wiring on the back BS.

[0084] In Figure 16, two power lines VDD(BPR) are placed in the portions where each of the two virtual power lines VVDD(BPR) extending in the X direction is cut. In this case, the number of power lines VDD(BPR) that can be placed can be increased compared to, for example, placing power lines VDD(BPR) in the region created by cutting the ground line VSS(BPR). This makes it possible to suppress the increase in the resistance of power lines VDD(BPR).

[0085] Figure 17 is a plan view showing an example of the power switch circuit PSW in Figure 16. Note that only a portion of the circuit of the standard cell area SCA is shown. Also, the input and output terminals of the control circuit CNTL provided in the power switch circuit PSW are omitted.

[0086] The power switch circuit PSW has a switch transistor SWT and a control circuit CNTL similar to the power switch circuit PSW shown in Figure 7. However, the number of p-channel transistors P included in the switch transistor SWT differs from that in Figure 7. In addition, one or both of the end cap cells PSW-EN1 and PSW-EN2, which are located at the ends of the power switch circuit array shown in Figure 15, may have dummy transistors and dummy buffers instead of the switch transistor SWT and control circuit CNTL. Furthermore, a specific example of when end cap cells PSW-EN1 or PSW-EN2 are located adjacent to the power switch circuit PSW is explained in Figure 19.

[0087] Figure 18 is a plan view showing an example of the end cap cell PSW-EN2 of Figure 15. For example, the end cap cell PSW-EN2 has a plurality of dummy gates DMYG extending in the Y direction, and the plurality of dummy gates DMYG are connected to fins FIN extending in the X direction.

[0088] Furthermore, in the end cap cell PSW-EN2, similar to the power switch circuit PSW shown in Figure 17, the virtual power line VVDD(BPR) is disconnected and the power line VDD(BPR) is provided. The X-direction spacings X1 and X2 between the two virtual power lines VVDD(BPR) and the power line VDD(BPR) are the same as the spacings between the two virtual power lines VVDD(BPR) and the power line VDD(BPR) aligned in the X direction in Figure 17.

[0089] This prevents a short circuit between the virtual power line VVDD(BPR) and the power line VDD(BPR) when a standard cell is placed adjacent to the power switch circuit PSW in the Y direction. However, if a standard cell with BPRs on both sides in the Y direction is placed adjacent to the power switch circuit PSW in the Y direction, the BPR of the standard cell will cause a short circuit between the virtual power line VVDD(BPR) and the power line VDD(BPR) of the power switch circuit PSW.

[0090] Figure 19 is a plan view showing an example where the end cap cell PSW-EN2 shown in Figure 18 is placed adjacent to the power switch circuit PSW shown in Figure 17. The end cap cell PSW-EN2 is positioned so that its two VVDD(BPR) and VDD(BPR) points overlap with the two VVDD(BPR) and VDD(BPR) points of the power switch circuit PSW, respectively.

[0091] This prevents a short circuit between the virtual power line VVDD(BPR) and the power line VDD(BPR) of the power switch circuit PSW. Note that the end cap cell PSW-EN2 in Figure 19 is positioned in the Y direction relative to the power switch circuit PSW in the opposite direction to that in Figure 15.

[0092] Figure 20 is a plan view showing an example of the end cap cell PSW-EN1 shown in Figure 15. Similar to the end cap cell PSW-EN2 shown in Figure 18, the end cap cell PSW-EN1 has multiple dummy gates DMYG extending in the Y direction, and these multiple dummy gates DMYG are connected to fins FIN extending in the X direction.

[0093] The end cap cell PSW-EN1 can be placed adjacent to the boundary of the standard cell area SCA because the side opposite to the side adjacent to the power switch circuit PSW (the side of the dashed oval) is terminated. Here, the termination of the end cap cell PSW-EN1 is the same as the termination of other end cap cells placed in the end cap area ECAP (Figure 15).

[0094] As described above, the same effects as in the embodiments described can be obtained in this embodiment as well. For example, a power switch circuit PSW can be placed in a standard cell block SCB on the back surface BS of a semiconductor substrate SUB, where grounding lines VSS (e.g., VSS1, VSS2) and power line VDD (e.g., VDD1) are wired. By supplying the power supply voltage VDD used by the power switch circuit PSW from wiring provided on the back surface BS, it is possible to suppress the increase in the power supply wiring area on the front surface side of the semiconductor substrate SUB.

[0095] Furthermore, in this embodiment, one or both of the end cap cells PSW-EN1 and PSW-EN2 are placed at both ends of a row of power switch circuits PSW arranged in one direction. In the end cap cell PSW-EN1, the side opposite to the side adjacent to the power switch circuit PSW is terminated in the same way as the termination of other end cap cells. This allows the end cap cell PSW-EN1 to be placed adjacent to the boundary of the standard cell area SCA.

[0096] The end cap cell PSW-EN2, like the power switch circuit PSW, has the virtual power line VVDD(BPR) disconnected and the power line VDD(BPR) provided. This prevents a short circuit between the virtual power line VVDD(BPR) and the power line VDD(BPR) when a normal standard cell is placed adjacent to the power switch circuit PSW in the Y direction.

[0097] Although the present invention has been described above based on various embodiments, the present invention is not limited to the requirements shown in the above embodiments. These points can be modified as long as they do not impair the spirit of the present invention, and can be appropriately determined according to their application. [Explanation of Symbols]

[0098] 100 Semiconductor Devices BCA Bit Cell Area BL, BLB bit lines BS (Back) CNTL control circuit DECA Decoder Area ECAP End Cap Area FIN1-FIN4 fins GT1-GT4 Gate IN2 Input Terminal IV1, IV2 Inverter LI1-LI8 Local Wiring N1, N2 n-channel transistors OUT2 output terminal P, P1, P2 p-channel transistors PCA Peripheral Circuit Area PSW, PSW1, PSW2 Power Switch Circuit PSW-EN1, PSW-EN2 Power switch circuit (end cap area) Q, QB memory node SCA Standard Cell Area SCB Standard Cell Block SPA isolation area SUB Semiconductor Substrate SWCNT Switch Control Signal SWT Switch Transistor T1, T2 transfer transistors VDD, VDD1, VDD2 power line VIA1, VIA2, VIA3 VSS, VSS1, VSS2 ground wire VVDD, VVDD1, VVDD2 virtual power lines WL Word Line X1, X2 spacing

Claims

1. A substrate having a first surface and a second surface facing the first surface, The first power line provided on the first surface, The second power line provided on the first surface, The first grounding wire provided on the first surface, The third power line provided on the second surface, A via is provided on the substrate to electrically connect the first power line and the third power line, A fourth power line electrically connected to the second power line, The second grounding wire provided on the first surface, A first region having the second power line, the first ground line, the third power line, and the via, A second region having the fourth power line and the second grounding line, A third region located between the first region and the second region in a plan view, A power switch circuit having a switch transistor electrically connected between the first power line and the second power line, and Semiconductor equipment.

2. The power switch circuit is provided in the third region. The semiconductor device according to claim 1.

3. The third region has a fifth power line electrically connected to the first power line and a sixth power line electrically connected to the second power line. The switch transistor is electrically connected to the fifth power line and the sixth power line. The semiconductor device according to claim 2.

4. The power switch circuit is provided in the first region. The semiconductor device according to claim 1.

5. The first region has a plurality of first grounding lines that extend in a first direction in a plan view and are spaced apart in a second direction different from the first direction in a plan view. The second region has a plurality of second grounding wires that extend in the first direction and are spaced apart in the second direction. The spacing between the multiple first grounding wires in the second direction is different from the spacing between the multiple second grounding wires in the second direction. A semiconductor device according to any one of claims 1 to 4.

6. The first power line and the second power line extend in the first direction and are spaced apart in the first direction in a plan view. A semiconductor device according to any one of claims 1 to 4.

7. The first power line, the second power line, and the fourth power line are arranged to be spaced apart in the first direction in a plan view. The semiconductor device according to claim 6.

8. The third power line is electrically connected in common to the multiple first power lines. A semiconductor device according to any one of claims 1 to 4.

9. A third grounding wire provided on the second surface of the first region and electrically connected in common to a plurality of first grounding wires, The second region is provided on the second surface and has a fourth grounding wire that is electrically connected in common to a plurality of second grounding wires. A semiconductor device according to any one of claims 1 to 4.

10. The second power line and the fourth power line, each extending in the first direction, are located at different positions in the second direction from the first direction. The second power line and the fourth power line are connected to each other via the first wiring. A semiconductor device according to any one of claims 1 to 4.

11. The fourth power line is provided on the first surface A semiconductor device according to any one of claims 1 to 4.

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