Semiconductor equipment

Abstract

This semiconductor device comprises: a first and a second power supply lines and a first and a second ground lines provided on a first surface of a substrate; and a third and a fourth power supply lines provided on a second surface of the substrate. The second power supply line and the third power supply line are connected through a via provided in the substrate. The semiconductor device comprises a first and a second regions disposed across a third region, and a power supply switch circuit including a switch transistor disposed between the third and fourth power supply lines. Thus, the power supply switch can be appropriately disposed by utilizing a wiring layer in which wiring for a power supply wiring network on the back surface of the substrate is provided.

Description

Technical Field

[0001] The present invention relates to a semiconductor device.

[0002] The present application claims priority based on U.S. Provisional Application No. 63 / 261,847 filed on September 30, 2021, and incorporates all the contents described in the above application by reference.

Background Art

[0003] In an SRAM (Static Random Access Memory), when the arrangement of power supply wirings is different between a bit cell region and a peripheral circuit region, an isolation region may be provided to secure a space between the bit cell region and the peripheral circuit region in plan view. A technique called BPR (Buried Power Rail), in which power supply wirings are embedded in a semiconductor substrate, is known. A technique of providing a power switch circuit between a power supply line and a virtual power supply line to switch between supplying and cutting off the supply of power supply voltage to the virtual power supply line of an internal circuit is known. A technique called BS-PDN (Backside-Power Delivery Network), in which a power supply wiring network is provided on the back surface of a semiconductor substrate and power supply voltage is supplied through a via penetrating the back surface and the front surface of the semiconductor substrate, is known. A technique of providing a transistor for switching between supplying and cutting off the supply of power supply voltage in a wiring layer is known.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

Patent Document 5

[0005] When forming transistors using a wiring layer where BS-PDN wiring is provided, detailed technical studies have not been conducted on how to arrange the power switch circuit.

[0006] The present invention has been made in view of the above points, and aims to appropriately position a power switch in a semiconductor device using a wiring layer on the back surface of a substrate where wiring for a power supply wiring network is provided. [Means for solving the problem]

[0007] In one aspect of the present invention, the semiconductor device includes a substrate having a first surface and a second surface facing the first surface, a first power line provided on the first surface, a first ground line provided on the first surface, a first region having the first power line and the first ground line, a second power line provided on the first surface, a second ground line provided on the first surface, a third power line provided on the second surface, a fourth power line provided on the second surface, a via provided on the substrate that electrically connects the second power line and the third power line, a second region having the second power line and the second ground line, a third region located between the first region and the second region in a plan view, and a first power switch circuit having a first switch transistor electrically connected between the third power line and the fourth power line on the second surface side of the substrate. [Effects of the Invention]

[0008] According to the disclosed technology, a power switch can be appropriately positioned in a semiconductor device using a wiring layer on the back of the substrate where the wiring for the power supply network is provided. [Brief explanation of the drawing]

[0009] [Figure 1] This is a plan view showing an overview of the layout of the semiconductor device in the first embodiment. [Figure 2] This is a circuit block diagram showing an overview of the power switch circuit located in the bit cell area of ​​Figure 1. [Figure 3] This is a plan view showing an example of the layout of power wiring in the area where the power switch circuit in Figure 1 is located. [Figure 4A] Figure 3 is a cross-sectional view showing an example of a cross-section of the switch transistor in the power switch circuit PSW1. [Figure 4B] Figure 3 shows another example of a cross-sectional view of the switch transistor in the power switch circuit PSW1. [Figure 4C] Figure 3 shows another example of a cross-sectional view of the switch transistor in the power switch circuit PSW1. [Figure 4D]It is a cross-sectional view showing still another example of a cross-section of the switch transistor of the power switch circuit PSW1 of FIG. 3. [Figure 5] It is a diagram showing an example of a bit cell arranged in the bit cell region of FIG. 1. [Figure 6] It is a diagram showing another example of a bit cell arranged in the bit cell region of FIG. 1. [Figure 7] It is a plan view showing an example of a power switch circuit arranged across an isolation region and a bit cell region. [Figure 8] It is a cross-sectional view showing a cross-section along the line Y1-Y1' of FIG. 7. [Figure 9] It is a cross-sectional view showing a cross-section along the line X1-X1' of FIG. 7. [Figure 10] It is a plan view showing a modification of the power switch circuit arranged in the bit cell region of FIG. 7. [Figure 11] It is a plan view showing an example of a power switch circuit arranged across an isolation region and a bit cell region in the semiconductor device according to the second embodiment. [Figure 12] It is a plan view showing a modification of the power switch circuit of FIG. 11. MODE FOR CARRYING OUT THE INVENTION

[0010] Hereinafter, embodiments will be described with reference to the drawings. In the following description, reference numerals denoting signals may also be used as reference numerals denoting signal values, signal lines or signal terminals. Reference numerals denoting a power supply may also be used as reference numerals denoting a power supply voltage, a power supply line to which the power supply voltage is supplied, or a power supply terminal.

[0011] (First Embodiment) Figure 1 is a plan view showing an overview of the layout of a semiconductor device in a first embodiment. The semiconductor device 100 shown in Figure 1 is, for example, an SRAM. The semiconductor device 100 has a bit cell area BCA and a peripheral circuit area PCA and a decoder area DECA arranged around the bit cell area BCA. The peripheral circuit area PCA and the decoder area DECA are examples of a first area. The bit cell area BCA is an example of a second area.

[0012] For example, the peripheral circuit region PCA and the bit cell region BCA are arranged side by side in the X direction, and the decoder region DECA and the bit cell region BCA are arranged side by side in the Y direction. The X direction is an example of a first direction. The Y direction is an example of a second direction different from the first direction. In a plan view, an isolation region SPA is placed between the bit cell region BCA, the peripheral circuit region PCA, and the decoder region DECA. The isolation region SPA is an example of a third region.

[0013] For example, different power supply voltages are supplied to the bit cell area BCA, the peripheral circuit area PCA, and the decoder area DECA. For example, multiple power lines extending in the X direction and arranged in the Y direction are provided for the bit cell area BCA, the peripheral circuit area PCA, and the decoder area DECA. Note that the positions and spacing of the power lines in the bit cell area BCA, the peripheral circuit area PCA, and the decoder area DECA may differ.

[0014] Furthermore, a predetermined number of power switch circuits PSW1 are provided on the back surface BS (Figure 4(A)) of the semiconductor substrate SUB of the semiconductor device 100 in the peripheral circuit area PCA and the decoder area DECA, respectively. A predetermined number of power switch circuits PSW2 are provided on the back surface BS of the semiconductor substrate SUB in the bit cell area BCA. Note that one or both of the power switch circuits PSW1 and PSW2 may be located on the back surface BS of the semiconductor substrate SUB in the isolation area SPA. The back surface BS of the semiconductor substrate SUB is an example of a second surface facing the front surface of the semiconductor substrate SUB. Power switch circuit PSW1 is an example of a second power switch circuit. Power switch circuit PSW2 is an example of a first power switch circuit. Hereinafter, when power switch circuits PSW1 and PSW2 are not distinguished, they will also be referred to as power switch circuit PSW.

[0015] Figure 2 is a circuit block diagram showing an overview of the power switch circuit PSW2 located in the bit cell area BCA of Figure 1. Note that the power switch circuit PSW1 located in the peripheral circuit area PCA and the decoder area DECA has a similar circuit configuration to that shown in Figure 2. The bit cell area BCA contains multiple bit cells BC (i.e., memory cells). Each bit cell BC is electrically connected to the virtual power line VVDD and the ground line VSS, and operates by receiving power from the virtual power line VVDD.

[0016] The power switch circuit PSW2 includes a switch transistor SWT and a control circuit CNTL. The switch transistor SWT is, for example, a p-channel transistor and operates by receiving a switch control signal SWCNT from the control circuit CNTL at its gate. The switch transistor SWT in the power switch circuit PSW2 is an example of a first switch transistor. The switch transistor SWT in the power switch circuit PSW1 is an example of a second switch transistor. Note that in Figure 2, for simplicity, only one switch transistor SWT is shown, but multiple switch transistor SWTs may be arranged between the power line VDD and the virtual power line VVDD.

[0017] While the switch transistor SWT is ON, the power line VDD and the virtual power line VVDD are electrically connected, and the power supply voltage VDD is supplied to the virtual power line VVDD. While the switch transistor SWT is OFF, the electrical connection between the power line VDD and the virtual power line VVDD is broken, and the virtual power line VVDD is set to a floating state.

[0018] The control circuit CNTL is, for example, a buffer circuit. When the control circuit CNTL operates the SRAM, it sets the switch control signal SWCNT to a low level to supply power voltage from the power line VDD to the virtual power line VVDD. When the control circuit CNTL stops the operation of the SRAM, it sets the switch control signal SWCNT to a high level to stop supplying power voltage from the power line VDD to the virtual power line VVDD.

[0019] Figure 3 is a plan view showing an example of the power wiring layout in the area where the power switch circuits PSW1 and PSW2 in Figure 1 are located. Figure 3 is an enlarged view of the area where the peripheral circuit area PCA and the bit cell area BCA are located, separated by the separation area SPA.

[0020] In the example shown in Figure 3, the wiring and BPR of the Mint layer extend in the X direction, while the local wiring LI and the wiring on the back surface BS of the semiconductor substrate SUB extend in the Y direction. For example, the Mint layer is provided on the front surface of the semiconductor substrate SUB. The local wiring LI is provided between the semiconductor substrate SUB and the Mint layer. The surface of the semiconductor substrate SUB is an example of the first surface.

[0021] In the following, power lines, virtual power lines, and ground lines wired to the peripheral circuit area PCA and the decoder area DECA are denoted by the symbols VDD1, VVDD1, and VSS1, respectively. Power lines, virtual power lines, and ground lines wired to the bit cell area BCA are denoted by the symbols VDD2, VVDD2, and VSS2, respectively. Note that power lines or ground lines wired to the peripheral circuit area PCA or the bit cell area BCA may be located on the side of the isolated area SPA.

[0022] Circuits located in the peripheral circuit area PCA and the decoder area DECA are electrically connected to the virtual power line VVDD1 and the ground line VSS1. Bit cells located in the bit cell area BCA are electrically connected to the virtual power line VVDD2 and the ground line VSS2. In the example shown in Figure 3, the power switch circuit PSW1 is electrically connected to the power line VDD1, the virtual power line VVDD1, and the ground line VSS1, and the power switch circuit PSW2 is electrically connected to the power line VDD2, the virtual power line VVDD2, and the ground line VSS2.

[0023] The peripheral circuit area PCA contains the grounding wire VSS1(BPR) and virtual power supply wire VVDD1(BPR) provided as BPR, and the grounding wire VSS1(BS), power supply wire VDD1(BS), and virtual power supply wire VVDD1(BS) provided on the back side BS. The grounding wires VSS1(BPR) and VSS1(BS) are connected to each other via TSV. The virtual power supply wires VVDD1(BPR) and VVDD1(BS) are connected to each other via TSV.

[0024] In the peripheral circuit region PCA, a power switch circuit PSW1 is provided on the back surface BS of the semiconductor substrate SUB, having a switch transistor (not shown) electrically connected to the power line VDD1(BS) and the virtual power line VVDD1(BS). The power switch circuit PSW1 supplies the power supply voltage VVDD1 to elements and circuits (not shown) provided in the peripheral circuit region PCA.

[0025] The bit cell area BCA contains the grounding line VSS2(BPR) and virtual power line VVDD2(BPR) provided as BPR, and the grounding line VSS(BS) and virtual power line VVDD2(BS) provided on the back surface BS. The grounding lines VSS2(BPR) and VSS2(BS) are connected to each other via TSV. The virtual power lines VVDD2(BPR) and VVDD2(BS) are connected to each other via TSV. The virtual power line VVDD2(BPR) is connected to the virtual power line VVDD2(Mint) of the Mint layer via the virtual power line VVDD2 of the local wiring LI. The virtual power line VVDD2(Mint) is an example of the first wiring.

[0026] In the isolated region SPA, the power line VDD2(BS) provided on the back surface BS is located. In the bit cell region BCA, a power switch circuit PSW2 is provided on the back surface BS of the semiconductor substrate SUB, having a switch transistor (not shown) electrically connected to the power line VDD2(BS) and the virtual power line VVDD2(BS). The power switch circuit PSW2 supplies the power supply voltage VVDD2 to the bit cell BC (Figure 5 or Figure 6) provided in the bit cell region BCA.

[0027] Note that the same power supply voltage may be supplied to the power supply line VDD1(BS) of the power supply switch circuit PSW1 and the power supply line VDD2(BS) of the power supply switch circuit PSW2 shown in Figure 3, or different power supply voltages may be supplied to them. When the same power supply voltage is supplied to power supply lines VDD1(BS) and VDD2(BS), power supply lines VDD1(BS) and VDD2(BS) may be electrically connected to each other. For example, power supply line VDD1(BS), virtual power supply line VVDD1(BS), ground line VSS1(BS), power supply line VDD2(BS), virtual power supply line VVDD2(BS), and ground line VSS2(BS) may be provided as BS-PDN.

[0028] Virtual power line VVDD1(BPR) is an example of the first power line. Virtual power line VVDD2(BPR) is an example of the second power line. Virtual power line VVDD2(BS) is an example of the third power line. Power line VDD2(BS) is an example of the fourth power line. Virtual power line VVDD1(BS) is an example of the fifth power line. Power line VDD1(BS) is an example of the sixth power line. Ground line VSS1(BPR) is an example of the first ground line. Ground line VSS2(BPR) is an example of the second ground line. Ground line VSS1(BS) is an example of the third ground line. Ground line VSS2(BS) is an example of the fourth ground line.

[0029] Figure 4A is a cross-sectional view showing an example of a cross-section of the region including the switch transistor SWT of the power switch circuit PSW1 in Figure 3. In Figure 4A, only the structure of the semiconductor substrate SUB and the back side BS of the semiconductor substrate SUB is shown, and transistors and wiring provided on the front side of the semiconductor substrate SUB are omitted from the illustration. The cross-sectional structure of the region including the switch transistor SWT of the power switch circuit PSW2 in Figure 3 is the same as in Figure 4A.

[0030] A switch transistor (SWT) has stacked semiconductor layers SEML, a gate insulating film GINS, and a gate electrode GT. A power line VDD1(BS) is connected to one side of the semiconductor layer SEML, with the gate electrode GT in between. A virtual power line VVDD1(BS) is connected to the other side of the semiconductor layer SEML, with the gate electrode GT in between. The switch transistor SWT is turned on or off by a control signal input to the gate electrode GT, and when it is on, it supplies a power voltage from the power line VDD1 to the virtual power line VVDD1.

[0031] As shown in Figure 4A, one or both of the power supply line VDD1 and the virtual power supply line VVDD1 may be connected to wiring provided in the wiring layer below the switch transistor SWT. In this case, the wiring in the upper wiring layer and the wiring in the lower wiring layer are connected to each other via vias (BS) provided by openings in the insulating film INS.

[0032] Furthermore, in Figure 4A, two wiring layers are provided on the back surface BS of the semiconductor substrate SUB, but three or more wiring layers may be provided. In this case, the wiring of the two stacked wiring layers may be connected via vias (BS) provided by openings in the insulating film INS.

[0033] Figure 4B is a cross-sectional view showing another example of the cross-section of the switch transistor in the power switch circuit PSW1 of Figure 3. In Figure 4B, only the structure of the semiconductor substrate SUB and the back side BS of the semiconductor substrate SUB is shown, and the transistors and wiring provided on the front side of the semiconductor substrate SUB are omitted from the illustration. The cross-sectional structure of the region including the switch transistor SWT in the power switch circuit PSW2 of Figure 3 is the same as in Figure 4B.

[0034] Figure 4B shows that the semiconductor layer SEML is located on the same layer as the power line VDD1(BS) and the virtual power line VVDD1(BS), and the gate insulating film GINS and gate electrode GT are located on the back surface BS of the semiconductor layer SEML. The power line VDD1(BS) and the virtual power line VVDD1(BS) are connected to the semiconductor layer SEML, respectively. The semiconductor layer SEML, the gate insulating film GINS, and the gate electrode GT are arranged sequentially toward the back surface BS. The other structures are the same as in Figure 4A. For example, the gate electrode GT extends in the depth direction of Figure 4B and is connected to the wiring provided on the back surface BS.

[0035] Figure 4C is a cross-sectional view showing another example of the cross-section of the switch transistor in the power switch circuit PSW1 of Figure 3. In Figure 4C, only the structure of the semiconductor substrate SUB and the back side BS of the semiconductor substrate SUB is shown, and the transistors and wiring provided on the front side of the semiconductor substrate SUB are omitted from the illustration. The cross-sectional structure of the region including the switch transistor SWT in the power switch circuit PSW2 of Figure 3 is the same as in Figure 4C. Figure 4C has the same structure as Figure 4A, except that the switch transistor SWT is provided in the second layer, not the top layer closest to the semiconductor substrate SUB.

[0036] Figure 4D is a cross-sectional view showing yet another example of the cross-section of the switch transistor SWT in the power switch circuit PSW1 of Figure 3. In Figure 4D, only the semiconductor substrate SUB and the structure of the back side BS of the semiconductor substrate SUB are shown, and the transistors and wiring etc. provided on the front side of the semiconductor substrate SUB are omitted from the illustration. The cross-sectional structure of the region including the switch transistor SWT in the power switch circuit PSW2 of Figure 3 is the same as in Figure 4D.

[0037] Figure 4D has a structure similar to Figure 4A, except that the semiconductor layer SEML, gate insulating film GINS, and gate electrode GT are sequentially provided from the back surface BS, and one side of the semiconductor layer SEML is connected to the front surface side of the semiconductor substrate SUB via a TSV.

[0038] One end of the semiconductor layer SEML is connected via a TSV to a virtual power line VVDD1 located on the surface side of the semiconductor substrate SUB. The other end of the semiconductor layer SEML is connected via a via VIA(BS) to a power line VVDD1(BS) located in the wiring layer below the switch transistor SWT.

[0039] The semiconductor layer SEML shown in Figures 4A to 4D may be provided using graphene or carbon nanotubes. Furthermore, the switch transistor SWT shown in Figures 4A to 4D may be a thin-film transistor (TFT).

[0040] Figure 5 shows an example of a bit cell BC located in the bit cell region BCA of Figure 1. To make the wiring layout easier to understand, Figure 5(A) shows the layout of the wiring in the Mint layer and the vias connected to the Mint layer, and Figure 5(B) shows the layout of the wiring, gates, fins, and vias in the layers below the Mint layer (semiconductor substrate side). Figure 5(C) shows the circuit of bit cell BC. The layouts shown in Figures 5(A) and 5(B) overlap each other in a plan view.

[0041] Via 1, indicated by a square, connects the wiring of the Mint layer to each gate. Via 2, indicated by a circle, connects the wiring of the Mint layer to the local wiring LI. Via 3, indicated by a diamond, connects the local wiring LI to the wiring of the BPR. The local wiring LI and fin FIN are connected at a position where they overlap in a plan view.

[0042] The dashed rectangles in Figure 5(B) represent p-channel transistors P1 and P2, n-channel transistors N1 and N2, and transfer transistors T1 and T2. Transfer transistors T1 and T2 are n-channel transistors. The symbols Q and QB shown in Figures 5(A) to 5(C) represent complementary storage nodes of bit cell BC. Storage node Q is connected to bit line BL via transfer transistor T1. Storage node QB is connected to bit line BLB via transfer transistor T2.

[0043] Two word lines WL on the Mint layer are connected to gates GT4 and GT1 of transfer transistors T1 and T2, respectively, via VIA1. A virtual power line VVDD2 on the Mint layer is connected to local wirings LI2 and LI7 via VIA2. Local wiring LI2 is connected to the source of p-channel transistor P1. Local wiring LI7 is connected to the source of p-channel transistor P2.

[0044] The wiring Q in the Mint layer is connected to local wiring LI5 and fins FIN3 and FIN4 via via VIA2, and to gate GT3 via via VIA1. Fin FIN3 functions as the source and drain of p-channel transistor P1, and fin FIN4 functions as the source and drain of transfer transistor T1 and n-channel transistor N1.

[0045] The wiring QB on the Mint layer is connected to local wiring LI4 and fins FIN2 and FIN1 via via VIA2, and to gate GT2 via via VIA1. Fin FIN2 functions as the source and drain of p-channel transistor P2, and fin FIN1 functions as the source and drain of transfer transistor T2 and n-channel transistor N2.

[0046] The bit line BLB, located in the Mint layer, is connected to local wiring LI1 and fin FIN1 via via VIA2. The bit line BL, also located in the Mint layer, is connected to local wiring LI8 and fin FIN4 via via VIA2. The ground wires VSS2 of the two BPRs located on either side in the Y direction in Figure 6(B) are connected to local wirings LI3 and LI6, respectively, via via VIA3. Local wiring LI3 is connected to the source of n-channel transistor N1. Local wiring LI6 is connected to the source of n-channel transistor N2.

[0047] Figure 6 shows another example of a bit cell BC located in the bit cell region BCA of Figure 1. Elements similar to those in Figure 5 are given the same reference numerals or patterns, and detailed explanations are omitted. Figure 6 has the same layout as Figure 5, except that the virtual power line VVDD2 is located in BPR.

[0048] Furthermore, the virtual power line VVDD2 of local wiring LI2 and LI7 is connected to the virtual power line VVDD2 of the BPR via via VIA3. The virtual power line VVDD2 of the BPR is located between the ground lines VSS2 of the two BPRs and extends in the X direction, similar to the ground lines VSS2 of the two BPRs.

[0049] Figure 7 is a plan view showing an example of a power switch circuit PSW2 that spans the isolation region SPA and the bit cell region BCA. The switch transistor SWT of the power switch circuit PSW2 shown in Figure 2 is located in the isolation region SPA. For example, the bit cell BC shown in Figure 5 is located in the bit cell region BCA. Note that some of the wiring and vias of the bit cell region BC in the bit cell region BCA are omitted from the illustration.

[0050] In the semiconductor layer SEML of the switch transistor SWT2 (Figures 4A to 4D), one end flanking the gate electrode GT is connected to the power line VDD2(BS) on the back surface BS of the semiconductor substrate SUB. The other end flanking the gate electrode GT in the semiconductor layer SEML of the switch transistor SWT2 is connected to the virtual power line VVDD2(BS) on the back surface BS. Note that in Figure 7, the wiring connected to the gate electrode GT is omitted.

[0051] The virtual power line VVDD2(BS) on the back surface BS is connected to the virtual power line VVDD2(Mint) of the Mint layer via the TSV and the virtual power line VVDD2(BPR). If the power switch circuit PSW2 is located within the bit cell region BCA, the virtual power line VVDD2(BPR) and the ground line VSS2(BPR) may extend over the switch transistor PSW2 provided on the back surface BS. Furthermore, multiple ground lines VSS(BPR) in the bit cell region BCA may be connected to each other via the ground line VSS2(BS) and TSV on the back surface BS.

[0052] Figure 8 is a cross-sectional view showing a section along the line Y1-Y1' in Figure 7. The virtual power line VVDD2(BS) on the back surface BS of the semiconductor substrate SUB is connected via VIA(BS) to the semiconductor layer SEML of the switch transistor SWT of the power switch circuit PSW2. The virtual power line VVDD2(BS) is also connected to the virtual power line VVDD2(BPR) of the BPR via TSV.

[0053] Figure 9 is a cross-sectional view showing a section along the line X1-X1' in Figure 7. The switch transistor SWT2 has a semiconductor layer SEML stacked on top of each other, a gate insulating film GINS, and a gate electrode GT, similar to Figure 4A.

[0054] In the semiconductor layer SEML of the switch transistor SWT of the power switch circuit PSW2, one end of the gate electrode GT is connected to the virtual power line VVDD2(BS) on the back surface BS of the semiconductor substrate SUB. In the semiconductor layer SEML, the other end of the gate electrode GT is connected to the power line VDD2(BS) on the back surface BS of the semiconductor substrate SUB.

[0055] Furthermore, the TSV connected to the virtual power line VVDD2(BS) on the back side BS may be connected through to the virtual power line VVDD2(Mint) on the Mint layer. Also, TSVs that are connected through to the BPR wiring and those that are connected through to the Mint layer wiring may be mixed together.

[0056] Figure 10 is a plan view showing a modified example of the power switch circuit PSW2 located in the bit cell region BCA of Figure 7. Elements similar to those in Figure 7 are given the same reference numerals, and detailed explanations are omitted.

[0057] In Figure 10, the semiconductor layer SEML and gate electrode GT of the switch transistor SWT are omitted. Figure 10 is similar in layout to Figure 7, except that the switch transistor SWT of the power switch circuit PSW2 and the power line VDD2(BS) on the back surface BS of the semiconductor substrate SUB are positioned to overlap with the bit cell BC.

[0058] The switch transistor SWT may be positioned in a location that overlaps with the bit cell region BCA, along with the virtual power supply line VVDD2(BS). Furthermore, multiple grounding lines VSS(BPR) of the bit cell region BCA may be connected via TSV to a common grounding line VSS2(BS) on the back surface BS.

[0059] In this embodiment, the power switch circuit PSW (or PSW1, PSW2) can be appropriately positioned using the wiring layer provided on the back surface BS of the semiconductor substrate SUB. For example, the power switch circuit PSW can be positioned in the bit cell area BCA or the isolation area SPA. Alternatively, the power switch circuits PSW1 and PSW2 can be positioned in the peripheral circuit area PCA and the bit cell area BCA, respectively.

[0060] Furthermore, the power switch circuit PSW located on the back side BS can supply power voltage to the virtual power line VVDD of the peripheral circuit area PCA, the decoder area DECA, and the bit cell area BCA. In other words, the power switch circuit PSW located on the back side BS can supply power voltage to the SRAM.

[0061] (Second embodiment) Figure 11 is a plan view showing an example of a power switch circuit PSW2 arranged across the isolation region SPA and the bit cell region BCA in a semiconductor device according to the second embodiment. Elements similar to those in the embodiments described above are denoted by the same reference numerals, and detailed descriptions are omitted. Figure 11 is the same as Figure 7, except that the virtual power line VVDD2 in the bit cell region BCA is provided using a BPR.

[0062] As shown in Figure 10, the power supply line VDD2(BS) of the switch transistor SWT of the power supply switch circuit PSW2 and the back surface BS of the semiconductor substrate SUB may be positioned to overlap with the bit cell BC. Also, when the power supply switch circuit PSW2 is located within the bit cell region BCA, the virtual power supply line VVDD2(BPR) and the ground line VSS2(BPR) may be provided extending over the switch transistor SWT. Furthermore, multiple ground lines VSS(BPR) of the bit cell region BCA may be connected to a common ground line VSS2(BS) on the back surface BS via a TSV.

[0063] Figure 12 is a plan view showing a modified example of the power switch circuit PSW2 of Figure 11. Elements similar to those in Figure 11 are given the same reference numerals, and detailed explanations are omitted. In Figure 12, the power line VDD2(BS) connected to the power switch circuit PSW2 is connected via a TSV to the power line VDD2(BPR) provided on the surface of the semiconductor substrate SUB. The power line VDD2(BPR) is an example of a seventh power line.

[0064] The TSV connecting power line VDD2(BS) to power line VDD2(BPR) is, for example, located in the bit cell region BCA. This prevents the BPR wiring from being located in the isolated region SPA. The pentagon shown at the intersection of power line VDD2(BS) extending in the Y direction and power line VDD2(BS) extending in the X direction is a via VIA(BS) on the back surface BS of the semiconductor substrate SUB that connects different wiring layers.

[0065] Furthermore, either or both of the power line VDD2(BS) and the virtual power line VVDD2(BS) may be arranged in a mesh pattern by wiring provided on multiple wiring layers on the back surface BS. In this case, the wiring on the multiple wiring layers is connected to each other via VIA(BS). In addition, multiple ground lines VSS2(BPR) of the bit cell area BCA may be connected to a common ground line VSS2(BS) on the back surface BS via TSV.

[0066] The layout configuration described in Figure 12 may also be applied to other embodiments described above, and may be applied to the power line VDD1(PSW1) or virtual power line VVDD1(PSW1) provided in the power switch circuit PSW1. When applied to the power switch circuit PSW1, the TSV connecting the power line VDD1(BS) on the back surface BS of the semiconductor substrate SUB and the power line VDD1(BPR) on the front surface is located in the peripheral circuit area PCA.

[0067] As described above, the same effects as those of the embodiments described can be obtained in this embodiment as well. For example, the power switch circuit PSW2 can be appropriately positioned using the wiring layer provided on the back surface BS of the semiconductor substrate SUB. For example, the power switch circuit PSW2 can be positioned in the bit cell area BCA or the isolation area SPA.

[0068] Although the present invention has been described above based on various embodiments, the present invention is not limited to the requirements shown in the above embodiments. These points can be modified as long as they do not impair the spirit of the present invention, and can be appropriately determined according to their application. [Explanation of symbols]

[0069] 100 Semiconductor Equipment BCA Bit Cell Area BL, BLB bit lines BS (Back) CNTL control circuit DECA Decoder Area FIN1-FIN4 fins GINS gate insulating film GT, GT1-GT4 gate INS insulating film LI1-LI8 Local Wiring N1, N2 n-channel transistors P, P1, P2 p-channel transistors PCA peripheral circuit area PSW, PSW1, PSW2 Power Switch Circuit Q, QB memory node SPA isolation area SEML (Semantic Layer) SUB Semiconductor Substrate SWCNT Switch Control Signal SWT Switch Transistor T1, T2 transfer transistors VDD, VDD1, VDD2 power lines VIA, VIA1, VIA2, VIA3 VSS, VSS1, VSS2 ground wire VVDD, VVDD1, VVDD2 virtual power lines WL Word Line

Claims

1. A substrate having a first surface and a second surface facing the first surface, The first power line provided on the first surface, The first grounding wire provided on the first surface, A first region having the first power line and the first ground line, The second power line provided on the first surface, The second grounding wire provided on the first surface, The third power line provided on the second surface, The fourth power line provided on the second surface, The second power line and the third power line are electrically connected, and vias provided on the circuit board are connected to, A second region having the second power line and the second ground line, A third region located between the first region and the second region in a plan view, A first power switch circuit having a first switch transistor electrically connected between the third power line and the fourth power line on the second side of the substrate, Semiconductor device.

2. Having the first wiring connected to the second power line The semiconductor device according to claim 1.

3. The second power line extends in the first direction within the second region. The semiconductor device according to claim 1.

4. The first power switch circuit is provided in the second region in a plan view. The semiconductor device according to any one of claims 1 to 3.

5. The first power switch circuit is provided in the third region in a plan view. The semiconductor device according to any one of claims 1 to 3.

6. A fifth power line provided on the second surface, The sixth power line provided on the second surface, A via provided on the substrate for connecting the fifth power line to the first power line provided on the first surface, The circuit board has a second switch transistor electrically connected between the fifth power line and the sixth power line on the second surface side, and a second power switch circuit provided in the first region in a plan view. The semiconductor device according to any one of claims 1 to 3.

7. The first grounding wire and the second grounding wire extend in a first direction and are spaced apart in a second direction different from the first direction. The spacing between the multiple first grounding wires in the second direction is different from the spacing between the multiple second grounding wires in the second direction. The semiconductor device according to any one of claims 1 to 3.

8. The third grounding wire provided on the second surface, The fourth grounding wire provided on the second surface, A via provided on the substrate, which connects the third ground wire to the first ground wire provided on the first surface, The substrate has vias provided therein, which connect the fourth ground wire to the second ground wire provided on the first surface. The semiconductor device according to any one of claims 1 to 3.

9. The first surface has a seventh power line, The fourth power line is connected to the seventh power line via vias provided on the circuit board. The semiconductor device according to any one of claims 1 to 3.

10. The sixth power line and the fourth power line are electrically connected to each other. The semiconductor device according to claim 6.

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