Semiconductor equipment

Abstract

In the present invention, a first-conductivity-type first impurity region and a second-conductivity-type second impurity region respectively in contact with a second-conductivity-type third impurity region and a first-conductivity-type fourth impurity region of a substrate are formed on the substrate with a space therebetween in a first direction. Wirings extending in a second direction different from the first direction are respectively formed on the fourth impurity region side of the third impurity region and the third impurity region side of the fourth impurity region in the substrate. Because of this, in a situation where multiple diodes are disposed adjacent to each other, an increase in the chip size of the semiconductor device can be suppressed.

Description

Technical Field

[0001] The present invention relates to a semiconductor device.

Background Art

[0002] An ESD protection circuit provided in a semiconductor device to protect an internal circuit of the semiconductor device from Electro-Static Discharge (ESD) is known. For example, a conductor embedded in a trench may be used for a wiring of a diode formed in an ESD protection circuit, or a wiring of a bidirectional diode disposed between mutually different power domains. A buried wiring used for a power supply line or a ground line is referred to as BPR (Buried Power Rail).

Prior Art Literature

Patent Literature

[0003]

Patent Literature 1

Patent Literature 2

Patent Literature 3

Summary of the Invention

Problem to be Solved by the Invention

[0004] In an ESD protection circuit, a bidirectional diode, or the like, when a plurality of diodes are arranged adjacent to each other, the diodes are arranged with a predetermined spacing therebetween in order to prevent a parasitic bipolar transistor formed between adjacent diodes from turning on. When the area of the layout region of the diodes is increased thereby, the chip size of the semiconductor device increases.

[0005] The present invention has been made in view of the above points, and an object thereof is to suppress an increase in the chip size of a semiconductor device when a plurality of diodes are arranged adjacent to each other. [Means for solving the problem]

[0006] In one aspect of the present invention, the semiconductor device includes a substrate and a first impurity region having a first conductivity type formed on the substrate at intervals in a first direction in a plan view and , a conductivity type different from the first conductivity type A second impurity region having a second conductivity type; a third impurity region formed in contact with the first impurity region on the substrate and having the second conductivity type; a fourth impurity region formed in contact with the second impurity region on the substrate and having the first conductivity type; a first wiring formed on the substrate in a plan view on the fourth impurity region side of the third impurity region, along a second direction different from the first direction; and a second wiring formed on the substrate in a plan view on the third impurity region side of the fourth impurity region, along a second direction. A first diode having the first impurity region and the third impurity region, and a second diode having the second impurity region and the fourth impurity region, to have Furthermore, in the first direction, a portion of the substrate is located between the first wiring and the second wiring, and in the first direction, the first diode and the second diode are adjacent to each other. ru. [Effects of the Invention]

[0007] According to the disclosed technology, when multiple diodes are arranged adjacent to each other, it is possible to suppress the increase in chip size of a semiconductor device. [Brief explanation of the drawing]

[0008] [Figure 1] This is a circuit diagram showing an example of the main components of a semiconductor device in the first embodiment. [Figure 2] This is a plan view showing an example of the layout of the region where the diode in Figure 1 is formed. [Figure 3] This is a cross-sectional view along the line X1-X2 in Figure 2. [Figure 4] This is a cross-sectional view along the line Y1-Y2 in Figure 2. [Figure 5] Figure 2 is a cross-sectional view showing an example where the transistor is formed using a FinFET transistor. [Figure 6] Figure 2 is a plan view showing an example of another structure of the diode region. [Figure 7] This is a cross-sectional view along the line X1-X2 in Figure 6. [Figure 8] Figure 2 is a plan view showing another example of a different structure of the diode region. [Figure 9] This is a cross-sectional view along the line X1-X2 in Figure 8. [Figure 10] This is a circuit diagram showing an example of the main components of a semiconductor device in the second embodiment. [Figure 11] Figure 10 is a plan view showing an example of the layout of the bidirectional diode region. [Figure 12] This is a circuit diagram showing an example of the main components of a semiconductor device in the third embodiment. [Figure 13] Figure 12 is a plan view showing an example of the layout of transistors and diodes. [Modes for carrying out the invention]

[0009] Embodiments will be described below with reference to the drawings. In the following, symbols indicating signals are also used to indicate signal lines or signal terminals. Symbols indicating voltage are also used to indicate voltage lines or voltage terminals to which voltage is supplied.

[0010] (First Embodiment) Figure 1 shows an example of the main components of a semiconductor device in the first embodiment. For example, the semiconductor device SEM1 shown in Figure 1 may be a SoC (System on Chip), a standalone CPU (Central Processing Unit), GPU (Graphics Processing Unit), DSP (Digital Signal Processor), FPGA (Field-Programmable Gate Array), or memory, etc. Figure 1 shows an example of an input buffer circuit IBUF that receives a signal SIG in the semiconductor device SEM1.

[0011] The input buffer circuit IBUF comprises an ESD protection circuit PC including diodes D10 and D20, a p-type field effect transistor PFET10, and an n-type field effect transistor NFET10. The p-type is an example of the first conductivity type or the second conductivity type, and the n-type is an example of the second conductivity type or the first conductivity type.

[0012] The diode D10 has an anode connected to the ground line VSS and a cathode connected to the signal line SIG. The diode D20 has an anode connected to the signal line SIG and a cathode connected to the power supply line VDD. The ground line VSS is connected to a ground pad VSSP, and the power supply line VDD is connected to a power supply pad VDDP. The signal line SIG is connected to a signal pad SIGP.

[0013] The field effect transistors PFET10 and NFET10 constitute an inverter that inverts and outputs the logic of the signal SIG. Hereinafter, a p-type field effect transistor PFET is also referred to as a transistor PFET, and an n-type field effect transistor NFET is also referred to as a transistor NFET. Although not particularly limited, for example, the transistors PFET10 and NFET10 are nanosheet transistors.

[0014] The gates of the transistors PFET10 and NFET10 are connected to the signal line SIG and receive the signal SIG supplied to the signal pad SIGP. The drains of the transistors PFET10 and NFET10 are connected to the output node OUT of the input buffer circuit IBUF. The source and back gate of the transistor PFET10 are connected to the power supply line VDD. The source and back gate of the transistor NFET10 are connected to the ground line VSS. The power supply line VDD is an example of a first power supply line or a second power supply line, and the ground line VSS is an example of a second power supply line or a first power supply line.

[0015] Figure 2 shows a plan view of an example layout of the regions where diodes D20 and D10 in Figure 1 are formed. Diodes D20 and D10 are arranged adjacent to each other in the X direction of Figure 2. In the region where diode D20 is formed, transistors PFET (PFET21, PFET22, PFET23) are arranged along the Y direction of Figure 2. In the region where diode D10 is formed, transistors NFET (NFET11, NFET12, NFET13) are arranged along the Y direction of Figure 2. The X direction is an example of a first direction. The Y direction is an example of a second direction that intersects the X direction.

[0016] For example, each transistor PFET and NFET is a nanosheet transistor. Each transistor PFET and NFET has a gate electrode GT extending in the X direction, diffusion regions (p+ (p-type) or n+ (n-type)) located on both sides of the gate electrode GT in the Y direction, and local wiring LI connected to each diffusion region. Hereafter, the region where diode D20 is formed will also be referred to as diode region D20, and the region where diode D10 is formed will also be referred to as diode region D10.

[0017] The diffusion region p+ of transistors PFET22, NFET11, and NFET13 corresponds to the source region and drain region of transistors PFET22, NFET11, and NFET13. The diffusion region n+ of transistors PFET21, PFET23, and NFET12 corresponds to the source region and drain region of transistors PFET21, PFET23, and NFET12.

[0018] In the diode region D20, the diffusion region p+ of the transistor PFET22 is connected to the embedded wiring BPR(SIG) via local wiring LI and via V1. The embedded wiring BPR(SIG) is connected to the signal line SIG. In Figure 2, via V1 is indicated by a dashed rectangle marked with an X. The transistor PFET22 is an example of a first transistor.

[0019] The diffuse regions n+ of transistors PFET21 and PFET23 are connected to the embedded wiring BPR(VDD) via local wiring LI and via V1. The embedded wiring BPR(VDD) is connected to the power line VDD. The diffuse regions n+ of transistors PFET21 and PFET23 are in contact with the n-type well region NW(VDD) on the surface of the p-type semiconductor substrate PSUB(VSS).

[0020] This allows the power supply voltage VDD of the embedded wiring BPR(VDD) to be supplied to the well region NW(VDD) via the diffusion region n+ of transistors PFET21 and PFET23. Then, the diode D20 shown in Figure 1 can be formed by the pn junction between the diffusion region p+ of transistor PFET22 and the well region NW(VDD).

[0021] The embedded wiring BPR(SIG) in diode region D20 is formed on the opposite side of diode region D10 in well region NW(VDD). The embedded wiring BPR(VDD) is formed on the diode region D10 side in well region NW(VDD). In other words, in diode region D20, the embedded wiring BPR(SIG) and BPR(VDD) are formed on both sides in the X direction of transistor PFET21-PFET23. In diode region D20, the embedded wiring BPR(SIG) is an example of a third wiring, and the embedded wiring BPR(VDD) is an example of a first wiring.

[0022] Furthermore, the embedded wiring BPR(SIG) may be formed on the diode region D10 side, and the embedded wiring BPR(VDD) may be formed on the opposite side of the diode region D10. In this case, the via V1 of transistor PFET22 is formed on the diode region D10 side, and the via V1 of transistors PFET21 and PFET23 is formed on the opposite side of the diode region D10. Alternatively, only one of the embedded wiring BPR(VDD) or embedded wiring BPR(SIG) may be formed on the diode region D10 side. In this case, instead of the other of the embedded wiring BPR(VDD) or embedded wiring BPR(SIG), the other power line VDD or signal line SIG is formed on the wiring layer above the transistor PFET and connected to wiring LI.

[0023] In the diode region D10, the diffuse region n+ of transistor NFET12 is connected to the embedded wiring BPR(SIG) via local wiring LI and via V1. The embedded wiring BPR(SIG) is connected to the signal line SIG. Transistor NFET12 is an example of a second transistor.

[0024] The diffusion regions p+ of transistors NFET11 and NFET13 are connected to the embedded wiring BPR(VSS) via local wiring LI and via V1. The embedded wiring BPR(VSS) is connected to the ground wire VSS. The diffusion regions p+ of transistors NFET11 and NFET13 are in contact with the p-type well region PW(VSS) on the surface of the semiconductor substrate PSUB(VSS).

[0025] This allows the ground voltage VSS of the embedded wiring BPR(VSS) to be supplied to the well region PW(VSS) via the diffusion region p+ of transistors NFET11 and NFET13. Then, the diode D10 shown in Figure 1 can be formed by the pn junction between the well region PW(VSS) and the diffusion region n+ of transistor NFET12.

[0026] The embedded wiring BPR(SIG) in diode region D10 is formed on the diode region D20 side in well region PW(VSS). The embedded wiring BPR(VSS) is formed on the opposite side of well region PW(VSS) from diode region D20. That is, in diode region D10, the embedded wiring BPR(SIG) and BPR(VSS) are formed on both sides in the X direction of transistor NFET11-NFET13. In diode region D10, the embedded wiring BPR(SIG) is an example of a second wiring, and the embedded wiring BPR(VSS) is an example of a fourth wiring.

[0027] In addition, in the diode region D10, the embedded wiring BPR(SIG) may be formed on the side opposite to the diode region D20, and the embedded wiring BPR(VSS) may be formed on the side of the diode region D20. In this case, the via V1 of transistor NFET12 is formed on the side opposite to the diode region D20, and the via V1 of transistors NFET11 and NFET13 is formed on the side of the diode region D20. Alternatively, only one of the embedded wiring BPR(VSS) or embedded wiring BPR(SIG) may be formed on the side of the diode region D20. In this case, instead of the other of the embedded wiring BPR(VSS) or embedded wiring BPR(SIG), the other of the ground wire VSS or signal wire SIG is formed in the wiring layer above the transistor NFET and connected to the wiring LI.

[0028] No semiconductor layer, such as a diffusion region or well region, is formed between diode regions D20 and D10; the semiconductor substrate PSUB(VSS) remains as is. Furthermore, the well region NW(VDD) of diode region D20 and the well region PW(VSS) of diode region D10 are separated by their respective embedded wirings BPR(VDD) and BPR(SIG).

[0029] Therefore, the leakage current component between the well regions NW (VDD) and PW (VSS) can be reduced, and the turning on of parasitic bipolar transistors can be suppressed. Alternatively, the formation of parasitic bipolar transistors between diode regions D20 and D10 can be suppressed. As a result, the spacing between diode regions D20 and D10 can be narrowed compared to when embedded wiring BPR (VDD) and BPR (SIG) are not formed, and the chip size of the semiconductor device SEM1 can be reduced.

[0030] Furthermore, diode regions D20 and D10 may be arranged alternately and repeatedly in the X direction. Embedded wiring BPRs are formed on both sides of diode region D20 in the X direction and on both sides of diode region D10 in the X direction. Therefore, even when diode regions D20 and D10 are arranged alternately and repeatedly in the X direction, it is possible to suppress the turning on of parasitic bipolar transistors or the formation of parasitic bipolar transistors themselves between adjacent diode regions D20 and D10. This makes it possible to narrow the spacing between multiple sets of diodes D20 and D10, and further reduce the chip size of the semiconductor device SEM1.

[0031] Furthermore, the diode region D20 may consist of four or more PFET transistors arranged in the Y direction. Similarly, the diode region D10 may consist of four or more NFET transistors arranged in the Y direction. In this case, diffusion regions p+ and n+ are alternately formed in each diode region D20 and D10.

[0032] Figure 3 shows a cross-section along the line X1-X2 in Figure 2. The nanosheet-type transistors PFET22 and NFET12 are formed on the semiconductor substrate PSUB(VSS). A Shallow Trench Isolation (STI) film is also formed on the surface of the semiconductor substrate PSUB(VSS) as an insulating film. The thick solid lines around the embedded wiring BPR(SIG), BPR(VDD), and BPR(VSS) indicate the insulating film. Although not particularly limited, the local wiring LI, embedded wiring BPR, and via V1 are formed using metallic materials such as ruthenium, tungsten, molybdenum, or copper.

[0033] As explained in Figure 2, in the diode region D20, the diffusion region p+ of the transistor PFET22 is connected to the embedded wiring BPR(SIG) via the local wiring LI and via V1. Between the local wiring LI and the embedded wiring BPR(SIG), an insulating film INS1 such as silicon nitride or silicon carbide is formed, except in the area where via V1 is formed. The diode D20 is then formed by the pn junction between the diffusion region p+ of the transistor PFET22 and the well region NW(VDD).

[0034] In the diode region D10, the diffusion region n+ of the transistor NFET12 is connected to the embedded wiring BPR(SIG) formed in the semiconductor substrate PSUB(VSS) via local wiring LI and via V1. An insulating film INS1 is formed between the local wiring LI and the embedded wiring BPR(SIG). The diode D10 is then formed by the pn junction between the p-type well region PW(VSS) and the diffusion region n+ of the transistor NFET12.

[0035] Figure 4 shows a cross-section along the Y1-Y2 line in Figure 2. In the transistor PFET 22, the diffusion regions p+ located on both sides of the gate GT in the Y direction are interconnected via multiple nanosheets NS. The local wiring LI of the transistor PFET 22 is connected to the well region NW (VDD) via the diffusion region p+.

[0036] In each transistor PFET21 and PFET23, the diffusion regions n+ located on both sides of the gate GT in the Y direction are interconnected via multiple nanosheets NS. The local wiring LI of each transistor PFET21 and PFET23 is connected to the well region NW (VDD) via the diffusion regions n+.

[0037] In each transistor PFET21-PFET23, multiple nanosheets NS are formed at intervals in the Z direction, which is the thickness direction of the semiconductor substrate PSUB. An insulating film INS2 is formed between the gate electrode GT and the diffusion region n+, and between the gate electrode GT and the diffusion region p+. As a result, in transistor PFET22, the gate electrode GT and the diffusion region p+ are insulated by the insulating film INS2, and in transistors PFET21 and PFET23, the gate electrode GT and the diffusion region n+ are insulated by the insulating film INS2. In addition, a gate insulating film (not shown) is formed between the gate electrode GT and the nanosheet NS.

[0038] Figure 5 shows an example where the transistors PFET21-PFET23 in Figure 2 are formed using FinFET transistors. In transistors PFET21 and PFET23, a p-type diffusion region p- is formed between the pair of diffusion regions n+ (fins) that form the source and drain regions, instead of the nanosheet NS in Figure 4. In transistor PFET22, an n-type diffusion region n- is formed between the pair of diffusion regions p+ (fins) that form the source and drain regions, instead of the nanosheet NS in Figure 4. In addition, a gate insulating film (not shown) is formed between the gate electrode GT and the fins.

[0039] The sign p- indicates a lower impurity concentration compared to the sign p+. The sign n- indicates a lower impurity concentration compared to the sign n+. Note that when the transistors NFET11-NFET23 in Figure 2 are formed with FinFET transistors, they have the same structure as in Figure 5. In this case, the diffusion regions n+ and p+ in Figure 5 are swapped, and the diffusion regions n- and p- in Figure 5 are swapped.

[0040] Figure 6 shows a plan view of an example of an alternative structure of diode regions D20 and D10 in Figure 2. Figure 6 is similar to the planar structure in Figure 2, except that the signal line SIG, power line VDD, and ground line VSS of diode regions D20 and D10 are connected to wiring formed in the wiring layer above the transistors PFET and NFET, respectively. The via V1 shown in Figure 2 is not formed in Figure 6. Therefore, each embedded wiring BPR is set to a floating state.

[0041] In the diode region D20, local wiring LI connected to the diffusion region p+ of transistor PFET22 is connected to wiring W1(SIG) for signal SIG via via V2. Similarly, local wiring LI connected to the diffusion regions n+ of transistors PFET21 and PFET23 is connected to wiring W1(VDD) for the power supply voltage VDD via via V2. For example, wiring W1(SIG) and wiring W1(VDD) are formed extending in the Y direction.

[0042] In the diode region D10, local wiring LI connected to the diffusion region n+ of transistor NFET12 is connected to wiring W1(SIG) for signal SIG via via V2. Similarly, local wiring LI connected to the diffusion regions p+ of transistors NFET11 and NFET13 is connected to wiring W1(VSS) for ground voltage VSS via via V2. For example, wiring W1(SIG) and wiring W1(VSS) are formed extending in the Y direction.

[0043] Furthermore, the wiring W1(SIG) in diode region D20 and the wiring W1(SIG) in diode region D10 are interconnected via via V3 and wiring W2(SIG) formed above wiring W1(SIG). For example, wiring W2(SIG) is formed extending in the X direction. In Figure 6, vias V2 and V3 are indicated by dashed rectangles marked with an X.

[0044] For example, wirings W1(SIG), W1(VDD), W1(VSS), and W2(SIG) are formed using the same or similar metallic material as the local wiring LI. Note that the formation of wiring W2(SIG), which connects wirings W1(SIG) in diode regions D20 and D10, may be omitted.

[0045] Figure 7 shows a cross-section along the X1-X2 line in Figure 6. Figure 7 is similar to the structure shown in Figure 3, except that the local wiring LI of transistors PFET22 and NFET12 is connected to the upper wiring W1(SIG) and W2(SIG), and the embedded wiring BPR is set to a floating state.

[0046] In the structures shown in Figures 6 and 7, as in the structures shown in Figures 2 to 4, the well regions NW (VDD) and PW (VSS) are separated by embedded wiring BPR. This suppresses the activation of parasitic bipolar transistors between the well regions NW (VDD) and PW (VSS), or the formation of parasitic bipolar transistors between diode regions D20 and D10. As a result, the spacing between diode regions D20 and D10 can be narrowed, and the chip size of the semiconductor device SEM1 can be reduced.

[0047] Figure 8 shows a plan view of yet another example of the structure of diode regions D20 and D10 in Figure 2. Detailed explanations of elements identical or similar to those in Figure 6 are omitted. In Figure 8, in diode region D20, as in Figure 2, the power supply voltage VDD of the diffusion region n+ of transistors PFET21 and PFET23 is supplied from the embedded wiring BPR(VDD) via via V1 and local wiring LI.

[0048] Furthermore, in diode region D10, similar to Figure 2, the ground voltage VSS of the diffusion region p+ of transistors NFET11 and NFET13 is supplied from the embedded wiring BPR(VSS) via via V1 and local wiring LI. Therefore, in Figure 8, the wirings W1(VDD) and W1(VSS) shown in Figure 6 are not formed. The other structures of diode regions D20 and D10 are the same as in Figure 2.

[0049] Figure 9 shows a cross-section along the line X1-X2 in Figure 8. Detailed explanations of elements identical or similar to those in Figure 7 are omitted. Figure 9 is identical or similar to the structure shown in Figure 7, except that it has the embedded wiring BPR(VDD) and BPR(VSS) of Figure 3, and the wiring W1(VDD) and W1(VSS) of Figure 7 are not formed. Note that the embedded wiring BPR(VDD) may be formed on the opposite side from the diode region D10, and the embedded wiring BPR(VSS) may be formed on the diode region D20 side.

[0050] In the structures shown in Figures 8 and 9, similar to the structures shown in Figures 2 to 4 and Figures 6 to 7, it is possible to suppress the activation of parasitic bipolar transistors between the well regions NW (VDD) and PW (VSS). Alternatively, it is possible to suppress the formation of parasitic bipolar transistors between the diode regions D20 and D10. This allows for a reduction in the spacing between the diode regions D20 and D10, thereby reducing the chip size of the semiconductor device SEM1.

[0051] In this embodiment, no semiconductor layer, such as a diffusion region or well region, is formed between the diode regions D20 and D10, which are adjacent to each other, in the ESD protection circuit PC. Furthermore, the well region NW (VDD) of diode region D20 and the well region PW (VSS) of diode region D10 are separated by embedded wiring BPR.

[0052] Therefore, the leakage current component between the well regions NW (VDD) and PW (VSS) can be reduced, and the turning on of parasitic bipolar transistors can be suppressed. Alternatively, the formation of parasitic bipolar transistors between diode regions D20 and D10 can be suppressed. Consequently, the formation of guard rings in diode regions D20 and D10 can be omitted.

[0053] This allows the spacing between diode regions D20 and D10 to be narrowed, thereby reducing the chip size of the semiconductor device SEM1. In other words, when multiple diodes D20 and D10 are arranged adjacent to each other, it is possible to suppress the increase in the area of ​​the layout region of diodes D20 and D10, thereby suppressing an increase in the chip size of the semiconductor device SEM1.

[0054] In Figure 2, by connecting the diffusion regions n+ of transistors PFET21 and PFET23 formed in the Y direction of transistor PFET22 to the embedded wiring BPR(VDD), the power supply voltage VDD can be supplied to the well region NW(VDD) of diode region D20. By connecting the diffusion regions p+ of transistors NFET11 and NFET13 formed in the Y direction of transistor NFET12 to the embedded wiring BPR(VSS), the ground voltage VSS can be supplied to the well region PW(VSS) of diode region D10.

[0055] Even when diode regions D20 and D10 are arranged alternately in the X direction, it is possible to suppress the turning on of parasitic bipolar transistors or the formation of parasitic bipolar transistors themselves between adjacent diode regions D20 and D10. This allows for a narrower spacing between multiple sets of diodes D20 and D10, thereby further reducing the chip size of the semiconductor device SEM1.

[0056] (Second embodiment) Figure 10 shows an example of the main components of a semiconductor device in the second embodiment. Elements identical or similar to those in Figure 1 are denoted by the same reference numerals, and detailed descriptions are omitted. The semiconductor device SEM2 shown in Figure 10 may be an SoC, a standalone CPU, GPU, DSP, FPGA, or memory, etc.

[0057] Figure 10 shows the input buffer circuit IBUF and buffer circuit BUF, which are in different power supply domains, and the bidirectional diode BID, which includes diodes D30 and D40 that interconnect the ground lines VSS1 and VSS2, in the semiconductor device SEM2. Hereafter, the region in which the bidirectional diode BID is formed will also be referred to as the bidirectional diode region BID.

[0058] The input buffer circuit IBUF is formed within power domain PD1, and the buffer circuit BUF is formed within power domain PD2. The input buffer circuit IBUF has the same configuration as in Figure 1, except that it is connected to power line VDD1 and ground line VSS1 instead of power line VDD and ground line VSS. Power line VDD1 is connected to power pad VDD1P, and ground line VSS1 is connected to ground pad VSS1P. Power domain PD1 is an example of a first power domain, and power domain PD2 is an example of a second power domain.

[0059] The buffer circuit BUF has an inverter that includes field-effect transistors PFET11 and NFET11 connected in series between the power line VDD2 and the ground line VSS2. The gates of transistors PFET11 and NFET11 are connected to the input node IN. The drains of transistors PFET11 and NFET11 are connected to the output node OUT2 of the buffer circuit BUF.

[0060] The source and back gate of transistor PFET11 are connected to power line VDD2. The source and back gate of transistor NFET11 are connected to ground line VSS2. Power line VDD2 is connected to power pad VDD2P, and ground line VSS2 is connected to ground pad VSS2.

[0061] In the bidirectional diode BID, diode D30 has its anode connected to the ground wire VSS2 and its cathode connected to the ground wire VSS1. In the bidirectional diode BID, diode D40 has its anode connected to the ground wire VSS1 and its cathode connected to the ground wire VSS2.

[0062] Figure 11 shows a plan view of an example of the layout of the bidirectional diode region (BID) in Figure 10. Elements identical or similar to those in Figure 2 are denoted by the same reference numerals, and detailed explanations are omitted. Hereafter, the region where diode D30 is formed will also be referred to as diode region D30. The region where diode D40 is formed will also be referred to as diode region D40.

[0063] In diode region D40, the embedded wiring BPRs located on both sides in the X direction are connected to the ground lines VSS1 and VSS2, respectively, instead of the signal line SIG and power line VDD in Figure 2. The other configurations and structures of diode D40 are the same as those of diode region D20 in Figure 2.

[0064] In diode region D30, the embedded wiring BPRs located on both sides in the X direction are connected to ground lines VSS1 and VSS2, respectively, instead of the signal line SIG and ground line VSS in Figure 2. The other configurations and structures of diode D30 are the same as those of diode region D10 in Figure 2.

[0065] For example, the transistors PFET21-PFET23 and NFET11-NFET13 are nanosheet transistors, but they may also be formed using FinFET transistors as shown in Figure 5. The diode regions D40 and D30 may be arranged alternately and repeatedly in the X direction. Also, the structure shown in Figure 6 may be applied instead of the structure shown in Figure 11.

[0066] As described above, the same effects as in the first embodiment can be obtained in this embodiment as well. For example, in a bidirectional diode BID, the well region NW (VDD) of diode region D40 and the well region PW (VSS) of diode region D30, which are formed adjacent to each other, are separated by embedded wiring BPR (VSS1) and BPR (VSS2). This makes it possible to suppress the turning on of parasitic bipolar transistors, or to suppress the formation of parasitic bipolar transistors between diode regions D40 and D30. As a result, for example, the spacing between diode regions D40 and D30 formed at the boundaries of multiple power supply domains PD1 and PD2 can be narrowed, and the chip size of the semiconductor device SEM2 can be reduced.

[0067] (Third embodiment) Figure 12 shows an example of the main components of a semiconductor device in the third embodiment. The same reference numerals are used for elements that are the same as or similar to those in Figure 1, and detailed descriptions are omitted. The semiconductor device SEM3 shown in Figure 12 may be an SoC, a standalone CPU, GPU, DSP, FPGA, or memory, etc. Figure 12 shows a fail-safe I / O buffer FSBUF and an ESD clamp circuit CLMP in the semiconductor device SEM3.

[0068] The fail-safe I / O buffer FSBUF includes an output control circuit OUTCNT, an input control circuit INCNT, a p-type field-effect transistor PFET62, an n-type field-effect transistor NFET52, and diodes D50, D60, D10, and D20. Diodes D50 and D60 are parasitic diodes formed along with the transistors PFET62 and NFET52. Diodes D10 and D20 are formed as an ESD protection circuit PC, as shown in Figure 1.

[0069] The fail-safe I / O buffer FSBUF is an I / O buffer that allows input of a signal from the signal pad SIGP when the power supply voltage VDD is not supplied from the power supply pad VDDP. When the power supply voltage VDD is not supplied from the power supply pad VDDP, the power line VDD becomes the ground voltage VSS. In this state, when a voltage is applied to the signal pad SIGP, current is controlled to prevent it from flowing through the power line VDD at the ground voltage VSS from the signal pad SIGP by known methods, preventing current from flowing through diodes D20 and D60, which are shown by dashed lines.

[0070] The output control circuit OUTCNT enters output mode when the output enable signal OEN is at the valid level, outputting a level opposite to the logic level of the internal output signal IOUT to the gates of transistors PFET62 and NFET52. When the output enable signal OEN is at the invalid level, the output control circuit OUTCNT enters output disable mode, outputting a high level to the gate of transistor PFET62 and a low level to the gate of transistor NFET52. In this way, the output control circuit OUTCNT operates as a tristate buffer.

[0071] The input control circuit INCNT enters input mode when the output enable signal OEN is at a high level. While in input mode, when the input selection signal INSEL is at an active level, the input control circuit INCNT outputs the signal SIG received at the signal pad SIGP as the internal input signal IIN. While in input mode, when the input selection signal INSEL is at an inactive level, the input control circuit INCNT fixes the internal input signal IIN at a low level, regardless of the logic level of the signal SIG received at the signal pad SIGP.

[0072] When a positive ESD voltage is applied from the signal pad SIGP with respect to the power supply voltage VDD, parasitic bipolar action by transistor NFET52 causes current to flow from the signal pad SIGP to the power supply line VDD via the ground wire VSS and the clamp circuit CLMP. The clamp circuit CLMP also causes current to flow from the power supply line VDD to the ground wire VSS when a negative ESD voltage is applied from the signal pad SIGP with respect to the power supply voltage VDD. The current flowing into the ground wire VSS then flows back to the signal pad SIGP via diodes D50 and D10.

[0073] This protects the fail-safe IO buffer FSBUF from ESD discharge. Note that when a positive ESD voltage is applied from the signal pad SIGP relative to the ground voltage VSS, the operation is the same as when a positive ESD voltage is applied relative to the power supply voltage VDD. Similarly, when a negative ESD voltage is applied from the signal pad SIGP relative to the ground voltage VSS, the operation is the same as when a negative ESD voltage is applied relative to the power supply voltage VDD.

[0074] Figure 13 shows a plan view of an example layout of the transistors PFET62 and NFET52 and diodes D60 and D50 shown in Figure 12. Elements identical or similar to those in Figure 2 are given the same reference numerals, and detailed explanations are omitted. The cross-sectional structure along the X1-X2 line in Figure 13 is the same as in Figure 3, except for the different location of via V formation. The cross-sectional structure along the Y1-Y2 line in Figure 13 is identical or similar to that in Figure 4. Hereafter, the region where diode D60 is formed will also be referred to as diode region D60, and the region where diode D50 is formed will also be referred to as diode region D50.

[0075] The diode region D60 contains transistors PFET61, PFET62, and PFET63. The diffused regions n+ of transistors PFET61 and PFET63 are connected to the power line VDD via local wiring LI, via V1, and embedded wiring BPR, similar to the diffused regions n+ of transistors PFET21 and PFET23 in Figure 2.

[0076] In transistor PFET62, the diffusion region p+ located on one side of the gate electrode GT in the Y direction is connected to the signal line SIG via local wiring LI, via V1, and embedded wiring BPR(SIG). Furthermore, in transistor PFET62, the diffusion region p+ located on the other side of the gate electrode GT in the Y direction is connected to the power line VDD via local wiring LI, via V1, and embedded wiring BPR(VDD). This allows for the formation of a transistor PFET62 that functions as a circuit. Transistor PFET62 is an example of a first transistor, and the gate electrode of transistor PFET62 is an example of a first gate electrode.

[0077] The diode region D50 contains transistors NFET51, NFET52, and NFET53. The diffusion regions p+ of transistors NFET51 and NFET53 are connected to the ground wire VSS via local wiring LI, via V1, and embedded wiring BPR(VSS), similar to the diffusion regions p+ of transistors NFET11 and NFET13 in Figure 2.

[0078] In transistor NFET52, the diffusion region n+ located on one side of the gate electrode GT in the Y direction is connected to the signal line SIG via local wiring LI, via V1, and embedded wiring BPR(SIG). Furthermore, the diffusion region n+ located on the other side of the gate electrode GT in the transistor NFET52 is connected to the ground line VSS via local wiring LI, via V1, and embedded wiring BPR(VSS). This allows for the formation of a transistor NFET52 that functions as a circuit. Additionally, because transistor NFET52 is connected to the well region PW(VSS) via the diffusion region n+, parasitic bipolar action via the well region PW becomes possible. Transistor NFET52 is an example of a second transistor, and the gate electrode of transistor NFET52 is an example of a second gate electrode.

[0079] Diode D60 is formed by a pn junction between the p-type diffusion region p+ and the n-type well region NW (VDD) of transistor PFET62. Diode D50 is formed by a pn junction between the p-type well region PW (VSS) and the n-type diffusion region n+ of transistor NFET52.

[0080] This forms the circuit shown in Figure 12, consisting of transistors PFET62 and NFET52 and diodes D60 and D50. In other words, diode D60 is formed as a parasitic diode of transistor PFET62, and diode D50 is formed as a parasitic diode of transistor NFET53.

[0081] For example, the transistors PFET61-PFET63 and NFET51-NFET53 are nanosheet transistors, but they may also be formed using FinFET transistors as shown in Figure 5. The diode regions D60 and D50 may be arranged alternately and repeatedly in the X direction. In addition, the structure shown in Figure 6 or Figure 8 may be applied instead of the structure shown in Figure 13.

[0082] Furthermore, if the transistor PFET62 is a nanosheet transistor, the diffusion region p+ and the well region NW(VDD) of the transistor PFET62 may be insulated by an STI film or the like. Also, if the diode D20 in Figure 12 is formed using a nanosheet transistor in the same way as in Figure 2, the diffusion region p+ and the well region NW(VDD) shown in Figure 3 may be insulated by an STI film or the like. As a result, the diodes D60 and D20 shown by dashed lines in Figure 12 will no longer exist, and the control to suppress the through-current described above will become unnecessary.

[0083] As described above, the same effects as in the first embodiment can be obtained in this embodiment as well. For example, in the fail-safe IO buffer FSBUF, it is possible to suppress the formation of parasitic bipolar transistors between the well regions NW(VDD) and PW(VSS) of diode regions D60 and D50 that are formed adjacent to each other.

[0084] This allows the spacing between diode regions D60 and D50 to be narrowed, thereby reducing the chip size of the semiconductor device SEM3. In other words, even when diodes D60 and D50 are formed as parasitic diodes of transistors PFET62 and NFET52, the spacing between diode regions D60 and D50 can be narrowed, thereby reducing the chip size of the semiconductor device SEM3.

[0085] Although the present invention has been described above based on various embodiments, the present invention is not limited to the requirements shown in the above embodiments. These points can be modified as long as they do not impair the spirit of the present invention, and can be appropriately determined according to their application. [Explanation of Symbols]

[0086] BID (Bidirectional Diode) BPR embedded wiring BUF buffer circuit CLMP clamp circuit D10, D20, D30, D40, D50, D60 diodes FSBUF Fail-safe I / O buffer GT Business Window IBUF Input Buffer Circuit IIN Internal Input Signal IN Input Management INCNT Input Control Circuit INS1, INS2 insulating film INSEL input selection signal IOUT Internal Output Signal LI local wiring NFET (Field-Effect Transistor) NS Nanosheet NW(VDD) well area n+, n- diffusion regions OEN output enable signal OUT, OUT2 output nodes OUTCNT Output Control Circuit PC protection circuit PD1, PD2 Power Domain PFET (Field-Effect Transistor) PSUB Semiconductor Substrate PW(VSS) well area p+, p- diffusion region SEM1, SEM2, SEM3 Semiconductor Device SIG signal line SIGP signal pad VDD, VDD1, VDD2 power line VDD1P, VDD2P, VDDP Power Pad V1, V2, V3 Via VSS, VSS1, VSS2 ground wire VSS1P, VSS2P, VSSP Grounding Pads W1, W2 wiring

Claims

1. circuit board and A first impurity region having a first conductivity type and formed on the substrate at intervals in a first direction in a plan view, and a second impurity region having a second conductivity type different from the first conductivity type, A third impurity region is formed in contact with the first impurity region on the substrate and has the second conductivity type, A fourth impurity region is formed in contact with the second impurity region on the substrate and has the first conductivity type, In a plan view, a first wiring is formed on the substrate along a second direction different from the first direction, on the fourth impurity region side of the third impurity region, In a plan view, the second wiring formed on the substrate along the second direction is located on the third impurity region side of the fourth impurity region, A first diode having the first impurity region and the third impurity region, A second diode having the aforementioned second impurity region and the aforementioned fourth impurity region, It has, In the first direction, a portion of the substrate is located between the first wiring and the second wiring. In the first direction, the first diode and the second diode are adjacent to each other. Semiconductor equipment.

2. A fifth impurity region having the second conductivity type is formed on the third impurity region, spaced apart from the first impurity region in the second direction, A sixth impurity region having the first conductivity type is formed on the fourth impurity region, spaced apart from the second impurity region in the second direction, The semiconductor device according to claim 1.

3. In a plan view, the third wiring is formed on the substrate along the second direction on the side opposite to the first wiring side of the third impurity region, In a plan view, the fourth wiring is formed on the substrate along the second direction on the side opposite to the second wiring side of the fourth impurity region. The semiconductor device according to claim 1 or claim 2.

4. A fifth impurity region having the second conductivity type is formed on the third impurity region, spaced apart from the first impurity region in the second direction, A sixth impurity region having the first conductivity type is formed on the fourth impurity region, spaced apart from the second impurity region in the second direction, The first impurity region and the second impurity region are connected to the signal line. The third impurity region and the fifth impurity region are connected to either the first power line or the second power line having a different voltage from the first power line. The fourth impurity region and the sixth impurity region are connected to the other of the first power line or the second power line. The first wiring is connected to either the first power line or the signal line, The third wiring is connected to the other of the first power line or the signal line. The second wiring is connected to either the second power line or the signal line. The fourth wiring is connected to the other of the second power line or the signal line. The semiconductor device according to claim 3.

5. A fifth impurity region having the second conductivity type is formed on the third impurity region, spaced apart from the first impurity region in the second direction, A sixth impurity region having the first conductivity type is formed on the fourth impurity region, spaced apart from the second impurity region in the second direction, The first impurity region and the second impurity region are connected to either the power line of the first power supply domain or the power line of the second power supply domain. The fifth impurity region and the sixth impurity region are connected to the power line of the first power supply domain or the other of the power line of the second power supply domain. The first wiring is connected to either the power line of the first power domain or the power line of the second power domain. The third wiring is connected to the power line of the first power domain or the other of the power line of the second power domain. The second wiring is connected to either the power line of the first power domain or the power line of the second power domain. The fourth wiring is connected to the power line of the first power domain or the other of the power line of the second power domain. The semiconductor device according to claim 3.

6. A first gate electrode positioned on the third impurity region, A second gate electrode positioned on the fourth impurity region, A first transistor having a first gate electrode and first impurity regions arranged on both sides of the first gate electrode in a plan view, A second transistor having the second gate electrode and the second impurity regions arranged on both sides of the second gate electrode in a plan view. The semiconductor device according to claim 1 or claim 2.

7. In a plan view, the third wiring is formed on the substrate along the second direction on the side opposite to the first wiring side of the third impurity region, In a plan view, the fourth wiring is formed on the substrate along the second direction on the side opposite to the second wiring side of the fourth impurity region, One of the first impurity regions located on either side of the first gate electrode is connected to one of the first power lines or signal lines. The other of the first impurity regions located on both sides of the first gate electrode is connected to the other of the first power line or the signal line. One of the second impurity regions located on either side of the second gate electrode is connected to either the second power line or the signal line. The other of the second impurity regions located on both sides of the second gate electrode is connected to the other of the second power line or the signal line. The semiconductor device according to claim 6.

8. The first wiring is connected to either the first power line or the signal line, The third wiring is connected to the other of the first power line or the signal line. The second wiring is connected to either the second power line or the signal line. The fourth wiring is connected to the other of the second power line or the signal line. The semiconductor device according to claim 7.

9. The first and second transistors are nanosheet transistors. The semiconductor device according to claim 6.

10. The first and second transistors are FinFET transistors. The semiconductor device according to claim 6.

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