Quantum bits and quantum computing devices

Abstract

To provide a method for manufacturing quantum bit and a quantum computing device that can achieve good crystallinity in a transition metal ditelluride layer.SOLUTION: A quantum bit includes an s-wave superconductor layer, a Te layer disposed on the s-wave superconductor layer, a high-order topological insulator layer disposed on the Te layer, a first ferromagnetic insulator layer disposed on the high-order topological insulator layer, and a first gate electrode disposed on the first ferromagnetic insulator layer, and the high-order topological insulator layer has a first region having a first hinge helical channel and a second region having a second hinge helical channel spaced from the first hinge helical channel, and the first ferromagnetic insulator layer covers the first hinge helical channel and the second hinge helical channel.SELECTED DRAWING: Figure 7

Description

[Technical Field]

[0001] This disclosure relates to qubits and quantum computing devices. [Background technology]

[0002] Research is being conducted on quantum computing devices using Majorana particles. A structure combining a two-dimensional topological insulator and an s-wave superconductor has been proposed as a structure for generating Majorana particles. As the two-dimensional topological insulator, a monolayer of WTe2, a layered material of transition metal ditellide, is being used. Furthermore, research is also being conducted on higher-order topological insulator layers composed of multilayer WTe2. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] U.S. Patent Application Publication No. 2019 / 0131129 [Patent Document 2] Japanese Patent Publication No. 2018-9201 [Non-patent literature]

[0004] [Non-Patent Document 1] N. Read and D. Green, Phys. Rev. B 61, 10267 (2000) [Non-Patent Document 2] V. Mourik et al., Science 336, 25 (2012) [Non-Patent Document 3] J. Alicea, Rep. Prog. Phys. 75, 076501 (2012) [Non-Patent Document 4] S. Wu et al., Science 359, 76 (2018) [Non-Patent Document 5] Y.-B. Choi et al., Nat. Mater 19, 974 (2020) Summary of the Invention Problem to be Solved by the Invention

[0005] Although proposals based on theory have been made so far, it is not easy to stably obtain a transition metal ditelluride layer such as WTe₂ with good crystallinity.

[0006] An object of the present disclosure is to provide a qubit and a quantum arithmetic device that can obtain good crystallinity in a transition metal ditelluride layer. Means for Solving the Problem

[0007] According to one aspect of the present disclosure, there is provided a qubit comprising: an s-wave superconductor layer; a Te layer provided on the s-wave superconductor layer; a higher-order topological insulator layer provided on the Te layer; a first ferromagnetic insulator layer provided on the higher-order topological insulator layer; and a first gate electrode provided on the first ferromagnetic insulator layer, wherein the higher-order topological insulator layer has a first region including a first hinge helical channel, and a second region including a second hinge helical channel spaced apart from the first hinge helical channel, and the first ferromagnetic insulator layer covers the first hinge helical channel and the second hinge helical channel. Effect of the Invention

[0008] According to the present disclosure, good crystallinity can be obtained in a transition metal ditelluride layer. Brief Description of the Drawings

[0009] [Figure 1] FIG. 1 is a cross-sectional view showing the structure according to the first embodiment. [Figure 2] FIG. 2 is a diagram showing the results of Raman spectroscopy measurement relating to the first embodiment. [Figure 3]Figure 3 is a cross-sectional view showing a structure according to the second embodiment. [Figure 4] Figure 4 shows the results of Raman spectroscopy measurements according to the second embodiment. [Figure 5] Figure 5 is a cross-sectional view showing a structure according to the third embodiment. [Figure 6] Figure 6 shows the results of Raman spectroscopy measurements according to the third embodiment. [Figure 7] Figure 7 is a top view showing a qubit according to the fourth embodiment. [Figure 8] Figure 8 is a cross-sectional view (part 1) showing a qubit according to the fourth embodiment. [Figure 9] Figure 9 is a cross-sectional view (part 2) showing a qubit according to the fourth embodiment. [Figure 10] Figure 10 is a perspective view showing a higher-order topological insulator layer. [Figure 11] Figure 11 is a top view (part 1) showing a method for manufacturing a qubit according to the fourth embodiment. [Figure 12] Figure 12 is a top view (part 2) showing a method for manufacturing a qubit according to the fourth embodiment. [Figure 13] Figure 13 is a top view (part 3) showing a method for manufacturing a qubit according to the fourth embodiment. [Figure 14] Figure 14 is a top view (part 4) showing a method for manufacturing a qubit according to the fourth embodiment. [Figure 15] Figure 15 is a top view (part 5) showing a method for manufacturing a qubit according to the fourth embodiment. [Figure 16] Figure 16 is a top view (part 6) showing a method for manufacturing a qubit according to the fourth embodiment. [Figure 17] Figure 17 is a cross-sectional view (part 1) showing a method for manufacturing a qubit according to the fourth embodiment. [Figure 18] Figure 18 is a cross-sectional view (part 2) showing a method for manufacturing a qubit according to the fourth embodiment. [Figure 19]Figure 19 is a cross-sectional view (part 3) showing a method for manufacturing a qubit according to the fourth embodiment. [Figure 20] Figure 20 is a cross-sectional view (part 4) showing a method for manufacturing a qubit according to the fourth embodiment. [Figure 21] Figure 21 is a cross-sectional view (part 5) showing a method for manufacturing a qubit according to the fourth embodiment. [Figure 22] Figure 22 is a cross-sectional view (part 6) showing a method for manufacturing a qubit according to the fourth embodiment. [Figure 23] Figure 23 shows a quantum computing device according to the fifth embodiment. [Modes for carrying out the invention]

[0010] Embodiments of this disclosure will be described in detail below with reference to the attached drawings. In this specification and drawings, components having substantially the same functional configuration will be denoted by the same reference numerals to avoid redundant explanations. In this disclosure, the X1-X2 direction, Y1-Y2 direction, and Z1-Z2 direction are mutually orthogonal directions. A plane including the X1-X2 direction and the Y1-Y2 direction is described as the XY plane, a plane including the Y1-Y2 direction and the Z1-Z2 direction is described as the YZ plane, and a plane including the Z1-Z2 direction and the X1-X2 direction is described as the ZX plane. For convenience, the Z1-Z2 direction is considered the up and down direction, with the Z1 side being the upper side and the Z2 side being the lower side. Furthermore, a plan view means viewing the object from the Z1 side, and a planar shape means the shape of the object as viewed from the Z1 side.

[0011] (First Embodiment) First, the first embodiment will be described. The first embodiment relates to a structure. Figure 1 is a cross-sectional view showing the structure according to the first embodiment.

[0012] The structure 100 according to the first embodiment includes a substrate 110, a first layer 120, and a second layer 130. The first layer 120 is formed on the substrate 110. The second layer 130 is formed on the first layer 120.

[0013] The substrate 110 is, for example, a single crystal substrate with a surface Miller index of (100). The material of the substrate 110 is, for example, MgO. In the first embodiment, the substrate 110 is an example of a base material.

[0014] The first layer 120 is a Te layer that does not contain W. The thickness of the first layer 120 is, for example, 1 nm to 20 nm.

[0015] The second layer 130 is, for example, multilayer WTe2. For example, multilayer WTe2 has 5 to 100 layers, preferably 10 to 50 layers, of WTe2, which is a two-dimensional material. Since the thickness of a single layer of WTe2 is 0.7 nm, if the second layer 130 contains 70 layers of WTe2, the thickness of the second layer 130 is approximately 50 nm.

[0016] Next, a method for manufacturing the structure 100 according to the first embodiment will be described. Here, a single crystal substrate of MgO with a Miller index of (100) is used as the substrate 110, a Te layer is formed as the first layer 120, and a multilayer WTe2 is formed as the second layer 130.

[0017] First, the substrate 110 is prepared and annealed at approximately 1200°C for 3 to 4 hours under an oxygen atmosphere at atmospheric pressure. Next, the substrate 110 is immersed in methanol for 20 to 30 minutes and then rinsed with ultrapure water. These processes improve the flatness of the substrate 110 surface.

[0018] Next, a first layer 120 is formed on the substrate 110, and a second layer 130 is formed on the first layer 120. The first layer 120 and the second layer 130 can be epitaxially grown in situ in the same vacuum chamber, for example, by pulse laser deposition (PLD). The basic vacuum level during the formation of the first layer 120 and the second layer 130 is, for example, 5 × 10⁻⁶. -6The pressure should be Pa or less. When forming the first layer 120 and the second layer 130 by the PLD method, a KrF excimer laser (λ=248nm) light source can be used as the laser light source. Note that the method of forming the first layer 120 and the second layer 130 is not limited to the PLD method. For example, the first layer 120 and the second layer 130 may be formed by sputtering, or the first layer 120 may be formed by evaporation and the second layer 130 by co-evaporation. In this way, the first layer 120 and the second layer 130 can be formed by physical evaporation in a vacuum-integrated process.

[0019] For example, when forming the first layer 120, a Te pure metal target can be used as the target. When forming the first layer 120, for example, the temperature of the substrate 110 is maintained at approximately 200°C, and the laser energy density is 1.0 J / cm². 2 The irradiation frequency is set to 1 Hz, the distance between the substrate 110 and the target is approximately 5 cm, and the film deposition rate is 1.0 nm / min.

[0020] When forming a multilayer WDe2 as the second layer 130 by the PLD method, for example, a WDe2 sintered target can be used as the target. When forming the second layer 130, for example, the temperature of the substrate 110 is maintained at 325°C and the laser energy density is 1.0 J / cm². 2 The irradiation frequency is set to 10 Hz, the distance between the substrate 110 and the target is approximately 5 cm, and the film deposition rate is 1.0 nm / min. The second layer 130 (multilayer WTe2) is oriented in the c-axis direction on the first layer 120, and the crystal structure of the second layer 130 is T d Show the structure.

[0021] In this way, the structure 100 according to the first embodiment can be manufactured.

[0022] In structure 100, a first layer 120 is formed between the substrate 110 and the second layer 130. The lattice mismatch between MgO with a Miller index of (100) and WTe2 on the surface is 33%, but the first layer 120 functions as a seed layer when forming the second layer 130. As a result, good crystallinity can be obtained in the second layer 130.

[0023] It is preferable to perform post-annealing at about 300° C. for 30 minutes to 1 hour after forming the multilayer WTe₂ film. This is to improve the crystallinity of the multilayer WTe₂.

[0024] Next, the results of Raman spectroscopy measurement related to the first embodiment performed by the present inventor will be described. In this measurement, a sample was prepared in accordance with the first embodiment, and Raman spectroscopy measurement was performed on this sample. The thickness of the first layer 120 was set to 10 nm, and the thickness of the second layer 130 was set to 50 nm. For reference, a sample in which the second layer 130 was formed on the substrate 110 without forming the first layer 120 (first reference example) and a sample including only the substrate 110 (second reference example) were prepared, and Raman spectroscopy measurement was also performed on these samples. FIG. 2 is a diagram showing the results of the Raman spectroscopy measurement related to the first embodiment.

[0025] As shown in FIG. 2, in the sample of the first embodiment, lattice vibration modes derived from WTe₂ (A1 2 , A1 5 , A1 8 , A1 9 , A2 4 ) sharp peaks can be confirmed, whereas in the sample of the first reference example, only broad peaks of the A1 2 mode and the A1 5 mode are observed. From these results, it can be confirmed that the crystallinity of the second layer 130 is improved by providing the first layer 120.

[0026] Note that the material of the substrate 110 may be mica, sapphire, SiC, or the like.

[0027] (Second Embodiment) Next, the second embodiment will be described. The second embodiment differs from the first embodiment mainly in the configuration of the substrate. FIG. 3 is a cross-sectional view showing a structure according to the second embodiment.

[0028] The structure 200 according to the second embodiment includes a substrate 210, a first layer 120, and a second layer 130. The first layer 120 is formed on the substrate 210. The second layer 130 is formed on the first layer 120.

[0029] The substrate 210 has a Si substrate 211 and an SiO2 film 212 formed on the Si substrate 211. The SiO2 film 212 is formed, for example, by thermal oxidation of the Si substrate 211. That is, the substrate 210 is a Si substrate with a thermally oxidized film. The first layer 120 is provided on the SiO2 film 212. In the second embodiment, the substrate 210 is an example of a base material.

[0030] The other configurations are the same as in the first embodiment.

[0031] Next, a method for manufacturing the structure 200 according to the second embodiment will be described.

[0032] First, the substrate 210 is prepared and annealed at approximately 800°C for 15 minutes under an oxygen atmosphere at atmospheric pressure. This annealing process removes organic deposits from the surface of the SiO2 film 212.

[0033] Next, a first layer 120 is formed on the substrate 210, and a second layer 130 is formed on the first layer 120. The first layer 120 and the second layer 130 can be formed in the same manner as in the first embodiment.

[0034] In this way, the structure 200 according to the second embodiment can be manufactured.

[0035] In the structure 200, the first layer 120 is formed between the substrate 210 and the second layer 130. The SiO2 film 212 present on the surface of the substrate 210 is amorphous, but the first layer 120 functions as a seed layer when forming the second layer 130. Therefore, good crystallinity can be obtained in the second layer 130.

[0036] Next, the results of Raman spectroscopy measurements performed by the inventors regarding the second embodiment will be described. In this measurement, a sample was prepared following the second embodiment, and Raman spectroscopy measurements were performed on this sample. The thickness of the first layer 120 was set to 10 nm, and the thickness of the second layer 130 was set to 50 nm. For reference, a sample in which the second layer 130 was formed on the substrate 210 without forming the first layer 120 (third reference example), and a sample consisting only of the substrate 210 (fourth reference example) were also prepared, and Raman spectroscopy measurements were performed on these samples as well. Figure 4 shows the results of Raman spectroscopy measurements regarding the second embodiment.

[0037] As shown in Figure 4, in the sample of the second embodiment, the lattice vibration mode (A1) originates from WTe2. 2 A1 5 A1 8 A1 9 A2 4 A sharp peak can be observed in the third reference example sample, whereas in the third reference example sample, A1 2 Mode and A1 5 Only broad peaks in the modes are observed. These results confirm that the crystallinity of the second layer 130 is improved by the addition of the first layer 120.

[0038] (Third embodiment) Next, a third embodiment will be described. The third embodiment differs from the first embodiment mainly in that it includes an s-wave superconducting layer. Figure 5 is a cross-sectional view showing the structure according to the third embodiment.

[0039] The structure 300 according to the third embodiment includes a substrate 110, an s-wave superconductor layer 340, a first layer 120, and a second layer 130. The s-wave superconductor layer 340 is formed on the substrate 110. The first layer 120 is formed on the s-wave superconductor layer 340. The second layer 130 is formed on the first layer 120.

[0040] The s-wave superconductor layer 340 is, for example, an Nb layer with a surface Miller index of (110). The thickness of the s-wave superconductor layer 340 is, for example, about 100 nm to 200 nm. In the third embodiment, the laminate 310 of the substrate 110 and the s-wave superconductor layer 340 is an example of a substrate.

[0041] The other configurations are the same as in the first embodiment.

[0042] Next, a method for manufacturing the structure 300 according to the third embodiment will be described.

[0043] First, the substrate 110 is prepared, and annealing and rinsing treatments are performed in the same manner as in the first embodiment.

[0044] Next, an s-wave superconductor layer 340 is formed on the substrate 110, a first layer 120 is formed on the s-wave superconductor layer 340, and a second layer 130 is formed on the first layer 120. Hereafter, the explanation will assume that an Nb layer is formed as the s-wave superconductor layer 340. The s-wave superconductor layer 340, the first layer 120, and the second layer 130 can be epitaxially grown in situ within the same vacuum chamber, for example, by the PLD method. The basic vacuum level during the formation of the s-wave superconductor layer 340, the first layer 120, and the second layer 130 is, for example, 5 × 10⁻⁶. -6 The pressure should be Pa or less. When forming the s-wave superconductor layer 340, the first layer 120, and the second layer 130 by the PLD method, a KrF excimer laser (λ=248nm) light source can be used as the laser light source. Note that the method for forming the s-wave superconductor layer 340, the first layer 120, and the second layer 130 is not limited to the PLD method. For example, the s-wave superconductor layer 340, the first layer 120, and the second layer 130 may be formed by sputtering, or the s-wave superconductor layer 340 and the first layer 120 may be formed by evaporation and the second layer 130 may be formed by co-evaporation.

[0045] When forming an Nb layer as an s-wave superconductor layer 340 using the PLD method, for example, a pure Nb metal target can be used. When forming the s-wave superconductor layer 340, for example, the temperature of the substrate 110 is maintained at approximately 400°C, and the laser energy density is 2.0 J / cm².2 The irradiation frequency is set to 10 Hz, the distance between the substrate 110 and the target is approximately 5 cm, and the deposition rate is 1.0 nm / min. On the substrate 110, which is maintained at approximately 400°C, the Nb layer is epitaxially grown while oriented in the

[0110] direction.

[0046] Next, a first layer 120 is formed on the s-wave superconductor layer 340, and a second layer 130 is formed on the first layer 120. The first layer 120 and the second layer 130 can be formed in the same manner as in the first embodiment. The s-wave superconductor layer 340, the first layer 120, and the second layer 130 can be formed by physical vapor deposition in a vacuum-integrated process.

[0047] In this way, the structure 300 according to the third embodiment can be manufactured.

[0048] In structure 300, the first layer 120 is formed between the s-wave superconductor layer 340 and the second layer 130. The lattice mismatch between Nb with a Miller index of (110) and WTe2 on the surface is 25%, but the first layer 120 functions as a seed layer when forming the second layer 130. As a result, good crystallinity can be obtained in the second layer 130.

[0049] Next, the results of Raman spectroscopy measurements performed by the inventors regarding the third embodiment will be described. In this measurement, a sample was prepared following the third embodiment, and Raman spectroscopy measurements were performed on this sample. The thickness of the s-wave superconductor layer 340 was set to 150 nm, the thickness of the first layer 120 was set to 5 nm, and the thickness of the second layer 130 was set to 20 nm. For reference, a sample in which the second layer 130 was formed on the s-wave superconductor layer 340 without forming the first layer 120 (fifth reference example), and a sample in which only the s-wave superconductor layer 340 was formed on the substrate 110 (sixth reference example) were also prepared, and Raman spectroscopy measurements were performed on these samples as well. Figure 6 shows the results of the Raman spectroscopy measurements regarding the third embodiment.

[0050] As shown in Figure 6, in the sample of the third embodiment, the lattice vibration mode (A1) originates from WTe2. 2 A1 5 A18 A1 9 A2 4 A sharp peak can be observed in the ) sample, whereas in the 5th reference example sample, A1 2 Mode and A1 5 Only broad peaks in the modes are observed. These results confirm that the crystallinity of the second layer 130 is improved by the addition of the first layer 120.

[0051] In this disclosure, the material of the layered transition metal ditellide layer included in the second layer is not limited to WTe2. The transition metal ditellide layer may include Mo, Nb, W, Ta, Ti, Zr, Fe, Pd, Ir, or Pt, or any combination thereof, as the transition metal. The layered transition metal ditellide layer included in the second layer may also be a single layer.

[0052] In this disclosure, the thickness of the first layer is preferably 1 nm to 20 nm. If the thickness of the first layer is less than 1 nm, it may be difficult to obtain good crystallinity in the second layer. Also, if the thickness of the first layer is greater than 20 nm, the electrical properties of the first layer may change. Furthermore, as in the third embodiment, when the first layer is provided between the s-wave superconductor layer and the second layer, if the thickness of the first layer is excessive, the proximity effect of superconductivity may decrease. The thickness of the first layer is more preferably 2 nm to 15 nm, and even more preferably 3 nm to 10 nm.

[0053] (Fourth Embodiment) Next, a fourth embodiment will be described. The fourth embodiment relates to a qubit. The qubit according to the fourth embodiment is used in a quantum computing device such as a quantum computer. Figure 7 is a top view showing the qubit according to the fourth embodiment. Figures 8 and 9 are cross-sectional views showing the qubit according to the fourth embodiment. Figure 8 corresponds to a cross-sectional view along the line VIII-VIII in Figure 7. Figure 9 corresponds to a cross-sectional view along the line IX-IX in Figure 7.

[0054] The qubit 1 according to the fourth embodiment includes a substrate 90, an s-wave superconductor layer 10, a Te layer 70, a higher-order topological insulator layer 20, a first ferromagnetic insulator layer 31, a second ferromagnetic insulator layer 32, and a third ferromagnetic insulator layer 33. The qubit 1 further includes a first gate electrode 41, a second gate electrode 42, a third gate electrode 43, a first superconducting quantum interference device (SQUID) 61, a second SQUID 62, and a third SQUID 63.

[0055] The substrate 90 is, for example, a single-crystal substrate with a surface Miller index of (100). Examples of materials for the substrate 90 include MgO, mica, sapphire, and SiC. The substrate 90 may also be a Si substrate with a thermal oxide film.

[0056] The s-wave superconductor layer 10 is provided on a part of the surface of the substrate 90. The s-wave superconductor layer 10 is, for example, an Nb layer with a Miller index of (110) on its surface. The thickness of the s-wave superconductor layer 10 is, for example, about 100 nm to 200 nm. The planar shape of the s-wave superconductor layer 10 is a rectangle with two sides parallel to the X1-X2 direction and two sides parallel to the Y1-Y2 direction.

[0057] The Te layer 70 is provided on the s-wave superconductor layer 10. The thickness of the Te layer 70 is preferably 1 nm to 20 nm, more preferably 2 nm to 15 nm, and even more preferably 3 nm to 10 nm. The thickness of the Te layer 70 is, for example, 5 nm.

[0058] The higher-order topological insulator layer 20 is provided on the Te layer 70. The higher-order topological insulator layer 20 is, for example, a multilayer WTe2. For example, the multilayer WTe2 has 5 to 100 layers, preferably 10 to 50 layers, of a two-dimensional material called WTe2. The thickness of the higher-order topological insulator layer 20 is, for example, 20 nm.

[0059] Figure 10 is a perspective view showing the higher-order topological insulator layer 20. The shape of the higher-order topological insulator layer 20 is approximately a rectangular parallelepiped. The a-axis direction of the higher-order topological insulator layer 20 is parallel to the Y1-Y2 direction, the b-axis direction is parallel to the X1-X2 direction, and the c-axis direction is parallel to the Z1-Z2 direction. The Miller index of the top surface of the higher-order topological insulator layer 20 is (001), the Miller index of the Y2 side surface is (100), and the Miller index of the X2 side surface is (010).

[0060] A T-shaped groove 50 is formed on the surface of the higher-order topological insulator layer 20 in a plan view. The groove 50 has a first groove 51, a second groove 52, and a third groove 53. For example, the width of the first groove 51, the second groove 52, and the third groove 53 is 20 nm, and the depth is 10 nm. The first groove 51 and the third groove 53 extend parallel to the X1-X2 direction, and the second groove 52 extends parallel to the Y1-Y2 direction. The first groove 51 is located near the center of the higher-order topological insulator layer 20 in the Y1-Y2 direction and extends from the X2 side end of the higher-order topological insulator layer 20 to the center in the X1-X2 direction. The third groove 53 is located near the center of the higher-order topological insulator layer 20 in the Y1-Y2 direction and extends from the X1 side end of the higher-order topological insulator layer 20 to the center in the X1-X2 direction. Therefore, the first groove 51 and the third groove 53 are formed in a straight line. The second groove 52 is provided near the center of the higher-order topological insulator layer 20 in the X1-X2 direction and extends from the Y1 side end of the higher-order topological insulator layer 20 to the center in the Y1-Y2 direction. Therefore, the second groove 52 is perpendicular to the first groove 51 and the third groove 53.

[0061] The higher-order topological insulator layer 20 has a first region 21 on the Y2 side of the first groove 51 and the third groove 53. The higher-order topological insulator layer 20 has a second region 22 on the Y1 side of the first groove 51 and on the X2 side of the second groove 52. The higher-order topological insulator layer 20 has a third region 23 on the Y1 side of the third groove 53 and on the X1 side of the second groove 52.

[0062] The first region 21, the second region 22, and the third region 23 each have a hinge helical channel on one of two intersection lines between a plane perpendicular to the a-axis and a plane perpendicular to the c-axis. The hinge helical channel is parallel to the b-axis. Specifically, the first region 21 has a first hinge helical channel 11 at the intersection line (edge) between the top surface and the side surface on the Y1 side. The second region 22 has a second hinge helical channel 12 at the intersection line between the side surface on the Y2 side and the bottom surface of the first groove 51. The third region 23 has a third hinge helical channel 13 at the intersection line between the side surface on the Y2 side and the bottom surface of the third groove 53. The first hinge helical channel 11 may be located at the intersection of the Y1-side surface of the first region 21 and the bottom surface of the groove 50, the second hinge helical channel 12 may be located at the intersection of the top surface of the second region 22 and the Y2-side surface, and the third hinge helical channel 13 may be located at the intersection of the top surface of the third region 23 and the Y2-side surface.

[0063] The first ferromagnetic insulator layer 31 is provided on the first region 21, the second region 22, and a portion of the groove 50, and covers a portion of the first hinge helical channel 11 and the second hinge helical channel 12. The second ferromagnetic insulator layer 32 is provided on the second region 22, the third region 23, and a portion of the groove 50, and covers a portion of the second hinge helical channel 12 and the third hinge helical channel 13. The third ferromagnetic insulator layer 33 is provided on the third region 23, the first region 21, and a portion of the groove 50, and covers a portion of the third hinge helical channel 13 and the first hinge helical channel 11. Examples of materials for the first ferromagnetic insulator layer 31, the second ferromagnetic insulator layer 32, and the third ferromagnetic insulator layer 33 include Cr2Ga2Te6. The materials for the first ferromagnetic insulator layer 31, the second ferromagnetic insulator layer 32, and the third ferromagnetic insulator layer 33 may be other dilution magnetic semiconductors. The thicknesses of the first ferromagnetic insulator layer 31, the second ferromagnetic insulator layer 32, and the third ferromagnetic insulator layer 33 are, for example, about 30 nm.

[0064] The second ferromagnetic insulator layer 32 is located on the second hinge helical channel 12, away from the first ferromagnetic insulator layer 31 towards the X1 side in the X1-X2 direction. The third ferromagnetic insulator layer 33 is located on the third hinge helical channel 13, away from the second ferromagnetic insulator layer 32 towards the X1 side in the X1-X2 direction. The third ferromagnetic insulator layer 33 is located on the first hinge helical channel 11, away from the first ferromagnetic insulator layer 31 towards the X1 side in the X1-X2 direction.

[0065] The first gate electrode 41 is provided on the first ferromagnetic insulator layer 31. The second gate electrode 42 is provided on the second ferromagnetic insulator layer 32. The third gate electrode 43 is provided on the third ferromagnetic insulator layer 33. Au is an example of a material for the first gate electrode 41, the second gate electrode 42, and the third gate electrode 43. The thickness of the first gate electrode 41, the second gate electrode 42, and the third gate electrode 43 is, for example, about 100 nm.

[0066] The first SQUID 61 has a lower superconductor layer 61A, a lower superconductor layer 61B, a tunnel barrier layer 61C, and an upper superconductor layer 61D.

[0067] The lower superconductor layers 61A and 61B protrude from the X2-side of the s-wave superconductor layer 10 towards the X2 direction. The lower superconductor layer 61A is located on the Y2 side of the lower superconductor layer 61B. In a plan view, the lower superconductor layer 61A protrudes from the first region 21 towards the X2 direction, and the lower superconductor layer 61B protrudes from the second region 22 towards the X2 direction. The lower superconductor layers 61A and 61B are formed integrally with the s-wave superconductor layer 10 from the same material. The lower superconductor layers 61A and 61B are connected to the s-wave superconductor layer 10. The lower superconductor layers 61A and 61B are, for example, Nb layers with a thickness of about 100 nm to 200 nm.

[0068] The tunnel barrier layer 61C and the upper superconductor layer 61D have a U-shaped planar shape. The material of the tunnel barrier layer 61C is NbO xExamples include Nb as the material for the upper superconductor layer 61D. The thickness of the tunnel barrier layer 61C is, for example, about 1 nm to 5 nm, and the thickness of the upper superconductor layer 61D is, for example, about 100 nm to 200 nm. One end of the tunnel barrier layer 61C is in contact with the lower superconductor layer 61A, and the other end is in contact with the lower superconductor layer 61B. The upper superconductor layer 61D is provided on top of the tunnel barrier layer 61C.

[0069] Tunnel barrier layers 61C are sandwiched between the lower superconductor layer 61A and the upper superconductor layer 61D, and between the lower superconductor layer 61B and the upper superconductor layer 61D. The first SQUID 61 is constructed using such Josephson junctions. The first SQUID 61 detects changes in magnetic flux between the first hinge helical channel 11 and the second hinge helical channel 12.

[0070] The second SQUID62 has a lower superconductor layer 62A, a lower superconductor layer 62B, a tunnel barrier layer 62C, and an upper superconductor layer 62D.

[0071] The lower superconductor layers 62A and 62B protrude from the Y1 side of the s-wave superconductor layer 10 toward the Y1 direction. The lower superconductor layer 62A is located on the X2 side of the lower superconductor layer 62B. In a plan view, the lower superconductor layer 62A protrudes toward the Y1 direction from the second region 22, and the lower superconductor layer 62B protrudes toward the Y1 direction from the third region 23. The lower superconductor layers 62A and 62B are formed integrally with the s-wave superconductor layer 10 from the same material as the s-wave superconductor layer 10. The lower superconductor layers 62A and 62B are connected to the s-wave superconductor layer 10. The lower superconductor layers 62A and 62B are, for example, Nb layers with a thickness of about 100 nm to 200 nm.

[0072] The tunnel barrier layer 62C and the upper superconductor layer 62D have a U-shaped planar shape. The material of the tunnel barrier layer 62C is NbO xExamples include Nb as the material for the upper superconductor layer 62D. The thickness of the tunnel barrier layer 62C is, for example, about 1 nm to 5 nm, and the thickness of the upper superconductor layer 62D is, for example, about 100 nm to 200 nm. One end of the tunnel barrier layer 62C is in contact with the lower superconductor layer 62A, and the other end is in contact with the lower superconductor layer 62B. The upper superconductor layer 62D is provided on top of the tunnel barrier layer 62C.

[0073] Tunnel barrier layers 62C are sandwiched between the lower superconductor layer 62A and the upper superconductor layer 62D, and between the lower superconductor layer 62B and the upper superconductor layer 62D. The second SQUID 62 is constructed using such Josephson junctions. The second SQUID 62 detects changes in magnetic flux between the second hinge helical channel 12 and the third hinge helical channel 13.

[0074] The third SQUID 63 has a lower superconductor layer 63A, a lower superconductor layer 63B, a tunnel barrier layer 63C, and an upper superconductor layer 63D.

[0075] The lower superconductor layers 63A and 63B protrude from the X1-side of the s-wave superconductor layer 10 toward the X1 direction. The lower superconductor layer 63A is located on the Y1 side of the lower superconductor layer 63B. In a plan view, the lower superconductor layer 63A protrudes toward the X1 direction from the third region 23, and the lower superconductor layer 63B protrudes toward the X1 direction from the first region 21. The lower superconductor layers 63A and 63B are formed integrally with the s-wave superconductor layer 10 from the same material as the s-wave superconductor layer 10. The lower superconductor layers 63A and 63B are connected to the s-wave superconductor layer 10. The lower superconductor layers 63A and 63B are, for example, Nb layers with a thickness of about 100 nm to 200 nm.

[0076] The tunnel barrier layer 63C and the upper superconductor layer 63D have a U-shaped planar shape. The material of the tunnel barrier layer 63C is NbO xExamples include Nb as the material for the upper superconductor layer 63D. The thickness of the tunnel barrier layer 63C is, for example, about 1 nm to 5 nm, and the thickness of the upper superconductor layer 63D is, for example, about 100 nm to 200 nm. One end of the tunnel barrier layer 63C is in contact with the lower superconductor layer 63A, and the other end is in contact with the lower superconductor layer 63B. The upper superconductor layer 63D is provided on top of the tunnel barrier layer 63C.

[0077] Tunnel barrier layers 63C are sandwiched between the lower superconductor layer 63A and the upper superconductor layer 63D, and between the lower superconductor layer 63B and the upper superconductor layer 63D. The third SQUID 63 is constructed using such Josephson junctions. The third SQUID 63 detects changes in magnetic flux between the third hinge helical channel 13 and the first hinge helical channel 11.

[0078] In the qubit 1 configured in this way, four Majorana particles γ1, γ2, γ3, and γ4 are expressed. For example, Majorana particle γ1 is stably expressed near the first gate electrode 41 of the first hinged helical channel 11, and Majorana particle γ4 is stably expressed near the third gate electrode 43 of the first hinged helical channel 11. Also, for example, Majorana particle γ2 is stably expressed between the first gate electrode 41 and the second gate electrode 42 of the second hinged helical channel 12, and Majorana particle γ3 is stably expressed between the second gate electrode 42 and the third gate electrode 43 of the third hinged helical channel 13. The exchange of Majorana particles γ1 to γ4 is carried out by the change in electrostatic potential due to the application of gate voltages to the first gate electrode 41, the second gate electrode 42, and the third gate electrode 43.

[0079] For example, during the exchange of Majorana particle γ1 and Majorana particle γ2, an electric field is applied from the first gate electrode 41, and the minute change in magnetic flux during the exchange of Majorana particles γ1 and γ2 is detected as a minute change in voltage signal by the first SQUID 61. During the exchange of Majorana particle γ2 and Majorana particle γ3, an electric field is applied from the second gate electrode 42, and the minute change in magnetic flux during the exchange of Majorana particles γ2 and γ3 is detected as a minute change in voltage signal by the second SQUID 62. Furthermore, during the exchange of Majorana particle γ3 and Majorana particle γ4, an electric field is applied from the third gate electrode 43, and the minute change in magnetic flux during the exchange of Majorana particles γ3 and γ4 is detected as a minute change in voltage signal by the third SQUID 63.

[0080] Monolayer films of WTe2, a layered material of transition metal dichalcogenide, are easily oxidized, and their properties change when exposed to the atmosphere. While it is possible to suppress oxidation by sandwiching the WTe2 monolayer film with chemically stable materials such as hexagonal boron nitride (h-BN) or graphene, this complicates the qubit manufacturing process. Furthermore, adjusting the size of the WTe2 monolayer film is difficult. In contrast, in this embodiment, a higher-order topological insulator layer 20 such as multilayer WTe2 is used, so a configuration to suppress oxidation is not required. Moreover, adjusting the size of the higher-order topological insulator layer 20 is easier compared to adjusting the size of the WTe2 monolayer film.

[0081] Furthermore, it is possible to create a multi-qubit system by providing multiple qubits 1 on the substrate 90, or to mount a semiconductor integrated circuit on the substrate 90. Therefore, according to this embodiment, research and development toward the realization of a practical error-tolerant quantum computer can be accelerated.

[0082] Next, a method for manufacturing the qubit 1 according to the fourth embodiment will be described. Figures 11 to 16 are top views showing the method for manufacturing the qubit 1 according to the fourth embodiment. Figures 17 to 22 are cross-sectional views showing the method for manufacturing the qubit 1 according to the fourth embodiment.

[0083] First, as shown in Figures 11 and 17, the substrate 90 is prepared and annealed at approximately 1200°C for 3 to 4 hours under an oxygen atmosphere at atmospheric pressure. Next, the substrate 90 is immersed in methanol for 20 to 30 minutes and rinsed with ultrapure water. These processes improve the flatness of the substrate 90 surface. Figure 17 corresponds to a cross-sectional view along the line XVII-XVII in Figure 11.

[0084] Subsequently, an s-wave superconductor layer 19 is formed on the substrate 90, a Te layer 79 is formed on the s-wave superconductor layer 19, and a higher-order topological insulator layer 29 is formed on the Te layer 79. Hereafter, we will explain assuming that an Nb layer is formed as the s-wave superconductor layer 19 and a multilayer WTe2 is formed as the higher-order topological insulator layer 29. The s-wave superconductor layer 19, the Te layer 79, and the higher-order topological insulator layer 29 can be epitaxially grown in situ within the same vacuum chamber, for example, by the PLD method. The basic vacuum level during the formation of the s-wave superconductor layer 19, the Te layer 79, and the higher-order topological insulator layer 29 is, for example, 5 × 10⁻⁶. -6 The pressure should be Pa or less. When forming the s-wave superconductor layer 19, Te layer 79, and higher-order topological insulator layer 29 by the PLD method, a KrF excimer laser (λ=248nm) light source can be used as the laser light source. Note that the method for forming the s-wave superconductor layer 19, Te layer 79, and higher-order topological insulator layer 29 is not limited to the PLD method. For example, the s-wave superconductor layer 19, Te layer 79, and higher-order topological insulator layer 29 may be formed by sputtering, or the s-wave superconductor layer 19 and Te layer 79 may be formed by evaporation and the higher-order topological insulator layer 29 may be formed by co-evaporation. Thus, the s-wave superconductor layer 19, Te layer 79, and higher-order topological insulator layer 29 can be formed by physical evaporation in a vacuum-integrated process.

[0085] When forming an Nb layer as an s-wave superconductor layer 19 by PLD, for example, a pure Nb metal target can be used. When forming the s-wave superconductor layer 19, for example, the temperature of the substrate 90 is maintained at approximately 400°C, and the laser energy density is 2.0 J / cm². 2 ~5.0J / cm2 The irradiation frequency is set to 10 Hz, the distance between the substrate 90 and the target is approximately 5 cm, and the film deposition rate is set to 0.5 nm / min to 1.0 nm / min. On the substrate 90, which is maintained at approximately 400°C, the Nb layer is epitaxially grown while oriented in the

[0110] direction.

[0086] When forming the Te layer 79, for example, a Te pure metal target can be used as the target. When forming the Te layer 79, for example, the temperature of the substrate 90 is maintained at approximately 200°C, and the laser energy density is 1.0 J / cm². 2 ~2.0J / cm 2 The irradiation frequency is set to 1 Hz, the distance between the substrate 110 and the target is approximately 5 cm, and the film deposition rate is set to 0.5 nm / min to 1.5 nm / min.

[0087] When forming a multilayer WDe2 as a higher-order topological insulator layer 29 by the PLD method, for example, a WDe2 sintered target can be used as the target. When forming the higher-order topological insulator layer 29, for example, the temperature of the substrate 90 is maintained at approximately 325°C, and the laser energy density is 1.0 J / cm². 2 ~2.0J / cm 2 The irradiation frequency is set to 10 Hz, the distance between the substrate 90 and the target is approximately 5 cm, and the film deposition rate is set to 0.5 nm / min to 1.5 nm / min. The higher-order topological insulator layer 29 (multilayer WTe2) is oriented in the c-axis direction on the s-wave superconductor layer 19 (Nb layer), and the crystal structure of the higher-order topological insulator layer 29 is T d Show the structure.

[0088] Furthermore, it is preferable to perform post-annealing at approximately 300°C for 30 minutes to 1 hour after the deposition of the multilayer WTe2 film. This is because it improves the crystallinity of the multilayer WTe2.

[0089] After the formation of the higher-order topological insulator layer 29, as shown in Figures 12 and 18, the s-wave superconductor layer 19, the Te layer 79, and the higher-order topological insulator layer 29 are processed to form the s-wave superconductor layer 10, the lower superconductor layer 61A, the lower superconductor layer 61B, the lower superconductor layer 62A, the lower superconductor layer 62B, the lower superconductor layer 63A, and the lower superconductor layer 63B from the s-wave superconductor layer 19. Figure 18 corresponds to a cross-sectional view along the line XVIII-XVIII in Figure 12.

[0090] When processing the s-wave superconductor layer 19, the Te layer 79, and the higher-order topological insulator layer 29, first, a first electron beam resist is spin-coated onto the higher-order topological insulator layer 29. Next, a first mask pattern is formed from the first electron beam resist by electron beam lithography. The first mask pattern covers the portion of the s-wave superconductor layer 19 where the s-wave superconductor layer 10, lower superconductor layer 61A, lower superconductor layer 61B, lower superconductor layer 62A, lower superconductor layer 62B, lower superconductor layer 63A, and lower superconductor layer 63B are to be formed, from above the higher-order topological insulator layer 29, leaving the other portions exposed. As the first electron beam resist, for example, a resist obtained by diluting ZEP 520A (manufactured by Nippon Zeon Co., Ltd.) with ZEP-A (manufactured by Nippon Zeon Co., Ltd.) in a 1:1 ratio can be used. After the formation of the first mask pattern, the s-wave superconductor layer 19, the Te layer 79, and the higher-order topological insulator layer 29 are fabricated by Ar ion milling. For Ar ion milling, for example, the beam acceleration voltage is set to 280V and the beam current to 150mA.

[0091] After processing the s-wave superconductor layer 19, the Te layer 79, and the higher-order topological insulator layer 29, the first mask pattern is removed, and the higher-order topological insulator layer 29 and the Te layer 79 are processed as shown in Figures 13 and 19. A higher-order topological insulator layer 29A with a rectangular planar shape and a flat top surface is formed from the higher-order topological insulator layer 29, and a Te layer 70 with a rectangular planar shape is formed from the Te layer 79. Figure 19 corresponds to a cross-sectional view along the line XIX-XIX in Figure 13.

[0092] When processing the higher-order topological insulator layer 29 and the Te layer 79, first, a second electron beam resist is spin-coated onto the higher-order topological insulator layer 29 and the substrate 90. Next, a second mask pattern is formed from the second electron beam resist by electron beam lithography. The second mask pattern covers the portion of the higher-order topological insulator layer 29 over the s-wave superconductor layer 10, exposing the portions over the lower superconductor layers 61A, 61B, 62A, 62B, 63A, and 63B. As the second electron beam resist, for example, a resist obtained by diluting ZEP 520A (manufactured by Nippon Zeon Co., Ltd.) with ZEP-A (manufactured by Nippon Zeon Co., Ltd.) in a 1:1 ratio can be used. After the formation of the second mask pattern, the higher-order topological insulator layer 29 and the Te layer 79 are processed by Ar ion milling. As a result, the higher-order topological insulator layer 29A and the Te layer 70 are formed, and the lower superconductor layers 61A, 61B, 62A, 62B, 63A, and 63B are exposed from the higher-order topological insulator layer 29A and the Te layer 70. In Ar ion milling, for example, the beam acceleration voltage is set to 280V and the beam current to 150mA.

[0093] After the formation of the higher-order topological insulator layer 29A and the Te layer 70, the second mask pattern is removed, and the higher-order topological insulator layer 29A is processed as shown in Figures 14 and 20 to form a higher-order topological insulator layer 20 having a first region 21, a second region 22, and a third region 23 from the higher-order topological insulator layer 29A. Figure 20 corresponds to a cross-sectional view along the line XX-XX in Figure 14.

[0094] When processing the higher-order topological insulator layer 29A, first, a third electron beam resist is spin-coated onto the higher-order topological insulator layer 29A, the substrate 90, the lower superconductor layer 61A, the lower superconductor layer 61B, the lower superconductor layer 62A, the lower superconductor layer 62B, the lower superconductor layer 63A, and the lower superconductor layer 63B. Next, a third mask pattern is formed from the third electron beam resist by electron beam lithography. The third mask pattern exposes the portion of the higher-order topological insulator layer 29A where the groove 50 is to be formed, and covers the other portions. As the third electron beam resist, for example, a resist obtained by diluting ZEP 520A (manufactured by Nippon Zeon Co., Ltd.) with ZEP-A (manufactured by Nippon Zeon Co., Ltd.) in a 1:1 ratio can be used. After the formation of the third mask pattern, the higher-order topological insulator layer 29A is processed by Ar ion milling. As a result, a groove 50 having a first groove 51, a second groove 52, and a third groove 53 is formed, and a higher-order topological insulator layer 20 having a first region 21, a second region 22, and a third region 23 is obtained. The first region 21 has a first hinged helical channel 11, the second region 22 has a second hinged helical channel 12, and the third region 23 has a third hinged helical channel 13 (see Figure 10). In Ar ion milling, for example, the beam acceleration voltage is set to 280V and the beam current to 150mA.

[0095] After the formation of the higher-order topological insulator layer 20, the third mask pattern is removed, and the first ferromagnetic insulator layer 31, the second ferromagnetic insulator layer 32, the third ferromagnetic insulator layer 33, the first gate electrode 41, the second gate electrode 42, and the third gate electrode 43 are formed, as shown in Figures 15 and 21. Figure 21 corresponds to a cross-sectional view along the line XXI-XXI in Figure 15.

[0096] When forming the first ferromagnetic insulator layer 31, the second ferromagnetic insulator layer 32, the third ferromagnetic insulator layer 33, the first gate electrode 41, the second gate electrode 42, and the third gate electrode 43, first, a fourth electron beam resist is spin-coated onto the higher-order topological insulator layer 20, the substrate 90, the lower superconductor layer 61A, the lower superconductor layer 61B, the lower superconductor layer 62A, the lower superconductor layer 62B, the lower superconductor layer 63A, and the lower superconductor layer 63B. Next, a fourth mask pattern is formed from the fourth electron beam resist by electron beam lithography. The fourth mask pattern exposes the areas where the first ferromagnetic insulator layer 31, the second ferromagnetic insulator layer 32, the third ferromagnetic insulator layer 33, the first gate electrode 41, the second gate electrode 42, and the third gate electrode 43 are to be formed, while covering the other areas. As the fourth electron beam resist, for example, a resist obtained by diluting ZEP 520A (manufactured by Nippon Zeon Co., Ltd.) in a 1:1 ratio with ZEP-A (manufactured by Nippon Zeon Co., Ltd.) can be used. After the formation of the fourth mask pattern, a Cr2Ga2Te6 layer and an Au layer are formed by the PLD method.

[0097] When forming a Cr2Ga2Te6 layer by PLD, for example, the temperature of the substrate 90 is maintained at 200°C, and the laser energy density is 1.0 J / cm². 2 ~2.0J / cm 2 The irradiation frequency is set to 1 Hz, the distance between the substrate 90 and the target is approximately 5 cm, and the film deposition rate is set to 1.0 nm / min to 2.0 nm / min.

[0098] When forming the Au layer using the PLD method, for example, the temperature of the substrate 90 is kept at room temperature, and the laser energy density is set to 1.0 J / cm². 2 ~2.0J / cm 2 The irradiation frequency is set to 5 Hz, the distance between the substrate 90 and the target is approximately 5 cm, and the film deposition rate is set to 5.0 nm / min to 10.0 nm / min.

[0099] After the formation of the Cr2Ga2Te6 layer and the Au layer, the fourth mask pattern is removed along with the Cr2Ga2Te6 layer and Au layer deposited thereon. In other words, a lift-off is performed. As a result, the first ferromagnetic insulator layer 31, the second ferromagnetic insulator layer 32, the third ferromagnetic insulator layer 33, the first gate electrode 41, the second gate electrode 42, and the third gate electrode 43 are obtained. In addition, four Majorana particles γ1, γ2, γ3, and γ4 are expressed.

[0100] Next, as shown in Figures 16 and 22, tunnel barrier layers 61C to 63C and upper superconductor layers 61D to 63D are formed. Figure 22 corresponds to a cross-sectional view along the line XXII-XXII in Figure 16.

[0101] When forming the tunnel barrier layers 61C-63C and the upper superconductor layers 61D-63D, first, a fifth electron beam resist is spin-coated onto the higher-order topological insulator layer 20, the substrate 90, the lower superconductor layer 61A, the lower superconductor layer 61B, the lower superconductor layer 62A, the lower superconductor layer 62B, the lower superconductor layer 63A, the lower superconductor layer 63B, the first gate electrode 41, the second gate electrode 42, and the third gate electrode 43. Next, a fifth mask pattern is formed from the fifth electron beam resist by electron beam lithography. The fifth mask pattern exposes the areas where the tunnel barrier layers 61C-63C and the upper superconductor layers 61D-63D are to be formed, and covers the other areas. As the fifth electron beam resist, for example, a resist obtained by diluting ZEP 520A (manufactured by Nippon Zeon Co., Ltd.) in a 1:1 ratio with ZEP-A (manufactured by Nippon Zeon Co., Ltd.) can be used. After the formation of the fifth mask pattern, NbO is processed by the PLD method. x Forms a layer and an Nb layer.

[0102] NbO x When forming the layer by the PLD method, for example, an Nb metal target is used, the temperature of the substrate 90 is maintained at room temperature, and the oxygen partial pressure in the vacuum chamber is adjusted to about 50 Pa to 55 Pa. The Nb layer can be formed under the same conditions as the s-wave superconductor layer 19.

[0103] NbO xAfter the formation of the layer and the Nb layer, the fifth mask pattern was deposited on top of it using NbO x The layers and Nb layers are removed together. In other words, a lift-off is performed. As a result, tunnel barrier layers 61C to 63C and upper superconductor layers 61D to 63D are obtained, and the first SQUID 61, second SQUID 62, and third SQUID 63 are formed.

[0104] In this way, the qubit 1 according to the fourth embodiment can be manufactured.

[0105] The material of the higher-order topological insulator layer 20 is not limited to multilayer WTe2. The higher-order topological insulator layer 20 may include Mo, Nb, W, Ta, Ti, Zr, Fe, Pd, Ir, or Pt, or any combination thereof, as a transition metal. Furthermore, the material of the s-wave superconductor layer 10 is not limited to Nb, but may be, for example, Al or Pd.

[0106] The thickness of the Te layer 70 is preferably 1 nm to 20 nm, more preferably 2 nm to 15 nm, and even more preferably 3 nm to 10 nm. If the thickness of the Te layer 70 is excessive, the proximity effect of superconductivity due to the s-wave superconductor layer may decrease.

[0107] (Fifth embodiment) Next, a fifth embodiment will be described. The fifth embodiment relates to a quantum computing device including the qubit 1 according to the fourth embodiment. Figure 23 is a diagram showing the quantum computing device according to the fifth embodiment.

[0108] As shown in Figure 23, the quantum computing device 2 according to the fifth embodiment includes a qubit chip 81, a signal generator 82, a signal demodulator 83, and a cryogenic dilution refrigerator 84. The qubit chip 81 includes a plurality of qubits 1 according to the fourth embodiment. The qubit chip 81 is housed in the cryogenic dilution refrigerator 84 and cooled to a temperature of 10 mK or less. The signal generator 82 generates a microwave pulse signal, and the microwave pulse signal is input to the qubit chip 81. The qubit chip 81 outputs a signal corresponding to the microwave pulse signal, and the signal demodulator 83 demodulates the signal output from the qubit chip 81. The signal generator 82 and the signal demodulator 83 are used at a temperature of, for example, room temperature.

[0109] Since the quantum computing device 2 according to the fifth embodiment includes the qubit 1 according to the fourth embodiment, Majorana particles can be stably generated, and stable computations can be performed.

[0110] Although preferred embodiments have been described in detail above, the invention is not limited to the embodiments described above, and various modifications and substitutions can be made to the embodiments described above without departing from the scope of the claims. [Explanation of Symbols]

[0111] 1: Quantum bit 2: Quantum computing device 10: s-wave superconductor layer 11: First hinged helical channel 12: Second hinged helical channel 13: Third hinged helical channel 20: Higher-order topological insulator layer 21:First area 22:Second area 23: Third area 31: First ferromagnetic insulator layer 32: Second ferromagnetic insulator layer 33: Third ferromagnetic insulator layer 41: First gate 42: Second gate electrode 43: Third Gate 50: Groove 51: 1st groove 52:Second groove 53: Third groove 61: First SQUID 62:2nd SQUID 63: Third SQUID 100, 200, 300: Structure 110, 210: Circuit board 120: 1st layer 130: 2nd layer 211: Si substrate 212:SiO2 film 310: Laminate 340: S-wave superconductor layer

Claims

1. s-wave superconductor layer, A Te layer provided on the aforementioned s-wave superconductor layer, A higher-order topological insulator layer is provided on the Te layer, A first ferromagnetic insulator layer provided on the aforementioned higher-order topological insulator layer, A first gate electrode provided on the first ferromagnetic insulator layer, It has, The aforementioned higher-order topological insulating layer is A first region having a first hinged helical channel, A second region having a second hinge helical channel located away from the first hinge helical channel, It has, A qubit characterized in that the first ferromagnetic insulator layer covers the first hinged helical channel and the second hinged helical channel.

2. The qubit according to claim 1, characterized by having a first superconducting quantum interferometer for detecting changes in magnetic flux between the first hinged helical channel and the second hinged helical channel.

3. The higher-order topological insulator layer has a third region comprising a third hinge helical channel separated from the first hinge helical channel and the second hinge helical channel. A second ferromagnetic insulator layer covering the second hinge helical channel and the third hinge helical channel, A second gate electrode provided on the second ferromagnetic insulator layer, The third hinge helical channel and the third ferromagnetic insulator layer covering the first hinge helical channel, A third gate electrode provided on the third ferromagnetic insulator layer, A qubit according to claim 1 or 2, characterized by having the following features.

4. The second superconducting quantum interferometer, The third superconducting quantum interferometer, It has, The second superconducting quantum interferometer detects the change in magnetic flux between the second hinged helical channel and the third hinged helical channel, The qubit according to claim 3, characterized in that the third superconducting quantum interferometer detects the change in magnetic flux between the third hinged helical channel and the first hinged helical channel.

5. In the aforementioned higher-order topological insulating layer, A first groove that defines the first region and the second region, A second groove that defines the second region and the third region, A third groove that defines the third region and the first region, The qubit according to claim 3 or 4, characterized in that a qubit is formed therein.

6. The first groove and the third groove extend in a common first direction, The second groove extends in a second direction perpendicular to the first direction, The qubit according to claim 5, characterized in that the first groove, the second groove, and the third groove are connected.

7. The qubit according to any one of claims 1 to 6, characterized in that the higher-order topological insulator layer includes Mo, Nb, W, Ta, Ti, Zr, Fe, Pd, Ir, or Pt.

8. A quantum computing device characterized by including a qubit as described in any one of claims 1 to 7.

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