Manufacturing method for semiconductor devices

Abstract

A first sacrificial layer (102) comprising InGaAs is formed on a substrate (101) comprising InP. A second sacrificial layer (103) comprising InAlAs is formed on the first sacrificial layer (102). An element 120 is formed on the second sacrificial layer (103). The first sacrificial layer (102) is formed thinner than the second sacrificial layer (103). For example, the thickness of the first sacrificial layer (102) can be one fifth or less of the thickness of the second sacrificial layer (103). For example, the thickness of the first sacrificial layer (102) can be in the range of 50-100 nm, and the thickness of the second sacrificial layer (103) can be 500 nm.

Description

TECHNICAL FIELD

[0001] The present invention relates to a method for manufacturing a semiconductor device. BACKGROUND ART

[0002] Transfer technologies such as transfer printing have been developed as technologies for highly efficiently integrating optical semiconductor devices made of compound semiconductors and optical circuits such as silicon photonics made of silicon. In this type of technology, a transfer stamp is used to take out elements from a semiconductor substrate, and transfer the taken-out elements onto another substrate.

[0003] For example, in the case of an element using an InP-based compound semiconductor, a sacrifice layer is formed on a substrate in advance, the element is formed on the sacrifice layer, and the sacrifice layer is removed after the element is formed, thereby enabling the element to be taken out from the substrate (Non-Patent Document 1). In this technology, the sacrifice layer is formed of InAlAs, which is more easily etched by a certain acid or alkaline solvent than InP constituting the element. InAlAs and InGaAs are materials that can be etched more easily with respect to InP, for example, by piranha solution or an aqueous solution of iron(III) chloride. When an aqueous iron(III) chloride solution is used as an etchant, a higher etching selectivity can be obtained for InAlAs. Therefore, by forming the sacrifice layer from InAlAs, the flatness of the surface of the InP layer exposed after removing the sacrifice layer can be improved. PRIOR ART DOCUMENTS NON-PATENT DOCUMENTS

[0004] Non-Patent Document 1 J. O'CALLAGHAN et al., "Comparison of InGaAs and InAlAs sacrificial layers for release of InP-based devices", Optical Materials Express, vol. 7, no. 12, pp. 4408-4414, 2017. [Overview of the project] [Problems that the invention aims to solve]

[0005] However, when the sacrificial layer was constructed from InAlAs, a problem arose where over-etching during the removal of the sacrificial layer reduced the surface flatness of the InP layer exposed by the removal of the sacrificial layer. Furthermore, the time required to remove the sacrificial layer led to a decrease in productivity. This is thought to be because InAlAs is easily oxidized, and undergoing high-temperature processes such as electrode processing and heat treatment before the sacrificial layer removal process causes oxidation, leading to a decrease in the etching rate.

[0006] This invention was made to solve the above-mentioned problems and aims to enable the removal of the sacrificial layer more quickly. [Means for solving the problem]

[0007] The present invention relates to a method for manufacturing a semiconductor device, comprising: a first step of forming a first sacrificial layer made of InGaAs on a substrate made of InP, and forming a second sacrificial layer made of InAlAs on the first sacrificial layer; a second step of forming an element made of an InP-based compound semiconductor with a semiconductor layer made of InP as the bottom layer on the second sacrificial layer; a third step of removing the second and first sacrificial layers around the element to expose the surface of the substrate; a fourth step of forming a protective layer that covers the element and has legs that reach the exposed surface of the substrate on the sides of the first and second sacrificial layers; a fifth step of removing the first and second sacrificial layers from the sides of the first and second sacrificial layers exposed around the legs using the protective layer as a mask by wet etching with iron(III) chloride, so that the element is supported on the substrate by the legs; and a sixth step of removing the element supported on the substrate by the legs from the substrate using a transfer stamp. [Effects of the Invention]

[0008] As described above, according to the present invention, since a first sacrificial layer made of InGaAs and a second sacrificial layer made of InAlAs are used, the sacrificial layers can be removed more quickly. [Brief explanation of the drawing]

[0009] [Figure 1A] Figure 1A is a cross-sectional view showing the state of a semiconductor device during an intermediate step in the manufacturing process of a semiconductor device according to an embodiment of the present invention. [Figure 1B] Figure 1B is a cross-sectional view showing the state of a semiconductor device during an intermediate step in the manufacturing process of a semiconductor device according to an embodiment of the present invention. [Figure 1C] Figure 1C is a cross-sectional view showing the state of a semiconductor device during an intermediate step in the manufacturing process of a semiconductor device according to an embodiment of the present invention. [Figure 1D] Figure 1D is a cross-sectional view showing the state of a semiconductor device during an intermediate step in the manufacturing process of a semiconductor device according to an embodiment of the present invention. [Figure 1E]Figure 1E is a cross-sectional view showing the state of a semiconductor device during an intermediate step in the manufacturing process of a semiconductor device according to an embodiment of the present invention. [Figure 1F] Figure 1F is a plan view showing the state of a semiconductor device during an intermediate step in the manufacturing process of an embodiment of the present invention. [Figure 1G] Figure 1G is a cross-sectional view showing the state of a semiconductor device during an intermediate step in the manufacturing process of a semiconductor device according to an embodiment of the present invention. [Figure 1H] Figure 1H is a cross-sectional view showing the state of a semiconductor device during an intermediate step in the manufacturing process of a semiconductor device according to an embodiment of the present invention. [Figure 1I] Figure 1I is a cross-sectional view showing the state of a semiconductor device during an intermediate step in the manufacturing process of a semiconductor device according to an embodiment of the present invention. [Modes for carrying out the invention]

[0010] Hereinafter, a method for manufacturing a semiconductor device according to an embodiment of the present invention will be described with reference to Figures 1A to 1I.

[0011] First, as shown in Figure 1A, a first sacrificial layer 102 made of InGaAs is formed on a substrate 101 made of InP, and a second sacrificial layer 103 made of InAlAs is formed on the first sacrificial layer 102 (first step). For example, the first sacrificial layer 102 is formed by growing InGaAs (epitaxial growth) on a substrate 101 made of InP with a (100) plane as its main surface. Subsequently, the second sacrificial layer 103 is formed by growing InAlAs (epitaxial growth) on the first sacrificial layer 102. These crystal growths can be carried out by known crystal growth methods such as metal-organic vapor deposition or molecular beam epitaxy.

[0012] In the first step described above, the first sacrificial layer 102 is formed to be thinner than the second sacrificial layer 103. For example, the thickness of the first sacrificial layer 102 can be formed to be one-fifth or less of the thickness of the second sacrificial layer 103. For example, the thickness of the first sacrificial layer 102 can be formed in the range of 50 to 100 nm, and the thickness of the second sacrificial layer 103 can be formed to be 500 nm.

[0013] Next, as shown in Figure 1B, the element 120 is formed on the second sacrificial layer 103 (second step). The element 120 is composed of an InP-based compound semiconductor, with a semiconductor layer 104 made of InP as the bottom layer. The element 120 includes, for example, a semiconductor layer 104, an active layer 105, a p-type region 104a, an n-type region 104b, a p-contact layer 106a, an n-contact layer 106b, a p-electrode 107a, and an n-electrode 107b. It also includes a protective film 108 formed on the semiconductor layer 104.

[0014] The active layer 105 is formed embedded in the semiconductor layer 104 and extends from the foreground to the background in Figure 1B. The active layer 105 can be a multiple quantum well structure consisting of well layers and barrier layers, each composed of, for example, InGaAlAs, InGaAs, and InGaAsP, each with a different composition. The p-type region 104a and the n-type region 104b are formed on either side of the active layer 105. For example, the p-type region 104a can be formed by introducing p-type impurities into the semiconductor layer 104. The n-type region 104b can be formed by introducing n-type impurities into the semiconductor layer 104. The semiconductor layers 104 above and below the active layer 105 are undoped.

[0015] The p-contact layer 106a can be made of, for example, InGaAs with a high concentration of p-type impurities. The n-contact layer 106b can be made of, for example, InGaAs with a high concentration of n-type impurities. The protective film 108 can be made of, for example, silicon oxynitride.

[0016] The element 120 is a known waveguide-type optical element having the active layer 105 as a core. For example, by using a p-electrode 107a and an n-electrode 107b and applying a predetermined voltage to a p-type region 104a and an n-type region 104b via a p-contact layer 106a and an n-contact layer 106b, the element can be configured as an optical modulator. Further, by forming a diffraction grating (not shown) above the active layer 105, and injecting current into the p-type region 104a and the n-type region 104b via the p-contact layer 106a and the n-contact layer 106b using the p-electrode 107a and the n-electrode 107b, the element 120 can be configured as a semiconductor laser.

[0017] Next, as shown in FIG. 1C, the second sacrificial layer 103 and the first sacrificial layer 102 around the element 120 are removed to expose the surface of the substrate 101 (third step). For example, the surface of the substrate 101 can be exposed by forming a mask pattern (not shown) covering the element 120, and etching away the second sacrificial layer 103 and the first sacrificial layer 102 by known dry etching using the mask pattern as a mask. Through this patterning, a columnar laminated structure formed of the first sacrificial layer 102 and the second sacrificial layer 103 is formed below the element 120. For example, the area of the upper surface (the surface facing the element 120 side) of the columnar laminated structure formed of the first sacrificial layer 102 and the second sacrificial layer 103 can be set to be slightly larger than the area of the bottom surface (the surface facing the substrate 101 side) of the element 120.

[0018] Next, as shown in FIG. 1D, a resin film 112 is formed so as to embed the element 120. For example, the resin film 112 can be formed by applying a well-known photoresist material onto the substrate 101 on which the element 120 is formed.

[0019] Next, the formed resin film 112 is patterned to form a protective layer 113 covering the element 120 as shown in FIGS. 1E and 1F (fourth step). The protective layer 113 is formed to have a leg portion 113a reaching the exposed surface of the substrate 101 on the side of the first sacrificial layer 102 and the second sacrificial layer 103. In this example, one leg portion 113a is provided on each of the four sides (lateral sides) of the protective layer 113 formed in a rectangular shape in plan view.

[0020] For example, when the resin film 112 is made of positive photoresist, the protective layer 113 including the leg portions 113a can be formed by patterning via a known photolithography technique. The portion of the leg portion 113a that reaches the surface of the substrate 101 from the lower end of the element 120 partially covers the side surfaces of the first sacrificial layer 102 and the second sacrificial layer 103, while the remaining side surfaces of the first sacrificial layer 102 and the second sacrificial layer 103 remain exposed.

[0021] Next, using the protective layer 113 as a mask, the first sacrificial layer 102 and the second sacrificial layer 103 are etched away from the side surfaces of the first sacrificial layer 102 and the second sacrificial layer 103 exposed around the leg portions 113a. The side surfaces of the first sacrificial layer 102 and the second sacrificial layer 103 epitaxially grown on the substrate 101 whose main surface is a (100) plane are (011) planes. This etching removal can be performed by wet etching using a solution (aqueous solution) of iron(III) chloride [FeCl₃] as an etchant.

[0022] In this wet etching, the etching proceeds isotropically in the first sacrificial layer 102 and the second sacrificial layer 103. In addition, since the first sacrificial layer 102 formed thicker than the second sacrificial layer 103 has a larger area in contact with the etchant, the etching removal of the first sacrificial layer 102 proceeds first, and the etching of the first sacrificial layer 102 further progresses through the opening expanded accordingly (FIG. 1G). Here, even after the formation process of the element 120 is completed, the first sacrificial layer 102 made of InGaAs is not oxidized, so the etching rate does not decrease. In addition, since the second sacrificial layer 103 is thin, the etching process can be completed in a relatively short time.

[0023] As described above, the first sacrificial layer 102 and the second sacrificial layer 103 are removed by wet etching, resulting in a state where the element 120 is supported on the substrate 101 by the legs 113a, as shown in Figure 1H (5th step). In addition, the wet etching process described above removes the first sacrificial layer 102 and the second sacrificial layer 103, exposing the entire lower surface of the bottom semiconductor layer of the element 120 facing the substrate 101. In this wet etching, InAlAs and InGaAs are etched with a high selectivity ratio to InP, and as described above, the etching process is completed in a relatively short time, so the exposed lower surface of the semiconductor layer 104 has high flatness.

[0024] Next, as shown in Figure 1I, the element 120, which is supported on the substrate 101 by its legs 113a, is removed from the substrate 101 using the transfer stamp 150 (sixth step). The element 120 can be picked up from the substrate 101 by attaching the convex portion 151 of the transfer stamp 150 to the upper surface of the protective layer 113 covering the element 120 and pulling it up. This pickup can be performed, for example, by separating the legs 113a from the protective layer 113. The picked-up element 120 can then be transferred (released), for example, onto a mounting substrate.

[0025] As described above, according to the present invention, since a first sacrificial layer made of InGaAs and a second sacrificial layer made of InAlAs are used, the sacrificial layers can be removed more quickly.

[0026] It should be noted that the present invention is not limited to the embodiments described above, and it is clear that many modifications and combinations can be implemented within the technical concept of the present invention by those with ordinary skill in the art. [Explanation of Symbols]

[0027] 101...Substrate, 102...First sacrificial layer, 103...Second sacrificial layer, 104...Semiconductor layer, 104a...p-type region, 104b...n-type region, 105...Active layer, 106a...p-contact layer, 106b...n-contact layer, 107a...p-electrode, 107b...n-electrode, 108...Protective film, 112...Resin film, 113...Protective layer, 113a...Legs, 120...Element, 150...Transfer stamp, 151...Protrusion.

Claims

1. A first step involves forming a first sacrificial layer made of InGaAs on a substrate made of InP, and forming a second sacrificial layer made of InAlAs on the first sacrificial layer. A second step involves forming an element on the second sacrificial layer, the element being composed of an InP-based compound semiconductor with a semiconductor layer made of InP as the bottom layer, A third step involves removing the second sacrificial layer and the first sacrificial layer around the element to expose the surface of the substrate, A fourth step is to form a protective layer that covers the element and has legs that reach the exposed surface of the substrate on the sides of the first sacrificial layer and the second sacrificial layer, A fifth step involves wet etching using iron(III) chloride to remove the first and second sacrificial layers from the sides of the first and second sacrificial layers exposed around the legs, using the protective layer as a mask, thereby restoring the element to a state where it is supported on the substrate by the legs. A sixth step involves removing the element, which is supported on the substrate by the legs, from the substrate using a transfer stamp. A method for manufacturing a semiconductor device comprising the same equipment.

2. In the method for manufacturing a semiconductor device according to claim 1, A method for manufacturing a semiconductor device, wherein the first step involves forming the first sacrificial layer thinner than the second sacrificial layer.

3. In the method for manufacturing a semiconductor device according to claim 2, A method for manufacturing a semiconductor device, wherein the first step involves forming the thickness of the first sacrificial layer to be one-fifth or less of the thickness of the second sacrificial layer.

4. In the method for manufacturing a semiconductor device according to claim 3, A method for manufacturing a semiconductor device, comprising the first step of forming the first sacrificial layer to a thickness of 50 to 100 nm and the second sacrificial layer to a thickness of 500 nm.

5. In the method for manufacturing a semiconductor device according to any one of claims 1 to 4, A method for manufacturing a semiconductor device, wherein the fifth step involves removing the first sacrificial layer and the second sacrificial layer to expose the entire lower surface of the bottom semiconductor layer of the element facing the substrate.

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