Multilayer ceramic capacitor

Abstract

Provided is a multilayer ceramic capacitor in which occurrence of "singing" is suppressed and which is reduced in size and increased in capacity.　This multilayer ceramic capacitor comprises a plurality of dielectric layers 20 and a plurality of inner electrode layers 30 which are alternately layered in a layering direction T, and a first side face WS1 and a second side face WS2 which face each other in a width direction W, wherein the distance L1 between the first side face WS1 and an end E1L which is the closest to the first side face WS1 of the ends of the plurality of inner electrode layers 30 on the first side face WS1 side is smaller than the distance L2 between the second side face WS2 and an end E2L which is the closest to the second side face WS2 of the ends of the plurality of inner electrode layers 30 on the second side face WS2 side, and a distance L3 which is the maximum of the distances in the width direction W between the ends of the plurality of inner electrode layers 30 in the width direction W that are side by side on the first side face WS1 side is smaller than a distance L4 which is the maximum of the distances in the width direction W between the ends of the plurality of inner electrode layers 30 in the width direction W that are side by side on the second side face WS2.

Description

Technical Field

[0001] The present invention relates to a multilayer ceramic capacitor.

Background Art

[0002] Conventionally, a multilayer ceramic capacitor, which has been widely used in various electronic devices such as mobile terminal devices including mobile phones or personal computers, has a structure comprising: a rectangular parallelepiped layered body including an inner layer portion in which dielectric layers and internal electrode layers are alternately stacked, and outer layer portions formed on the upper and lower sides of the inner layer portion; and external electrodes provided on both end faces in the longitudinal direction of the layered body. With the development of electronic devices in recent years, further miniaturization and higher capacity have been demanded for such multilayer ceramic capacitors.

[0003] On the other hand, when a multilayer ceramic capacitor is mounted on a substrate, vibrating noise that becomes noise, so-called "singing", is likely to occur. In order to suppress the occurrence of "singing", a multilayer ceramic capacitor including a spacer formed so as to cover a part of an external electrode on the side where the multilayer ceramic capacitor is mounted on the substrate is known.

Prior Art Literature

Patent Literature

[0004]

Patent Literature 1

Summary of the Invention

Problem to be Solved by the Invention

[0005] However, the multilayer ceramic capacitor provided with a spacer has problems in the cost for arranging the spacer and in the accuracy when arranging the spacer.

[0006] An object of the present invention is to provide a multilayer ceramic capacitor that suppresses the occurrence of "singing" while achieving miniaturization and higher capacity. [Means for solving the problem]

[0007] The inventors of the present invention have discovered that by adjusting the arrangement of multiple ends in the width direction of the internal electrode layers aligned along two opposing sides of the laminate, it is possible to suppress the occurrence of "sound" in a multilayer ceramic capacitor while achieving miniaturization and high capacitance, and have completed the present invention.

[0008] In other words, the present invention provides a substantially rectangular parallelepiped laminate comprising a plurality of dielectric layers and a plurality of internal electrode layers alternately stacked in the stacking direction, and having a first main surface and a second main surface facing each other in the stacking direction, a first side surface and a second side surface facing each other in the width direction perpendicular to the stacking direction, and a first end surface and a second end surface facing each other in the length direction perpendicular to the stacking direction and the width direction. At both ends of the laminate in the longitudinal direction, a pair of external electrodes are provided, which are arranged to cover at least the first end face and the second end face respectively and are connected to the internal electrode layer. Equipped with, The distance between the first side surface and the first side surface is smaller than the distance between the second side surface and the second side surface. The multilayer ceramic capacitor is such that the maximum distance in the width direction between the ends of the plurality of internal electrode layers aligned on the first side surface is smaller than the maximum distance in the width direction between the ends of the plurality of internal electrode layers aligned on the second side surface. [Effects of the Invention]

[0009] According to the present invention, it is possible to reduce the size and increase the capacitance of multilayer ceramic capacitors while suppressing the occurrence of "sound." [Brief explanation of the drawing]

[0010] [Figure 1] This is a perspective view showing a multilayer ceramic capacitor according to this embodiment. [Figure 2] Figure 1 shows a cross-sectional view (LT section) of a multilayer ceramic capacitor along line II-II. [Figure 3] Figure 1 shows a cross-sectional view (WT section) of a multilayer ceramic capacitor along line III-III. [Figure 4] Figure 1 shows a cross-sectional view (WT cross-section) of the multilayer ceramic capacitor in its mounted state. [Figure 5] Figure 4 is a magnified view of the edge of the internal electrode layer of the multilayer ceramic capacitor shown. [Figure 6] Figure 1 is a perspective view showing the laminate chip, which is the precursor to the laminate that makes up the multilayer ceramic capacitor shown in Figure 1. [Figure 7] This figure shows the laminated chip shown in Figure 6 with the side covering portion attached. [Modes for carrying out the invention]

[0011] The following describes embodiments of the multilayer ceramic capacitor of the present invention, but the present invention is not limited thereto. Furthermore, the drawings may be schematically simplified to illustrate the content of the invention, and the ratios of dimensions of the depicted components or between components may not match the ratios of those dimensions described in the specification. Also, components described in the specification may be omitted in the drawings, or their quantities may be omitted.

[0012] (Multilayer ceramic capacitor) Figure 1 is a perspective view showing a multilayer ceramic capacitor according to this embodiment, Figure 2 is a cross-sectional view of the multilayer ceramic capacitor shown in Figure 1 along line II-II, and Figure 3 is a cross-sectional view of the multilayer ceramic capacitor shown in Figure 1 along line III-III. The multilayer ceramic capacitor 1 shown in Figures 1 to 3 comprises a laminate 10 and external electrodes 40. The external electrodes 40 include a first external electrode 41 and a second external electrode 42.

[0013] An XYZ orthogonal coordinate system is shown in Figures 1 to 3. The X direction corresponds to the length direction L of the multilayer ceramic capacitor 1 and the multilayer body 10, the Y direction corresponds to the width direction W of the multilayer ceramic capacitor 1 and the multilayer body 10, and the Z direction corresponds to the lamination direction T of the multilayer ceramic capacitor 1 and the multilayer body 10. Accordingly, the cross-section shown in FIG. 2 is also referred to as an LT cross-section, and the cross-section shown in FIG. 3 is also referred to as a WT cross-section.

[0014] Note that the length direction L, width direction W, and lamination direction T are not necessarily orthogonal to each other, and may be in a relationship of intersecting each other.

[0015] The multilayer body 10 has a substantially rectangular parallelepiped shape, and includes a first main surface TS1 and a second main surface TS2 opposed to each other in the lamination direction T, a first side surface WS1 and a second side surface WS2 opposed to each other in the width direction W, and a first end surface LS1 and a second end surface LS2 opposed to each other in the length direction L. Note that the surface of each surface may be provided with irregularities or may be roughened.

[0016] It is preferable that corners and ridges of the multilayer body 10 are rounded. A corner is a portion where three surfaces of the multilayer body 10 intersect, and a ridge is a portion where two surfaces of the multilayer body 10 intersect.

[0017] As shown in FIGS. 2 and 3, the multilayer body 10 includes a plurality of dielectric layers 20 and a plurality of internal electrode layers 30 laminated in the lamination direction T. Further, the multilayer body 10 has, in the lamination direction T, an inner layer portion 100, and a first outer layer portion 101 and a second outer layer portion 102 arranged so as to sandwich the inner layer portion 100 therebetween.

[0018] The inner layer portion 100 includes a part of the plurality of dielectric layers 20 and the plurality of internal electrode layers 30. In the inner layer portion 100, the plurality of internal electrode layers 30 are arranged to face each other with the dielectric layers 20 interposed therebetween. The inner layer portion 100 is a portion that generates capacitance and substantially functions as a capacitor.

[0019] The first outer layer 101 is located on the side of the first main surface TS1 of the laminate 10, and the second outer layer 102 is located on the side of the second main surface TS2 of the laminate 10. More specifically, the first outer layer 101 is located between the internal electrode layer 30 closest to the first main surface TS1 and the first main surface TS1, and the second outer layer 102 is located between the internal electrode layer 30 closest to the second main surface TS2 and the second main surface TS2. The first outer layer 101 and the second outer layer 102 do not include the internal electrode layers 30.

[0020] As the material for the dielectric layer 20, for example, a dielectric ceramic containing BaTiO3, CaTiO3, SrTiO3, or CaZrO3 as the main component can be used. In addition, Mn compounds, Fe compounds, Cr compounds, Co compounds, or Ni compounds may be added as minor components to the material for the dielectric layer 20.

[0021] The thickness of the dielectric layer 20 is not particularly limited, but is preferably 0.40 μm or more and 0.50 μm or less, and more preferably 0.40 μm or more and 0.45 μm or less. The number of dielectric layers 20 is not particularly limited, but is preferably 100 or more and 2000 or less. Note that this number of dielectric layers 20 is the total number of dielectric layers in the inner layer and the dielectric layers in the outer layer.

[0022] The multiple internal electrode layers 30 include multiple first internal electrode layers 31 and multiple second internal electrode layers 32. The multiple first internal electrode layers 31 and multiple second internal electrode layers 32 are arranged alternately in the stacking direction T of the laminate 10.

[0023] The first internal electrode layer 31 includes a counter electrode portion 311 and an extraction electrode portion 312, and the second internal electrode layer 32 includes a counter electrode portion 321 and an extraction electrode portion 322.

[0024] The opposing electrode portion 311 and the opposing electrode portion 321 face each other via the dielectric layer 20 in the stacking direction T of the laminate 10. The shape of the opposing electrode portion 311 and the opposing electrode portion 321 is not particularly limited and may be, for example, substantially rectangular. The opposing electrode portion 311 and the opposing electrode portion 321 are parts that generate capacitance and function substantially as capacitors.

[0025] The lead-out electrode portion 312 extends from the counter electrode portion 311 toward the first end face LS1 of the laminate 10 and is exposed at the first end face LS1. The lead-out electrode portion 322 extends from the counter electrode portion 321 toward the second end face LS2 of the laminate 10 and is exposed at the second end face LS2. The widthwise lengths W of the counter electrode portion 311 and the lead-out electrode portion 312 may be the same or different. Furthermore, the widthwise lengths W of these portions may gradually change toward the exposed first end face LS1. The widthwise lengths W of the counter electrode portion 321 and the lead-out electrode portion 322 may be the same or different. Furthermore, the widthwise lengths W of these portions may gradually change toward the exposed second end face LS2.

[0026] As a result, the first internal electrode layer 31 is connected to the first external electrode 41, and a gap is provided between the first internal electrode layer 31 and the second end face LS2 of the laminate 10, i.e., the second external electrode 42. In addition, the second internal electrode layer 32 is connected to the second external electrode 42, and a gap is provided between the second internal electrode layer 32 and the first end face LS1 of the laminate 10, i.e., the first external electrode 41.

[0027] The first internal electrode layer 31 and the second internal electrode layer 32 mainly contain metallic Ni. Furthermore, the first internal electrode layer 31 and the second internal electrode layer 32 may also mainly contain at least one selected from metals such as Cu, Ag, Pd, or Au, or alloys containing at least one of these metals, such as Ag-Pd alloys, or may contain other components. In addition, the first internal electrode layer 31 and the second internal electrode layer 32 may also contain dielectric particles of the same composition system as the ceramic contained in the dielectric layer 20 as components other than the main component. In this specification, the main component metal refers to the metal component with the highest weight percentage.

[0028] The thickness of the first internal electrode layer 31 and the second internal electrode layer 32 is not particularly limited, but is preferably, for example, 0.30 μm or more and 0.40 μm or less, and more preferably 0.30 μm or more and 0.35 μm or less. The number of the first internal electrode layer 31 and the second internal electrode layer 32 is not particularly limited, but is preferably, for example, 10 or more and 1000 or less.

[0029] Furthermore, a method for measuring the thickness of the dielectric layer 20 and the internal electrode layer 30 is, for example, to observe the LT cross-section near the center in the width direction of the laminate exposed by polishing using a scanning electron microscope. In addition, each value may be the average of measurements taken at multiple locations in the length direction, or further, the average of measurements taken at multiple locations in the stacking direction.

[0030] As shown in Figure 3, the laminate 10 has, in the width direction W, an electrode-facing portion W30 on which the internal electrode layer 30 faces, and a first side gap portion WG1 and a second side gap portion WG2 arranged to sandwich the electrode-facing portion W30. The first side gap portion WG1 is located between the electrode-facing portion W30 and the first side surface WS1, and the second side gap portion WG2 is located between the electrode-facing portion W30 and the second side surface WS2. More specifically, the first side gap portion WG1 is located between the end of the internal electrode layer 30 on the first side surface WS1 side and the first side surface WS1, and the second side gap portion WG2 is located between the end of the internal electrode layer 30 on the second side surface WS2 side and the second side surface WS2. The first side gap portion WG1 and the second side gap portion WG2 do not include the internal electrode layer 30, but include only the dielectric layer 20. The first side gap WG1 and the second side gap WG2 are also referred to as W gaps.

[0031] Si segregation may be present at the end of the internal electrode layer 30 in the width direction W on the first side surface WS1 side, and the presence of Si segregation improves the flexural strength of the multilayer ceramic capacitor 1. The amount of Si segregation in the width direction W on the second side surface WS2 side of the internal electrode layer 30 may be less than that at the end of the width direction W on the first side surface WS1 side.

[0032] As shown in Figure 2, the laminate 10 has, in the longitudinal direction L, an electrode-facing portion L30 where the first internal electrode layer 31 and the second internal electrode layer 32 of the internal electrode layer 30 face each other, a first end gap portion LG1, and a second end gap portion LG2. The first end gap portion LG1 is located between the electrode-facing portion L30 and the first end face LS1, and the second end gap portion LG2 is located between the electrode-facing portion L30 and the second end face LS2. More specifically, the first end gap portion LG1 is located between the end of the second internal electrode layer 32 on the first end face LS1 side and the first end face LS1, and the second end gap portion LG2 is located between the end of the first internal electrode layer 31 on the second end face LS2 side and the second end face LS2. The first end gap portion LG1 does not include the second internal electrode layer 32, but includes the first internal electrode layer 31 and the dielectric layer 20, and the second end gap portion LG2 does not include the first internal electrode layer 31, but includes the second internal electrode layer 32 and the dielectric layer 20. The first end gap portion LG1 functions as an extraction electrode portion to the first end face LS1 of the first internal electrode layer 31, and the second end gap portion LG2 functions as an extraction electrode portion to the second end face LS2 of the second internal electrode layer 32. The first end gap portion LG1 and the second end gap portion LG2 are also called L gaps.

[0033] The electrode opposing portion L30 contains the opposing electrode portion 311 of the first internal electrode layer 31 and the opposing electrode portion 321 of the second internal electrode layer 32. The leading electrode portion 312 of the first internal electrode layer 31 is located in the first end gap portion LG1, and the leading electrode portion 322 of the second internal electrode layer 32 is located in the second end gap portion LG2.

[0034] One method for measuring the thickness of the laminate 10 is to observe the LT cross-section near the center in the width direction of the laminate exposed by polishing, or the WT cross-section near the center in the length direction of the laminate exposed by polishing, using a scanning electron microscope. Alternatively, each value may be the average of measurements taken at multiple locations in the length or width direction. Similarly, a method for measuring the length of the laminate 10 is, for example, to observe the LT cross-section near the center in the width direction of the laminate, which has been exposed by polishing, using a scanning electron microscope. Furthermore, each value may be the average of measurements taken at multiple locations in the lamination direction. Similarly, a method for measuring the width of the laminate 10 is, for example, to observe the WT cross-section near the center in the longitudinal direction of the laminate, which has been exposed by polishing, using a scanning electron microscope. Furthermore, each value may be the average of measurements taken at multiple locations in the lamination direction.

[0035] The external electrode 40 includes a first external electrode 41 and a second external electrode 42.

[0036] The first external electrode 41 is positioned on the first end face LS1 of the laminate 10 and is connected to the first internal electrode layer 31. The first external electrode 41 may extend from the first end face LS1 to a portion of the first main surface TS1 and a portion of the second main surface TS2. Alternatively, the first external electrode 41 may extend from the first end face LS1 to a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0037] The second external electrode 42 is positioned on the second end face LS2 of the laminate 10 and is connected to the second internal electrode layer 32. The second external electrode 42 may extend from the second end face LS2 to a portion of the first main surface TS1 and a portion of the second main surface TS2. Alternatively, the second external electrode 42 may extend from the second end face LS2 to a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0038] The first external electrode 41 has a first base electrode layer 415 and a first plating layer 416, and the second external electrode 42 has a second base electrode layer 425 and a second plating layer 426. The first external electrode 41 may consist only of the first plating layer 416, and the second external electrode 42 may consist only of the second plating layer 426.

[0039] The first and second base electrode layers 415 and 425 may be fired layers containing metal and glass. Examples of glass include glass components containing at least one selected from B, Si, Ba, Mg, Al, or Li. Borosilicate glass can be used as a specific example. The metal mainly contains Cu. The metal may also mainly contain at least one selected from metals such as Ni, Ag, Pd, or Au, or alloys such as Ag-Pd alloys, or may be included as a component other than the main component.

[0040] The fired layer is a layer obtained by applying a conductive paste containing metal and glass to the laminate using a dip method and then firing it. It may be fired after the firing of the internal electrode layer, or it may be fired simultaneously with the internal electrode layer. Furthermore, there may be multiple fired layers.

[0041] Alternatively, the first base electrode layer 415 and the second base electrode layer 425 may be resin layers containing conductive particles and a thermosetting resin. The resin layers may be formed on the above-described firing layer, or they may be formed directly on the laminate without forming a firing layer.

[0042] The resin layer is a layer obtained by coating a laminate with a conductive paste containing conductive particles and a thermosetting resin using a coating method and then firing it. It may be fired after the firing of the internal electrode layer, or it may be fired simultaneously with the internal electrode layer. Furthermore, there may be multiple resin layers.

[0043] The thickness of each layer of the first base electrode layer 415 and the second base electrode layer 425, which are fired layers or resin layers, is not particularly limited and may be 1 μm or more and 10 μm or less.

[0044] Alternatively, the first underlay electrode layer 415 and the second underlay electrode layer 425 may be thin films of 1 μm or less in thickness, formed by a thin film formation method such as sputtering or vapor deposition, with metal particles deposited on them.

[0045] The first plating layer 416 covers at least a portion of the first underlay electrode layer 415, and the second plating layer 426 covers at least a portion of the second underlay electrode layer 425. The first plating layer 416 and the second plating layer 426 include at least one selected from metals such as Cu, Ni, Ag, Pd, or Au, or alloys such as Ag-Pd alloys.

[0046] The first plating layer 416 and the second plating layer 426 may each be formed from multiple layers. Preferably, they are a two-layer structure of Ni plating and Sn plating. The Ni plating layer can prevent the underlying electrode layer from being corroded by the solder when mounting ceramic electronic components, and the Sn plating layer improves the wettability of the solder when mounting ceramic electronic components, making mounting easier. The first plating layer 416 and the second plating layer 426 may also be a three-layer structure, such as by laminating Sn plating, Ni plating, and Sn plating. The outermost layer may be Au plating.

[0047] The thickness of each layer of the first plating layer 416 and the second plating layer 426 is not particularly limited and may be 1 μm or more and 10 μm or less.

[0048] As shown in Figure 4, the mounting structure of the multilayer ceramic capacitor 1 is such that the second side surface WS2 faces the circuit board CB, and the multilayer ceramic capacitor 1 is mounted on the circuit board CB.

[0049] (Internal electrode layer) Next, the internal electrode layers 30, namely the first internal electrode layer 31 and the second internal electrode layer 32, will be described further. Figure 5 is an enlarged view of the edges of the internal electrode layers of the multilayer ceramic capacitor shown in Figure 4, schematically illustrating the variation in the arrangement of the edges of the internal electrode layers 30, namely the first internal electrode layer 31 and the second internal electrode layer 32, in the width direction W.

[0050] As shown in Figure 5, the distance L1 between the first side surface WS1 and the first side surface WS1 is smaller than the distance L2 between the second side surface WS2 and the second side surface WS2. Furthermore, the maximum distance L3 in the width direction W between the ends of the internal electrode layer 30 aligned on the first side surface WS1 is smaller than the maximum distance L4 in the width direction W between the ends of the internal electrode layer 30 aligned on the second side surface WS2.

[0051] Here, the maximum distance L3 in the width direction W between the ends of the internal electrode layer 30 aligned on the first side surface WS1 corresponds to the distance in the width direction W between the end E1L closest to the first side surface WS1 and the end E1S closest to the second side surface WS2 among the ends of the internal electrode layer 30 aligned on the first side surface WS1. Furthermore, the maximum distance L4 in the width direction W between the ends of the internal electrode layer 30 aligned on the second side surface WS2 corresponds to the distance in the width direction W between the end E2L closest to the second side surface WS2 and the end E2S closest to the first side surface WS1 among the ends of the internal electrode layer 30 aligned on the second side surface WS2.

[0052] In a multilayer ceramic capacitor 1 in which the ends of the internal electrode layer 30 in the width direction W are arranged in this manner, by mounting it on the circuit board CB with the second side surface WS2 facing the circuit board CB, the part that forms capacitance can be moved away from the mounting surface, thereby suppressing the occurrence of "whirring." As a result, there is no need to provide spacers or dielectric ceramic layers that were conventionally placed to create a space between the internal electrode layer 30 and the circuit board CB, making it possible to miniaturize and increase the capacitance of the multilayer ceramic capacitor 1 while suppressing the occurrence of "whirring."

[0053] The end of the internal electrode layer 30 on the second side surface WS2 in the width direction W can be positioned at any position in the stacking direction T, with appropriate offsets in the width direction W. For example, if the end of the internal electrode layer 30 on the second side surface WS2 in the width direction W is positioned towards the center of the width direction W at the center of the stacking direction T of the laminate 10, the area in which adjacent dielectric layers 20 come into contact with each other in the stacking direction T increases, thereby suppressing the occurrence of delamination and cracks that occur at the center of the stacking direction T of the laminate 10. Also, the end of the internal electrode layer 30 on the second side surface WS2 located above or below the center of the stacking direction T of the laminate 10 The end in the width direction W By arranging them offset toward the center in the width direction W, it is possible to suppress the intrusion of moisture from the outside and improve the moisture resistance of the multilayer ceramic capacitor 1.

[0054] Furthermore, in the multilayer ceramic capacitor 1 of the present invention, as shown in Figure 5, the distance L5 between the end E1S, which is the end of the first side surface WS1 of the internal electrode layer 30 that is closest to the second side surface WS2, and the first side surface WS1 is smaller than the distance L6 between the end E2S, which is the end of the second side surface WS2 of the internal electrode layer 30 that is closest to the first side surface WS1, and the second side surface WS2. Furthermore, the maximum distance L3 in the width direction W between the ends of the internal electrode layer 30 aligned on the first side surface WS1 is smaller than the maximum distance L4 in the width direction W between the ends of the internal electrode layer 30 aligned on the second side surface WS2.

[0055] In a multilayer ceramic capacitor 1 in which the ends of the internal electrode layer 30 in the width direction W are arranged in this manner, by mounting it on the circuit board CB with the second side surface WS2 facing the circuit board CB, the part that forms capacitance can be moved away from the mounting surface, thereby suppressing the occurrence of "whirring." Furthermore, unlike conventional designs, there is no need to provide spacers or dielectric ceramic layers to create a space between the internal electrode layer 30 and the circuit board CB, making it possible to miniaturize and increase the capacitance of the multilayer ceramic capacitor 1 while suppressing the occurrence of "whirring."

[0056] The maximum distance L3 in the width direction W between the ends of the internal electrode layer 30 aligned on the first side surface WS1 side is preferably 10 μm or less. In this way, by aligning the ends of the internal electrode layer 30 in the width direction W on the first side surface WS1, the internal electrode layer 30 can be positioned closer to the first side surface WS1, and the ends of the internal electrode layer 30 aligned on the second side surface WS2 can be positioned away from the mounting surface. This makes it possible to achieve a noise suppression effect without reducing the capacitance of the multilayer ceramic capacitor 1.

[0057] The arrangement and distance relationships of the edges of the internal electrode layer 30 in the width direction W can be observed or measured, for example, by the following method.

[0058] First, the multilayer ceramic capacitor 1 is polished along its length L, and the dimensions of the multilayer ceramic capacitor 1 along its length L are 1 / 3 and 1 / 2 The WT cross section is exposed. Then, using a VHX5000 from Keyence Corporation, the region between the edges of the first internal electrode layer 31 and the second internal electrode layer 32 in the width direction W and the side surface of the laminate 10 is observed or measured with respect to the obtained cross-section at a magnification that allows observation of the outermost internal electrode layer in the stacking direction T and allows observation of the edges in the width direction of each layer.

[0059] Si is deposited at the ends in the width direction W aligned with the first side surface WS1 side of the internal electrode layer 30, and Si is deposited in the second side gap WG2 between the end E2L closest to the second side surface WS2 and the second side surface WS2 among the ends in the width direction aligned with the second side surface WS2 side of the internal electrode layer 30. Si may also be deposited at the ends in the width direction aligned with the second side surface WS2 side of the internal electrode layer 30.

[0060] The presence of Si segregation at the widthwise edge W of the internal electrode layer 30 improves the flexural strength of the multilayer ceramic capacitor 1. The amount of Si segregation in the widthwise edge W on the second side surface WS2 of the internal electrode layer 30 may be less than that at the widthwise edge W on the first side surface WS1.

[0061] (Manufacturing method) Next, an example of a method for manufacturing the multilayer ceramic capacitor 1 described above will be explained. First, a dielectric sheet for the dielectric layer 20 and a conductive paste for the internal electrode layer 30 are prepared. The dielectric sheet and conductive paste contain a binder and a solvent. Known materials can be used as the binder and solvent.

[0062] Next, an internal electrode pattern is formed on the dielectric sheet by printing a conductive paste onto the dielectric sheet, for example, in a predetermined pattern. Screen printing or gravure printing can be used as methods for forming the internal electrode pattern.

[0063] Next, a predetermined number of dielectric sheets for the second outer layer 102, which do not have the internal electrode pattern printed on them, are stacked. On top of that, dielectric sheets for the inner layer 100, which have the internal electrode pattern printed on them, are stacked sequentially. On top of that, a predetermined number of dielectric sheets for the first outer layer 101, which do not have the internal electrode pattern printed on them, are stacked. This completes the production of the laminated sheet.

[0064] Next, the laminated sheets are pressed in the lamination direction using means such as a hydrostatic press to produce a laminated block. Then, the laminated block is cut to a predetermined size to cut out laminated chips 10T.

[0065] As shown in Figure 6, the laminated chip 10T is formed by alternately stacking multiple material sheets, one on which a conductive pattern 131 forming the first internal electrode layer 31 and the other on which a conductive pattern 132 forming the second internal electrode layer 32 is printed, on the surface of a ceramic green sheet 120 for lamination which will become the dielectric layer 20. The stacking is then cut along the stacking direction T to form a roughly rectangular parallelepiped shape as shown in the figure.

[0066] On one end face 10Ta of the laminated chip 10T, a conductive pattern 131 is exposed, and on the other end face, a conductive pattern 132 is exposed.

[0067] On the first side surface 10Tb1 of the laminated chip 10T, all ends in the width direction W of the laminated conductive patterns 131 and 132 are arranged along the stacking direction T on the cut-out and exposed first side surface 10Tb1. As a result, on the first side surface WS1 side of the multilayer ceramic capacitor 1, the edges of the multiple internal electrode layers 30 in the width direction W can be arranged so that they are aligned within a range of 10 μm in the width direction W. On the other hand, on the second side surface 10Tb2 of the laminated chip 10T, the ends of the laminated conductive patterns 131 and 132 in the width direction W are not cut and are not exposed on the second side surface 10Tb2. Therefore, the ends of the conductive patterns 131 and 132 in the width direction W are uneven compared to the first side surface 10Tb1. Therefore, as shown in Figure 5, the maximum distance L3 in the width direction W between the ends of the internal electrode layer 30 aligned on the first side surface WS1 is smaller than the maximum distance L4 in the width direction W between the ends of the internal electrode layer 30 aligned on the second side surface WS2.

[0068] On the first side surface 10Tb1 and the second side surface 10Tb2 of the laminated chip 10T, covering ceramic green sheets forming the first side gap WG1 and the second side gap WG2 are respectively attached, so as to cover them, thereby forming a side covering portion SC. As a result, the ends of the conductive patterns 131 and 132 in the width direction W on the first side surface 10Tb1 of the laminated chip 10T are covered by the side covering portion SC.

[0069] By making the thickness of the covering ceramic green sheet attached to the first side surface 10Tb1 and the second side surface 10Tb2 of the laminated chip 10T sufficiently thin, the thickness of the first side gap portion WG1 and the second side gap portion WG2 can be reduced.

[0070] The distance L1 between the end E1L of the inner electrode layer 30 that is closest to the first side surface WS1 in the width direction W on the first side surface WS1 and the first side surface WS1 is preferably 5 μm to 40 μm, and particularly preferably 5 μm to 15 μm. This makes it possible to increase the distance between the electrode facing portion W30 and the mounting surface, thereby suppressing the occurrence of "squeaking" without reducing capacitance.

[0071] Furthermore, on the second side surface 10Tb2 of the laminated chip 10T, the edges of the conductive patterns 131 and 132 in the width direction W are not exposed, so there is no need to protect the edges, and it is not necessarily required to attach a ceramic green sheet for covering.

[0072] The ceramic green sheet for coating has a different composition from the ceramic green sheet 120 for multilayering, which forms the dielectric layer 20. This allows for differences in the concentration of specific elements, or the provision of multiple regions with different concentrations of specific elements within the ceramic green sheet for coating. For example, if the concentration of Ba contained in the ceramic green sheet 120 is higher than the concentration of Ba in the ceramic green sheet for coating, it is possible to suppress the intrusion of moisture into the inner layer 100 of the multilayer ceramic capacitor 1. In particular, in the embodiment of the present invention, since the thickness in the width direction W of the first side gap WG1 is thin, this is an effective means of suppressing the intrusion of moisture and improving reliability.

[0073] As a result, an unfired laminated chip 10S with a side covering portion SC is formed, as shown in Figure 7. Next, the unfired laminated chip 10S with the side coating SC is fired to produce the laminate 10. The firing temperature is preferably between 900°C and 1400°C, although this depends on the dielectric and internal electrode materials.

[0074] Next, the conductive paste for the first base electrode layer 415 is applied to the first end face LS1 of the laminate 10 by dipping it into a conductive paste, which is the electrode material for the base electrode layer, using the dipping method. Similarly, the conductive paste for the second base electrode layer 425 is applied to the second end face LS2 of the laminate 10 by dipping it into a conductive paste, which is the electrode material for the base electrode layer, using the dipping method. Subsequently, the first base electrode layer 415 and the second base electrode layer 425 are formed by firing these conductive pastes. The firing temperature is preferably 600°C or higher and 900°C or lower.

[0075] As described above, the first and second base electrode layers 415 and 425, which are resin layers, may be formed by applying a conductive paste containing conductive particles and a thermosetting resin by a coating method and firing it, or the first and second base electrode layers 415 and 425, which are thin films, may be formed by a thin film formation method such as sputtering or vapor deposition.

[0076] Subsequently, a first plating layer 416 is formed on the surface of the first base electrode layer 415 to form the first external electrode 41, and a second plating layer 426 is formed on the surface of the second base electrode layer 425 to form the second external electrode 42. Through these steps, the multilayer ceramic capacitor 1 described above is obtained. [Explanation of Symbols]

[0077] 1. Multilayer ceramic capacitor 10 Laminate 20 Dielectric layer 30 Internal electrode layer 31 First internal electrode layer 311 First counter electrode section 312 First extraction electrode section 32 Second internal electrode layer 321 Second counter electrode section 322 Second extraction electrode section 40 External electrode 41 First external electrode 415 First Underlay Electrode Layer 416 First plating layer 42 Second external electrode 425 Second base electrode layer 426 Second plating layer 100 Inner layer 101 First outer layer 102 Second outer layer L30 Electrode facing part LG1 First end gap section LG2 Second end gap section W30 Electrode facing part WG1 First side gap section WG2 Second side gap section L (Length direction) T Stacking direction W (width direction) LS1 First end face LS2 Second end face TS1 First main surface TS2 Second main surface WS1 First Aspect WS2 Second Aspect

Claims

1. A substantially rectangular parallelepiped laminate comprising a plurality of dielectric layers and a plurality of internal electrode layers stacked alternately in the stacking direction, having a first main surface and a second main surface facing each other in the stacking direction, a first side surface and a second side surface facing each other in the width direction perpendicular to the stacking direction, and a first end surface and a second end surface facing each other in the length direction perpendicular to the stacking direction and the width direction, A pair of external electrodes are provided at both ends of the laminate in the longitudinal direction, positioned to cover at least the first end face and the second end face respectively, and connected to the internal electrode layer. Equipped with, The distance between the first side surface and the first side surface is smaller than the distance between the second side surface and the second side surface. A multilayer ceramic capacitor in which the maximum distance in the width direction between the ends in the width direction of the plurality of internal electrode layers arranged on the first side surface is smaller than the maximum distance in the width direction between the ends in the width direction of the plurality of internal electrode layers arranged on the second side surface.

2. A substantially rectangular parallelepiped laminate comprising a plurality of dielectric layers and a plurality of internal electrode layers stacked alternately in the stacking direction, having a first main surface and a second main surface facing each other in the stacking direction, a first side surface and a second side surface facing each other in the width direction perpendicular to the stacking direction, and a first end surface and a second end surface facing each other in the length direction perpendicular to the stacking direction and the width direction, A pair of external electrodes are provided at both ends of the laminate in the longitudinal direction, positioned to cover at least the first end face and the second end face respectively, and connected to the internal electrode layer. Equipped with, The distance between the first side surface and the first side surface is smaller than the distance between the first side surface and the second side surface, among the widthwise ends of the second side surface of the plurality of internal electrode layers. A multilayer ceramic capacitor in which the maximum distance in the width direction between the ends in the width direction of the plurality of internal electrode layers arranged on the first side surface is smaller than the maximum distance in the width direction between the ends in the width direction of the plurality of internal electrode layers arranged on the second side surface.

3. The multilayer ceramic capacitor according to claim 1 or 2, wherein the maximum distance in the width direction between the width direction ends of the plurality of internal electrode layers that are aligned on the first side surface is 10 μm or less.

4. Si is deposited at the widthwise ends of the plurality of internal electrode layers that are aligned on the first side surface, The multilayer ceramic capacitor according to claim 1 or 2, wherein Si is deposited between the end of the widthwise end of the plurality of internal electrode layers that is aligned on the second side surface and the second side surface.

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