Semiconductor equipment

Abstract

A semiconductor device (101) comprises semiconductor elements (11, 12) and heat sinks (21, 22) on which the semiconductor elements are mounted. In addition, the semiconductor device (101) also comprises: a core layer (31) provided with through holes (311) and in which the heat sinks are disposed; a build-up layer (32) that is provided facing the top surface of the core layer and one surface of each heat sink and has wirings (33, 34) including a portion electrically connected to the semiconductor elements; and a heat dissipation / insulating layer (40) in contact with the opposite surface of the core layer and the reverse surface of each heat sink.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application is based on Japanese Patent Application No. 2023-180472 filed on October 19, 2023 and Japanese Patent Application No. 2024-172789 filed on October 1, 2024, and the entire content of the base applications is incorporated herein by reference. Technical Field

[0002] The present disclosure relates to a semiconductor device. Background Art

[0003] Conventionally, as an example of a semiconductor device, there is a substrate with a built-in MOS transistor disclosed in Patent Document 1. The substrate with a built-in MOS transistor has four insulating resin layers and wiring layers located on each surface of the insulating resin layers. Two MOS transistors are embedded in the third insulating resin layer. An electrode formed on the lower surface of the MOS transistor is connected to the wiring layer via a via conductor provided penetrating the first and second insulating resin layers. Further, an electrode formed on the upper surface of the MOS transistor is connected to another wiring layer via a via conductor provided penetrating the third insulating resin layer. Prior Art Documents Patent Documents

[0004] Patent Document 1 Japanese Unexamined Patent Publication No. 2020-53593 Summary of the Invention

[0005] Incidentally, in the substrate with a built-in MOS transistor, both the lower electrode and the upper electrode are connected to the wiring layer via via conductors. Therefore, the substrate with a built-in MOS transistor has a problem of insufficient heat dissipation. Further, from the above viewpoint or other viewpoints not mentioned, further improvement is required for semiconductor devices.

[0006] The purpose of the disclosure is to provide a semiconductor device with improved heat dissipation.

[0007] The semiconductor device disclosed herein is A semiconductor device comprising a semiconductor element, A heat sink with semiconductor elements mounted on its surface, A core layer having one side and the opposite side of the first side, with a through hole extending from one side to the opposite side, and a heat sink positioned in the through hole. A build-up layer having wiring that includes a portion electrically connected to the semiconductor element, provided opposite the surface and one surface, On the opposite side and the back of the heatsink Without going through beer It is equipped with a heat-dissipating insulating layer that is in contact with it.

[0008] Thus, the semiconductor device includes a heat-dissipating insulating layer that contacts the back surface of the heat sink and the opposite surface of the core layer. Therefore, the semiconductor device can improve heat dissipation compared to a configuration in which the heat sink and the heat-dissipating insulating layer are connected via vias.

[0009] The semiconductor device disclosed herein is A semiconductor device comprising a plurality of semiconductor elements, A heat sink is provided for each semiconductor element, with the semiconductor element mounted on the surface side, Each heatsink has a heatsink on the back Without going through beer The heat dissipation insulating layer in contact with, The back metal layer in contact with the side opposite to the heat sink in the heat dissipation insulating layer, A core layer having one face and the opposite face, with multiple through holes extending from one face to the opposite face, and each through hole containing a pair of semiconductor elements, a heat sink, a heat dissipation insulating layer, and a back metal layer, The device comprises a surface and a build-up layer provided opposite one surface, having wiring that includes a portion electrically connected to the semiconductor element.

[0010] Thus, the semiconductor device comprises a heat-dissipating insulating layer in contact with the back surface of the heat sink, and a back metal layer in contact with the side of the heat-dissipating insulating layer opposite to the heat sink. Therefore, the semiconductor device can improve heat dissipation compared to a configuration in which the heat sink and the heat-dissipating insulating layer are connected via vias.

[0011] The various embodiments disclosed in this specification employ different technical means to achieve their respective purposes. The claims and the reference numerals in parentheses in this section are illustrative in their correspondence with the embodiments described later and are not intended to limit the technical scope. The purposes, features, and effects disclosed in this specification will become clearer by referring to the subsequent detailed description and the accompanying drawings. [Brief explanation of the drawing]

[0012] [Figure 1] This is a plan view showing the schematic configuration of the semiconductor device in the first embodiment. [Figure 2] This is a cross-sectional view showing the schematic configuration of a semiconductor device. [Figure 3] This is a cross-sectional view showing the schematic configuration of the heat sink and semiconductor element. [Figure 4] This is a partial cross-sectional view showing the schematic configuration of a semiconductor device. [Figure 5] This is a circuit diagram using a semiconductor device. [Figure 6] This is a cross-sectional view showing the process of mounting semiconductor elements onto a heat sink. [Figure 7] This is a cross-sectional view showing the process of embedding semiconductor elements into a wiring board. [Figure 8] This is a cross-sectional view showing the process of forming wiring on a wiring board. [Figure 9] This is a cross-sectional view showing the schematic configuration of the heat sink and semiconductor element in Modified Example 1. [Figure 10] This is a plan view showing the schematic configuration of the heat sink and semiconductor element in modified example 2. [Figure 11] This is a cross-sectional view along the line XI-XI in Figure 10. [Figure 12] It is a cross-sectional view taken along line XII-XII in FIG. 10. [Figure 13] It is a plan view showing a schematic configuration of the heat sink of Modification 3. [Figure 14] It is a plan view showing a schematic configuration of the core layer of Modification 3. [Figure 15] It is a plan view showing a schematic configuration of the heat sink and the core layer of Modification 3. [Figure 16] It is a cross-sectional view showing a schematic configuration of the heat sink and the core layer of Modification 4. [Figure 17] It is a cross-sectional view taken along line XVII-XVII in FIG. 16. [Figure 18] It is a plan view showing a schematic configuration of the semiconductor device according to the second embodiment. [Figure 19] It is a cross-sectional view showing a schematic configuration of the semiconductor device according to the third embodiment. [Figure 20] It is a cross-sectional view showing a schematic configuration of the semiconductor device according to the fourth embodiment. [Figure 21] It is a cross-sectional view showing a schematic configuration of the semiconductor device according to the fifth embodiment. [Figure 22] It is a cross-sectional view showing a schematic configuration of the semiconductor device according to the sixth embodiment. [Figure 23] It is a cross-sectional view showing a schematic configuration of the heat sink and the semiconductor element of Modification 5. [Figure 24] It is a cross-sectional view showing a schematic configuration of the heat sink and the semiconductor element of Modification 6. [Figure 25] It is a cross-sectional view showing a schematic configuration of the semiconductor device according to the seventh embodiment. [Figure 26] It is a cross-sectional view showing a schematic configuration of the semiconductor device according to the eighth embodiment. [Figure 27] It is a cross-sectional view showing a schematic configuration of the semiconductor device according to the ninth embodiment. [Figure 28] It is a circuit diagram to which the semiconductor device according to the tenth embodiment is applied. [Figure 29] It is a cross-sectional view showing a schematic configuration of the semiconductor device according to the tenth embodiment. [Figure 30]This is a circuit diagram applying the mechanism of the 11th embodiment. [Figure 31] This is a cross-sectional view showing the schematic configuration of the semiconductor device in the 11th embodiment. [Figure 32] This is a circuit diagram applying the semiconductor device of the 12th embodiment. [Figure 33] This is a cross-sectional view showing the schematic configuration of a semiconductor device in the twelfth embodiment. [Figure 34] This is a cross-sectional view showing the schematic configuration of a semiconductor device in a modified example. [Figure 35] This is a cross-sectional view showing the schematic configuration of the heatsink in a modified example. [Figure 36] This is an enlarged cross-sectional view of section XXXVI in Figure 34. [Figure 37] This is a cross-sectional view showing the schematic configuration of a semiconductor device in a modified example. [Figure 38] This is a cross-sectional view showing the schematic configuration of a semiconductor device in a modified example. [Figure 39] This is a cross-sectional view showing the manufacturing process of a semiconductor device in a modified example. [Figure 40] This is a cross-sectional view showing the schematic configuration of a semiconductor device in a modified example. [Figure 41] This is an enlarged cross-sectional view showing the schematic configuration of a semiconductor device in a modified example. [Figure 42] This is a cross-sectional view showing the schematic configuration of the semiconductor device before cutting in a modified example. [Figure 43] This is a cross-sectional view showing the schematic configuration of the core layer in a modified example. [Figure 44] This is a plan view showing the schematic configuration of the core layer in a modified example. [Figure 45] This is a plan view showing the schematic configuration of the core layer in a modified example. [Figure 46] This is a cross-sectional view showing the schematic configuration of the core layer in a modified example. [Figure 47] This is a cross-sectional view showing the schematic configuration of a semiconductor device in a modified example. [Figure 48] This is a cross-sectional view showing a method for manufacturing a heat sink in a modified example. [Figure 49] This is a plan view showing the schematic configuration of the heat sink in a modified example. [Figure 50] This is a cross-sectional view along the LL line in Figure 49. [Figure 51] This is a cross-sectional view along the LI-LI line in Figure 49. [Figure 52] This is a plan view showing the schematic configuration of the heat sink in a modified example. [Figure 53] This is a cross-sectional view along the line LIII-LIII in Figure 52. [Figure 54] This is a cross-sectional view along the LIV-LIV line in Figure 52. [Figure 55] This is a cross-sectional view showing the schematic configuration of the semiconductor device in the 13th embodiment. [Figure 56] This is a cross-sectional view showing the process of embedding semiconductor elements into a wiring board. [Figure 57] This is a cross-sectional view showing the process of forming wiring on a wiring board. [Figure 58] This is a cross-sectional view showing the schematic configuration of the heatsink in a modified example. [Figure 59] This is a cross-sectional view showing the schematic configuration of the heatsink in a modified example. [Figure 60] This is a cross-sectional view showing the schematic configuration of a semiconductor device in a modified example. [Figure 61] This is a cross-sectional view showing a method for manufacturing a semiconductor device in a modified example. [Figure 62] This is a cross-sectional view showing a method for manufacturing a semiconductor device in a modified example. [Figure 63] This is a cross-sectional view showing the schematic configuration of the heatsink in a modified example. [Figure 64] This is a cross-sectional view along the LXIV-LXIV line in Figure 63. [Figure 65] This is a cross-sectional view showing the schematic configuration of the heatsink in a modified example. [Figure 66] This is a cross-sectional view along the LXVI-LXVI line in Figure 65. [Figure 67] This is a cross-sectional view showing the schematic configuration of a semiconductor device in a modified example. [Figure 68] This is a plan view showing the schematic configuration of a semiconductor element in a modified example. [Figure 69] This is a cross-sectional view showing a method for manufacturing a semiconductor device in a modified example. [Figure 70] This is a plan view showing the schematic configuration of the core layer in a modified example. [Figure 71] This is a cross-sectional view along the line LXXI-LXXI in Figure 70 with the heatsink attached. [Figure 72] This is a cross-sectional view of a heat sink with a heat dissipation insulating layer and a build-up layer. [Figure 73] This is a partial cross-sectional view showing the schematic configuration of the heatsink in a modified example. [Figure 74] This is a partial cross-sectional view showing the modified form with the build-up layer and heat-dissipating insulating layer provided. [Figure 75] This is a partial plan view showing the schematic configuration of the heatsink in a modified example. [Figure 76] This is a cross-sectional view showing the schematic configuration of the semiconductor device in the 14th embodiment. [Figure 77] This is a cross-sectional view showing the manufacturing process of a semiconductor device according to the 14th embodiment. [Figure 78] This is a cross-sectional view showing the schematic configuration of a semiconductor device in a modified example. [Figure 79] This is a partial cross-sectional view showing the schematic configuration of a semiconductor element in a modified example. [Figure 80] This is a cross-sectional view showing the schematic configuration of a semiconductor device in a modified example. [Figure 81] This is a cross-sectional view along the line LXXXI-LXXXI in Figure 80. [Figure 82] This is a plan view showing the schematic configuration of a semiconductor device in a modified example. [Figure 83] This is a cross-sectional view along the line LXXXIII-LXXXIII in Figure 82. [Figure 84] This is a partial cross-sectional view showing the schematic configuration of a semiconductor device in a modified example. [Figure 85] This is a partial cross-sectional view showing the schematic configuration of a semiconductor device in a modified example. [Figure 86] This is a plan view showing the heat sink, core layer, and semiconductor element in a modified example. [Figure 87] This is a plan view showing the wiring of the first layer LA1 in a modified example. [Figure 88] This is a plan view showing the wiring of the second layer LA2 in a modified example. [Figure 89] This is a plan view showing the overlapping wiring in a modified example. [Figure 90] This is a cross-sectional view along the XC-XC line in Figure 89. [Figure 91] This is a cross-sectional view along the XCI-XCI line in Figure 89. [Figure 92] This is a cross-sectional view along the XCII-XCII line in Figure 89. [Figure 93] This is a plan view showing the heat sink, core layer, and semiconductor element in a modified example. [Figure 94] This is a plan view showing the wiring in a modified example. [Figure 95] This is a cross-sectional view along the XCV-XCV line in Figure 94. [Figure 96] This is a plan view showing the heat sink, core layer, and semiconductor element in a modified example. [Figure 97] This is a plan view showing the wiring of the first layer LA1 in a modified example. [Figure 98] This is a plan view showing the wiring of the second layer LA2 in a modified example. [Figure 99] This is a plan view showing the overlapping wiring in a modified example. [Figure 100] This is a cross-sectional view along the CC line in Figure 99. [Figure 101] This is a cross-sectional view along the CI-CI line in Figure 99. [Figure 102] This is a cross-sectional view showing the schematic configuration of the integrated substrate in a modified example. [Figure 103] This is a plan view showing the schematic configuration of a semiconductor device in a modified example. [Figure 104] This is a plan view showing the schematic configuration of a semiconductor device in a modified example. [Figure 105]This is a plan view showing the schematic configuration of the core layer in a modified example. [Figure 106] This is a cross-sectional view along the CVI-CVI line in Figure 105. [Figure 107] This is a plan view showing the schematic configuration of the heat sink in a modified example. [Modes for carrying out the invention]

[0013] In the following, several embodiments for implementing this disclosure will be described with reference to the drawings. In each embodiment, parts corresponding to matters described in a prior embodiment may be denoted by the same reference numerals, and redundant descriptions may be omitted. If only a part of the configuration is described in each embodiment, other parts of the configuration can be referred to and applied to other embodiments described in advance.

[0014] (First Embodiment) The semiconductor device 101 of the first embodiment will be described with reference to Figures 1 to 8. The semiconductor device 101 can be applied to, for example, a power converter. Furthermore, the semiconductor device 101 can be applied to an in-vehicle transformer or charger. In this embodiment, as an example, a semiconductor device 101 comprising two semiconductor elements 11 and 12 is used. As shown in Figure 5, the two semiconductor elements 11 and 12 are connected in series. The first semiconductor element 11 is an upper arm element. The second semiconductor element 12 is a lower arm element. However, the semiconductor device 101 only needs to comprise at least one semiconductor element.

[0015] <Overall configuration of semiconductor device> The semiconductor device 101 comprises semiconductor elements 11 and 12, heat sinks 21 and 22, a wiring board 30, a heat dissipation insulating layer 40, a back metal layer 50, and the like. The semiconductor device 101 has a structure in which the semiconductor elements 11 and 12 and the heat sinks 21 and 22 are embedded in the wiring board 30. The semiconductor device 101 can also be called a semiconductor package or a power semiconductor package.

[0016] The semiconductor elements 11 and 12 generate heat when they operate. Therefore, the semiconductor device 101 is provided with heat sinks 21 and 22. A heat dissipation insulating layer 40 is bonded to the heat sinks 21 and 22. A back metal layer 50 is bonded to the opposite side of the heat dissipation insulating layer 40 from the side to which the heat sinks 21 and 22 are bonded. The semiconductor device 101 is provided with the back metal layer 50 as part of the portion exposed to the outside.

[0017] Therefore, the heat from the semiconductor elements 11 and 12 is transferred to the heat dissipation insulating layer 40 and the back metal layer 50 via the heat sinks 21 and 22. Then, the heat from the semiconductor elements 11 and 12 is dissipated from the back metal layer 50 to the outside of the semiconductor device 101.

[0018] <Semiconductor elements> The first semiconductor element 11 and the second semiconductor element 12 have the same configuration. Therefore, the following explanation will use the first semiconductor element 11. Furthermore, it will also be simply referred to as semiconductor element 11. These points are the same for other variations as well.

[0019] The semiconductor element 11 can be, for example, a MOSFET, an IGBT, or a transistor. It can also be said that the semiconductor element 11 can be a semiconductor switching element. The semiconductor element 11 can also be a power element. Here, a vertical semiconductor element with a vertical structure is used as the semiconductor element 11. The semiconductor element 11 can use Si, SiC, GaN, etc. as its main components. That is, the semiconductor element 11 can be, for example, a Si-IGBT, a SiC-MOSFET, or a GaN-transistor. Note that the IGBT may also be an RC-IBGT.

[0020] Furthermore, the semiconductor element 11 can also be a lateral semiconductor element having a lateral structure. Examples of lateral semiconductor elements include GaN-based lateral transistors with GaN as the main component. In the lateral semiconductor element, the gate electrode, source electrode, drain electrode, etc., are formed on the element surface S12, which will be explained later. Also, for stable operation, the back surface potential of the lateral semiconductor element is connected to the source electrode on the element surface S12 side. Similarly, in a configuration that includes a lateral semiconductor element, the wiring board 30 requires wiring from the heat sink 21 to the element surface S12.

[0021] Furthermore, in this embodiment, the same elements are used as the first semiconductor element 11 and the second semiconductor element 12. However, the first semiconductor element 11 and the second semiconductor element 12 may be different. For example, the first semiconductor element 11 and the second semiconductor element 12 may be different in size or of type.

[0022] As shown in Figure 3, the semiconductor element 11 has an element-facing surface S11 that faces the heat sink 21 (bottom 211) and an element surface S12 that is the opposite surface of the element-facing surface S11. For example, the semiconductor element 11 has an element-facing surface S11 which is a flat surface and an element surface S12 which is a flat surface.

[0023] The semiconductor element 11 has electrodes on the element-facing surface S11 and the element surface S12. The semiconductor element 11 has a gate electrode, a source electrode, and a Kelvin source electrode on the element surface S12. The semiconductor element 11 also has a drain electrode on the element-facing surface S11. The surface of each electrode is coated with copper plating or the like to improve connectivity with vias 34 and the like.

[0024] <Heat sink> As shown in Figures 1 and 2, the semiconductor device 101 is equipped with two heat sinks 21 and 22. The first heat sink 21 is on which the first semiconductor element 11 is mounted. The second heat sink 22 is on which the second semiconductor element 12 is mounted. In this way, the two heat sinks 21 and 22 are individually equipped with the two semiconductor elements 11 and 12.

[0025] Heatsinks 21 and 22 have the same configuration. Therefore, the following explanation will use the first heatsink 21. The first heatsink 21 will also be simply referred to as heatsink 21. These points are the same for other variations as well.

[0026] As shown in Figures 1, 2, and 3, the heat sink 21 has a heat sink surface S22 and a heat sink opposite surface S21 which is the opposite side of the heat sink surface S22. The heat sink surface S22 and the heat sink opposite surface S21 are, for example, flat surfaces. The heat sink surface S22 corresponds to the front surface of the heat sink 21. The heat sink opposite surface S21 corresponds to the back surface of the heat sink 21. The heat sink surface S22 is also referred to as the front surface S22, and the heat sink opposite surface S21 is also referred to as the back surface S21.

[0027] The heat sink 21 is a plate-shaped or block-shaped component. The heat sink 21 is mainly composed of metals such as aluminum or copper. The heat sink 21 is made of a material with a higher thermal conductivity than the core layer 31, which will be explained later.

[0028] As shown in Figure 3, the heat sink 21 is provided with a recess 213 that is recessed relative to the heat sink surface S22. The recess 213 is the area where the semiconductor element 11 is mounted. The recess 213 is formed by a bottom portion 211 and an annular side wall 212. The side wall 212 is a surface that is continuous with the bottom portion 211 and the heat sink surface S22. The bottom portion 211 is, for example, a flat surface. The state in which the semiconductor element 11 is mounted in the recess 213 can also be called the element mounting state.

[0029] As shown in Figure 2, the heatsink 21 has a thickness similar to that of the core layer 31. In other words, the heatsink 21 is sufficiently thicker than the pattern wiring 33, which will be explained later. Therefore, the heatsink 21 has a larger heat capacity than the pattern wiring 33. Also, the heatsink 21 is thicker than the pattern wiring 33.

[0030] The thickness of the heatsink 21 differs between the area where the recess 213 is provided and the surrounding area. The thickness of the surrounding area is sufficiently greater than the thickness of the pattern wiring 33. Also, the thickness of the area where the recess 213 is provided is sufficiently greater than the thickness of the pattern wiring 33. The thickness of the area where the recess 213 is provided corresponds to the distance between the bottom 211 and the opposite surface S21 of the heatsink. The thickness of the surrounding area corresponds to the distance between the heatsink surface S22 and the opposite surface S21 of the heatsink.

[0031] The thickness here is the length along a virtual straight line perpendicular to the heat sink surface S22 and the heat sink opposite surface S21. This virtual straight line coincides with the thickness direction of the heat sink 21 and the depth direction of the recess 213. The thickness direction of the heat sink 21 can also be called the plate thickness direction. The thickness direction of the heat sink 21 can also be called the stacking direction of the semiconductor elements 11 relative to the heat sink 21. The direction perpendicular to the stacking direction is also called the planar direction.

[0032] The recess 213 is on which the semiconductor element 11 is mounted via a connecting member 60. The semiconductor element 11 is electrically connected to the heat sink 21 via the connecting member 60. The connecting member 60 connects the drain electrode of the semiconductor element 11 to the heat sink 21. The connecting member 60 is a conductive bonding material. The connecting member 60 can be made of, for example, a metal sintered material such as silver or copper. The connecting member 60 can also be called a die attach material or die bonding material. The recess 213 has an opening area such that the side wall 212 and the semiconductor element 11 do not come into contact.

[0033] As will be explained later, in the manufacturing method of the semiconductor device 101, the semiconductor element 11 is mounted in the recess 213 by applying pressure (pressing) with the connecting member 60 placed between the semiconductor element 11 and the bottom 211 (die attach bonding process). Therefore, it is preferable that the depth of the recess 213 be shallower than the combined thickness of the semiconductor element 11 and the connecting member 60. This allows for appropriate pressure to be applied to the semiconductor element 11.

[0034] Therefore, in the mounted state, it is preferable that the element surface S12 is at a higher position than the heat sink surface S22. In other words, the semiconductor element 11 is mounted in the recess 213 such that the element surface S12 protrudes from the heat sink surface S22. Alternatively, in the mounted state, the element surface S12 may be on the same virtual plane as the heat sink surface S22. The virtual plane is a plane that is substantially parallel to the element surface S12 and the heat sink surface S22.

[0035] The thickness of the semiconductor element 11 corresponds to the distance between the element surface S12 and the element-facing surface S11. Alternatively, the thickness of the semiconductor element 11 can be said to be the length along the aforementioned hypothetical straight line.

[0036] <Wiring board> As shown in Figures 1 and 2, the wiring board 30 comprises a core layer 31, a build-up layer 32, and a solder resist 35. The core layer 31 is provided with a heat dissipation insulating layer 40. Furthermore, the heat dissipation insulating layer 40 is provided with a back metal layer 50. Therefore, it can also be said that the wiring board 30 comprises a heat dissipation insulating layer 40 and a back metal layer 50.

[0037] In Figure 1, the parts exposed from the solder resist 35 are shown with solid lines, and the parts hidden by the solder resist 35 are shown with dashed lines. Figure 2 is a diagram showing cross-sections of the semiconductor elements 11, 12, heat sinks 21, 22, core layer 31, build-up layer 32, pads 331-335, and solder resist 35.

[0038] As shown in Figure 2, the core layer 31 has a core surface S32 and a core opposite surface S31 which is the opposite surface of the core surface S32. The core surface S32 corresponds to one surface. The core opposite surface S31 corresponds to the opposite surface. The core layer 31 is mainly composed of an electrically insulating material. For example, the core layer 31 is composed of multiple electrically insulating resin layers laminated together. The resin layers are as thick as, or thicker than, the pattern wiring 33 which will be described later. Therefore, the core layer 31 is a material that is sufficiently thicker than the pattern wiring 33. The thickness of the core layer 31 is the length in the same direction as the thickness of the heat sink 21. Note that the core layer 31 may be a single electrically insulating resin material having a thickness similar to that of multiple laminated resin layers. The core layer 31 can also be called the core material.

[0039] The core layer 31 has through holes 311 extending from the core surface S32 to the opposite core surface S31. The through holes 311 are the regions where the heat sinks 21 and 22 are placed. The through holes 311 have an opening area sufficient to form a gap between them and the heat sinks 21 and 22.

[0040] The core layer 31 is provided with two through-holes 311, each for which two heat sinks 21 and 22 are individually positioned. In other words, the core layer 31 is provided with a through-hole 311 for which the first heat sink 21 is positioned and a through-hole 311 for which the second heat sink 22 is positioned. Thus, the core layer 31 is provided with the same number of through-holes 311 as the heat sinks 21 and 22. The first heat sink 21 with the first semiconductor element 11 mounted on it and the second heat sink 22 with the second semiconductor element 12 mounted on it are positioned in the through-holes 311.

[0041] As shown in Figure 2, a build-up layer 32 is provided on the core surface S32. The build-up layer 32 is provided facing the core surface S32 and the heat sink surface S22. Furthermore, the build-up layer 32 is also provided facing the element surface S12.

[0042] The build-up layer 32 includes an electrically insulating resin portion and conductive wiring. The build-up layer 32 is provided for drawing out the wiring. The build-up layer 32 can also be called the wiring layer. Hereinafter, the resin portion of the build-up layer 32 will be simply referred to as the resin portion.

[0043] The resin portion is provided in contact with the element surface S12, the heat sink surface S22, and the core surface S32. The resin portion is also provided in the gap between the heat sinks 21, 22 and the core layer 31. In this gap, the resin portion is in contact with the heat sinks 21, 22 and the core layer 31. Therefore, the resin portion covers the semiconductor elements 11, 12 and the heat sinks 21, 22. The resin portion has a layer surface S33. The layer surface S33 is a surface that is substantially parallel to the core surface S32 and the element surface S12.

[0044] As shown in Figures 1 and 2, the wiring includes patterned wiring 33 and vias 34. The patterned wiring 33 is provided on the layer surface S33. The patterned wiring 33 is provided facing the core surface S32 and the element surface S12. In other words, the patterned wiring 33 includes a portion facing the core surface S32 and a portion facing the element surface S12. The patterned wiring 33 is provided in multiple locations. That is, the patterned wiring 33 is a patterned thin film of copper or the like. The patterned wiring 33 is part of the layer wiring. The patterned wiring 33 corresponds to the main wiring. The patterned wiring 33 and vias 34 correspond to portions electrically connected to the semiconductor element 11.

[0045] The pattern trace 33 is covered with solder resist 35 with a portion exposed. The pattern trace 33 includes pads 331 to 337, which are the parts exposed from the solder resist 35. In other words, the pattern trace 33 includes P pad 331, first gate pad 332, O pad 333, second gate pad 334, N pad 335, first Kelvin source pad 336, and second Kelvin source pad 337.

[0046] As shown in Figure 5, the P pad 331 is a high-potential terminal. The N pad 335 is a low-potential terminal. The O pad 333 is an output terminal. Each of the pads 331 to 337 is electrically connected to, for example, a circuit board provided outside the semiconductor device 101. These pads 331 to 337 can also be called electrodes or external connection parts. The P pad 331, O pad 333, and N pad 335 can also be called power connection parts. The first gate pad 332, the second gate pad 334, the first Kelvin source pad 336, and the second Kelvin source pad 337 can also be called signal connection parts. Hereafter, the first gate pad 332, the second gate pad 334, the first Kelvin source pad 336, and the second Kelvin source pad 337 will be collectively referred to as the signal pad 332.

[0047] As shown in Figure 1, the pattern wiring 33 is divided into sections containing pads 331 to 337. The sections of the pattern wiring 33 containing pads 331 to 337 are described by replacing the pads 331 to 337 with the wiring section. That is, the section containing pad P 331 is described as the P wiring section. The section containing the first gate pad 332 is described as the first gate wiring section. The section containing O pad 333 is described as the O wiring section. The section containing the second gate pad 334 is described as the second gate wiring section. The section containing N pad 335 is described as the N wiring section. The section containing the first Kelvin source pad 336 is described as the first Kelvin source wiring section. The section containing the second Kelvin source pad 337 is described as the second Kelvin source wiring section.

[0048] The P-wiring section is provided facing the peripheral portion of the first semiconductor element 11 on the first heat sink 21. The P-wiring section is connected to the first heat sink 21 via vias 34. Here, an example is used in which the P-wiring section and the first heat sink 21 are connected by multiple vias 34. The P-wiring section is provided facing a portion of the heat sink surface S22.

[0049] The O-wiring section is provided extending from the source electrode of the first semiconductor element 11 to the periphery of the second semiconductor element 12 on the second heat sink 22. The O-wiring section is connected to the source electrode of the first semiconductor element 11 and the second heat sink 22 via vias 34. Here, an example is taken in which the O-wiring section and the source electrode are connected by multiple vias 34. Similarly, an example is taken in which the O-wiring section and the second heat sink 22 are connected by multiple vias 34. The O-wiring section is provided facing a portion of the heat sink surface S22.

[0050] In this way, the O-wiring section electrically connects the source electrode of the first semiconductor element 11 and the drain electrode of the second semiconductor element 12. In other words, the pattern wiring 33 electrically connects the first semiconductor element 11 and the second semiconductor element 12.

[0051] The N-circuit section is provided extending from the source electrode of the second semiconductor element 12 to outside the opposing region of the second semiconductor element 12. The N-circuit section is connected to the source electrode of the second semiconductor element 12 via vias 34. Here, an example is adopted in which the N-circuit section and the source electrode are connected by multiple vias 34.

[0052] The first gate wiring section is provided extending from the gate electrode of the first semiconductor element 11 to outside the opposing region of the first semiconductor element 11. The first gate wiring section is connected to the gate electrode of the first semiconductor element 11 via via 34. The second gate wiring section is provided extending from the gate electrode of the second semiconductor element 12 to outside the opposing region of the second semiconductor element 12. The second gate wiring section is connected to the gate electrode of the second semiconductor element 12 via via 34.

[0053] The first Kelvin source wiring section is provided extending from the Kelvin source electrode of the first semiconductor element 11 to outside the opposing region of the first semiconductor element 11. The first Kelvin source wiring section is connected to the Kelvin source electrode of the first semiconductor element 11 via via 34. The second Kelvin source wiring section is provided extending from the Kelvin source electrode of the second semiconductor element 12 to outside the opposing region of the second semiconductor element 12. The second Kelvin source wiring section is connected to the Kelvin source electrode of the second semiconductor element 12 via via 34.

[0054] As shown in Figure 1, the P pad 331, O pad 333, and N pad 335 are arranged biasedly in the same direction on the wiring board 30. That is, the P pad 331, O pad 333, and N pad 335 are arranged biasedly on one side of the wiring board 30. Furthermore, it is preferable that the via 34 for the drain electrode is provided in an area narrower than the width X1 of each semiconductor element 11, 12. This forms mutual inductance between the drain wiring and the source wiring, and reduces the total inductance.

[0055] The vias 34 for the drain electrode are the via 34 connected to the P wiring section and the via 34 connected to the second heat sink 22. The width direction of each semiconductor element 11, 12 coincides with the direction in which the two semiconductor elements 11, 12 are aligned.

[0056] Vias 34 are provided at multiple locations in the resin portion. The build-up layer 32 includes vias 34 electrically connected to the gate electrode, source electrode, and Kelvin source electrode of the first semiconductor element 11, and the gate electrode, source electrode, and Kelvin source electrode of the second semiconductor element 12. The build-up layer 32 also includes vias 34 electrically connected to the first heat sink 21 and the second heat sink 22. Each source electrode is connected to multiple vias 34. Similarly, each heat sink 21 and 22 is connected to multiple vias 34.

[0057] Thus, one wiring board 30 incorporates two semiconductor elements 11 and 12, and is provided with an O-wiring section that electrically connects the two semiconductor elements 11 and 12. Therefore, the semiconductor device 101 can shorten the O-wiring section that connects the two semiconductor elements 11 and 12. By shortening the O-wiring section, the semiconductor device 101 can reduce its inductance and improve the switching characteristics of the semiconductor elements 11 and 12.

[0058] Furthermore, the wiring board 30 can be said to have built-in heat sinks 21 and 22 on which the semiconductor elements 11 and 12 are mounted. Moreover, the two semiconductor elements 11 and 12 can be said to be built into a single semiconductor package.

[0059] As shown in Figure 2, a heat dissipation insulating layer 40 is provided on the core opposite surface S31 and the heat sink opposite surface S21. The heat dissipation insulating layer 40 is in contact with the core opposite surface S31 and the heat sink opposite surface S21. It can also be said that the heat dissipation insulating layer 40 is directly connected to the core opposite surface S31 and the heat sink opposite surface S21. The heat dissipation insulating layer 40 contains a filler with good thermal conductivity and an electrically insulating resin containing the filler. In other words, the heat dissipation insulating layer 40 contains a filler and an electrically insulating resin. The heat dissipation insulating layer 40 has high thermal conductivity and is an electrically insulating layer.

[0060] The heat dissipation insulating layer 40 is primarily provided to dissipate the heat transferred to the heat sinks 21 and 22. Furthermore, the heat dissipation insulating layer 40 is provided to electrically insulate the heat sinks 21 and 22 from the back metal layer 50 while reducing the thermal resistance between the heat sinks 21 and 22 and the back metal layer 50.

[0061] Thus, the wiring board 30 does not have a build-up layer containing wiring such as vias on the core-opposite side S31 of the core layer 31. In other words, the core layer 31 and the heat sinks 21 and 22 are connected to the heat dissipation insulating layer 40 without vias 34.

[0062] Let the relative dielectric constant of the heat dissipation insulating layer 40 be Er2, and the relative dielectric constant of the build-up layer 32 be Er1. It is preferable that Er1<Er2. Accordingly, the semiconductor device 101 can reduce leakage of common-mode noise from the heat dissipation insulating layer 40 to the outside. Further, let t1 be the thickness between the pattern wiring and the heat sink surface S22 of the build-up layer 32, and let t2 be the thickness of the heat dissipation insulating layer 40. In this case, Er1 / t1>Er2 / t2 may be satisfied. Note that t2 corresponds to the distance between the back metal layer 50 and the heat sinks 21, 22.

[0063] As shown in FIG. 2, the back metal layer 50 is provided in contact with the heat dissipation insulating layer 40. The back metal layer 50 is, for example, a thin film mainly composed of a metal such as copper. Further, as shown in FIGS. 1 and 4, it is preferable that the back metal layer 50 has a large opposing area with respect to the heat sinks 21 and 22. Therefore, the back metal layer 50 includes an extension portion L2 provided to extend beyond the end portions of the heat sinks 21 and 22. Note that the opposing area can also be referred to as a projection area in the plate thickness direction. The surface of the heat dissipation insulating layer 40 on which the back metal layer 50 is provided can also be referred to as a metal formation surface.

[0064] Here, let the thickness of the heat dissipation insulating layer 40 be L1. It is preferable that the relationship between L1 and L2 satisfies L1<L2. Accordingly, the semiconductor device 101 can improve heat dissipation from the back metal layer 50.

[0065] Further, it is preferable that the heat dissipation insulating layer 40 does not contain glass cloth. That is, the heat dissipation insulating layer 40 contains a filler and an electrically insulating resin without containing glass cloth. The heat dissipation insulating layer 40 is composed of, for example, only the filler and the resin. Therefore, the heat dissipation insulating layer 40 can contain a larger amount of filler than a configuration containing glass cloth. As described above, the filler has favorable thermal conductivity. Further, the filler is a member for improving heat dissipation. Therefore, the heat dissipation insulating layer 40 can achieve high heat dissipation. Glass cloth corresponds to glass fiber.

[0066] Incidentally, the semiconductor device 101 is divided from a multi-layer substrate on which multiple structures that will become the semiconductor device 101 are formed, by dicing or other means. Therefore, the side walls of the semiconductor device 101 can also be called dicing lines DL.

[0067] As shown in Figures 1 and 4, the back metal layer 50 is provided in the region surrounded by the annular end of the heat dissipation insulating layer 40. In other words, the metal forming surface includes a portion exposed from the back metal layer 50, so as to surround the back metal layer 50. Furthermore, the back metal layer 50 is not provided in a predetermined range from the dicing line DL on the metal forming surface.

[0068] Therefore, when dicing multi-layer substrates with a blade, blade clogging can be suppressed. In addition, the back metal layer 50 can be scraped off and scattered. Thus, the semiconductor device 101 can suppress electrical malfunctions caused by the adhesion of metal debris.

[0069] <Manufacturing method> Here, the manufacturing method of the semiconductor device 101 will be explained using Figures 6 to 8. First, the manufacturing method of the first semiconductor element 11 and the first heat sink 21 embedded in the wiring board 30 will be explained using Figure 6. The same applies to the manufacturing method of the second semiconductor element 12 and the second heat sink 22.

[0070] As shown in Figures 6a and 6b, the first semiconductor element 11 and the first heat sink 21 are prepared. Here, the first heat sink 21 with a recess 213 is prepared. The recess 213 of the first heat sink 21 is formed by machining or die casting.

[0071] Subsequently, as shown in Figure 6c, the connecting member 60 is attached to the element-facing surface S11. For example, the connecting member 60 is attached by transfer. Then, as shown in Figure 6d, the first semiconductor element 11 with the connecting member 60 attached is mounted in the recess 213. At this time, the first semiconductor element 11 is pressed in the direction of the white arrow (die attach bonding process). When a metal sintered material is used as the connecting member 60, the first semiconductor element 11 is mounted by heating and pressurizing the connecting member 60.

[0072] In this way, the first semiconductor element 11 and the first heat sink 21 are electrically connected. The first heat sink 21 on which the first semiconductor element 11 is mounted, and the second heat sink 22 on which the second semiconductor element 12 is mounted, can also be considered semiconductor components.

[0073] Next, the process of embedding semiconductor components in the wiring board 30 will be explained using Figure 7. As shown in Figure 7a, a core layer 31 is prepared. Then, as shown in Figure 7b, through holes 311 are formed in the region of the core layer 31 where the semiconductor components will be placed. The through holes 311 are formed, for example, by punching.

[0074] Next, as shown in Figure 7c, the core layer 31 is placed on the heat dissipation insulating layer 40, which has a back metal layer 50 (layup). The heat dissipation insulating layer 40 can also be called a high thermal conductivity insulating layer prepreg. Then, as shown in Figure 7d, the semiconductor material is placed in the through hole 311 (layup).

[0075] Furthermore, as shown in Figure 7e, a build-up layer 32 is placed on the core layer 31. Here, the build-up layer 32 does not have pattern wiring 33 or vias 34 formed on it. Reference numeral 33 denotes a thin film of copper or the like before patterning. The build-up layer 32 can also be called a wiring layer prepreg.

[0076] Then, as shown in Figure 7f, press molding is performed. Here, the build-up layer 32 is pressed in the direction of the white arrow. As a result, the resin portion of the build-up layer 32 fills the gaps between the core layer 31 and the heat sinks 21 and 22. In this way, the semiconductor component is embedded in the wiring board 30. The heat dissipation insulating layer 40 is also connected to the core layer 31 and the heat sinks 21 and 22.

[0077] Next, the process of forming the wiring and solder resist 35 will be explained using Figure 8. As shown in Figure 8a, vias 34 are formed. Filled vias are formed as vias 34 (filled via formation process). In other words, vias 34 are filled vias in which a conductor is embedded in a hole made by a laser or the like. Then, as shown in Figure 8b, the thin film is patterned to form pattern wiring 33 (pattern wiring formation process). Then, as shown in Figure 8c, solder resist 35 is formed (solder resist formation process). This forms each of the pads 331 to 337.

[0078] <Effects> As described above, the semiconductor device 101 is equipped with a heat-dissipating insulating layer 40 that is in contact with the opposite surface S21 of the heat sink and the opposite surface S31 of the core. Therefore, the semiconductor device 101 can improve heat dissipation compared to a configuration in which the heat sinks 21, 22 and the heat-dissipating insulating layer 40 are connected via vias.

[0079] Furthermore, the semiconductor device 101 does not have a wiring layer on the S21 side opposite the heat sink. Therefore, the semiconductor device 101 does not need to consider the resin fluidity of the wiring layer during manufacturing. In addition, the thermal conductivity of the semiconductor device 101 on the S21 side opposite the heat sink can be improved by increasing the amount of filler in the heat dissipation insulating layer 40.

[0080] As described above, the semiconductor device 101 can be manufactured at a relatively low temperature by using the core layer 31 and the build-up layer 32. Therefore, the semiconductor device 101 can use semiconductor elements 11 and 12 with low heat resistance temperatures. Thus, the semiconductor device 101 can be manufactured inexpensively.

[0081] Preferred embodiments of the present disclosure have been described above. However, the present disclosure is not limited to the above embodiments, and various modifications are possible without departing from the spirit of the present disclosure.

[0082] Other forms of the present disclosure are described below. The above embodiments and other forms can be implemented individually, but they can also be implemented in various combinations as appropriate. The present disclosure is not limited to the combinations shown in the embodiments, but can be implemented in various combinations. In other words, the following modifications 1 to 4 can also be applied to other embodiments.

[0083] (Variation 1) Figure 9 will be used to explain Modification 1. In Modification 1, the configuration of the first heatsink 21a differs from that of the first heatsink 21.

[0084] The heat sink 21a is provided with a recess 213a formed by the bottom portion 211a and the annular side wall 212a. Furthermore, the heat sink 21a is provided with a protrusion 214a on the bottom portion 211a. The protrusion 214a is the area on which the semiconductor element 11 is mounted. The protrusion 214a can also be called the mounting area for the semiconductor element 11. In other words, the heat sink 21a has a portion around the protrusion 214a on which the semiconductor element 11 is mounted that is lower than the surface on which the semiconductor element 11 is mounted. In addition, the side wall 212a is inclined such that the opening area of ​​the recess 213a gradually widens from the bottom portion 211a towards the opening end.

[0085] Therefore, the heat sink 21a can reduce variations in the mounting position of the semiconductor element 11. In addition, the heat sink 21a can suppress stress concentration on the connecting member 60. Furthermore, since the heat sink 21a has a protrusion 214a, the semiconductor element 11 is configured to easily protrude from the recess 213a. Therefore, it is easier to apply pressure to the semiconductor element 11 during the die attach bonding process.

[0086] Furthermore, the heat sink 21a has a gradually widening opening area in the recess 213a. This makes it easier to apply pressure to the semiconductor element 11 during the die attach bonding process. In addition, the resin portion of the build-up layer 32 is easily inserted into the recess 213a. In other words, the semiconductor element 11 and the connecting member 60 are covered with the resin portion. Therefore, the semiconductor element 11 and the connecting member 60 are subjected to stress due to the curing shrinkage of the resin portion, which suppresses delamination.

[0087] (Modification 2) Modification 2 will be explained using Figures 10 to 12. Modification 2 mainly differs from the first heatsink 21 in the configuration of the first heatsink 21b.

[0088] As shown in Figures 10 and 11, the heat sink 21b is provided with a recess 213b formed by the bottom portion 211b and the annular first side wall 212b1 and second side wall 212b2. Furthermore, the opening area of ​​the recess 213b is progressively increased by the first side wall 212b1 and the second side wall 212b2.

[0089] The first side wall 212b1 is provided in conjunction with the bottom 211b. The second side wall 212b2 is provided in conjunction with the first side wall 212b1. Therefore, the first side wall 212b1 and the second side wall 212b2 are provided in the order of bottom 211b. The angle between the second side wall 212b2 and bottom 211b is wider than the angle between the first side wall 212b1 and bottom 211b.

[0090] A resin portion 215b is provided in the recess 213b. The resin portion 215b is an electrically insulating resin such as epoxy material or polyimide. The resin portion 215b is provided so as to be in contact with the connecting member 60 and the connection between the connecting member 60 and the semiconductor element 11. Therefore, the resin portion 215b is also in contact with a part of the side surface of the semiconductor element 11.

[0091] As shown in Figures 10 and 12, the heat sink 21b includes a resin reservoir 216b in which a portion of the resin part 215b is located. The resin reservoir 216b is positioned higher than the recess 213b.

[0092] The resin portion 215b is potted into the recess 213b on which the semiconductor element 11 is mounted. For example, the resin portion 215b is supplied to the resin reservoir 216b in a fluid state. Then, the resin portion 215b is supplied from the resin reservoir 216b into the recess 213b by capillary action. However, the heat sink 21b does not necessarily have to be provided with a resin reservoir 216b.

[0093] As described above, the semiconductor device 101 is provided with a resin portion 215b. Therefore, the semiconductor device 101 can suppress cracking and peeling of the connecting member 60.

[0094] (Variation 3) Modification 3 will be explained using Figures 13 to 15. Modification 3 mainly differs from the first heatsink 21 and core layer 31 in the configuration of the first heatsink 21c and core layer 31c.

[0095] As shown in Figure 13, the heat sink 21c is provided with a recess 213c formed by the bottom portion 211c and the annular side wall 212c. The heat sink 21c is provided with a positioning portion 217c. The positioning portion 217c is a recess provided on the surface facing the core layer 31c. The heat sink 21c is provided with two positioning portions 217c.

[0096] As shown in Figure 14, the core layer 31c is provided with through holes 311c. The core layer 31c is provided with positional protrusions 312c. The positional protrusions 312c are projections provided on the surface facing the heat sink 21c. The core layer 31c is provided with two positional protrusions 312c. Furthermore, the positional protrusions 312c are provided at positions corresponding to the positional protrusions 217c.

[0097] As shown in Figure 15, the heat sink 21c is positioned in the through-hole 311c of the core layer 31c. In this state, the positional projection 312c is positioned in the recess 213c. The positional projection 312c and the recess 213c are positioned so that at least a portion of them are in contact.

[0098] This allows the semiconductor device 101 to suppress misalignment of the heat sink 21c relative to the core layer 31c. The heat sink 21c may have a protrusion for positioning, and the core layer 31c may have a recess for positioning.

[0099] (Modification 4) Modification 4 will be explained using Figures 16 and 17. Modification 4 mainly differs from the first heatsink 21 and core layer 31 in the configuration of the first heatsink 21d and core layer 31d.

[0100] As shown in Figure 16, the heat sink 21d has a cylindrical shape. The core layer 31d is provided with through holes 311d corresponding to the shape of the heat sink 21d. The heat sink 21d is press-fitted into the through holes 311d.

[0101] Therefore, as shown in Figure 17, virtually no gap is formed between the heat sink 21d and the core layer 31d. In other words, the heat sink 21d is positioned in the through hole 311d in contact with the core layer 31d. The heat sink 21d, like the heat sink 21, has a recess where the semiconductor element 11 is placed.

[0102] As a result, the semiconductor device 101 does not need to insert the resin portion of the build-up layer 32 between the heat sink 21d and the core layer 31d. Therefore, processing costs during press molding can be reduced. In addition, the semiconductor device 101 can be made lighter, its reliability improved, and the material cost of the heat sink 21d can be reduced.

[0103] (Second Embodiment) The semiconductor device 102 of the second embodiment will be described with reference to Figure 18. The semiconductor device 102 differs from the semiconductor device 101 in that it includes a ground layer 36.

[0104] As shown in Figure 18, the semiconductor device 102 has layer wiring provided on the layer surface S33 as part of the wiring. The layer wiring includes a pattern wiring 33 electrically connected to the semiconductor element 11 and a ground layer 36 provided around the pattern wiring 33 and electrically connected to the ground. The ground layer 36 has a ground electrode 37. The ground layer 36 corresponds to dummy wiring.

[0105] The ground layer 36 is a wiring layer on the same layer as the pattern wiring 33. The ground layer 36 is formed using the same process as the pattern wiring 33. Like the pattern wiring 33, the ground layer 36 is made of a thin film of copper or the like that has been patterned.

[0106] The semiconductor device 102 can achieve the same effects as the semiconductor device 101. Furthermore, since the semiconductor device 102 is equipped with a ground layer 36, noise can be reduced.

[0107] (Third embodiment) The semiconductor device 103 of the third embodiment will be described with reference to Figure 19. The semiconductor device 103 differs from the semiconductor device 101 in that it is equipped with a heat sink pad 70.

[0108] As shown in Figure 19, the semiconductor device 103 has a heat sink pad 70 provided between the semiconductor elements 11 and 12 and the via 34. The heat sink pad 70 is a material mainly composed of metal such as copper. The heat sink pad 70 is a chip-shaped or plate-shaped metal material.

[0109] More specifically, the heat sink pad 70 is provided on the source electrodes of the semiconductor elements 11 and 12. The heat sink pad 70 is electrically connected to the source electrodes and vias 34. The source electrode of the first semiconductor element 11 is electrically connected to the O wiring section via the heat sink pad 70 and vias 34. The source electrode of the second semiconductor element 12 is electrically connected to the N wiring section via the heat sink pad 70 and vias 34.

[0110] The semiconductor device 103 can achieve the same effects as the semiconductor device 101. Furthermore, the semiconductor device 103 is equipped with a heat sink pad 70. Therefore, the semiconductor device 103 can temporarily store heat in response to the rapid heat generation of the semiconductor elements 11 and 12. Thus, the semiconductor device 103 can suppress the failure of the semiconductor elements 11 and 12. Note that the semiconductor elements 11 and 12 may generate rapid heat during short circuits or avalanches.

[0111] (Fourth Embodiment) The semiconductor device 104 of the fourth embodiment will be described with reference to Figure 20. The semiconductor device 104 differs from the semiconductor device 101 in that it is equipped with stud bumps 71.

[0112] As shown in Figure 20, semiconductor elements 11 and 12 have stud bumps 71 provided on the electrodes on the element surface S12 side. The stud bumps 71 are bumps mainly composed of metal such as copper. The stud bumps 71 are formed using a bonding method.

[0113] The stud bump 71 is electrically connected to the via 34. Therefore, the electrode on the element surface S12 side is electrically connected to the via 34 via the stud bump 71.

[0114] The semiconductor device 104 can achieve the same effects as the semiconductor device 101. Furthermore, since the semiconductor device 104 is equipped with stud bumps 71, it is not necessary to pre-form copper plating on the electrodes on the element surface S12 side. Therefore, the semiconductor device 104 can be made more cost-effective.

[0115] (Fifth embodiment) The semiconductor device 105 of the fifth embodiment will be described with reference to Figure 21. The semiconductor device 105 differs from the semiconductor device 101 mainly in the configuration of the back metal layer 50a.

[0116] As shown in Figure 21, the semiconductor device 105 is mounted on the cooler 200 via a thermal conductive part 80a on the back metal layer 50a side. The thermal conductive part 80a can also be called a TIM. TIM is an abbreviation for Thermal Interface Material. Note that semiconductor devices of other embodiments may also be mounted on the cooler 200 via a thermal conductive part 80a.

[0117] The back metal layer 50a has a roughened shape to increase the contact area with the heat conduction part 80a. In other words, the back metal layer 50a has an uneven surface.

[0118] The semiconductor device 105 can achieve the same effects as the semiconductor device 101. Furthermore, the semiconductor device 105 is equipped with a roughened back metal layer 50a. Therefore, the semiconductor device 105 can increase the contact area between the back metal layer 50a and the heat conduction part 80a, and efficiently transfer heat from the back metal layer 50a to the heat conduction part 80a. Thus, the semiconductor device 105 can improve heat dissipation.

[0119] (Sixth Embodiment) The semiconductor device 106 of the sixth embodiment will be described with reference to Figure 22. The semiconductor device 106 differs from the semiconductor device 101 mainly in the configuration of the heat sinks 21e and 22e.

[0120] As shown in Figure 22, the heat sinks 21e and 22e have a plate shape. The heat sinks 21e and 22e do not have a recess 213. The heat sinks 21e and 22e have a rectangular parallelepiped shape. Therefore, the heat sink surface S22 is a flat surface. The semiconductor elements 11 and 12 are mounted on the heat sink surface S22.

[0121] The semiconductor device 106 is equipped with pads 21e1 and 22e1 having the same thickness as the semiconductor elements 11 and 12. The first pad 21e1 is electrically connected to the first heat sink 21e via a connecting member 21e2. The second pad 22e1 is electrically connected to the second heat sink 22e via a connecting member 22e2. The surfaces of the pads 21e1 and 22e1 are at the same height as the element surface S12. The connecting members 21e2 and 22e2 can be made of the same material as the connecting member 60. The pads 21e1 and 22e1 correspond to terminal members.

[0122] The first pad 21e1 is electrically connected to the P wiring section via via 34. The second pad 22e1 is electrically connected to the O wiring section via via 34. Therefore, the first heatsink 21e is electrically connected to the P wiring section via the first pad 21e1 and via 34. The second heatsink 22e is electrically connected to the O wiring section via the second pad 22e1 and via 34.

[0123] The semiconductor device 106 can achieve the same effects as the semiconductor device 101. Furthermore, the semiconductor device 106 eliminates the need for processing the heat sinks 21e and 22e. In addition, since the semiconductor device 106 has pads 21e1 and 22e1, the same vias 34 can be used on the semiconductor elements 11 and 12 and on the pads 21e1 and 22e1. It can also be said that vias 34 of the same thickness can be used.

[0124] (Variation 5) Using Figure 23, a modified example 5, which is a modified example of the sixth embodiment, will be described. As shown in Figure 23, the connecting member 60a contains a ball 60a1. In other words, the connecting member 60a is a metal sintered material containing a ball 60a1. The ball 60a1 can be made of a metal such as nickel or copper, or a resin. The ball 60a1 is there to keep the amount of pressure constant when pressurizing the connecting member 60a. The method of mounting the semiconductor element 11 using the connecting member 60a is the same as in the first embodiment.

[0125] The semiconductor device 106 can suppress variations in the connecting member 60a after heating and pressurizing. This reduces variations in the amount of air gap in the connecting member 60a. Furthermore, it can improve the flatness of the semiconductor elements 11 and 12. As a result, the wiring performance of the via 34, the reliability of the connection between the via 34 and the semiconductor elements 11 and 12, and the heat dissipation can be improved.

[0126] The ball 60a1 can also be included in the connecting members 21e2 and 22e2. Modification 5 can also be applied to other embodiments and modifications.

[0127] (Experimental variation 6) Using Figure 24, a modified example 6 of the sixth embodiment will be described. As shown in Figure 24, the heat sink 21f includes a mounting portion 21f1 on which the semiconductor element 11 is mounted, and grooves 21f2 to 21f4 provided around the mounting portion 21f1. The grooves 21f2 to 21f4 are provided in an annular shape so as to surround the mounting portion 21f1.

[0128] The heat sink 21f has grooves 21f2 to 21f4 formed by, for example, coining. It could also be said that the grooves 21f2 to 21f4 of the heat sink 21f are formed by press forming.

[0129] The grooves 21f2 to 21f4 are composed of two protrusions 21f2 and 21f3 and a recess 21f4 provided between the protrusions 21f2 and 21f3. The recess 21f4 is a recessed portion relative to one protrusion 21f2 and the other protrusion 21f3. In other words, the heat sink 21f has a recess 21f4, which is a recessed portion created by press working, and protrusions 21f2 and 21f3, which are raised portions created by press working. Therefore, the bottom of the recess 21f4 is lower than the mounting portion 21f1. The second heat sink 22e is configured similarly.

[0130] As a result, the semiconductor device 106 can ensure position recognition when mounting semiconductor elements 11 and 12. Furthermore, the semiconductor device 106 can suppress the protrusion of the connecting member 60 from the opposing region of the semiconductor elements 11 and 12, and can ensure the applied pressure to the connecting member 60. Therefore, an appropriate sintering state can be ensured in the connecting member 60. Thus, the semiconductor device 106 can improve the reliability of the connection by the connecting member 60. Note that modification 6 can also be applied to other embodiments and modifications.

[0131] (Seventh Embodiment) The semiconductor device 107 of the seventh embodiment will be described with reference to Figure 25. The semiconductor device 107 differs from the semiconductor device 101 mainly in the configuration of the heat sinks 21g and 22g.

[0132] As shown in Figure 25, the heat sinks 21g and 22g have an uneven surface. The first heat sink 21g has a recess 21g1 and a protrusion 21g2 around the area where the first semiconductor element 11 is mounted. The protrusion 21g2 is located opposite the P wiring section. The recess 21g1 is located between the area where the first semiconductor element 11 is mounted and the protrusion 21g2. Similarly, the second heat sink 22g has a recess 22g1 and a protrusion 22g2. The protrusion 22g2 is located opposite the O wiring section. The uneven surface of the heat sinks 21g and 22g is formed, for example, by coining.

[0133] The surfaces of the protrusions 21g2 and 22g2 are at the same height as the element surface S12. Protrusion 21g2 is electrically connected to the P wiring section via via 34. Protrusion 22g2 is electrically connected to the O wiring section via via 34.

[0134] The semiconductor device 106 can achieve the same effects as the semiconductor device 101. Furthermore, because the semiconductor device 106 has an uneven surface formed by coining, it can be made more cost-effective than the semiconductor device 101.

[0135] (Eighth embodiment) The semiconductor device 108 of the eighth embodiment will be described with reference to Figure 26. The semiconductor device 108 differs from the semiconductor device 106 mainly in the configuration of the back metal layer 50b and the attachment of the heat dissipation spring member 80b.

[0136] As shown in Figure 26, the back metal layer 50b has irregularities formed on it. These irregularities are formed by etching the back metal layer 50b. A heat dissipation spring member 80b is attached to these irregularities. The irregularities are provided according to the shape of the heat dissipation spring member 80b. For example, the back metal layer 50b may have irregularities formed on it so that the heat dissipation spring member 80b can be fitted and fixed in place. The heat dissipation spring member 80b is a spring with good thermal conductivity and can also be called a heat conducting spring. The semiconductor device 108 is attached to the cooler 200 via the heat dissipation spring member 80b.

[0137] In this example, a semiconductor device 108 mounted on a circuit board 300 is used. Conductive connecting members 400 are electrically connected to each pad 331 to 337. The semiconductor device 108 is electrically connected to the circuit board 300 via the connecting members 400. The other semiconductor devices 101 to 107 and 109 may be similarly connected to the circuit board 300.

[0138] The semiconductor device 108 can achieve the same effects as the semiconductor device 105. The heat dissipation spring member 80b is fixed to the irregularities of the back metal layer 50b of the semiconductor device 108. Therefore, the semiconductor device 108 can suppress displacement of the heat dissipation spring member 80b. Thus, the semiconductor device 108 can reduce the contact thermal resistance between the back metal layer 50b and the heat dissipation spring member 80b, thereby improving heat dissipation.

[0139] Furthermore, the back metal layer 50b and the heat dissipation spring member 80b can also be applied to the first to fourth embodiments and the seventh embodiment.

[0140] (Ninth Embodiment) The semiconductor device 109 of the ninth embodiment will be described with reference to Figure 27. The semiconductor device 109 differs from the semiconductor device 108 in that it is equipped with a connecting member 80c.

[0141] As shown in Figure 27, the connecting member 80c joins the back metal layer 50 and the heat dissipation spring member 80b. The connecting member 80c can be made of solder, sintered material, or the like.

[0142] The semiconductor device 109 can achieve the same effects as the semiconductor device 108. Furthermore, the semiconductor device 109 can reduce the contact thermal resistance between the back metal layer 50 and the heat dissipation spring member 80b compared to the semiconductor device 108. Therefore, the semiconductor device 109 can improve heat dissipation compared to the semiconductor device 108.

[0143] (Tenth embodiment) The semiconductor device 110 of the tenth embodiment will be described with reference to Figures 28 and 29. The configuration of semiconductor elements 11 and 12 in the semiconductor device 110 differs from that of the semiconductor device 101.

[0144] As shown in Figure 28, the semiconductor device 110 has a configuration in which two first semiconductor elements 11 are connected in parallel as upper arm elements, and two second semiconductor elements 12 are connected in parallel as lower arm elements. The two first semiconductor elements 11 have the same configuration. The two second semiconductor elements 12 also have the same configuration.

[0145] As shown in Figure 29, the two first semiconductor elements 11 are mounted on a single first heat sink 21 via a connecting member 60. The two first semiconductor elements 11 are connected in parallel via wirings 33 and 34. More specifically, the two first semiconductor elements 11 have a configuration in which their drain electrodes are electrically connected to each other via the first heat sink 21, and their source electrodes are electrically connected to each other via wirings 33 and 34. In this way, the two first semiconductor elements 11 are connected in parallel. The two second semiconductor elements 12 are mounted on a single second heat sink 22 via a connecting member 60. The two second semiconductor elements 12 are connected in parallel in a configuration similar to that of the first semiconductor elements 11. Thus, the wiring board 30 incorporates the two first semiconductor elements 11 and the two semiconductor elements 12.

[0146] In this example, two semiconductor elements are connected in parallel. However, the semiconductor device 110 may have three or more semiconductor elements connected in parallel. Therefore, three or more first semiconductor elements 11 may be mounted on the first heat sink 21. Similarly, three or more second semiconductor elements 12 may be mounted on the second heat sink 22.

[0147] The semiconductor device 110 can achieve the same effects as the semiconductor device 101. Furthermore, the semiconductor device 110 is composed of multiple first semiconductor elements 11 in the upper arm element and multiple second semiconductor elements 12 in the lower arm element. Therefore, the first semiconductor elements 11 and the second semiconductor elements 12 can be made smaller than in the first embodiment. Thus, the number of semiconductor elements 11 and 12 that can be placed on the same wafer can be increased, thereby reducing costs. Also, for the same wafer size, the smaller the size of the semiconductor elements 11 and 12, the greater the effective area. The yield of the elements also increases when the size of the semiconductor elements 11 and 12 is smaller.

[0148] The semiconductor device 110 can suppress heat concentration by distributing multiple first semiconductor elements 11 within a single first heat sink 21. Furthermore, the semiconductor device 110 can reduce the temperature difference between the multiple first semiconductor elements 11. Therefore, the semiconductor device 110 can reduce the characteristic differences between the multiple first semiconductor elements 11, thereby reducing load imbalance. The same applies to the second semiconductor element 12.

[0149] The semiconductor device 110 allows for shorter wiring lengths between multiple first semiconductor elements 11 compared to the case where multiple first semiconductor elements 11 are mounted on different heat sinks. Therefore, switching variations in multiple parallel-connected first semiconductor elements 11 can be reduced. The same applies to the multiple second semiconductor elements 12.

[0150] Furthermore, the semiconductor device 110 may have multiple semiconductor elements 11, 12 of different types connected in parallel mounted on a single heat sink 21, 22. For example, the heat sink 21 may have a MOSFET and an IGBT connected in parallel mounted on it.

[0151] (11th embodiment) The semiconductor device 111 of the 11th embodiment will be described with reference to Figures 30 and 31. The configuration of the elements mounted on each heat sink 21, 22 of the semiconductor device 111 differs from that of the semiconductor device 101.

[0152] As shown in Figure 30, the semiconductor device 111 has a configuration in which a first semiconductor element 11 and a first diode 11a are connected in parallel, and a second semiconductor element 12 and a second diode 12a are connected in parallel. Thus, the first semiconductor element 11 is connected in parallel with the first diode 11a, which is a different circuit element from the first semiconductor element 11. The second semiconductor element 12 is connected in parallel with the second diode 12a, which is a different circuit element from the second semiconductor element 12. Diodes 11a and 12a are freewheeling diodes.

[0153] As shown in Figure 31, the first semiconductor element 11 and the first diode 11a are mounted on a first heat sink 21 via a connecting member 60. The first semiconductor element 11 and the first diode 11a are connected in parallel via wirings 33 and 34. More specifically, the first semiconductor element 11 and the first diode 11a have a configuration in which the drain electrode and cathode electrode are electrically connected via the first heat sink 21, and the source electrode and anode electrode are electrically connected via wirings 33 and 34. In this way, the first semiconductor element 11 and the first diode 11a are connected in parallel. The second semiconductor element 12 and the second diode 12a are mounted on a second heat sink 22 via a connecting member 60. The second semiconductor element 12 and the second diode 12a are connected in parallel in a similar configuration to the first semiconductor element 11 and the first diode 11a. Thus, the wiring board 30 incorporates two semiconductor elements 11 and 12 and two diodes 11a and 12a.

[0154] The semiconductor device 111 can achieve the same effects as the semiconductor device 101. Furthermore, the semiconductor device 111 can shorten the wiring length between the first semiconductor element 11 and the first diode 11a. Therefore, the semiconductor device 111 can reduce the wiring inductance between the first semiconductor element 11 and the first diode 11a, thereby reducing surge voltage, loss, and generated noise. The same applies to the wiring between the second semiconductor element 12 and the second diode 12a.

[0155] Furthermore, the first semiconductor element 11 and the first diode 11a do not operate simultaneously. In other words, the timing at which the first semiconductor element 11 and the first diode 11a require heat dissipation via the first heat sink 21 is different. Therefore, the semiconductor device 111 can share the function of the first heat sink 21 between the first semiconductor element 11 and the first diode 11a. The same applies to the second heat sink 22.

[0156] (12th embodiment) The semiconductor device 112 of the twelfth embodiment will be described with reference to Figures 32 and 33. The configuration of the elements mounted on each heat sink 21, 22 of the semiconductor device 112 differs from that of the semiconductor device 111.

[0157] As shown in Figure 32, the semiconductor device 112 has a configuration in which a first semiconductor element 11 and a first capacitor 11b are connected in parallel, and a second semiconductor element 12 and a second capacitor 12b are connected in parallel. Thus, the first semiconductor element 11 is connected in parallel with the first capacitor 11b, which is a different circuit element from the first semiconductor element 11. The second semiconductor element 12 is connected in parallel with the second capacitor 12b, which is a different circuit element from the second semiconductor element 12. Capacitors 11b and 12b are capacitor elements that function as a snubber circuit.

[0158] As shown in Figure 33, the first semiconductor element 11 and the first capacitor 11b are mounted on a single first heat sink 21 via a connecting member 60. The first semiconductor element 11 and the first capacitor 11b are connected in parallel via wiring 33 and 34. More specifically, the first semiconductor element 11 and the first capacitor 11b have a configuration in which the drain electrode and one electrode of the first capacitor 11b are electrically connected via the first heat sink 21, and the source electrode and the other electrode of the first capacitor 11b are electrically connected via wiring 33 and 34. In this way, the first semiconductor element 11 and the first capacitor 11b are connected in parallel. The second semiconductor element 12 and the second capacitor 12b are mounted on a single second heat sink 22 via a connecting member 60. The second semiconductor element 12 and the second capacitor 12b are connected in parallel in a similar configuration to the first semiconductor element 11 and the first capacitor 11b. Thus, the wiring board 30 incorporates two semiconductor elements 11 and 2 and two capacitors 11b and 12b.

[0159] Furthermore, capacitors 11b and 12b are thinner than semiconductor elements 11 and 12. Therefore, by adjusting the thickness of the connecting member 60, the heights of capacitors 11b and 12b and semiconductor elements 11 and 12 can be matched. In other words, the connecting member 60 on the capacitor 11b and 12b side is thicker than the connecting member 60 on the semiconductor element 11 and 12 side. Methods for adjusting the thickness include increasing the supply amount of connecting member 60, adjusting the pressure, and changing the size of the height-adjusting ball.

[0160] As a result, the semiconductor device 112 can use the same via 34 on both the semiconductor elements 11,12 and the capacitors 11b,12b. Furthermore, because the semiconductor device 112 uses the same via 34, it is no longer necessary to individually change the thickness of the heat sinks 21,22. The semiconductor device 112 can achieve the same effects as the semiconductor device 111.

[0161] Furthermore, the semiconductor device 112 can be a circuit element that is thicker than the semiconductor elements 11 and 12, as it is connected in parallel with each of the semiconductor elements 11 and 12. In this case, the same effect can be achieved by making the connecting member 60 on the circuit element side thinner than the connecting member 60 on the semiconductor elements 11 and 12 side.

[0162] Furthermore, capacitors 11b and 12b are narrower in width (element width) than semiconductor elements 11 and 12. In other words, capacitors 11b and 12b are smaller in size than semiconductor elements 11 and 12. However, this disclosure can also be used even if capacitors 11b and 12b are the same size as semiconductor elements 11 and 12. In addition, this disclosure can also be used even if capacitors 11b and 12b are the same width as semiconductor elements 11 and 12, but thinner in thickness than semiconductor elements 11 and 12.

[0163] The following describes other modifications and other embodiments. As shown in the modified example in Figure 34, the semiconductor device 113 may include a floating conductor layer 321. The floating conductor layer 321 is provided in the build-up layer 32. In the stacking direction, the floating conductor layer 321 is provided between the wiring (pattern wiring 33) and the heat sinks 21 and 22. The floating conductor layer 321 is not electrically connected to the pattern wiring 33 and the vias 34. Furthermore, the floating conductor layer 321 is not electrically connected to ground. This allows the semiconductor device 113 to mitigate the electric field between the pattern wiring 33 and the heat sinks 21 and 22. The semiconductor device 113 can improve the insulation between the pattern wiring 33 and the heat sinks 21 and 22.

[0164] As shown in the modified examples in Figures 35 and 36, the semiconductor element 11 may be mounted on the first heat sink 21 via a connecting member 61. The connecting member 61 is a silver sintered material. In other words, the connecting member 61 is a bonding material mainly composed of silver. The connecting member 61 is then sintered and bonded. It can be said that the connecting member 61 contains a sintered silver layer.

[0165] On the other hand, the first heat sink 21 is plated. That is, a silver plating layer 62 is provided on the surface of the first heat sink 21. In Figures 35 and 36, for convenience, a configuration is shown in which the silver plating layer 62 is provided only on the bottom 211 of the recess 213. Note that it is sufficient for the silver plating layer 62 to be provided at least on the bottom 211. This improves the bonding between the first semiconductor element 11 and the first heat sink 21. The same applies to the bond between the second semiconductor element 12 and the second heat sink 22.

[0166] Furthermore, as shown in the modified example in Figure 36, it is preferable that the silver plating layer 62 is porous with gaps 62h. The silver plating layer 62 can also be described as a porous plating layer. Therefore, the silver plating layer 62 can also be described as a matte plating layer. This allows the silver plating layer 62 to relieve stress generated by thermal cycles and the like. In other words, the porous nature of the silver plating layer 62 allows for deformation, which can suppress cracking in the sintered silver layer of the connecting member 61.

[0167] As shown in the modified examples in Figures 37 and 38, the heat dissipation insulating layers 41 and 42 may have a two-layer structure. The heat dissipation insulating layer includes a heat dissipation insulating adhesive layer 41 that is in contact with the opposite surface S21 of the heat sink, and a highly insulating, high-thermal-conductivity insulating layer 42 that is in contact with the heat dissipation insulating adhesive layer 41. The heat dissipation insulating adhesive layer 41 is an adhesive that has higher adhesion to metals and the like than the high-thermal-conductivity insulating layer 42. The high-thermal-conductivity insulating layer 42 includes a filler with good thermal conductivity and an electrically insulating resin containing the filler.

[0168] This allows the heat dissipation insulating layers 41 and 42 to be connected to the core layer 31 and heat sinks 21 and 22. Another example of a manufacturing method is to press-molde the build-up layer 32 with the core layer 31 and heat sinks 21 and 22 fixed in place, and then connect the heat dissipation insulating layer 40. This can be done by using the heat dissipation insulating layers 41 and 42. In other words, the high thermal conductivity insulating layer 42 needs to be molded with a higher press pressure than normal to ensure heat dissipation. Therefore, the high thermal conductivity insulating layer 42 is pre-molded at high pressure in a separate process and then connected via the heat dissipation insulating adhesive layer 41. This helps to avoid damage to the elements due to high-pressure pressing.

[0169] As shown in the modified example in Figure 38, the heat dissipation insulating layers 41 and 42 may be provided with positioning recesses 40a in which the heat sinks 21 and 22 are positioned. In other words, the heat dissipation insulating layers 41 and 42 are provided with positioning recesses 40a in advance before the heat sinks 21 and 22 are connected.

[0170] The positioning recess 40a has an opening area sufficient to allow the heat sinks 21 and 22 to be positioned without gaps. It can also be said that the positioning recess 40a has an opening area sufficient to prevent the heat sinks 21 and 22 from moving in the planar direction once they are positioned. This improves the assembly accuracy of the heat sinks 21 and 22. However, a gap may occur between the positioning recess 40a and the heat sinks 21 and 22, provided that manufacturing tolerances and positional misalignments are within an acceptable range.

[0171] As shown in the modified example in Figure 39a, a polyamide layer 32p, mainly composed of polyamide, may be provided on the surface of the second heat sink 22 or the second semiconductor element 12 before providing the build-up layer 32. The step of providing the polyamide layer 32p is performed between the steps shown in Figure 7d and Figure 7e. The polyamide layer 32p is provided to improve the adhesion between the resin portion of the build-up layer 32 and the second heat sink 22 or the second semiconductor element 12, and to protect the second semiconductor element 12 from lasers.

[0172] Subsequently, a build-up layer 32 is provided, as shown in Figure 39b. The process in Figure 39b is the same as in Figures 7e and 7f.

[0173] Then, as shown in Figure 39c, holes 34h are made in the build-up layer 32 by a laser to form vias 34. At this time, a portion of the polyamide layer 32p is removed by laser irradiation. Subsequently, desmear treatment removes the resin residue generated during laser processing and the polyamide layer 32p that has been irradiated with the laser. As shown in Figure 8a, a conductor is embedded in the holes 34h to form vias 34.

[0174] Therefore, the semiconductor device 101 has polyamide layers 32p provided around multiple electrodes on at least the element surface S12. In other words, the polyamide layers 32p are provided around multiple electrodes (such as gate electrodes) exposed on the element surface S12, at least on the element surface S12. Naturally, the polyamide layers 32p may also be provided on the side surface of the second semiconductor element 12. Furthermore, the semiconductor device 101 also has polyamide layers 32p provided on a part of the surface of the second heat sink 22. In other words, the semiconductor device 101 has polyamide layers 32p provided around the area where the vias 34 of the second heat sink 22 are electrically connected.

[0175] Similarly, the first semiconductor element 11 and the first heat sink 21 may also be provided with a polyamide layer 32p. The parts where the vias 34 in the semiconductor elements 11, 12 and the heat sinks 21, 22 are electrically connected can also be called energized parts.

[0176] Therefore, the semiconductor device 101 can be configured to have improved adhesion between the resin portion of the build-up layer 32 and the heat sinks 21 and 22. In addition, the semiconductor device 101 can be configured to include semiconductor elements 11 and 12 that are less susceptible to laser damage.

[0177] As shown in the modified example in Figure 40, the semiconductor device 116 may also have a two-layer build-up layer 32. The build-up layer 32 comprises a first resin layer 323 that does not contain glass cloth and a second resin layer 322 that contains glass cloth, on the heat sinks 21 and 22. That is, the first resin layer 323 is mainly composed of resin without containing glass cloth. On the other hand, the second resin layer 322 is mainly composed of glass cloth and resin. In the stacking direction, the first resin layer 323 and the second resin layer 322 are stacked. The resin of the first resin layer 323 may be the same material as the resin of the second resin layer 322, or it may be a different material. This makes it possible to suppress a decrease in insulation between the pattern wiring 33 and the heat sinks 21 and 22.

[0178] As shown in the modified example in Figure 41, the build-up layer 32 may have fiber filler 324 embedded in it. This allows the build-up layer 32 to suppress deformation in the lamination direction.

[0179] As shown in the modified example in Figure 42, the semiconductor device 101 may be cut and individualized from a large substrate on which multiple semiconductor devices 101 are formed. The large substrate is a substrate from which multiple semiconductor devices 101 are cut. In this case, the dicing line DL on the large substrate may be composed of the resin portion of the build-up layer 32. That is, the core layer 31 may be covered with the resin in the build-up layer 32. Also, the sidewalls of the individualized semiconductor device 101 may be made of the resin in the build-up layer 32. Furthermore, the dicing line DL is not provided with pattern wiring 33 or the back metal layer 50. This suppresses the generation of metallic foreign matter when cutting the large substrate. Furthermore, it suppresses the adhesion of metallic foreign matter to wiring exposed on the surface. Note that metallic foreign matter can also be called metal shavings or cutting residue.

[0180] As shown in the modified examples in Figures 43, 44, and 45, the core layer 31e may be provided with through-holes 311 whose opening area gradually increases from the heat dissipation insulating layer 40 side. The first heat sink 21 is in contact with the part of the core layer 31e with the smallest opening area. The part with the smallest opening area is the part that is in contact with the first heat sink 21 and is therefore referred to as the contact part 31e2.

[0181] For example, as shown in Figure 43, the core layer 31e has a tapered shape 31e1 on the surface facing the first heat sink 21. In other words, a portion of the through hole 311 is surrounded by the tapered shape 31e1.

[0182] As shown in Figure 44, the tapered portion 31e1 and the contact portion 31e2 are positioned opposite the side surface of the first heat sink 21. Alternatively, as shown in the modified example in Figure 45, the tapered portion 31e1 and the contact portion 31e2 may be positioned opposite the corner of the first heat sink 21.

[0183] Furthermore, as shown in the modified example in Figure 46, the core layer 31f can also be used, which has through-holes 311 whose opening area gradually widens from the heat dissipation insulating layer 40 side. The core layer 31f has a stepped shape 31f1 on the surface facing the first heat sink 21. In other words, a part of the through-holes 311 is surrounded by the stepped shape 31f1. The first heat sink 21 is in contact with the contact portion 31f2, which has the narrowest opening area in the core layer 31f. The stepped shape 31f1 and the contact portion 31f2 are provided at positions facing the side surface of the first heat sink 21, or at positions facing the corner of the first heat sink 21, as described above.

[0184] The core layers 31e and 31f are configured similarly in the area where the second heatsink 22 is positioned. This improves the positional accuracy of the heatsinks 21 and 22 relative to the core layers 31e and 31f.

[0185] As shown in the modified example in Figure 47, the heat sinks 21h and 22h may have a chamfered shape at the corner 21h1 between the back surface S21 and the side surface S23 connected to the back surface S21. In Figure 47, a curved corner 21h1 is shown as an example.

[0186] As shown in Figure 48, the heat sinks 21h and 22h can be manufactured by press working. In other words, in press working, a plate-shaped member including the portion that will become the heat sinks 21h and 22h is placed on the die 510 and pressed in the direction of the white arrow by the punch 520. As a result, the plate-shaped member is cut at the cut surface CS, and the heat sinks 21h and 22h are formed. At this time, a burr 21h2 and a curved corner portion 21h1 are formed around the cut surface CS. The cut surface CS also becomes the side surface S23. The burr 21h2 can also be described as a protrusion.

[0187] The heat sinks 21h and 22h are used such that the surface adjacent to the corner 21h1 becomes the back surface S21, and the surface adjacent to the burr 21h2 becomes the front surface S22. Therefore, the heat sinks 21h and 22h are placed on the heat dissipation insulating layer 40 such that the surface adjacent to the corner 21h1 becomes the back surface S21. In addition, the heat sinks 21h and 22h are placed on the heat dissipation insulating layer 40 such that the burr 21h2 protruding from the front surface S22 faces the pattern wiring 33 side. The adjacent surfaces here refer to surfaces other than the side surface S23.

[0188] As a result, no burrs 21h2 are formed on the back surface S21 side of the semiconductor device 101, thus suppressing electric field concentration on the back surface S21 side. Therefore, the thickness of the heat dissipation insulating layer 40 of the semiconductor device 101 can be reduced, and heat dissipation can be improved. In other words, it becomes easier to ensure insulation and heat dissipation in the heat dissipation insulating layer 40.

[0189] Furthermore, the same effect can be achieved even if the corner portion 21h1 has a flat chamfered shape. In addition, by increasing the thickness of the resin in the build-up layer 32, the spacing between the pattern wiring 33 and the burr 21h2 can be increased.

[0190] Furthermore, the resin portion of the build-up layer 32 has a higher coefficient of thermal expansion than the heat sinks 21 and 22. In particular, there is a large difference in the coefficient of thermal expansion between the resin portion and the heat sinks 21 and 22 in the lamination direction. Also, the coefficient of thermal expansion in the lamination direction is significantly larger for the resin portion than for the heat sinks 21 and 22. Therefore, the resin portion expands more thermally than the heat sinks 21 and 22.

[0191] Therefore, stress due to the difference in coefficients of thermal expansion is easily applied to the areas where the resin part and the heat sinks 21 and 22 are in contact. In particular, repeated stress is applied to the resin part and the heat sinks 21 and 22 during solder reflow and thermal cycles, which may cause cracks or delamination at the corners 21h1.

[0192] However, the semiconductor device 101 has a curved shape at the corner 21h1. Therefore, the stress on the resin part at the point where it contacts the corner 21h1 is reduced.

[0193] As shown in the modified examples in Figures 49, 50, and 51, the first heat sink 21i has a plurality of side surfaces S23 connected to the back surface S21. The first heat sink 21i may also have a groove-shaped recess 213i provided across two side surfaces S23. In other words, the first heat sink 21i has a groove-shaped recess 213i as the area on which the first semiconductor element 11 is mounted. The groove-shaped recess 213i is provided by a bottom portion 211i and two side walls 212i connected to both ends of the bottom portion 211i. It can also be said that the groove-shaped recess 213i is defined by the bottom portion 211i and two opposing side walls 212i. Therefore, the groove-shaped recess 213i is provided between two side surfaces S23 that are in a positional relationship with each other.

[0194] Furthermore, as shown in the modified examples in Figures 52, 53, and 54, the first heat sink 21j may have groove-shaped recesses 213j provided across two sides S23. In other words, the first heat sink 21j has groove-shaped recesses 213j as the area on which the first semiconductor element 11 is mounted. The groove-shaped recess 213j is provided by a bottom portion 211j and a side wall 212j connected to one end of the bottom portion 211j. It can also be said that the groove-shaped recess 213j is defined by the bottom portion 211j and the side wall 212j.

[0195] The first heat sinks 21i and 21j can be manufactured by roll rolling. Therefore, the first heat sinks 21i and 21j can be manufactured at a relatively low cost. Thus, the cost of the first heat sinks 21i and 21j can be reduced. The heat sink 22 on which the second semiconductor element 12 is mounted may be configured in a similar manner.

[0196] The other modifications described so far are applicable to the above embodiments and modifications. Furthermore, the other modifications are applicable to the embodiments and modifications described below.

[0197] (13th Embodiment) The semiconductor device 117 of the 13th embodiment will be described with reference to Figures 55, 56, and 57. The semiconductor device 117 differs from the above embodiments and modifications mainly in that a heat dissipation insulating layer 40 is provided for each heat sink 21, 22.

[0198] As shown in Figure 55, the semiconductor device 117 comprises multiple integrated substrates, each of which is an integrated heat sink and heat dissipation insulating layer 40. In other words, the semiconductor device 117 has a heat sink 21, 22 and a heat dissipation insulating layer 40 for each semiconductor element 11, 12. That is, the semiconductor device 117 has the same number of heat sinks 21, 22 and the same number of heat dissipation insulating layers 40 as there are semiconductor elements 11, 12.

[0199] More specifically, the first semiconductor element 11 is mounted on the first heat sink 21. The back surface S21 of the first heat sink 21 is provided with a heat dissipation insulating layer 40. The heat dissipation insulating layer 40 is in contact with the back surface S21 of the first heat sink 21. The first heat sink 21 and the heat dissipation insulating layer 40 to which the first heat sink 21 is connected can also be called the first integrated substrate.

[0200] The second semiconductor element 12 is mounted on the second heat sink 22. The back surface S21 of the second heat sink 22 is provided with a heat dissipation insulating layer 40. The heat dissipation insulating layer 40 is in contact with the back surface S21 of the second heat sink 22. The second heat sink 22 is connected to a heat dissipation insulating layer 40 that is separate from the heat dissipation insulating layer 40 on the first integrated substrate. The second heat sink 22 and the heat dissipation insulating layer 40 to which the second heat sink 22 is connected can also be considered the second integrated substrate.

[0201] Furthermore, the semiconductor device 117 includes a back metal layer 50 in contact with the side of each heat dissipation insulating layer 40 opposite to the heat sinks 21 and 22. In other words, the heat dissipation insulating layer 40 has the heat sinks 21 and 22 connected to one side and the back metal layer 50 connected to the other side. The other side is the side opposite to the one side.

[0202] The first integrated substrate may include a back metal layer 50. Similarly, the second integrated substrate may include a back metal layer 50. In this case, the first integrated substrate comprises a pair of first heat sinks 21, a heat dissipation insulating layer 40, and a back metal layer 50. On the other hand, the second integrated substrate comprises a pair of second heat sinks 22, a heat dissipation insulating layer 40, and a back metal layer 50. The first heat sink 21 and the back metal layer 50 of the first integrated substrate are electrically insulated by the heat dissipation insulating layer 40 of the first integrated substrate. The second heat sink 22 and the back metal layer 50 of the second integrated substrate are electrically insulated by the heat dissipation insulating layer 40 of the second integrated substrate.

[0203] In this embodiment, as an example, heat sinks 21 and 22 with a plate thickness greater than the back metal layer 50 are used. However, the heat sinks 21 and 22 and the back metal layer 50 may have similar plate thicknesses. Also, the heat sinks 21 and 22 and the back metal layer 50 may be configured to the extent that they can be patterned. The heat sinks 21 and 22 can also be called the first metal layer or the first metal film. On the other hand, the back metal layer 50 can also be called the second metal layer or the second metal film.

[0204] Each integrated substrate is placed in a through-hole 311 of the core layer 31. In other words, the core layer 31 is provided with multiple through-holes 311. Each integrated substrate is individually placed in each through-hole 311.

[0205] The semiconductor device 117, like the semiconductor device 101, includes a build-up layer 32. Furthermore, the semiconductor device 117 has a back-side build-up layer 32a on the heat dissipation insulating layer 40 side. In this embodiment, as an example, a back-side build-up layer 32a is employed which includes an electrically insulating resin portion, conductive heat dissipation vias 34a, and a conductive heat dissipation metal layer 33a.

[0206] The heat dissipation vias 34a are connected to the side of the back metal layer 50 opposite to the side in contact with the heat dissipation insulating layer 40. Multiple heat dissipation vias 34a are connected to the heat dissipation metal layer 33a. The back side build-up layer 32a has the heat dissipation metal layer 33a exposed from the resin portion. The heat dissipation metal layer 33a functions as a heat dissipation component on the back side.

[0207] However, the present disclosure does not require the provision of heat dissipation vias 34a and heat dissipation metal layer 33a. In this case, it is preferable that the back metal layer 50 of the semiconductor device 117 is exposed from the resin portion of the back side build-up layer 32a. This allows the semiconductor device 117 to dissipate heat from the back metal layer 50 even without the provision of heat dissipation vias 34a and heat dissipation metal layer 33a.

[0208] Here, we will explain the integrated substrate in detail. As shown in Figure 55, the heat dissipation insulating layer 40 is provided so as to protrude in the planar direction from the heat sink sides of the heat sinks 21 and 22 and the back metal layer sides of the back metal layer 50. In other words, the heat dissipation insulating layer 40 is longer than the heat sinks 21 and 22 and the back metal layer 50 in the planar direction. To put it another way, the heat sinks 21 and 22 and the back metal layer 50 are shorter than the heat dissipation insulating layer 40 in the planar direction.

[0209] This allows for a longer creepage distance (insulation distance) between the first heat sink 21 and the back metal layer 50 of the first integrated substrate. Similarly, the creepage distance between the second heat sink 22 and the back metal layer 50 of the second integrated substrate can be increased. In other words, the semiconductor device 117 can have a longer creepage distance than a configuration in which the heat dissipation insulating layer 40 does not protrude. The semiconductor device 117 can ensure sufficient insulation distance between the heat sinks 21, 22 and the back metal layer 50 within the integrated substrate. Note that the heat dissipation insulating layer 40 only needs to protrude in the planar direction relative to at least one of the heat sinks 21, 22 and the back metal layer 50.

[0210] Furthermore, as described above, the semiconductor device 117 has a configuration in which the heat dissipation insulating layer 40 protrudes relative to the heat sinks 21, 22 and the back metal layer 50. Therefore, in the semiconductor device 117, the distance between the heat sinks 21, 22, the back metal layer 50 and the core layer 31 is larger than that in the semiconductor device 101. The distance herein refers to a distance in the planar direction. The distance herein can also be referred to as a gap between the heat sinks 21, 22, the back metal layer 50 and the core layer 31.

[0211] Therefore, in the semiconductor device 117, it is necessary to increase the amount of resin in the build-up layer 32 compared to the semiconductor device 101. However, there is a concern that the amount of resin in the build-up layer 32 is insufficient in the semiconductor device 117, leading to large overall thickness variation. In addition, the resin portion of the build-up layer 32 has a larger coefficient of linear expansion than that of the heat sinks 21, 22 and the like. Therefore, there is a risk that increasing the amount of resin in the semiconductor device 117 increases the stress caused by the difference in coefficient of linear expansion. There is a concern that the stress may cause cracks in the resin portion of the semiconductor device 117, or peeling at the boundary between the resin portion and the heat sinks 21, 22.

[0212] In view of this, the integrated substrate is provided with an electrically insulating insulating member 38 on a side surface of the heat sink. The insulating member 38 is provided on one side in the lamination direction with respect to the heat dissipation insulating layer 40, and is provided in the planar direction with respect to the heat sinks 21, 22. The insulating member 38 is in contact with the heat dissipation insulating layer 40 and the heat sinks 21, 22. It is preferable that the insulating member 38 is made of a material having a coefficient of linear expansion close to that of the heat sinks 21, 22. When the heat sinks 21, 22 are mainly composed of copper, it is preferable that the insulating member 38 is made of a material having a coefficient of linear expansion close to that of copper. The insulating member 38 can be provided by molding or the like.

[0213] Thereby, the semiconductor device 117 can suppress an increase in the amount of resin in the build-up layer 32. Therefore, the semiconductor device 117 can suppress the aforementioned thickness variation, cracks and peeling. Note that the insulating member 38 only needs to be provided on at least one of the side surface of the heat sink and the side surface of the back metal layer.

[0214] Here, the manufacturing method of the semiconductor device 117 will be explained using Figures 56 and 57. In this manufacturing method, the process shown in Figure 7b is followed by the process shown in Figure 56a. In Figure 56a, the core layer 31 is placed on the back-side build-up layer 32a, and the integrated substrate is placed in the through-hole 311. In this case, the integrated substrate provided with the insulating member 38 is placed.

[0215] Subsequently, in Figure 56b, a build-up layer 32 is placed on the core layer 31, similar to Figure 7e. Here, the build-up layer 32 does not have pattern wiring 33 or vias 34 formed on it. Reference numeral 33 denotes a thin film of copper or the like before patterning. Then, in Figure 56c, press molding is performed, similar to Figure 7f.

[0216] Next, as shown in Figure 57a, vias 34 and heat dissipation vias 34a are formed. Filled vias are formed as vias 34 and heat dissipation vias 34a (filled via formation step). Then, as shown in Figure 57b, the thin film is patterned to form pattern wiring 33 (pattern wiring formation step). Finally, as shown in Figure 57c, solder resist 35 is formed (solder resist formation step).

[0217] As shown in Figure 58, the insulating member 38 may be provided on both the side surface of the heat sink and the side surface of the back metal layer. The insulating member 38 is provided on one side in the stacking direction relative to the heat dissipation insulating layer 40 and on the planar side relative to the heat sinks 21 and 22. Furthermore, the insulating member 38 is provided on the other side in the stacking direction relative to the heat dissipation insulating layer 40 and on the planar side relative to the back metal layer 50. The insulating member 38 is in contact with the heat dissipation insulating layer 40, the heat sinks 21 and 22, and the back metal layer 50. The insulating member 38 can be provided by molding or the like.

[0218] As shown in Figure 59, the insulating member 38 may be provided so as to cover the entire integrated substrate and also cover the semiconductor elements 11 and 12 mounted on the heat sinks 21 and 22. The insulating member 38 may also be provided in the gap between the semiconductor elements 11 and 12 and the heat sinks 21 and 22. The insulating member 38 may also be provided so as to cover the electrodes of the semiconductor elements 11 and 12. In this case, the insulating member 38 in areas where wiring needs to be routed may be removed with a laser. The insulating member 38 can be provided by potting or the like.

[0219] Furthermore, as shown in Figures 60 to 62, the shape of the core layer 31g may suppress an increase in the gap between the heat sink and the core, thereby suppressing an increase in the amount of resin in the build-up layer 32. The semiconductor device 118 is a modified example of the semiconductor device 117. The semiconductor device 118 includes a core layer 31g. The core layer 31g includes a core base 31g1 and a core projection 31g2 that protrudes in a planar direction relative to the core base 31g1. The core projection 31g2 is provided adjacent to the heat sinks 21 and 22 in the planar direction. The core base 31g1 is the same as that of the core layer 31. The planar direction can also be said to be a direction intersecting the stacking direction. As a result, the semiconductor device 118 can suppress an increase in the amount of resin in the build-up layer 32 without including an insulating member 38.

[0220] The core base 31g1 and the core protrusion 31g2 can be provided as separate components. In this case, as shown in Figure 61, the core base 31g1 is placed on the back-side build-up layer 32a, and the integrated substrate is placed in the through-hole 311. Then, as shown in Figure 62, the core protrusion 31g2 is placed on the core base 31g1. However, the core base 31g1 and the core protrusion 31g2 may be provided as a single integrated component.

[0221] Incidentally, as shown in Figure 39c, vias 34 are formed by embedding a conductor in a hole 34h formed by a laser. Laser irradiation is performed using a positioning reference. The core layer 31 is embedded in the build-up layer 32. Therefore, the positioning reference is detected by X-rays or the like. The positioning reference can also be called an alignment mark.

[0222] The positioning reference is provided on the surface of the core layer 31, etc. In this case, the positioning reference is located relatively far from the electrodes of the semiconductor elements 11 and 12. Therefore, there is a concern that the position tolerance variation to the electrodes will be large with this positioning reference. If the position tolerance is large, it becomes necessary to enlarge the electrodes of the semiconductor elements 11 and 12, which are the target values. Therefore, if the size of the semiconductor elements 11 and 12 is not changed, the active area will be reduced. Also, in order to secure the active area, the size of the semiconductor elements 11 and 12 needs to be increased. The electrodes of the semiconductor elements 11 and 12 are electrodes (gate electrodes, etc.) provided on the element surface S12.

[0223] Therefore, as shown in Figures 63 and 64, a first integrated substrate having positioning holes 21ph that penetrate in the thickness direction may be used as a modified example of the semiconductor device 117. In other words, as shown in Figure 64, the heat sink 21, the heat dissipation insulating layer 40, and the back metal layer 50 are provided with positioning holes 21ph that penetrate in the stacking direction. The positioning holes 21ph are holes that serve as a positioning reference for laser irradiation.

[0224] Therefore, when forming vias 34, the positioning holes 21ph are detected using X-rays or the like. Then, a laser is irradiated to the position where the vias 34 will be formed, using the positioning holes 21ph as a reference. The position where the vias 34 are formed is, for example, a portion formed on the electrode of the element surface S12 in the build-up layer 32. In Figure 63, the element surface S12 of the semiconductor element 11 is shown. Therefore, gate electrodes and the like are provided within the semiconductor element 11 shown in Figure 63. The positioning holes 21ph may also be provided on the second integrated substrate.

[0225] This reduces positional tolerance variations. As a result, semiconductor elements 11 and 12 can secure an active area without increasing their size.

[0226] Furthermore, the positioning hole 21ph can be applied to configurations other than the semiconductor device 117. In other words, even in configurations other than the conductor device 117, the positioning hole 21ph can be used as a positioning reference for laser irradiation. Configurations other than the semiconductor device 117 include the semiconductor device 118, the first to twelfth embodiments, and their respective modified configurations. Configurations other than the semiconductor device 117 also include the embodiments and their respective modified configurations described below.

[0227] Furthermore, as shown in Figures 65 and 66, a first integrated substrate provided with a positioning boundary portion 21bd may be used as a modified example of the semiconductor device 117. The first integrated substrate comprises a first heat sink 21 mainly composed of copper and a heat dissipation insulating layer 40 mainly composed of resin. Therefore, as shown in Figure 65, in a plan view, the boundary between the first heat sink 21 and the heat dissipation insulating layer 40 of the first integrated substrate is provided as a positioning boundary portion 21bd. The positioning boundary portion 21bd is a positioning reference that utilizes the difference in X-ray transmittance.

[0228] In this way, even if the positional boundary portion 21bd is formed, the variation in positional tolerance can be reduced. Therefore, the semiconductor elements 11 and 12 can secure an active area without increasing the size of the elements.

[0229] Furthermore, the positioning boundary portion 21bd can be applied to configurations other than the semiconductor device 117. In other words, even in configurations other than the conductive device 117, the positioning boundary portion 21bd can be used as a positioning reference for laser irradiation. Also, the positioning boundary portion 21bd can be applied to any configuration in which the heat dissipation insulating layer 40 protrudes in the planar direction relative to the heat sinks 21 and 22.

[0230] As shown in the modified example in Figure 67, the semiconductor device 119 may also be provided with heat dissipation wiring 338. The semiconductor device 119 is a modified example of the semiconductor device 101. The build-up layer 32 is provided with stacked pattern wiring 33. Note that the semiconductor device 119 is a cross-sectional view of a location where semiconductor elements 11 and 12 are not provided.

[0231] In Figure 67, reference numeral 331 indicates a P-wiring section in pattern wiring 33, including a P-pad 331. The P-pad 331 is a terminal on the high-potential side. Therefore, the P-wiring section can also be called a high-potential side wiring section. Here, reference numeral 331 is also used for the P-wiring section. The P-wiring section 331 is connected to the high-potential side electrodes of semiconductor elements 11 and 12. Note that the P-wiring section 331 only needs to be electrically connected to the high-potential side electrodes; it does not need to be directly connected.

[0232] Furthermore, in Figure 67, reference numeral 335 represents the N wiring section in the pattern wiring 33, including the N pad 335. The N pad 335 is a terminal on the low-potential side. Therefore, the N wiring section can also be called the low-potential side wiring section. Here, reference numeral 335 is also used for the N wiring section. The N wiring section 335 is connected to the low-potential side electrodes of the semiconductor elements 11 and 12. Note that the N wiring section 335 only needs to be electrically connected to the low-potential side electrodes; it does not need to be directly connected. Also, in Figure 67, reference numeral 333 represents the O wiring section in the pattern wiring 33, including the O pad 333. The O pad 333 is an output terminal. Here, reference numeral 333 is also used for the O wiring section. The O wiring section can also be called the output wiring section.

[0233] As shown in Figure 67, the heat dissipation wiring 338 is part of the pattern wiring 33. In the stacking direction, the heat dissipation wiring 338 is positioned between the P wiring section 331 and the N wiring section 335 and the O wiring section 333. In the planar direction, the heat dissipation wiring 338 is positioned between the P wiring section 331 and the O wiring section 333, between the P wiring section 331 and the N wiring section 335, and between the N wiring section 335 and the O wiring section 333. The heat dissipation wiring 338 is connected to the second heat sink 22 via via 34. The heat dissipation wiring 338 may also be connected to the first heat sink 21.

[0234] Heat is transferred to the heat radiation wiring 338 from the P wiring portion 331, the O wiring portion 333, and the N wiring portion 335, as indicated by the dashed-dotted arrow. The heat radiation wiring 338 can dissipate heat to the second heat sink 22 via the via 34. That is, the heat radiation wiring 338 functions as a heat radiation path.

[0235] Therefore, the semiconductor device 119 can improve the heat radiation performance of the wiring in the build-up layer 32. In addition, the heat radiation wiring 338 also functions as an electric field relaxation layer.

[0236] Note that the heat radiation wiring 338 can also be applied to configurations other than the semiconductor device 101. Configurations other than the semiconductor device 101 refer to the configurations of the second to thirteenth embodiments and each modification. In addition, configurations other than the semiconductor device 101 also include the configurations of the embodiments and modifications described below.

[0237] As shown in FIG. 68 and FIG. 69, the first semiconductor element 11 may have a dummy electrode 11de on the element surface S12. The dummy electrode 11de can also be referred to as a dummy pad provided on the element surface S12 of the first semiconductor element 11. In addition, the dummy electrode 11de is a non-conductive electrode. That is, unlike a gate electrode or the like, the dummy electrode 11de does not have an electrical function.

[0238] The dummy electrode 11de is provided at the same position as a gate electrode or the like provided on the element surface S12 of the first semiconductor element 11. The position herein refers to the position in the lamination direction.

[0239] It is preferable that the dummy electrode 11de is provided in the inactive region of the first semiconductor element 11. As will be described later, the dummy electrode 11de is irradiated with laser. By providing the dummy electrode 11de in the inactive region, the influence on the characteristics of the first semiconductor element 11 can be suppressed even if it is damaged by laser irradiation.

[0240] The dummy electrode 11de is preferably composed mainly of silver or aluminum, which have high laser reflectivity. Silver or aluminum can be formed by electrode plating, stud bonding, paste coating, sputtering, etc.

[0241] As shown in Figure 69, when forming the via 34, a hole 34h is created by irradiating it with a laser from the direction of the white arrow. The distance at which the laser drills the hole varies depending on the thickness of the build-up layer 32. Normally, the laser drills the hole according to predetermined laser processing conditions. Therefore, if the thickness of the build-up layer 32 is thinner than expected, damage to the first semiconductor element 11 may occur. To mitigate damage to the first semiconductor element 11, it is conceivable to increase the thickness of the electrodes on the element surface S12. However, increasing the plating thickness of the electrodes increases costs.

[0242] The dummy electrode 11de is used to measure the distance when creating the hole 34h. In other words, the dummy electrode 11de is used to measure the depth hd1 of the hole 34h. The depth hd1 can also be described as the distance from the surface of the pattern wiring 33 to the electrode on the element surface S12. Furthermore, the depth hd1 can also be described as the distance at which the hole 34h is made.

[0243] Therefore, when forming the via 34, the dummy electrode 11de is first irradiated with a laser to measure the depth hf1 of the hole 34h to be formed. Then, using the measurement result as the laser processing condition, the hole 34h is formed in the build-up layer 32 with a laser. As a result, damage to the first semiconductor element 11 can be suppressed without increasing the plating thickness.

[0244] Furthermore, the dummy electrode 11de can be applied to configurations other than the semiconductor device 101. The dummy electrode 11de may also be provided on the second semiconductor element 12.

[0245] In the first embodiment, an example was adopted in which through holes 311 were formed in the core layer 31 by punching. However, as a modified example of the semiconductor device 101, a core layer 31 manufactured by injection molding using liquid crystal polymer or transfer molding using epoxy resin may be used. As shown in Figure 70, the core layer 31 has through holes 311 provided in advance without punching or drilling.

[0246] In this case, the core layer 31 can be a liquid crystal polymer that does not contain glass cloth, or an epoxy resin that does not contain glass cloth. Furthermore, the core layer 31 can be said to be composed of a resin having an isotropic coefficient of thermal expansion.

[0247] As shown in Figure 71, the heat sinks 21 and 22 are placed in the through-holes 311 of the core layer 31. Figure 71 is a cross-sectional view of the area corresponding to the cross-sectional indicator line in Figure 70. Then, as shown in Figure 72, the build-up layer 32 is formed. Note that in Figure 72, the wiring is omitted from the diagram for simplicity. A portion of the build-up layer 32 is also placed in the gap between the heat sinks 21 and 22 and the core layer 31. However, for convenience, it is referred to as the build-up layer 32 in this disclosure.

[0248] The core layer 31 is formed by resin molding using a mold. Therefore, the core layer 31 can have less dimensional variation than if through holes 311 were formed by drilling or other methods. Thus, variations in the gap between the core layer 31 and the heat sinks 21 and 22 can be suppressed. Consequently, variations in the amount of resin in the build-up layer 32 provided in that gap can also be suppressed. Furthermore, the semiconductor device 101 can suppress cracks and delamination caused by an increase in the amount of resin in the build-up layer 32.

[0249] Furthermore, it is preferable that the core layer 31 is made of a material with a coefficient of thermal expansion close to that of the resin portion of the build-up layer 32. This allows the core layer 31 and the build-up layer 32 to relieve stress associated with the difference in coefficients of thermal expansion. As a result, the semiconductor device 101 can suppress the application of stress to the pattern wiring 33, vias 34, and semiconductor elements 11 and 12, thereby improving reliability.

[0250] Furthermore, the core layer 31, which is formed by resin molding using a mold, can be applied to configurations other than the semiconductor device 101. The core layer 31, which is made of a resin having an isotropic coefficient of thermal expansion, can be applied to configurations other than the semiconductor device 101.

[0251] As shown in the modified examples in Figures 73 and 74, the semiconductor device 101 can also be a heat sink 21k in which a heat sink protrusion 21k1 is provided on the surface facing the core layer 31. The heat sink protrusion 21k1 is a portion that protrudes from the side surface S23. The surface facing the core layer 31 corresponds to the side surface S23.

[0252] As shown in Figure 73, in the manufacturing process of the semiconductor device 101, a build-up layer 32 is formed with a gap between the core layer 31 and the heat sink 21k. At this time, it may not be possible to completely fill the gap between the core layer 31 and the heat sink 21k with the build-up layer 32. In other words, a recess may be formed between the core layer 31 and the heat sink 21k in the build-up layer 32.

[0253] Therefore, as shown in Figure 74, the heat dissipation insulating layer 40 is connected to the core layer 31 and the heat sink 21k with a recess formed between them. As a result, the heat dissipation insulating layer 40 takes on a shape that fits into this recess. In other words, a portion of the heat dissipation insulating layer 40 is also formed between the core layer 31 and the heat sink 21k. Furthermore, this recess may not be filled by the heat dissipation insulating layer 40. In other words, voids may occur between the heat dissipation insulating layer 40 and the build-up layer 32.

[0254] Figure 74 shows the state in which the depression is filled with the heat dissipation insulating layer 40. Reference numeral 40V indicates the apex of the heat dissipation insulating layer 40. If the depression is not filled with the heat dissipation insulating layer 40, a void will be formed at the apex 40V.

[0255] In this case, stress concentrates in the build-up layer 32 near the apex 40V of the heat dissipation insulating layer 40. Then, cracks may develop in the build-up layer 32, starting from near the apex 40V of the heat dissipation insulating layer 40. Furthermore, if these cracks reach the heat sink 21k, the interface between the build-up layer 32 and the heat sink 21k may delaminate.

[0256] However, the heat sink 21k is provided with a heat sink protrusion 21k1. Therefore, the semiconductor device 101 can suppress the propagation of cracks and delamination. The heat sink protrusion 21k1 may also be provided on the second heat sink 22.

[0257] As shown in the modified example in Figure 75, the semiconductor device 101 can also be a heat sink 21k in which a heat sink recess 21k2 is provided on the surface facing the core layer 31. The heat sink recess 21k2 is a recessed portion relative to the side surface S23. Even if the semiconductor device 101 is equipped with a heat sink 21k with a heat sink recess 21k2, the propagation of cracks and delamination can be suppressed. The heat sink recess 21k2 may also be provided on the second heat sink 22. The heat sink protrusion 21k1 and the heat sink recess 21k2 can also be applied to configurations other than the semiconductor device 101.

[0258] (14th Embodiment) The semiconductor device 120 of the 14th embodiment will be described with reference to Figures 76 and 77. The semiconductor device 120 differs from the above embodiments and modifications mainly in that it is equipped with a surface heat dissipation insulating layer 40t.

[0259] As shown in Figure 76, the semiconductor device 120 has the same configuration as the semiconductor device 101. Furthermore, the semiconductor device 120 is provided with a surface heat dissipation insulating layer 40t. The surface heat dissipation insulating layer 40t is provided so as to be in contact with the build-up layer 32. In other words, the semiconductor device 120 has a core layer 31 between the heat dissipation insulating layer 40 and the surface heat dissipation insulating layer 40t. Also, in the stacking direction, the semiconductor device 120 is provided in the order of heat dissipation insulating layer 40, core layer 31, and surface heat dissipation insulating layer 40t. Note that the heat dissipation insulating layer 40 and the surface heat dissipation insulating layer 40t may be made of the same material or different materials.

[0260] The semiconductor device 120 has pattern wiring 33 and vias 34 between the surface heat dissipation insulating layer 40t and the semiconductor elements 11 and 12. The surface heat dissipation insulating layer 40t and the semiconductor elements 11 and 12 are connected by the pattern wiring 33 and vias 34. In addition, the surface heat dissipation insulating layer 40t and the semiconductor elements 11 and 12 are connected by pattern wiring 33 and vias 34 provided directly above the semiconductor elements 11 and 12. As a result, the semiconductor device 120 can more easily transfer heat from the semiconductor elements 11 and 12 to the surface heat dissipation insulating layer 40t, thereby improving heat dissipation.

[0261] Furthermore, the semiconductor device 120 includes a surface metal layer 50t in contact with the side of the surface heat dissipation insulating layer 40t opposite to the build-up layer 32. In other words, the semiconductor device 120 has a back metal layer 50 on one surface and a surface metal layer 50t on the opposite surface. The surface metal layer 50t may be made of the same material as the back metal layer 50, or it may be made of a different material. Therefore, the semiconductor device 120 can also be said to have a double-sided heat dissipation structure.

[0262] The wiring of the semiconductor device 120 includes a plurality of external connection parts 331 to 337 exposed from the surface heat dissipation insulating layer 40t. It can also be said that a portion of the wiring in the semiconductor device 120 is exposed to the outside of the build-up layer 32. In this embodiment, a surface metal layer 50t is provided on the surface heat dissipation insulating layer 40t. Therefore, the plurality of external connection parts 331 to 337 are exposed from both the surface heat dissipation insulating layer 40t and the surface metal layer 50t. Figure 76 shows a first gate pad 332 and a second gate pad 334 as examples of external connection parts.

[0263] In other words, the surface heat dissipation insulating layer 40t and the surface metal layer 50t have holes to expose the external connection parts 331 to 337. It can also be said that the surface heat dissipation insulating layer 40t and the surface metal layer 50t have holes to allow the external connection parts 331 to 337 to be electrically connected to the terminals of the external device. The external device is a device provided outside the semiconductor device 120.

[0264] Here, the manufacturing method of the semiconductor device 120 will be explained using Figure 77. In this manufacturing method, the process shown in Figure 77a is performed after the process shown in Figure 8b. In Figure 77a, an electrically insulating resin 35a is embedded between the patterned wirings 33. Then, in Figure 77b, a surface heat dissipation insulating layer 40t and a surface metal layer 50t are placed on the build-up layer 32. Then, as shown in Figure 77c, press molding is performed. Alternatively, the surface heat dissipation insulating layer 40t may be patterned (perforated) after being joined to the build-up layer 32 in order to extract electrodes. In this way, the gaps between the patterned wirings can be filled with the resin of the surface heat dissipation insulating layer 40t. In other words, resin can be provided between the patterned wirings 33 without using resin 35a.

[0265] The semiconductor device 120 can dissipate heat not only from the back metal layer 50 side but also from the front metal layer 50t side. Therefore, the semiconductor device 120 can achieve improved heat dissipation compared to the semiconductor device 101.

[0266] As shown in Figure 78, the semiconductor device 121 may have a heat-diffusing wiring section 34hd in part of its wiring that is wider than the heat sinks 21 and 22. In other words, the length of the heat-diffusing wiring section 34hd in the planar direction is longer than that of the heat sinks 21 and 22.

[0267] As a result, heat from the semiconductor element 12 is transferred to the heat diffusion wiring section 34hd via the via 34 in the semiconductor device 121. Then, the semiconductor device 121 can diffuse the heat through the heat diffusion wiring section 34hd.

[0268] The semiconductor device 121 is a modified version of the semiconductor device 120. The heat diffusion wiring section 34hd can also be applied to configurations other than the semiconductor device 121. Configurations other than the semiconductor device 121 include the configurations of the first to thirteenth embodiments and each modified version. Furthermore, configurations other than the semiconductor device 121 also include the configurations of each modified version described below.

[0269] As shown in the modified example in Figure 79, the first semiconductor element 11 may have a protective element film 11e provided around the electrodes on the element surface S12 to protect the first semiconductor element 11. The protective element film 11e is mainly composed of polyimide or the like. The electrodes have a two-layer structure, for example, a nickel plating layer 11c and a copper plating layer 11d.

[0270] Furthermore, the electrodes on the element surface S12 may be taller than the element protective film 11e. Here, height refers to the thickness in the stacking direction. In other words, the value obtained by subtracting the element protective film height L12 from the electrode height L11 is greater than or equal to 0.

[0271] The first semiconductor element 11 is mounted (bonded) to the first heat sink 21 by sintering, using a metal sintered material such as silver or copper as the connecting member 60. In the sintering process, a pressurizing step is required to pressurize the first semiconductor element 11 and the first heat sink 21 in a direction that brings them closer together.

[0272] During the pressurization process, the pressurizing jig comes into contact with the element surface S12 of the first semiconductor element 11. At this time, the pressurization process may be performed with foreign matter trapped between the pressurizing jig and the element protective film 11e. In this case, the element protective film 11e may be damaged by the foreign matter. If the element protective film 11e of the first semiconductor element 11 is damaged, electrical malfunctions such as short circuits may occur.

[0273] However, since the electrode height L11 and the element protective film height L12 of the first semiconductor element 11 are set as described above, the pressurizing jig is less likely to come into contact with the element protective film 11e. Therefore, the semiconductor device 120 can suppress electrical malfunctions.

[0274] The configuration of the first semiconductor element 11 can also be applied to configurations other than those of the semiconductor device 120. Configurations other than those of the semiconductor device 120 include the configurations of the first to thirteenth embodiments and their respective modifications. Furthermore, configurations other than those of the semiconductor device 120 also include the configurations of the respective modifications described below. The same configuration may also be applied to the second semiconductor element 12.

[0275] Incidentally, the solder resist 35 used in semiconductor device 101 has relatively low heat resistance and a larger coefficient of thermal expansion compared to other components. Therefore, the semiconductor device 101 is prone to cracks originating from the solder resist 35. Furthermore, it is possible that these cracks in the semiconductor device 101 may propagate into the build-up layer 32.

[0276] Therefore, the solder resist 35 of the semiconductor device 101 may be made of the same material used for the element protection film 11e. In other words, the element protection film 11e may cover a portion of the wiring that is exposed to the outside. This allows the semiconductor device 101 to suppress the occurrence and propagation of cracks. The solder resist 35 made of the same material used for the element protection film 11e can also be applied to configurations other than the semiconductor device 101.

[0277] As shown in Figures 80 and 81, the semiconductor device 101 may be mounted on the cooler 200. A graphite sheet 80e is provided between the semiconductor device 101 and the cooler 200. The graphite sheet 80e is a sheet-like material mainly composed of graphite. The graphite sheet 80e is a thermally conductive sheet with high thermal conductivity.

[0278] The graphite sheet 80e has adhesive 80e1 embedded in it. The adhesive 80e1 is provided so as to be exposed on both sides of the graphite sheet 80e. In other words, the adhesive 80e1 is provided along the thickness direction of the graphite sheet 80e. Preferably, the adhesive 80e1 is provided, for example, around the periphery of the opposing regions of the semiconductor elements 11 and 12 in the lamination direction. The adhesive 80e1 can be provided by creating through holes in the graphite sheet 80e and filling those through holes with the adhesive. Note that a graphite sheet without adhesive 80e1 is also called a thermal conductive sheet.

[0279] Thermal conductive sheets generally do not have an adhesive 80e1 and therefore do not possess adhesive properties. For this reason, the thermal conductive sheet is used under pressure between the back metal layer 50 and the cooler 200 to facilitate contact between the back metal layer 50 and the cooler 200. Furthermore, the thermal conductive sheet is used under pressure to reduce thermal resistance between the back metal layer 50 and the cooler 200. A pressurizing member, such as a spring, is used for this pressurization.

[0280] However, the graphite sheet 80e is equipped with an adhesive 80e1. Therefore, the graphite sheet 80e adheres easily to the back metal layer 50 and the cooler 200. Thus, the semiconductor device 101 can make contact between the back metal layer 50 and the cooler 200 without using a pressurizing member. Since the semiconductor device 101 does not require a pressurizing member, an increase in its size can be suppressed.

[0281] Incidentally, the adhesive 80e1 has a lower thermal conductivity than the material mainly composed of graphite. However, in the graphite sheet 80e, the adhesive 80e1 is provided around the regions facing the semiconductor elements 11 and 12. In other words, in the graphite sheet 80e, the parts mainly composed of graphite are positioned in the regions facing the semiconductor elements 11 and 12. Therefore, the graphite sheet 80e can improve the heat dissipation of the semiconductor elements 11 and 12 while maintaining its adhesive function. To put it another way, the graphite sheet 80e can suppress the reduction in heat dissipation caused by the adhesive 80e1.

[0282] Note that both sides of the graphite sheet 80e are two surfaces in the lamination direction. Both sides of the graphite sheet 80e correspond to the surface of the sheet-like member. The thickness direction of the graphite sheet 80e coincides with the lamination direction.

[0283] As shown in Figure 82, the semiconductor device 123 includes power connection sections P pad 331, O pad 333, and N pad 335. The semiconductor device 123 also includes a signal connection section signal pad 332. In other words, the semiconductor device 123 includes multiple power connection sections and multiple signal connection sections. The semiconductor device 123 is a modified example of the semiconductor device 120.

[0284] The P pad 331, O pad 333, and N pad 335 are positioned biasedly on one side wall of the semiconductor device 123. The multiple signal pads 332 are positioned biasedly on the other side wall of the semiconductor device 123. Note that the two side walls are opposite each other.

[0285] Furthermore, as shown in Figures 82 and 83, the P pad 331, O pad 333, N pad 335, and the multiple signal pads 332 are spaced apart. The surface metal layer 50t is provided between the O pad 333, N pad 335, and the multiple signal pads 332. Therefore, the semiconductor device 123 can be easily fitted with a cooler 200 not only on the back metal layer 50 side but also on the front metal layer 50t side.

[0286] Figure 83 is a cross-sectional view taken along the cross-sectional indicator line in Figure 82. Furthermore, Figure 83 shows the cooler 200, connector 902, and external power terminal 903 connected to the semiconductor device 123.

[0287] The connector 902 is equipped with multiple external signal terminals 901. The external signal terminals 901 are electrically connected to the signal pads 332 via a conductive block 801 and solder 700. In other words, each signal pad 332 is individually electrically connected to an external signal terminal 901.

[0288] The external power terminal 903 is electrically connected to the N pad 335 via a conductive block 802 and solder 700. The external power terminal 903 is similarly connected to the P pad 331 and the O pad 333. In other words, the semiconductor device 123 has the same number of external power terminals 903 connected as the number of power connection points.

[0289] As shown in Figure 83, the heat dissipation insulating layer 40 is thinner than the surface heat dissipation insulating layer 40t. The back metal layer 50 is thinner than the surface metal layer 50t. However, the heat dissipation insulating layer 40 and the surface heat dissipation insulating layer 40t may be of similar thickness. The back metal layer 50 and the surface metal layer 50t may be of similar thickness.

[0290] As shown in Figure 84, the semiconductor device 123 may be connected to a flexible substrate 904 instead of the connector 902. The flexible substrate 904 may be provided with, for example, a reinforcing plate 905.

[0291] As shown in Figure 85, the connector 902 is equipped with an external signal terminal 906 that includes a bent portion. This allows the connector 902 to be connected to the signal pad 332 via solder 700 without using the block body 801.

[0292] Here, we will explain an example of wiring arrangement in a semiconductor device with a double-sided heat dissipation structure, such as semiconductor device 123. First, we will explain one wiring example using Figures 86 to 92 (first wiring example). Figure 86 shows the heat sink surface S22 of heat sinks 21 and 22 and the element surface S12 of semiconductor elements 11 and 12. In the first wiring example, similar to semiconductor device 123, the P pad 331, O pad 333, and N pad 335 are arranged biased to one side wall, and the multiple signal pads 332 are arranged biased to the other side wall.

[0293] As shown in Figure 86, the heat sink surface S22 is provided with a group of vias including multiple vias 34. Each heat sink 21, 22 is provided with one group of vias. The spacing between the semiconductor elements 11, 12 and each group of vias is different. The spacing between the group of vias and the first semiconductor element 11 is narrower than the spacing between the group of vias and the second semiconductor element 12.

[0294] The element surface S12 of the first semiconductor element 11 is provided with a source electrode as the main electrode 11me and a plurality of signal electrodes 11se. The element surface S12 of the second semiconductor element 12 is provided with a source electrode as the main electrode 12me and a plurality of signal electrodes 12se. The signal electrodes 11se and 12se are gate electrodes, source electrodes, Kelvin source electrodes, etc.

[0295] Multiple vias 34 are provided on the main electrodes 11me and 12me. At least one via 34 is provided on each signal electrode 11se and 12se.

[0296] As shown in Figure 87, the first layer LA1 is provided with P pads 331, O pads 333, and N pads 335. The first layer LA1 is also provided with N wiring section 33n and O wiring section 33o. The first layer LA1 is the surface wiring layer, as shown in Figure 90 and other figures.

[0297] The N-wiring section 33n is provided extending from the second semiconductor element 12 to the first heat sink 21. The N-wiring section 33n is connected to the main electrode 12me via a plurality of vias 34. By extending onto the first heat sink 21, the N-wiring section 33n functions as a heat diffusion wiring section.

[0298] The O-wiring section 33o is provided extending from the first semiconductor element 11 to the via group of the second heat sink 22. The O-wiring section 33o is connected to the main electrode 11me via a plurality of vias 34. The O-wiring section 33o is also connected to the second heat sink 22 via the via group of the second heat sink 22. The O-pad 333 is part of the O-wiring section 33o.

[0299] As shown in Figure 88, the second layer LA2 is provided with N wiring section 33n, O wiring section 33o, and P wiring section 33p. The second layer LA2 is also provided with multiple signal wiring sections 33s. The signal wiring sections 33s include a first gate wiring section, a second gate wiring section, a first Kelvin source wiring section, and a second Kelvin source wiring section. As shown in Figure 90 and other figures, the second layer LA2 is the second wiring layer from the surface layer.

[0300] The N-circuit section 33n is provided on the second semiconductor element 12, extending to the region opposite the N-pad 335. The N-circuit section 33n is connected to the main electrode 12me via a plurality of vias 34. In addition, a plurality of vias for connection to the N-pad 335 are provided on the N-circuit section 33n.

[0301] The O-wiring section 33o is provided in two locations. The first O-wiring section 33o extends from the first semiconductor element 11 to the second heat sink 22. The O-wiring section 33o is connected to the main electrode 11me via a plurality of vias 34. By extending the O-wiring section 33o onto the second heat sink 22, it functions as a heat diffusion wiring section.

[0302] The second O-wiring section 33o is provided in the region opposite the O-pad 333. Multiple vias 34 for connecting to the O-pad 333 are provided on the O-wiring section 33o.

[0303] The P wiring section 33p is provided across the area facing the via group of the first heatsink 21 and the P pad 331. The P wiring section 33p is connected to the via group of the first heatsink 21. Multiple vias 34 are provided on the P wiring section 33p for connection to the P pad 331.

[0304] The signal wiring section 33s extends from above the signal electrodes 11se and 12se. One end of the signal wiring section 33s is connected to the signal electrodes 11se and 12se via a via 34. Another via 34 is provided on the other end of the signal wiring section 33s.

[0305] When heatsinks 21 and 22 are stacked with the first layer LA1 and the second layer LA2, the wiring sections 33p, 33o, and 33n overlap, as shown in Figure 89. Then, as shown in Figures 90, 91, and 92, the O wiring section 33o and the N wiring section 33n are arranged in parallel. This allows the semiconductor device 123 to reduce its inductance. As a result, the semiconductor device 123 can be made smaller and its switching speed can be improved.

[0306] Next, we will explain another wiring example using Figures 93 to 95 (Second Wiring Example). Here, we will mainly explain the differences from the First Wiring Example. In the Second Wiring Example, the first layer LA1 is provided on the heatsinks 21 and 22. The Second Wiring Example does not have a second layer LA2.

[0307] As shown in Figure 93, the second heat sink 22 is provided with two via groups. In other words, the second heat sink 22 is also provided with a via group between the second semiconductor element 12 and the first semiconductor element 11.

[0308] As shown in Figure 94, the first layer LA1 is provided with an N wiring section 33n and an O wiring section 33o. The N wiring section 33n is provided from the second semiconductor element 12 to the region opposite the first heat sink 21. The N wiring section 33n is connected to the main electrode 12me via a plurality of vias 34. The N wiring section 33n includes an N pad 335 in the portion that spans the first heat sink 21 and the second heat sink 22.

[0309] The O-wiring section 33o is provided extending from the first semiconductor element 11 to the second heat sink 22. The O-wiring section 33o is connected to the main electrode 11me via a plurality of vias 34. By extending onto the second heat sink 22, the O-wiring section 33o functions as a heat diffusion wiring section. Figure 94 shows the wiring in a state where the heat sinks 21, 22 and the first layer LA1 are stacked on top of each other.

[0310] As shown in Figure 95, in the second wiring example, the pattern wiring 33 can be made into only one layer. Therefore, variations in the semiconductor device 123 can be reduced. Furthermore, the semiconductor device 123 can reduce the number of components in the build-up layer 32.

[0311] Furthermore, Figures 96 to 101 will be used to explain other wiring examples (third wiring example). Here, we will mainly explain the differences from the first wiring example.

[0312] As shown in Figure 96, the heat sink surface S22 is provided with a group of vias including multiple vias 34. The first heat sink 21 is provided with two groups of vias. The second heat sink 22 is provided with one group of vias.

[0313] As shown in Figure 97, the first layer LA1 is provided with a P pad 331, an O pad 333, and an N pad 335. The first layer LA1 is also provided with a P wiring section 33p, an O wiring section 33o, and an N wiring section 33n.

[0314] The N-circuit section 33n is provided on the second semiconductor element 12. The N-circuit section 33n is connected to the main electrode 12me via a plurality of vias 34.

[0315] The P-wiring section 33p is provided extending from the first heatsink 21 to the second heatsink 22. The P-wiring section 33p is connected to the first heatsink 21 via a plurality of vias 34. The P-wiring section 33p is also connected to the second heatsink 22 via a plurality of vias 34. Furthermore, the P-pad 331 is provided between the N-pad 335 and the N-wiring section 33n. In other words, in the third wiring example, the P-pad 331, O-pad 333, and N-pad 335 are not arranged in a line.

[0316] The O-wiring section 33o extends from the first semiconductor element 11 to just before the O-pad 333. The O-wiring section 33o includes a portion on the first semiconductor element 11 and a portion that becomes the O-pad 333. The O-wiring section 33o is connected to the main electrode 11me via a plurality of vias 34.

[0317] As shown in Figure 98, the second layer LA2 is provided with an N wiring section 33n, an O wiring section 33o, and a P wiring section 33p. The N wiring section 33n is provided from the second semiconductor element 12 to the region opposite the N pad 335. The N wiring section 33n is connected to the main electrode 12me via a plurality of vias 34. In addition, a plurality of vias for connection to the N pad 335 are provided on the N wiring section 33n.

[0318] The O-wiring section 33o is provided extending from the first semiconductor element 11 to the second heat sink 22 and the region opposite the O-pad 333. The O-wiring section 33o is connected to the main electrode 11me via a plurality of vias 34. The O-wiring section 33o is also connected to the second heat sink 22 via a plurality of vias 34. In addition, a plurality of vias are provided on the O-wiring section 33o for connection to the O-pad 333.

[0319] The P wiring section 33p is provided in the region opposite the first heat sink 21, facing the P wiring section 33p in the first layer LA1. The P wiring section 33p is provided in two locations; that is, the P wiring section 33p is provided on both sides of the O wiring section 33o. The P wiring section 33p is provided with multiple vias for connecting to the P wiring section 33p in the first layer LA1.

[0320] When heat sinks 21 and 22 are stacked with the first layer LA1 and the second layer LA2, the wiring sections 33p, 33o, and 33n overlap as shown in Figure 99. Furthermore, as shown in Figure 100, the P wiring section 33p and the N wiring section 33n are arranged in parallel. Also, as shown in Figure 101, the O wiring section 33o and the P wiring section 33p are arranged in parallel. This allows the semiconductor device 123 to reduce its inductance. As a result, the semiconductor device 123 can be made smaller and its switching speed can be improved. Note that the first to third wiring examples can also be applied to configurations other than the semiconductor device 123.

[0321] As shown in the modified example in Figure 102, the semiconductor device 117 may have a first heat sink 21 and a mounting portion 21ad formed on the heat dissipation insulating layer 40, with a patterned metal film. As described above, the semiconductor device 117 can employ patternable heat sinks 21 and 22 and a back metal layer 50. In other words, the first heat sink 21 and the mounting portion 21ad are metal films formed on the same surface of the heat dissipation insulating layer 40. The metal film is mainly composed of metals such as aluminum and copper. The metal film can also be said to be divided into a portion that functions as the first heat sink 21 and a portion that functions as the mounting portion 21ad.

[0322] This allows circuit components constituting the semiconductor device 117 to be mounted on the first heat sink 21 and the mounting section 21ad. In other words, the first integrated substrate can mount other circuit components in addition to the first semiconductor element 11. These circuit components include, for example, resistors and capacitors. The second integrated substrate can be configured similarly.

[0323] As shown in the modified examples in Figures 103 and 104, the semiconductor device 101 may include a core layer 31 on which a core plating film 31m is provided. The core plating film 31m is mainly composed of metal. Preferably, the core plating film 31m is made of the same material as the heat sinks 21 and 22. The heat sinks 21 and 22 and the core plating film 31m are, for example, mainly composed of copper. The core plating film 31m has a thickness of, for example, about 10 μm to 50 μm. The core plating film 31m corresponds to a wall film.

[0324] As shown in Figure 103, the core plating film 31m only needs to be provided on the core side surface of the core layer 31. The core side surface is the surface along the lamination direction of the core layer 31. The core side surface is also the surface that is continuous with the core surface S32 and the core opposite surface S31. The core side surface corresponds to the side surface facing the heat sinks 21 and 22.

[0325] As shown in Figure 104, the core plating film 31m may be provided on the core surface S32 and the core opposite surface S31. However, the first heat sink 21 and the second heat sink 22 have different potentials. Also, the core layer 31 is provided between the first heat sink 21 and the second heat sink 22.

[0326] Therefore, it is preferable that the core layer 31 between the heat sinks 21 and 22 is provided with a core plating film 31m divided into the first heat sink 21 side and the second heat sink 22 side. This makes it easier to ensure electrical insulation between the heat sinks 21 and 22 in the semiconductor device 101.

[0327] As described above, the difference in the coefficient of linear expansion between the resin part and the heat sinks 21 and 22 in the lamination direction is large. Similarly, the difference in the coefficient of linear expansion between the core layer 31 and the heat sinks 21 and 22 in the lamination direction is large. Therefore, stress due to the difference in coefficient of linear expansion is easily applied to the parts where the resin part and the heat sinks 21 and 22 are in contact. In particular, this stress may cause cracks or delamination at the corners 21h1 of the resin part and the heat sinks 21 and 22.

[0328] Therefore, the semiconductor device 101 is equipped with a core plating film 31m. The semiconductor device 101 can suppress thermal expansion in the stacking direction of the core layer 31 and the resin part. As a result, the semiconductor device 101 can reduce the stress applied to the parts where the resin part and the heat sinks 21 and 22 are in contact with each other. In addition, the semiconductor device 101 can suppress the occurrence of cracks and delamination in parts where the resin part and the heat sinks 21 and 22 are in contact with each other, such as corners 21h1. The core plating film 31m can also be applied to configurations other than the semiconductor device 101.

[0329] As shown in the modified examples in Figures 105 and 106, the semiconductor device 101 may include a core layer 31 having a through-plating film 31m1 and plating through-holes 31h. However, the core plating film 31m is not required.

[0330] The core layer 31 is provided with a plating through-hole 31h that penetrates from the core surface S32 to the opposite core surface S31. A through-plating film 31m1 is placed in the plating through-hole 31h. Here, as an example, a plating through-hole 31h surrounded by a through-plating film 31m1 is used. The plating through-hole 31h is provided in the lamination direction.

[0331] The through-hole 31h is filled with the resin portion of the build-up layer 32. In other words, the through-hole 31h is filled with resin. However, the through-hole 31h may also be filled with a resin-filling material different from the resin portion. The resin-filling material is a resin component containing a metal filler. Furthermore, the plated through-hole 31h may also be filled with the through-plating film 31m1.

[0332] The through-plating film 31m1 is made of the same material as the core plating film 31m. The through-plating film 31m1 has a thickness similar to that of the core plating film 31m. The plating through-holes 31h are provided in a circular shape. The through-plating film 31m1 corresponds to the through-wall film. The plating through-holes 31h correspond to the metal through-holes.

[0333] As shown in Figure 105, the plating through-holes 31h are provided at the four corners of the core layer 31 and in the area between the first heat sink 21 and the second heat sink 22. However, the plating through-holes 31h may be provided only at the four corners of the core layer 31. Alternatively, the plating through-holes 31h may be provided only in the area facing the side surface S23 of the heat sinks 21 and 22.

[0334] Furthermore, the plating through-holes 31h are not limited to being circular. The plating through-holes 31h may include bent portions in a plan view. For example, the plating through-holes 31h may be located at the four corners of the core layer 31 and in portions facing the two adjacent side surfaces S23 of the heat sinks 21 and 22.

[0335] The core layer 31 has plating through-holes 31h in which the through-plating film 31m1 is arranged, thus suppressing thermal expansion in the lamination direction. Furthermore, as described above, the resin portion of the core layer 31 and the build-up layer 32 has a large difference in the coefficient of linear expansion in the lamination direction compared to the heat sinks 21 and 22. The stress associated with this difference in the coefficient of linear expansion tends to be large around the four corners of the core layer 31 and between the heat sinks 21 and 22.

[0336] Therefore, it is preferable to provide the plating through-holes 31h at the four corners of the core layer 31. In other words, the stress applied to the boundary between the resin part and the heat sinks 21 and 22 can be reduced around the four corners of the core layer 31. As a result, it is possible to suppress the occurrence of cracks and delamination at the boundary between the resin part and the heat sinks 21 and 22 around the four corners of the core layer 31.

[0337] As shown in the modified example in Figure 107, the first heat sink 21 may have a curved corner between its two sides S23. It can also be said that the first heat sink 21 has a rounded corner between its two sides S23. The same applies to the second heat sink 22. In other words, the heat sinks 21 and 22 may have curved corners. Furthermore, the heat sinks 21 and 22 may have chamfered corners. That is, the heat sinks 21 and 22 may have flat corners between their two sides S23. For example, the semiconductor device 101 can employ a configuration that includes heat sinks 21 and 22 with curved corners.

[0338] This prevents the stress caused by the difference in coefficient of thermal expansion described above from being applied to the four corners of the heat sinks 21 and 22. Therefore, it is possible to prevent cracks and delamination from occurring at the boundary with the resin part at the four corners of the heat sinks 21 and 22.

[0339] This disclosure is described in accordance with embodiments, but it is understood that this disclosure is not limited to such embodiments or structures. This disclosure also includes various modifications and variations within the scope of equivalents. In addition, while various combinations and forms are shown in this disclosure, other combinations and forms that include one, more, or fewer of those elements also fall within the scope and idea of ​​this disclosure.

[0340] This specification discloses several technical concepts and several combinations thereof, as listed below.

[0341] (Technical thought 1) A semiconductor device comprising semiconductor elements (11,12), A heat sink (21, 21a~21k, 22, 22e, 22g, 22h) on which the semiconductor element is mounted on the surface (S22) side, A core layer (31, 31c, 31d~31f) having one surface (S32) and the opposite surface (S31) of the one surface, with through holes (311, 311c, 311d, 31e1, 32f1) extending from the one surface to the opposite surface, and the heat sink being positioned in the through holes, A build-up layer (32) is provided opposite to the aforementioned surface and the aforementioned surface, and has wiring (33, 34) including a portion electrically connected to the semiconductor element, A semiconductor device comprising a heat dissipation insulating layer (40-42) in contact with the opposite surface and the back surface (S21) of the heat sink.

[0342] (Technical thought 2) The semiconductor element is a vertical semiconductor element, and has electrodes on both sides: an element-facing surface (S11) that faces the heat sink and an element surface (S12) that is the opposite side of the element-facing surface. The semiconductor device according to technical concept 1, wherein the electrode on the element-facing surface is electrically connected to the wiring via the heat sink.

[0343] (Technical Thought 3) The semiconductor element is a lateral semiconductor element and has an element-facing surface (S11) that faces the heat sink and an element surface (S12) that is the opposite surface of the element-facing surface. The surface of the element has a plurality of electrodes, The semiconductor device according to technical concept 1, wherein the element-facing surface is electrically connected to one of the plurality of electrodes.

[0344] (Technical Thought 4) The semiconductor device according to technical concept 3, wherein the semiconductor device has a dummy electrode (11de) on the surface of the device.

[0345] (Technical Thought 5) The element surface is provided with an element protective film (11e) around the electrodes to protect the semiconductor element, The semiconductor device according to technical concept 3, wherein the electrodes on the surface of the element are taller than the protective film of the element.

[0346] (Technical Thought 6) A portion of the aforementioned wiring is exposed to the outside of the build-up layer. The semiconductor device according to technical concept 5, wherein the element protective film covers a portion of the externally exposed part of the wiring.

[0347] (Technical Thought 7) A semiconductor device according to any one of the technical ideas 1 to 6, wherein the relative permittivity of the build-up layer is smaller than the relative permittivity of the heat-dissipating insulating layer.

[0348] (Technical Thought 8) The two semiconductor elements, The system comprises two heat sinks on which two of the semiconductor elements are individually mounted, The core layer is provided with two through holes in which the two heat sinks are individually arranged. The aforementioned wiring electrically connects the two semiconductor elements in the semiconductor device according to any one of the technical concepts 1 to 7.

[0349] (Technical Thought 9) The aforementioned wiring has layer wiring provided on the layer surface (S33) of the build-up layer, The semiconductor device according to any one of technical ideas 1 to 8, wherein the layer wiring comprises a main wiring (33) electrically connected to the semiconductor element and a dummy wiring (36) provided around the main wiring and electrically connected to ground.

[0350] (Technical Thought 10) The heat sink is provided with recesses (213, 213a~213c) that are recessed relative to the surface, The semiconductor element is mounted in the recess via a connecting member (60). The semiconductor device according to any one of the technical concepts 1 to 9, wherein the depth of the recess is shallower than the combined thickness of the semiconductor element and the connecting member.

[0351] (Technical Thought 11) The heat sink is a semiconductor device according to technical concept 10, wherein the opening area of ​​the recess is progressively wider.

[0352] (Technical Thought 12) The heat sink has a plurality of side surfaces (S23) connected to the back surface, and groove-shaped recesses (213i, 213j) are provided across two of the side surfaces. The semiconductor element is a semiconductor device according to any one of the technical concepts 1 to 9, mounted in the groove-shaped recess.

[0353] (Technical Thought 13) The semiconductor element is mounted on the heat sink via a connecting member (61). The heat sink has a silver plating layer (62) formed on its surface. The aforementioned connecting member is a silver sintered material, as described in any one of the technical concepts 1 to 12 of the semiconductor device.

[0354] (Technical Thought 14) The aforementioned silver plating layer is porous, as described in technical concept 13 for the semiconductor device.

[0355] (Technical Thought 15) The heat sink has a plate shape, A semiconductor device according to technical concept 2 or 3, comprising terminal members (21e1, 22e1) mounted on the surface and electrically connecting the heat sink and the wiring.

[0356] (Technical Thought 16) The semiconductor device according to technical concept 2 or 3, wherein the heat sink comprises a mounting portion (21f1) on which the semiconductor element is mounted, and grooves (21f2 to 21f4) provided around the mounting portion.

[0357] (Technical Thought 17) The heat dissipation insulating layer has an uneven surface, A semiconductor device according to any one of the technical concepts 1 to 16, wherein a heat dissipation spring member is attached to the aforementioned protrusions.

[0358] (Technical Thought 18) One heat sink has multiple semiconductor elements with the same configuration mounted on it. A semiconductor device according to any one of technical ideas 1 to 17, wherein a plurality of the semiconductor elements are connected in parallel via the wiring.

[0359] (Technical Thought 19) One of the heat sinks has a semiconductor element, and the semiconductor element has different circuit elements mounted on it. The semiconductor device according to any one of the technical concepts 1 to 17, wherein the semiconductor element and the circuit element are connected in parallel via the wiring.

[0360] (Technical Thought 20) The semiconductor device according to any one of the technical ideas 1 to 19, wherein the heat dissipation insulating layer contains a filler and an electrically insulating resin, without containing glass fibers.

[0361] (Technical Thought 21) The heat sink is a semiconductor device according to any one of the technical concepts 1 to 20, wherein the corner (21h1) between the back surface and the side surface (S23) connected to the back surface has a chamfered shape.

[0362] (Technical Thought 22) The semiconductor device according to any one of the technical concepts 1 to 21, wherein the build-up layer is provided between the wiring and the heat sink, and a floating conductor layer (321) is provided between them.

[0363] (Technical Thought 23) The semiconductor device according to any one of the technical ideas 1 to 22, wherein the heat dissipation insulating layer includes a heat dissipation insulating adhesive layer (41) in contact with the back surface.

[0364] (Technical Thought 24) The heat dissipation insulating layer is provided with a positioning recess (40a) in which the heat sink is positioned, as described in technical concept 23 for the semiconductor device.

[0365] (Technical Thought 25) The semiconductor device according to technical concept 3, wherein at least the surface of the semiconductor device is provided with a polyamide layer (32p) around a plurality of electrodes.

[0366] (Technical Thought 26) The semiconductor device according to any one of technical ideas 1 to 25, wherein the build-up layer comprises a first resin layer (323) that does not contain glass cloth and a second resin layer (322) that contains glass cloth, on the heat sink.

[0367] (Technical Thought 27) The aforementioned build-up layer is a semiconductor device according to any one of the technical concepts 1 to 26, in which a fiber filler (324) is embedded.

[0368] (Technical Thought 28) The semiconductor device according to any one of the technical ideas 1 to 27, wherein the core layer is covered with the resin in the build-up layer.

[0369] (Technical Thought 29) The core layer is provided with through holes whose opening area gradually increases from the heat dissipation insulating layer side. The semiconductor device according to any one of the technical concepts 1 to 28, wherein the heat sink is in contact with the part of the core layer with the smallest opening area.

[0370] (Technical Thought 30) A semiconductor device according to any one of the technical ideas 1 to 29, further comprising a surface heat dissipation insulating layer (40t) in contact with the build-up layer.

[0371] (Technical Thought 31) A semiconductor device according to technical concept 30, comprising a surface metal layer (50t) in contact with the side of the surface heat dissipation insulating layer opposite to the build-up layer.

[0372] (Technical Thought 32) The semiconductor device according to technical concept 30, wherein the wiring comprises a plurality of external connection parts (331-337) exposed from the surface heat dissipation insulating layer.

[0373] (Technical Thought 33) The aforementioned wiring includes a signal connection section and a power connection section. The semiconductor device according to technical concept 31, wherein the surface metal layer is provided between the signal connection portion and the power connection portion.

[0374] (Technical Thought 34) The semiconductor device according to any one of the technical concepts 30 to 33, wherein the wiring has a heat diffusion wiring portion (34hd) that is wider than the heat sink.

[0375] (Technical Thought 35) A semiconductor device comprising multiple semiconductor elements (11,12), A heat sink (21, 22) is provided for each of the aforementioned semiconductor elements, with the semiconductor element mounted on the surface (S22) side, A heat dissipation insulating layer (40-42) is provided for each of the heat sinks and is in contact with the back surface (S21) of the heat sink, The back metal layer (50) of the heat dissipation insulating layer is in contact with the side opposite to the heat sink, A core layer (31, 31g) having one surface (S32) and the opposite surface (S31) of the one surface, with a plurality of through holes (311) provided extending from the one surface to the opposite surface, and each through hole containing a pair of semiconductor elements, the heat sink, the heat dissipation insulating layer, and the back metal layer, A semiconductor device comprising: a build-up layer (32) provided opposite the surface and the one surface, having wiring (33, 34) including portions electrically connected to the semiconductor element.

[0376] (Technical Thought 36) The heat dissipation insulating layer is provided protruding from the heat sink side surface of the heat sink and the back metal layer side surface of the back metal layer, according to technical concept 35, the semiconductor device.

[0377] (Technical Thought 37) The semiconductor device according to technical concept 36, wherein at least one of the heat sink side surface and the back metal layer side surface is provided with an insulating member (38).

[0378] (Technical Thought 38) The direction in which the semiconductor elements are stacked relative to the heat sink is defined as the stacking direction. The semiconductor device according to technical idea 36 or 37, wherein the core layer has core protrusions (31g2) that protrude in a direction intersecting the stacking direction and are arranged in the stacking direction relative to the heat dissipation insulating layer.

[0379] (Technical Thought 39) The heat sink is composed mainly of copper, as described in any one of the technical concepts 35 to 38.

[0380] (Technical Thought 40) The wiring comprises a high-potential side wiring portion connected to the high-potential side electrode of the semiconductor element, a low-potential side wiring portion connected to the low-potential side electrode of the semiconductor element, and a heat dissipation wiring (338) disposed at least between the high-potential side wiring portion and the low-potential side wiring portion. The heat dissipation wiring is connected to the heat sink. This semiconductor device is described in any one of the technical concepts 1 to 29 or 35 to 39.

[0381] (Technical Thought 41) The semiconductor device according to any one of the technical ideas 1 to 40, wherein the heat sink and the heat dissipation insulating layer are provided with positioning holes (21ph) that penetrate in the thickness direction.

[0382] (Technical Thought 42) The semiconductor device according to any one of the technical ideas 1 to 41, wherein the core layer is made of a resin having an isotropic coefficient of thermal expansion.

[0383] (Technical Thought 43) The semiconductor device according to any one of the technical concepts 1 to 42, wherein the heat sink is provided with a heat sink protrusion (21k1) on the surface facing the core layer.

[0384] (Technical Thought 44) The semiconductor device according to any one of the technical concepts 1 to 43, wherein the heat sink is provided with a heat sink recess (21k2) on the surface facing the core layer.

[0385] (Technical Thought 45) It is mounted on the cooler (200) located on the heat dissipation insulating layer side, A semiconductor device according to any one of the technical concepts 1 to 44, comprising a heat dissipation connecting member (80e) which is a sheet-like member mainly composed of graphite and has an adhesive (80e1) exposed on the surface of the sheet-like member, between itself and the cooler.

[0386] (Technical Thought 46) The semiconductor device according to technical concept 28, comprising a wall film (31m) mainly composed of metal, provided on at least the side surface of the core layer facing the heat sink.

[0387] (Technical Thought 47) The semiconductor device according to technical concept 46, wherein the core layer has a metal through-hole (31h) that penetrates from one surface to the opposite surface and has a through-wall film (31m1) mainly composed of metal.

Claims

1. A semiconductor device comprising semiconductor elements (11, 12), A heat sink (21, 21a to 21k, 22, 22e, 22g, 22h) on which the semiconductor element is mounted on the surface (S22) side, A core layer (31, 31c, 31d-31f) having one surface (S32) and the opposite surface (S31) of the one surface, with through holes (311, 311c, 311d, 31e1, 32f1) extending from the one surface to the opposite surface, and the heat sink being positioned in the through holes, A build-up layer (32) is provided facing the aforementioned surface and the aforementioned surface, and has wiring (33, 34) including portions electrically connected to the semiconductor element, A semiconductor device comprising a heat dissipation insulating layer (40-42) that contacts the opposite surface and the back surface (S21) of the heat sink without vias.

2. The semiconductor element is a vertical semiconductor element, and has electrodes on both sides of the element facing surface (S11) that faces the heat sink and the element surface (S12) that is the opposite side of the element facing surface. The semiconductor device according to claim 1, wherein the electrode on the element-facing surface is electrically connected to the wiring via the heat sink.

3. The semiconductor element is a lateral semiconductor element and has an element-facing surface (S11) that faces the heat sink and an element surface (S12) that is the opposite surface of the element-facing surface. The surface of the element has a plurality of electrodes, The semiconductor device according to claim 1, wherein the element-facing surface is electrically connected to one of the plurality of electrodes.

4. The semiconductor device according to claim 3, wherein the semiconductor element has a dummy electrode (11de) on the surface of the element.

5. A protective element film (11e) is provided around the electrodes on the surface of the element to protect the semiconductor element. The semiconductor device according to claim 3, wherein the electrodes on the surface of the element are taller than the protective film of the element.

6. A portion of the aforementioned wiring is exposed to the outside of the build-up layer. The semiconductor device according to claim 5, wherein the element protective film covers a portion of the wiring that is exposed to the outside.

7. The semiconductor device according to any one of claims 1 to 6, wherein the relative permittivity of the build-up layer is smaller than the relative permittivity of the heat-dissipating insulating layer.

8. The two semiconductor elements, The system comprises two heat sinks on which two of the semiconductor elements are individually mounted, The core layer is provided with two through holes in which the two heat sinks are individually arranged. The semiconductor device according to any one of claims 1 to 6, wherein the wiring electrically connects the two semiconductor elements.

9. The aforementioned wiring has layer wiring provided on the layer surface (S33) of the build-up layer, The semiconductor device according to any one of claims 1 to 6, wherein the layer wiring comprises a main wiring (33) electrically connected to the semiconductor element and a dummy wiring (36) provided around the main wiring and electrically connected to ground.

10. The heat sink is provided with recesses (213, 213a to 213c) that are recessed relative to the surface, The semiconductor element is mounted in the recess via a connecting member (60). The semiconductor device according to any one of claims 1 to 6, wherein the depth of the recess is shallower than the combined thickness of the semiconductor element and the connecting member.

11. The semiconductor device according to claim 10, wherein the heat sink has an opening area of ​​the recess that increases in stages.

12. The heat sink has a plurality of side surfaces (S23) connected to the back surface, and groove-shaped recesses (213i, 213j) are provided across two of the side surfaces. The semiconductor device according to any one of claims 1 to 6, wherein the semiconductor element is mounted in the groove-shaped recess.

13. The semiconductor element is mounted on the heat sink via a connecting member (61). The heat sink has a silver plating layer (62) formed on its surface. The semiconductor device according to any one of claims 1 to 6, wherein the connecting member is made of silver sintered material.

14. The semiconductor device according to claim 13, wherein the silver plating layer is porous.

15. The heat sink has a plate shape, The semiconductor device according to claim 2 or 3, further comprising terminal members (21e1, 22e1) mounted on the surface and electrically connecting the heat sink and the wiring.

16. The semiconductor device according to claim 2 or 3, wherein the heat sink comprises a mounting portion (21f1) on which the semiconductor element is mounted, and grooves (21f2 to 21f4) provided around the mounting portion.

17. The heat dissipation insulating layer has an uneven surface, The semiconductor device according to any one of claims 1 to 6, wherein a heat dissipation spring member is attached to the aforementioned irregularities.

18. One heat sink has multiple semiconductor elements with the same configuration mounted on it. The semiconductor device according to any one of claims 1 to 6, wherein a plurality of the semiconductor elements are connected in parallel via the wiring.

19. One of the heat sinks has a semiconductor element, and the semiconductor element has different circuit elements mounted on it. The semiconductor device according to any one of claims 1 to 6, wherein the semiconductor element and the circuit element are connected in parallel via the wiring.

20. The semiconductor device according to any one of claims 1 to 6, wherein the heat dissipation insulating layer comprises a filler and an electrically insulating resin, without containing glass fibers.

21. The semiconductor device according to any one of claims 1 to 6, wherein the heat sink has a chamfered shape at the corner (21h1) between the back surface and the side surface (S23) connected to the back surface.

22. The semiconductor device according to any one of claims 1 to 6, wherein the build-up layer is provided between the wiring and the heat sink, and a floating conductor layer (321) is provided between them.

23. The semiconductor device according to any one of claims 1 to 6, wherein the heat dissipation insulating layer includes a heat dissipation insulating adhesive layer (41) in contact with the back surface.

24. The semiconductor device according to claim 23, wherein the heat dissipation insulating layer is provided with a positioning recess (40a) in which the heat sink is positioned.

25. The semiconductor device according to claim 3, wherein at least the surface of the semiconductor element is provided with a polyamide layer (32p) around a plurality of electrodes.

26. The semiconductor device according to any one of claims 1 to 6, wherein the build-up layer comprises a first resin layer (323) that does not contain glass cloth and a second resin layer (322) that contains glass cloth, on the heat sink.

27. The semiconductor device according to any one of claims 1 to 6, wherein the build-up layer has a fiber filler (324) embedded in it.

28. The semiconductor device according to any one of claims 1 to 6, wherein the core layer is covered with the resin in the build-up layer.

29. The core layer is provided with through holes whose opening area gradually increases from the heat dissipation insulating layer side. The semiconductor device according to any one of claims 1 to 6, wherein the heat sink is in contact with the portion of the core layer with the smallest opening area.

30. The semiconductor device according to any one of claims 1 to 6, further comprising a surface heat dissipation insulating layer (40t) in contact with the build-up layer.

31. The semiconductor device according to claim 30, further comprising a surface metal layer (50t) in the surface heat dissipation insulating layer that is in contact with the side opposite to the build-up layer.

32. The semiconductor device according to claim 30, wherein the wiring comprises a plurality of external connection portions (331 to 337) exposed from the surface heat dissipation insulating layer.

33. The aforementioned wiring includes a signal connection section and a power connection section. The semiconductor device according to claim 31, wherein the surface metal layer is provided between the signal connection portion and the power connection portion.

34. The semiconductor device according to claim 30, wherein the wiring has a heat diffusion wiring portion (34hd) that is wider than the heat sink.

35. A semiconductor device comprising a plurality of semiconductor elements (11, 12), A heat sink (21, 22) is provided for each of the semiconductor elements, with the semiconductor element mounted on the surface (S22) side, A heat dissipation insulating layer (40-42) is provided for each of the heat sinks and is in contact with the back surface (S21) of the heat sink without vias, The back metal layer (50) of the heat dissipation insulating layer is in contact with the side opposite to the heat sink, A core layer (31, 31g) having one surface (S32) and the opposite surface (S31) of the one surface, with a plurality of through holes (311) provided extending from the one surface to the opposite surface, and a pair of semiconductor elements, the heat sink, the heat dissipation insulating layer, and the back metal layer arranged in each through hole, A semiconductor device comprising: a build-up layer (32) provided opposite the surface and the one surface, having wiring (33, 34) including portions electrically connected to the semiconductor element.

36. The semiconductor device according to claim 35, wherein the heat dissipation insulating layer is provided so as to protrude from the heat sink side surface of the heat sink and the back metal layer side surface of the back metal layer.

37. The semiconductor device according to claim 36, wherein at least one of the heat sink side surface and the back metal layer side surface is provided with an insulating member (38).

38. The direction in which the semiconductor elements are stacked relative to the heat sink is defined as the stacking direction. The semiconductor device according to claim 36 or 37, wherein the core layer has core protrusions (31g2) that protrude in a direction intersecting the stacking direction and are arranged in the stacking direction relative to the heat dissipation insulating layer.

39. The semiconductor device according to any one of claims 35 to 37, wherein the heat sink is mainly composed of copper.

40. The wiring comprises a high-potential wiring portion connected to the high-potential side electrode of the semiconductor element, a low-potential wiring portion connected to the low-potential side electrode of the semiconductor element, and a heat dissipation wiring (338) disposed at least between the high-potential wiring portion and the low-potential wiring portion. The semiconductor device according to any one of claims 1 to 6, 35 to 37, wherein the heat dissipation wiring is connected to the heat sink.

41. The semiconductor device according to any one of claims 1 to 6, 35 to 37, wherein the heat sink and the heat dissipation insulating layer are provided with positioning holes (21ph) that penetrate in the thickness direction.

42. The semiconductor device according to any one of claims 1 to 6, 35 to 37, wherein the core layer is made of a resin having an isotropic coefficient of thermal expansion.

43. The semiconductor device according to any one of claims 1 to 6, 35 to 37, wherein the heat sink is provided with a heat sink protrusion (21k1) on the surface facing the core layer.

44. The semiconductor device according to any one of claims 1 to 6, 35 to 37, wherein the heat sink is provided with a heat sink recess (21k2) on the surface facing the core layer.

45. It is mounted on a cooler (200) located on the heat dissipation insulating layer side, A semiconductor device according to any one of claims 1 to 6, 35 to 37, comprising a heat dissipation connecting member (80e) which is a sheet-like member mainly composed of graphite and has an adhesive (80e1) exposed on the surface of the sheet-like member, between itself and the cooler.

46. The semiconductor device according to claim 28, further comprising a metal-based wall film (31m) provided on at least the side surface of the core layer facing the heat sink.

47. The semiconductor device according to claim 46, wherein the core layer has a metal through-hole (31h) that penetrates from one surface to the opposite surface and has a through-wall film (31m1) mainly composed of metal disposed therein.

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