Compensated digital-to-analog converter (DAC)

Abstract

The circuit includes a digital-to-analog converter (DAC) (200) and a compensation circuit (210). The DAC (200) has a first terminal (VA) and a second terminal (VB). The compensation circuit (210) has a third terminal (211) and a fourth terminal (212). The third terminal (211) is coupled to the first terminal (VA) and the fourth terminal (212) is coupled to the second terminal (VB). The compensation circuit (210) is configured to source a current to the first terminal (VA) in response to an increase in a voltage on the second terminal (VB) and to sink a current from the first terminal (VA) in response to a decrease in a voltage on the second terminal (VB).

Description

Technical Field

[0001] A digital-to-analog converter (DAC) converts a digital signal into an analog signal. A current steering DAC is a type of DAC that includes a current source and two or more transistors. The control terminals of the transistors (e.g., their gates) are controlled by a digital input signal or the logical inversion thereof. In response to one state of the digital input signal to the DAC, a first transistor is turned on to cause current from the current source to flow to one output terminal of the current steering DAC. In response to another state of the digital input signal, another transistor is turned on to cause current from the current source to flow to another output terminal of the current steering DAC. Current steering DACs can be used, for example, in sigma-delta modulators employed in analog-to-digital converters (ADCs).

Summary of Invention

[0002] In one example, a circuit includes a digital-to-analog converter (DAC) and a compensation circuit. The DAC has a first terminal and a second terminal. The compensation circuit has a third terminal and a fourth terminal. The third terminal is coupled to the first terminal, and the fourth terminal is coupled to the second terminal. The compensation circuit is configured to supply current to the first terminal in response to an increase in voltage on the second terminal, and sink current from the first terminal in response to a decrease in voltage on the second terminal.

Brief Description of Drawings

[0003] [Figure 1] An exemplary implementation of a current steering DAC is shown.

[0004] [Figure 2] An exemplary implementation of a compensated current steering DAC including a p-type metal oxide semiconductor field effect transistor is shown.

[0005] [Figure 3] An exemplary implementation of the current steering DAC of FIG. 2 is shown with additional details.

[0006] [Figure 4] Examples of second-order delta-sigma modulators including multiple compensated current-steering DACs are shown in Figures 2, 3, and 5.

[0007] [Figure 5] This document provides an example implementation of a compensated current-steering DAC including an n-type metal oxide semiconductor field-effect transistor. [Modes for carrying out the invention]

[0008] As described above, a current-steering DAC has a transistor that "steering" current to one or another output terminal of the DAC. Threshold voltage mismatches between transistors, and feedback effects from delta-sigma modulators in which current-steering DACs may be used, can undesirably introduce harmonics and noise. Such harmonics and noise can degrade the signal-to-noise ratio (SNR) and, for example, distort the output signal from a sigma-delta analog-to-digital converter (ADC) in which a sigma-delta modulator is used. Figure 1 is used to illustrate the harmonic and noise problem.

[0009] Figure 1 shows an example of a current-steering DAC 100. In this example, the current-steering DAC 100 includes transistors MP0, MP1, PCAS, and PBIAS. Transistor PBIAS is a p-type metal oxide semiconductor field-effect transistor (PMOS transistor). A bias voltage BIAS1 is supplied to the gate of the PBIAS transistor, thereby causing the transistor PBIAS to generate a fixed reference current IREF1. Transistor PBIAS operates as a current source. The drain of transistor PBIAS is connected to the source of transistor PCAS, which operates as a cascode transistor to increase the output resistance of the current source (transistor PBIAS). A bias voltage BIAS2 is supplied to the gate of the PCAS transistor.

[0010] The drain of transistor PCAS is coupled to the sources of PMOS transistors MP0 and MP1 at the terminal labeled VA. The current steering DAC 100 is a single-bit DAC, and its single-bit digital inputs are a digital input signal Q and its logic inverter QZ. The digital input signal Q is coupled to the gate of transistor MP0, and QZ is coupled to the gate of transistor MP1. Terminals VP and VM are the output terminals of the current steering DAC. The drain of transistor MP0 is coupled to terminal VP, and the drain of transistor MP1 is coupled to terminal VM. The IREF1 reference current flows through transistor MP0 to terminal VP, or through transistor MP1 to terminal VM, depending on the state of the digital input signal. When signal Q is low (and therefore QZ is high), the IREF1 reference current flows through transistor MP0 to terminal VP. Conversely, when signal QZ is low (and therefore Q is high), the IREF1 reference current flows through transistor MP1 to terminal VM. Terminals VP and VM are coupled to other components in the system, such as a delta-sigma modulator, in which the current-steering DAC 100 may be used. An example of a delta-sigma modulator using a current-steering DAC is provided in Figure 4 and described below.

[0011] Capacitor Cpar is shown coupled between terminal VA and ground. Capacitor Cpar represents the parasitic capacitance of transistors MP0, MP1, and PCAS, and the layout circuit capacitance between them and terminal VA. For transistors MP0 and MP1, capacitor Cpar represents the gate-source capacitance (CGS), source-body capacitance (CSB), and drain-source capacitance (CDS) of MP1 and MP0. For transistor PCAS, capacitor Cpar represents the gate-drain capacitance (CGD), drain-body capacitance (CDB), and CDS.

[0012] In the ideal case (i.e., without parasitic capacitor Cpar), the total IREF1 current flows through either the VP or VM terminal via the respective transistors MP0 or MP1. The voltage across terminal VA may increase or decrease with each digital input transition (e.g., Q changing from low to high or high to low). In some cases, transistors MP0 and MP1 operate in the saturation region. If the threshold voltage of transistor MP0 is equal to the threshold voltage of transistor MP1, the voltage across terminal VA remains a fixed voltage and does not change during digital input changes in the state of signals Q and QZ. However, due to manufacturing tolerances, there may be a difference in the threshold voltages of transistors MP0 and MP1. This threshold voltage difference causes a change in the voltage across terminal VA during digital input changes. For example, the voltage across terminal VA may increase or decrease by the amount of the threshold voltage difference between transistors MP0 and MP1, depending on whether the threshold voltage of one transistor is higher or lower than the threshold voltage of the other.

[0013] In some implementations, transistors MP0 and MP1 operate in their linear region. In such implementations, during the data transitions of Q and QZ (e.g., Q changes from "0" to "1" and QZ changes from "1" to "0"), the voltage across terminal VA increases to VP + VDS (where VDS is the drain-source voltage of the ON transistor MP0 or MP1). In some implementations, the magnitude of VDS can generally be 2–3mV. The voltage between terminals VP and VM has a signal swing with some offset voltage. The offset voltage can generally be 10–20mV in some implementations.

[0014] Due to the presence of a parasitic capacitor Cpar, which responds to a rapid increase in the voltage at terminal VA, the voltage across capacitor Cpar increases, and therefore current flows from terminal VA to capacitor Cpar, as indicated by arrow 110. Conversely, in response to a decrease in the voltage at terminal VA, the voltage across capacitor Cpar decreases, and therefore current flows from capacitor Cpar to terminal VA, as indicated by arrow 111. In the scenario where capacitor Cpar is charged (due to an increase in the voltage at terminal VA), a portion of the IREF1 current is supplied to capacitor Cpar. Therefore, when capacitor Cpar receives current from terminal VA, a current less than the total IREF1 flows through either the ON transistor MP0 or MP1. In the scenario where capacitor Cpar is discharged (due to a decrease in the voltage at terminal VA), the current supplied by capacitor Cpar is supplied to terminal VA and added to the IREF1 current from transistor PBIAS. Therefore, when capacitor Cpar supplies current to terminal VA, a current greater than the total IREF1 current flows through either the ON transistor MP0 or MP1. In either case, while the digital signals Q and QZ transition to the gates of transistors MP0 and MP1, the current through MP0 or MP1 (whichever transistor is on) temporarily deviates from the magnitude of IREF1. Once the parasitic capacitor Cpar is fully charged or discharged, the (110) current to or from capacitor Cpar drops to 0A, and the drain current through MP0 or MP1 returns to IREF1. Unfortunately, the upward and downward deviations of IREF1 caused by the above data transitions introduce harmonics into the output current from the current-steering DAC (the current through transistors MP0 and MP1), increasing the noise floor due to aliasing noise.

[0015] Figure 2 shows an example of a compensated current-steering DAC 200 that reduces or eliminates the harmonic and noise floor issues described above by using a compensation circuit 210. The compensation circuit 210 ensures that the current through MP0 or MP1 is approximately equal to IREF1 despite any excess current flow to or from capacitor Cpar. The compensation circuit 210 includes a transistor M21, a compensation capacitor Ccomp, and a bias current circuit Ibias ("Ibias" refers to both the bias current circuit and the current it generates). In this example, transistor M21 is an n-type metal oxide semiconductor field-effect transistor (NMOS transistor). The drain of transistor M21 is coupled to the supply voltage terminal, and the source of transistor M21 is coupled to the compensation capacitor Ccomp and to the bias current source circuit Ibias at terminal VC. The drain current through transistor M21 is denoted as I_M21. The current through the compensation capacitor Ccomp is denoted as I_comp. The current through the parasitic capacitor Cpar is denoted as I_cpar. The currents I_cpar and I_comp are shown as solid arrows in one direction and dashed arrows in the opposite direction. The solid arrows represent the direction of currents I_cpar and I_comp in response to an increase in voltage across terminal VA (and charging of capacitor Cpar), while the dashed arrows represent the direction of currents I_cpar and I_comp in response to a decrease in voltage across terminal VA (and discharging of capacitor Cpar).

[0016] The gate of transistor M21 provides the first terminal 211 of the compensation circuit 210. The compensation capacitor Ccomp provides the second terminal 212 of the compensation circuit 210 (opposite the capacitor terminal coupled to the source of transistor M21). Compensation circuit terminal 211 is coupled to terminal VA. The compensation capacitor Ccomp of the compensation circuit (and therefore terminal 212) is coupled to the connection point between transistors PBIAS and PCAS (the terminal labeled VB in Figure 2).

[0017] As the voltage across terminal VA increases, a current I_cpar flows from terminal VA to the parasitic capacitor Cpar, thereby charging the parasitic capacitor. The direction of the current flow of I_cpar to the parasitic capacitor Cpar is represented by the solid arrow. The increase in voltage across terminal VA also increases the gate-source voltage (Vgs) of transistor M21. The increase in Vgs of transistor M21 causes an increase in the drain current (I_M21) through transistor M21. Since Ibias is a fixed current, as the current I_M21 increases, the portion of current I_M21 exceeding Ibias flows as I_comp (solid arrow) through the compensating capacitor Ccomp to terminal VB. Thus, as the voltage across terminal VA increases, a current I_cpar flows from terminal VA to the parasitic capacitor Cpar, and a current of approximately equal magnitude I_comp flows from the compensating capacitor Ccomp to terminal VB. The net effect of the current I_cpar leaving terminal VA and the nearly equal current I_comp entering terminal VB is that the current through either transistor MP0 or MP1 is nearly equal to Iref1, even during the transition of digital input signals Q and QZ to the compensated current-steering DAC200.

[0018] When the voltage across terminal VA decreases, a current I_cpar flows from the parasitic capacitor Cpar to terminal VA (dashed arrow), thereby discharging the parasitic capacitor. The decrease in voltage across terminal VA also decreases the Vgs of transistor M21. The decrease in Vgs of transistor M21 causes a decrease in the current I_M21 through the transistor. When the current I_M21 decreases to less than the magnitude of the fixed current Ibas, the current I_comp (dashed arrow) flows from terminal VB through capacitor Comp to terminal VC such that the sum of I_M21 and I_comp is approximately equal to Ibias. Thus, when the voltage across terminal VA decreases, a current I_cpar flows from the parasitic capacitor Cpar to terminal VA, and a current of approximately equal magnitude I_comp flows from terminal VB to the compensating capacitor Ccomp. The net effect of the current I_cpar flowing through terminal VA and the nearly equal current I_comp flowing from terminal VB is that the current through either the ON transistor MP0 or MP1 is nearly equal to Iref1, even during the transition of the digital input signals Q and QZ to the compensated current-steering DAC200.

[0019] The compensation circuit 210 has a common drain type configuration. The voltage gain of this configuration is ideally 1, but in practice it can be slightly less than 1 (e.g., less by an amount α than 1). The current I_comp is made approximately equal to the current I_cpar, taking into account the value α (i.e., α × Ccomp = Cpar) by making the capacitance of capacitor Ccomp equal to the capacitance of capacitor Cpar. The current value Ibias is selected so that the amplifier has sufficient bandwidth. Thus, the voltage at terminal VC can track the voltage at terminal VA.

[0020] As described above, the compensation circuit 210 responds to changes in the voltage on terminal VA by supplying current to or drawing current from terminal VB. The current supplied to or from terminal VB by the compensation circuit 210 is approximately equal in magnitude to the current that charges or discharges the parasitic capacitor Cpar, thereby making the current through MP0 (or MP1) approximately equal to Iref1.

[0021] Figure 3 shows a compensated current-steering DAC 300, which is similar to the compensated current-steering DAC 200 but with additional details. These additional details include the implementation of an enable switch P_EN and a bias current source circuit Ibias. In this example, the enable switch P_EN is a PMOS transistor that couples VDD with the PBIAS transistor. The signal to the gate of the enable switch P_EN is a signal called EN. The EN signal turns P_EN on / off. When P_EN is off, the compensated current-steering DAC 300 is disabled, and when P_EN is on, the compensated current-steering DAC 300 is enabled.

[0022] The bias current source circuit Ibias includes a current source 306 coupled to a current mirror formed by NMOS transistors M2 and M3. The current source 306 generates the current Ibias that flows through transistor M2. In one example, the current ratio of the current mirror is 1:1, and therefore the current through transistor M3 is also approximately Ibias, as shown in Figure 3.

[0023] The compensated current-steering DACs described herein can be used as standalone DACs or as part of a larger system such as an ADC. Examples of ADCs that can use the compensated current-steering DACs described herein include sigma-delta ADCs, successive approximation register (SAR) ADCs, and pipelined ADCs. The current-steering DACs described herein can also be used as part of a charge pump.

[0024] FIG. 4 illustrates an example implementation of a second-order (where ADC may be of any order) sigma-delta modulator-based ADC 400. In the example of FIG. 4, the sigma-delta modulator-based ADC includes integrators 415 and 419, a comparator 420, and compensated current steering DACs 402 and 412. In one example, each of the compensated current steering DACs 402 and 412 is implemented as shown for the compensated current steering DAC 200 or 300 in FIGS. 2 and 3. Compensated current steering DAC 412 includes PBIAS1 and PCAS1 transistors, which represent the aforementioned transistors PBIAS and PCAS. Transistors MP0 and MP1 from FIG. 2 are also shown similarly. A compensation circuit 410 in current steering DAC 412 is connected to terminals VA and VB as described above. In one example, compensation circuit 410 is implemented as shown for compensation circuit 210 in FIG. 2 or FIG. 3. Similarly, compensated current steering DAC 402 includes transistors PBIAS2 and PCAS2 (connected together at terminal VB1), which represent the aforementioned transistors PBIAS and PCAS. Transistors MP0 and MP1 of FIGS. 2 and 3 are shown as transistors MP2 and MP3 of DAC 402, respectively, the sources of which are connected together at terminal VA1. A compensation circuit 411 in current steering DAC 402 is connected to terminals VA1 and VB1 as described above. In one example, compensation circuit 411 is implemented as shown for compensation circuit 210 in FIG. 2 or FIG. 3.

[0025] An analog input signal to the sigma-delta modulator-based ADC 400 is encoded as the voltage difference between input voltage VINP and VINM. The integrator 415 comprises two resistor-capacitor pairs R41 / C41 and R42 / C42. Voltage VINP is supplied to the respective resistor R41 thereof, and voltage VINM is supplied to the resistor R42 thereof. Resistor R41 is connected to the respective capacitor C41 at terminal 416 as illustrated, and resistor R42 is connected to the respective capacitor C42 at terminal 417. The voltage on terminal 416 is denoted as VAP (note that terminal 416 is also referred to as VAP terminal 416), and the voltage on terminal 417 is denoted as VAM (note that terminal 417 is also referred to as VAM terminal 417). The drain of transistor MP2 of the compensated current steering DAC 402 is coupled to terminal VAP, and the drain of transistor MP3 of the compensated current steering DAC 402 is coupled to terminal VAM. In the case of the compensated current steering DAC 402, VAP terminal 416 and VAM terminal 417 are respectively the VP terminal and VM terminal in FIG. 2.

[0026] The integrator 419 comprises a transconductance amplifier (Gm) 418, and capacitors C43 and C44. The positive input of Gm 418 is coupled to resistor R41 and capacitor C41 at VAP terminal 416. The negative input of Gm 418 is coupled to resistor R42 and capacitor C42 at VAM terminal 417. In this example, resistors R41 and R42 have the same resistance, and capacitors C41 and C42 have the same capacitance. Accordingly, the voltage on VAP terminal 416 is supplied to the positive input of Gm 418, and the voltage on VAM terminal 417 is supplied to the negative input of Gm 418. The positive output of Gm 418 is coupled to the positive input of comparator 420 at terminal 421, and the negative output of Gm 418 is coupled to the negative input of comparator 420 at terminal 422.

[0027] Capacitor C43 is coupled between terminal 422 and ground, as shown in the figure. Similarly, capacitor C44 is coupled between terminal 421 and ground. In this example, capacitors C43 and C44 have the same capacitance. Current from Gm418, as well as current from the compensated current-steering DAC402, charges capacitors C44 and C43, thereby forming a differential voltage between VP terminal 421 and VM terminal 422. Comparator 420 outputs the aforementioned digital signal Q and its logic inversion QZ. Q is asserted high by comparator 420 (and QZ is asserted low) in response to the voltage on VP terminal 421 being higher than the voltage on VM terminal 422. Q is forced low by comparator 420 (and QZ is forced high) in response to the voltage on VP terminal 421 being lower than the voltage on VM terminal 422. The Q signal is connected to the gates of transistors MP0 and MP2, and the QZ signal is connected to the gates of transistors MP1 and MP3. The clock signal (CLK) is used to cause comparator 420 to sample the inputs on terminals VP 421 and VM 422. In the compensated current-steering DAC 412, the drain of transistor MP0 is connected to terminal VP 421, and the drain of transistor MP1 is connected to terminal VM 422. In the case of the compensated current-steering DAC 412, terminals VP 421 and VM 422 are the VP terminal and VM terminal in Figure 2, respectively.

[0028] The compensated current-steering DACs 402 and 412 inject current into terminals VAP 416 and VP 421, respectively, in response to a low Q signal, turning on transistors MP2 and MP0. Conversely, the compensated current-steering DACs 402 and 412 inject current into terminals VAM 417 and VM 422, respectively, in response to a low QZ signal, turning on transistors MP3 and MP1. The compensation circuit 411, as described above, supplies current to terminal VB1 or draws current from terminal VB1 in response to a change in voltage on terminal VA1. Similarly, the compensation circuit 410 supplies current to terminal VB or draws current from terminal VB in response to a change in voltage on terminal VA.

[0029] The signal-to-noise ratio (SNR) of a current-steering DAC can be increased by including a compensation circuit (e.g., compensation circuit 210). Table 1 below shows the SNR of a sigma-delta ADC with a current-steering DAC, with and without the compensation circuit described (e.g., current-steering DAC 100 in Figure 1), and with the compensation circuit described (e.g., compensated current-steering DAC 200 (Figure 2)). SNR values ​​are provided for various offset voltages. The offset voltage represents the change in voltage on the VA terminal during data transitions. For a 0mV offset, there is little or no difference in SNR between the two types of current-steering DACs. However, the SNR of a sigma-delta ADC with a compensated current-steering DAC is higher for offset voltages of 20mV, 40mV, and 60mV than for a sigma-delta ADC with an uncompensated current-steering DAC. For example, the SNR of an uncompensated current-steering DAC is 58 dB in the absence of an offset voltage, but decreases to 43.2 dB in the presence of a 40 mV offset. However, by using a compensation circuit as described herein, the SNR becomes 55.5 dB with a 40 mV offset. JPEG0007917109000001.jpg58168

[0030] While the compensated current-steering DACs in Figures 2 and 3 include PMOS transistors, the compensation circuits described herein can be used with NMOS transistor-based current-steering DACs. Figure 5 shows a compensated current-steering DAC 500 including NMOS transistors. The compensated current-steering DAC 500 includes NMOS transistors MN0, MN1, NCAS, and NBIAS, and a compensation circuit 510. The compensation circuit 510 includes a transistor M51, a compensation capacitor Ccomp 51, and a bias current circuit Ibias 51 ("Ibias 51" refers to both the bias current circuit and the current it generates). In this example, transistor M51 is a PMOS transistor. The drain of transistor M51 is coupled to ground, and the source of transistor M51 is coupled to the compensation capacitor Ccomp 51 and to the bias current source circuit Ibias 51 at terminal VC 51. The drain current through transistor M51 is denoted as I_M51. The current through the compensation capacitor Ccomp is denoted as I_comp 51. The current through the parasitic capacitor Cpar is denoted as I_cpar51.

[0031] The gate of transistor M51 provides the first terminal 511 of the compensation circuit 510. The compensation capacitor Ccomp 51 provides the second terminal 512 of the compensation circuit 210 (opposite the capacitor terminal coupled to the source of transistor M51). Compensation circuit terminal 511 is coupled to terminal VA 51. The compensation capacitor Ccomp 51 (and therefore terminal 512) of the compensation circuit is coupled to the connection point between transistors NBIAS and NCAS (terminal labeled VB 51 in Figure 5).

[0032] As the voltage across terminal VA51 increases, current I_cpar51 (solid arrow) flows from terminal VA51 to the parasitic capacitor Cpar, thereby charging the capacitor. The increase in voltage across terminal VA51 also decreases the Vgs of transistor M51. The decrease in Vgs of transistor M51 causes a decrease in the drain current (I_M51) through transistor M51. Since Ibias51 is a fixed current, as the current I_M51 decreases, the portion of Ibias51 exceeding I_M51 flows through the compensating capacitor Ccomp as current I_comp51 to terminal VB51 (solid arrow). Therefore, as the voltage across terminal VA51 increases, current I_cpar51 flows from terminal VA51 to the parasitic capacitor Cpar, and a current of approximately the same magnitude, I_comp51, flows from the compensating capacitor Ccomp to terminal VB51.

[0033] When the voltage across terminal VA51 decreases, a current I_cpar flows from the parasitic capacitor Cpar to terminal VA (dashed arrow), thereby discharging the parasitic capacitor Cpar. The decrease in voltage across terminal VA51 also increases the Vgs of transistor M51. The increase in Vgs of transistor M51 causes an increase in the current I_M51 through transistor M51. When the current I_M51 increases beyond the magnitude of the fixed current Ibias51, the current I_comp51 (dashed arrow) flows from terminal VB51 through capacitor Ccomp51 to terminal VC51 so that the sum of I_M51 and I_comp51 is approximately equal to Ibias51. Therefore, when the voltage across terminal VA51 decreases, a current I_cpar51 flows from the parasitic capacitor Cpar to terminal VA51, and a current of approximately equal magnitude I_comp51 flows from terminal VB51 to compensating capacitor Ccomp51.

[0034] In this specification, the term “to couple” may include connections, communications, or signaling paths that enable a functional relationship consistent with this description. For example, if device A controls device B to generate a signal for performing a certain action, then (a) in the first example, device A is coupled to device B by a direct connection, or (b) in the second example, device A is coupled to device B via intermediary component C, where intermediary component C does not alter the functional relationship between device A and device B, and device B is controlled by device A via a control signal generated by device A.

[0035] Within the scope of the claims of the present invention, modifications may be made to the exemplary embodiments described, and other embodiments are possible.

Claims

1. It is a circuit, A digital-to-analog converter (DAC) including a first transistor coupled between a first voltage terminal and a first terminal, a second transistor coupled between the first terminal and a second terminal, and a differential input circuit element coupled to the second terminal, A compensation circuit having a third terminal connected to the first terminal and a fourth terminal connected to the second terminal, In response to an increase in the voltage on the second terminal, current is supplied to the first terminal. In response to a decrease in the voltage on the second terminal, current is drawn from the first terminal. The compensation circuit is configured as follows: A circuit that includes this.

2. The circuit according to claim 1, The aforementioned compensation circuit A transistor having a gate, drain, and source connected to the fourth terminal, A capacitor having a first terminal connected to the source and a second terminal connected to the third terminal, A circuit that includes this.

3. The circuit according to claim 2, A circuit wherein the compensation circuit further includes a current source circuit coupled to the source.

4. The circuit according to claim 3, A circuit in which the current source circuit is coupled between the source and either the ground terminal or the supply voltage terminal.

5. The circuit according to claim 1, A circuit in which the DAC is a current-steering DAC.

6. The circuit according to claim 1, A circuit in which the DAC is a current-steering single-bit DAC.

7. The circuit according to claim 6, The first transistor is configured to supply a bias current, The differential input circuit element includes a third transistor coupled to the second terminal and a fourth transistor coupled in parallel with the third transistor to the second terminal.

8. A current steering digital-to-analog converter, The first transistor and The second transistor, A bias current transistor having a first terminal, A third transistor coupled to the first terminal, the third transistor having a second terminal coupled to the first and second transistors, A compensation circuit having a third terminal connected to the first terminal and a fourth terminal connected to the second terminal, In response to an increase in the voltage on the second terminal, current is supplied to the first terminal. In response to a decrease in the voltage on the second terminal, current is drawn from the first terminal. The compensation circuit is configured as follows: Includes current steering digital-to-analog converters.

9. A current steering digital-to-analog converter according to claim 8, The aforementioned compensation circuit A metal oxide semiconductor field-effect transistor (MOSFET) having a gate coupled to a fourth terminal, a drain, and a source, A capacitor having a first terminal connected to the source and a second terminal connected to the third terminal, Includes current steering digital-to-analog converters.

10. A current steering digital-to-analog converter according to claim 9, A current-steering digital-to-analog converter wherein the compensation circuit further includes a current circuit coupled to the source.

11. A current steering digital-to-analog converter according to claim 10, A current-steering digital-to-analog converter, wherein the current circuit is coupled between the source and either a ground terminal or a supply voltage terminal.

12. A current steering digital-to-analog converter according to claim 8, The aforementioned compensation circuit Current source circuit and A capacitor having a first terminal connected to the current source circuit and a second terminal connected to the third terminal, Includes current steering digital-to-analog converters.

13. A current steering digital-to-analog converter according to claim 8, The third transistor is a cascode transistor in a current-steering digital-to-analog converter.

14. It is a circuit, A first digital-to-analog converter (DAC) comprising a first transistor coupled between a first voltage terminal and a first digital-to-analog converter terminal (first DAC terminal), a second transistor coupled between the first DAC terminal and a second DAC terminal, and a first differential circuit element coupled to the second DAC terminal, A first compensation circuit having a first compensation circuit terminal connected to the first DAC terminal and a second compensation circuit terminal connected to the second DAC terminal, In response to an increase in voltage on the second DAC terminal, current is supplied to the first DAC terminal. In response to a decrease in voltage on the second DAC terminal, current is drawn from the first DAC terminal. The first compensation circuit is configured as follows, A circuit that includes this.

15. The circuit according to claim 14, The first compensation circuit, A transistor having a gate, a drain, and a source, coupled to the second compensation circuit terminal, A capacitor having a first terminal connected to the source and a second terminal connected to the first compensation circuit terminal, A circuit that includes this.

16. The circuit according to claim 15, A circuit wherein the first compensation circuit further includes a current circuit coupled to the source.

17. The circuit according to claim 14, A circuit in which the first DAC is a current-steering DAC.

18. The circuit according to claim 14, A circuit in which the first DAC is a current-steering single-bit DAC.

19. The circuit according to claim 14, A second DAC comprising a third transistor coupled between a second voltage terminal and a third DAC terminal, a fourth transistor coupled between the third DAC terminal and a fourth DAC terminal, and a second differential circuit element coupled to the fourth DAC terminal, A second compensation circuit having a third compensation circuit terminal connected to the third DAC terminal and a fourth compensation circuit terminal connected to the fourth DAC terminal,

20. The circuit according to claim 19, The second compensation circuit is In response to an increase in voltage on the fourth DAC terminal, current is supplied to the third DAC terminal. In response to a decrease in voltage on the fourth DAC terminal, current is drawn from the third DAC terminal. A circuit configured in such a way.

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