Semiconductor device manufacturing method

Abstract

The present invention relates to a method for manufacturing a semiconductor device. According to one embodiment, a method for manufacturing a semiconductor device may include forming an insulating layer, forming a barrier layer on the insulating layer, performing a nitridation process on the barrier layer, and forming a metal electrode on the barrier layer. In one embodiment, performing the nitridation process may include performing a high-pressure nitridation (HPN) process. According to this embodiment, improving the quality of the barrier layer during a semiconductor device manufacturing process may improve the electrical characteristics of the barrier layer and the metal electrode, thereby improving the electrical characteristics of the semiconductor device.

Description

Technical Field

[0001] The present invention relates to a method for manufacturing a semiconductor device.

Background Art

[0002] A semiconductor device is a component mainly used in electronic circuits utilizing the electrical conduction properties of semiconductors and similar devices. Semiconductors can be classified into memory semiconductors and non-memory semiconductors. Memory semiconductors can be classified into volatile memories such as DRAM and SRAM, and non-volatile memories such as Mask ROM, EP ROM, EEP ROM and flash memory.

[0003] FIG. 1 shows the structure of a conventional semiconductor device.

[0004] Referring to FIG. 1, the semiconductor device may comprise an insulating layer 12 formed on a substrate 11 having a predetermined structure formed thereon, and a metal electrode 14 formed on the insulating layer 12.

[0005] The metal electrode 14 may be made of a metal material such as Al, Cu, W, Mo, Ru, for example. Metal ions contained in the metal electrode 14, or oxygen, moisture or the like may diffuse into the insulating layer 12, causing contamination of the insulating layer 12 or problems such as spike defects. In order to prevent such problems, in the manufacturing process of a semiconductor device, a barrier layer 13 acting as a barrier may be formed between the insulating layer 12 and the metal electrode 14. The barrier layer 13 may comprise a metal material (e.g., Ti, Ta, TiN, TaN, TiOx, TaOx, W, WN, WO, etc.).

[0006] However, if a metal electrode 14 is formed on top of the barrier layer 13 after the barrier layer 13 has been formed, the conformality of the barrier layer 13 decreases, leading to the problem of foreign matter (e.g., H2 or D2) being present inside the barrier layer 13. This deterioration in electrical properties due to the low quality of the barrier layer 13 can also degrade the electrical properties of the metal electrode 14. This results in a problem of reduced electrical properties for the semiconductor device. [Overview of the project] [Problems that the invention aims to solve]

[0007] The object of the present invention is to provide a method for manufacturing semiconductor devices that can improve the electrical characteristics of the barrier layer and metal electrodes by improving the quality of the barrier layer during the manufacturing process of the semiconductor device.

[0008] The purposes of this specification are not limited to those mentioned above. Other purposes and advantages of this specification not mentioned can be better understood from the examples described below. Furthermore, the purposes and advantages of this specification can be achieved by the components and combinations thereof described in the claims. [Means for solving the problem]

[0009] A method for manufacturing a semiconductor device according to one embodiment may include the steps of forming an insulating layer, forming a barrier layer on the insulating layer, performing a nitriding process on the barrier layer, and forming a metal electrode on the barrier layer.

[0010] In one embodiment, the step of performing the nitriding process may include the step of performing the HPN (High Pressure Nitridation) process.

[0011] In one embodiment, the HPN process can be carried out in a chamber into which a reactive gas containing nitrogen is injected in an inert gas atmosphere.

[0012] In one embodiment, when the HPN process is carried out, the concentration of the reactive gas in the chamber may be 5% or more.

[0013] In one embodiment, when the HPN process is performed, the internal pressure of the chamber can be maintained at 2 to 50 atmospheres.

[0014] In one embodiment, when the HPN process is performed, the internal temperature of the chamber can be maintained at 200 to 1000°C.

[0015] The method for manufacturing a semiconductor device according to one embodiment may further include a step of performing an HPA (High Pressure Anneal) process on the barrier layer.

[0016] In one embodiment, the HPA process can be carried out in a chamber into which a reactive gas containing hydrogen is injected in an inert gas atmosphere.

[0017] In one embodiment, when the HPA process is carried out, the concentration of the reactive gas in the chamber may be 5% or more.

[0018] In one embodiment, when the HPA process is performed, the internal pressure of the chamber can be maintained at 2 to 50 atmospheres.

[0019] In one embodiment, when the HPA process is performed, the internal temperature of the chamber can be maintained at 200 to 1000°C. [Effects of the Invention]

[0020] According to the examples, improving the quality of the barrier layer during the semiconductor device manufacturing process can improve the electrical properties of the barrier layer and metal electrodes, thereby improving the electrical properties of the semiconductor device. [Brief explanation of the drawing]

[0021] [Figure 1] This is a diagram showing the structure of a typical semiconductor device. [Figure 2] It is a diagram illustrating a manufacturing process of a semiconductor device according to one embodiment. [Figure 3] It is a diagram illustrating a manufacturing process of a semiconductor device according to one embodiment. [Figure 4] It is a diagram illustrating a manufacturing process of a semiconductor device according to another embodiment. [Figure 5] It is a diagram illustrating a manufacturing process of a semiconductor device according to another embodiment. [Figure 6] It is a diagram illustrating a manufacturing process of a semiconductor device according to another embodiment. [Figure 7] It is a diagram illustrating a manufacturing process of a semiconductor device according to another embodiment. [Figure 8] It is a diagram illustrating a manufacturing process of a semiconductor device according to another embodiment. [Figure 9] It is a graph showing resistance values of a barrier layer measured when a voltage is applied to a conventional semiconductor device and a semiconductor device according to one embodiment. [Figure 10] It is a graph showing resistance values of a metal electrode measured when a voltage is applied to a conventional semiconductor device and a semiconductor device according to one embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0022] The above objects, features and advantages will be described in detail below with reference to the accompanying drawings, whereby a person having ordinary knowledge in the technical field to which the present specification belongs can easily implement the embodiments of the present specification. In the description of the present specification, when it is determined that a detailed description of a known technology related to the present specification would obscure the gist of the present specification, the detailed description thereof will be omitted. Hereinafter, preferred embodiments of the present specification will be described in detail with reference to the accompanying drawings. The same reference numerals in the drawings denote the same or similar components.

[0023] FIG. 2 and FIG. 3 illustrate a manufacturing process of a semiconductor device according to one embodiment.

[0024] As shown in Figures 2 and 3, according to one embodiment of the semiconductor device manufacturing method, an insulating layer 22 is formed on the substrate 21, and a barrier layer 23 is formed on the insulating layer 22.

[0025] In one embodiment, the substrate 21 may be a silicon substrate, a germanium substrate, or a silicon-germanium substrate.

[0026] In one embodiment, the insulating layer 22 may be a silicon oxide film formed by a thermal oxidation process or a silicon oxide film formed using vapor deposition technology.

[0027] In one embodiment, the barrier layer 23 may contain a metallic material (for example, Ti, Ta, TiN, TaN, TiOx, TaOx, W, WN, WO, etc.).

[0028] Once the barrier layer 23 is formed, a nitriding process is performed on the barrier layer 23 24. By performing the nitriding process on the barrier layer 23, the content of the internal nitrogen (N) component of the barrier layer 23 increases, and internal impurities of the barrier layer 23 can be removed. In addition, by performing the nitriding process on the barrier layer 23, the conformality of the barrier layer 23 can be increased.

[0029] In one embodiment, the nitriding process performed on the barrier layer 23 may include a High Pressure Nitridation (HPN) process.

[0030] In one embodiment, the HPN process can be carried out in a chamber into which a reactive gas containing nitrogen is injected in an inert gas atmosphere.

[0031] Examples of inert gases include N2, Ar, and He, but the types of inert gases are not limited to these.

[0032] Examples of nitrogen-containing reactive gases include NH2 and NH3, but the types of nitrogen-containing reactive gases are not limited to these.

[0033] In one embodiment, when the HPN process is performed, the concentration of the nitrogen-containing reactive gas in the chamber may be 5% or more. For example, when the HPN process is performed, the concentration of the nitrogen-containing reactive gas in the chamber may be between 5% and 100%.

[0034] In one embodiment, when the HPN process is performed, the internal pressure of the chamber can be maintained at 2 to 50 atmospheres.

[0035] In one embodiment, when the HPN process is performed, the internal temperature of the chamber can be maintained at 200 to 1000°C.

[0036] When the nitriding process described above is performed on the barrier layer 23, the conformality of the barrier layer 23 is increased, which can improve the electrical properties of the barrier layer 23. Furthermore, if the barrier layer 23 has high conformality, the conformality of the metal electrode 25 formed on the barrier layer 23 will also be increased, which can improve the electrical properties of the metal electrode 25.

[0037] After the nitriding process 24 is performed on the barrier layer 23, a metal electrode 25 can be formed on the nitrided barrier layer 23.

[0038] The metal electrode 25 may be formed by a PVD (Physical Vapor Deposition) process such as plasma sputtering or evaporation, but the method of forming the metal electrode 25 is not limited to this. For example, the metal electrode 25 may contain a metallic substance such as W, Al, Ti, Ta, Co, Mo, Ru, or Cu.

[0039] On the other hand, according to other embodiments, a High Pressure Annealing (HPA) process can be performed on the barrier layer 23.

[0040] In one embodiment, the HPA process can be carried out in a chamber into which a reactive gas containing hydrogen is injected in an inert gas atmosphere.

[0041] Examples of inert gases include N2, Ar, and He, but the types of inert gases are not limited to these.

[0042] Examples of reactive gases containing hydrogen include H2 and D2, but the types of reactive gases containing hydrogen are not limited to these.

[0043] In one embodiment, when the HPA process is performed, the concentration of the hydrogen-containing reactive gas in the chamber may be 5% or more. For example, when the HPN process is performed, the concentration of the hydrogen-containing reactive gas in the chamber may be between 5% and 100%.

[0044] In one embodiment, when the HPA process is performed, the internal pressure of the chamber can be maintained at 2 to 50 atmospheres.

[0045] In one embodiment, when the HPA process is performed, the internal temperature of the chamber can be maintained at 200 to 1000°C.

[0046] In one embodiment, the HPN process can be performed on the barrier layer 23 after the HPA process. In another embodiment, the HPN process can be performed on the barrier layer 23 after the HPN process.

[0047] When the HPA process and HPN process are performed on the barrier layer 23 together, the isoangularity of the barrier layer 23 and the isoangularity of the metal electrode 25 are further improved compared to when only the HPN process is performed on the barrier layer 23. As a result, the electrical properties of the barrier layer 23 and the metal electrode 25 can be further improved.

[0048] Figures 4 to 8 show the manufacturing process of semiconductor devices according to other embodiments.

[0049] Referring to Figure 4, a thin film structure (TS) can be formed by alternately and repeatedly depositing a sacrificial layer 112 and an insulating layer 110 onto a substrate 100.

[0050] In one embodiment, the substrate 100 may be a silicon substrate, a germanium substrate, or a silicon-germanium substrate.

[0051] In one embodiment, the sacrificial layers 112 may be formed to have the same thickness. However, in other embodiments, the bottommost and topmost sacrificial layers 112 may be formed to be thicker than the sacrificial layers 112 located between them.

[0052] In one embodiment, the insulating layer 110 may have the same thickness. In other embodiments, parts of the insulating layer 110 may have different thicknesses.

[0053] In one embodiment, the sacrificial layer 112 and the insulating layer 110 may be formed using thermal CVD, plasma-enhanced CVD, physical CVD, or atomic layer deposition (ALD) processes.

[0054] In one embodiment, the sacrificial layer 112 and the insulating layer 110 may contain materials having different etching selectivity. For example, the sacrificial layer 112 may be at least one of a silicon film, a silicon oxide film, a silicon carbide, a silicon oxynitride film, and a silicon nitride film. The insulating layer 110 may be at least one of a silicon film, a silicon oxide film, a silicon carbide film, a silicon oxynitride film, and a silicon nitride film, but may be a different material from the sacrificial layer 112. For example, the sacrificial layer 112 may be formed of a silicon nitride film and the insulating layer 110 may be formed of a silicon oxide film. However, according to other embodiments, the sacrificial layer 112 may be formed of a conductive material and the insulating layer 110 may be formed of an insulating material.

[0055] Through-holes (H) can be formed through the thin film structure (TS) to expose the substrate 100. From a planar viewpoint, the through-holes (H) may be formed two-dimensionally on the upper surface of the thin film structure (TS). According to one embodiment, the through-holes (H) may be arranged along a first direction (D1). However, according to another embodiment, the through-holes (H) may be arranged in a zigzag pattern along the first direction (D1).

[0056] Forming through-holes (H) may include forming a first mask pattern (not shown) on the thin-film structure (TS) having openings that define the region where the through-holes (H) are formed, and anisotropically etching the thin-film structure (TS) using the first mask pattern as an etching mask. The first mask pattern may be formed of a material that is selective to the sacrificial layer 112 and the insulating layer 110. The etching process may cause the upper surface of the substrate 100 to be over-etched, resulting in a recess of the upper part of the substrate 100.

[0057] Next, as shown in Figure 5, charge storage structures 150 and first semiconductor patterns 160 can be formed to cover the inner walls of each through-hole (H) and expose the substrate 100.

[0058] Specifically, a charge storage structure film (not shown) and a first semiconductor film (not shown) can be sequentially formed to cover the inner wall of each through-hole (H). The charge storage structure film and the first semiconductor film can be formed to fill a portion of each through-hole (H). Each through-hole (H) may not be completely filled by the charge storage structure film and the first semiconductor film.

[0059] The charge storage structure film can cover the upper surface of the substrate 100 exposed by through-holes (H). The charge storage structure film can be deposited, in one example, using plasma-enhanced chemical vapor deposition (CVD), physical chemical vapor deposition (CVD), or atomic layer deposition (ALD) techniques.

[0060] The first semiconductor film may be formed on a charge storage structure film. According to one embodiment, the first semiconductor film may be a semiconductor material formed using one of the following techniques: atomic layer deposition (ALD) or chemical vapor deposition (CVD). The first semiconductor film may be a polycrystalline silicon film, for example. According to one embodiment, the first semiconductor film is amorphous during deposition but can be crystallized using an annealing process or the like.

[0061] After the charge storage structure film and the first semiconductor film are formed sequentially, the charge storage structure film and the first semiconductor film can be anisotropically etched to expose the substrate 100. This allows the first semiconductor pattern 160 and the charge storage structure 150 to be formed on the inner walls of each of the through holes (H). That is, the charge storage structure 150 and the first semiconductor pattern 160 may be formed in a cylindrical shape with open ends. If the first semiconductor film and the charge storage structure film are over-etched during anisotropic etching, the upper surface of the substrate 100 exposed by the first semiconductor pattern 160 and the charge storage structure 150 may be recessed.

[0062] In one embodiment, the charge storage structure 150 may include a tunnel insulating layer, a charge storage layer, and a blocking insulating layer sequentially laminated between the first semiconductor pattern 160 and the thin film structure (TS). The blocking insulating layer, the charge storage layer, and the tunnel insulating layer can be sequentially deposited on the inner walls of each through-hole (H) using plasma-enhanced chemical vapor deposition (CVD), physical chemical vapor deposition (CVD), or atomic layer deposition (ALD) techniques.

[0063] Next, a second semiconductor pattern 165 and an embedded insulating pattern 170 can be formed to fill the remaining portion of each through-hole (H).

[0064] Specifically, a second semiconductor film (not shown) and an embedded insulating film (not shown) can be sequentially formed on the substrate 100 on which the charge storage structure 150 and the first semiconductor pattern 160 are formed.

[0065] The second semiconductor film may be formed to a thickness that does not completely fill each of the through-holes (H). The second semiconductor film can cover the inner walls of each of the through-holes (H) and can cover the upper surface of the substrate 100 exposed by the charge storage structure 150 and the first semiconductor pattern 160. The second semiconductor film can connect the substrate 100 and the first semiconductor pattern 160.

[0066] The second semiconductor film may be a semiconductor material formed using either atomic layer deposition (ALD) or chemical vapor deposition (CVD) technology. In one example, the second semiconductor film may be a polycrystalline silicon film. According to one embodiment, the second semiconductor film is amorphous during deposition but can be crystallized using an annealing process or the like. The embedded insulating film may be formed to completely fill the interior of each through-hole (H). The embedded insulating film may be at least one of an insulating material formed using SOG technology and a silicon oxide film.

[0067] The embedded insulating film and the second semiconductor film can be planarized to form the second semiconductor pattern 165 and the embedded insulating pattern 170 within their respective through-holes (H). The planarization process may result in the second semiconductor pattern 165 and the embedded insulating pattern 170 being formed locally within their respective through-holes (H). The first and second semiconductor patterns 160 and 165 can be defined as semiconductor patterns (SP).

[0068] Next, as shown in Figure 6, the thin film structure (TS) can be patterned to form trenches (T) that expose the substrate 100 between adjacent through holes (H).

[0069] Forming a trench (T) may include forming a second mask pattern (not shown) on the thin film structure (TS) that defines the planar location where the trench (T) is formed, and anisotropically etching the thin film structure (TS) using the second mask pattern as an etching mask.

[0070] The trench (T) may be formed away from the semiconductor pattern (SP) to expose the sidewalls of the sacrificial layer 112 and the insulating layer 110. From a horizontal viewpoint, the trench (T) may be formed in a linear or rectangular shape, and in terms of vertical depth, the trench (T) may be formed to expose the upper surface of the substrate 100. During the etching process, the upper part of the substrate 100 may be over-etched, resulting in a recess of the upper part of the substrate 100.

[0071] Contrary to the illustration, the trench (T) may have different widths depending on its distance from the substrate 100 due to an anisotropic etching process. That is, the width of the lower part of the trench (T) may be narrower than the width of the upper part of the trench (T).

[0072] Next, the sacrificial layer 112 exposed by the trench (T) may be removed to form a recess region (R) between the insulating layers 110. The recess region (R) may also be formed by isotropically etching the sacrificial layer 112 using etching conditions that are etching selective to the insulating layer 110, the charge storage structure 150, the semiconductor pattern (SP), the lower insulating film 105, and the substrate 100. The sacrificial layer 112 can be completely removed by the isotropic etching process. In one example, if the sacrificial layer 112 is a silicon nitride film and the insulating layer 110 is a silicon oxide film, the etching process can be carried out using an etching solution containing phosphoric acid.

[0073] Next, as shown in the enlarged view 300 of Figure 7, a barrier layer 200 is formed inside each recess region (R). The barrier layer 200 may be formed on the insulating layer 110 and the charge storage structure 150.

[0074] In one embodiment, the barrier layer 200 may contain a metallic material (for example, Ti, Ta, TiN, TaN, TiOx, TaOx, W, WN, WO, etc.).

[0075] Once the barrier layer 200 is formed, a nitriding process is performed on the barrier layer 200 202. By performing the nitriding process on the barrier layer 200, the internal nitrogen (N) content of the barrier layer 200 increases, and internal impurities of the barrier layer 200 can be removed. In addition, by performing the nitriding process on the barrier layer 200, the isometricity of the barrier layer 200 can be increased.

[0076] In one embodiment, the nitriding step performed on the barrier layer 200 may include an HPN step.

[0077] In one embodiment, the HPN process can be carried out in a chamber into which a reactive gas containing nitrogen is injected in an inert gas atmosphere.

[0078] Examples of inert gases include N2, Ar, and He, but the types of inert gases are not limited to these.

[0079] Examples of nitrogen-containing reactive gases include NH2 and NH3, but the types of nitrogen-containing reactive gases are not limited to these.

[0080] In one embodiment, when the HPN process is performed, the concentration of the nitrogen-containing reactive gas in the chamber may be 5% or more. For example, when the HPN process is performed, the concentration of the nitrogen-containing reactive gas in the chamber may be between 5% and 100%.

[0081] In one embodiment, when the HPN process is performed, the internal pressure of the chamber can be maintained at 2 to 50 atmospheres.

[0082] In one embodiment, when the HPN process is performed, the internal temperature of the chamber can be maintained at 200 to 1000°C.

[0083] When the nitriding process described above is performed on the barrier layer 200, the isogonality of the barrier layer 200 is increased, which can improve the electrical properties of the barrier layer 200. Furthermore, if the barrier layer 200 has high isogonality, the isogonality of the metal electrode 204 formed on the barrier layer 200 will also be increased, which can improve the electrical properties of the metal electrode 204.

[0084] Nitriding process for barrier layer 200 202 After this is performed, a metal electrode 204 can be formed on the nitrided barrier layer 200.

[0085] The metal electrode 204 may be formed by a PVD process such as plasma sputtering or evaporation, but the method of forming the metal electrode 204 is not limited to this. For example, the metal electrode 204 may contain a metallic substance such as W, Al, Ti, Ta, Co, Mo, Ru, or Cu.

[0086] On the other hand, according to other embodiments, the HPA process can be performed on the barrier layer 200.

[0087] In one embodiment, the HPA process can be carried out in a chamber into which a reactive gas containing hydrogen is injected in an inert gas atmosphere.

[0088] Examples of inert gases include N2, Ar, and He, but the types of inert gases are not limited to these.

[0089] Examples of reactive gases containing hydrogen include H2 and D2, but the types of reactive gases containing hydrogen are not limited to these.

[0090] In one embodiment, when the HPA process is performed, the concentration of the reactive gas containing hydrogen in the chamber may be 5% or more. For example, when the HPA process is performed, the concentration of the reactive gas containing hydrogen in the chamber may be between 5% and 100%.

[0091] In one embodiment, when the HPA process is performed, the internal pressure of the chamber can be maintained at 2 to 50 atmospheres.

[0092] In one embodiment, when the HPA process is performed, the internal temperature of the chamber can be maintained at 200 to 1000°C.

[0093] In one embodiment, the HPA process can be performed on the barrier layer 200, followed by the HPN process. In another embodiment, the HPN process can be performed on the barrier layer 200, followed by the HPA process.

[0094] When the HPA process and the HPN process are performed on the barrier layer 200 together, the isoangularity of the barrier layer 200 and the isoangularity of the metal electrode 204 are further improved compared to when only the HPN process is performed on the barrier layer 200. As a result, the electrical properties of the barrier layer 200 and the metal electrode 204 can be further improved.

[0095] Through these processes, a semiconductor device like the one shown in Figure 8 can be completed.

[0096] Figure 9 is a graph showing the resistance values ​​of the barrier layer measured when a voltage is applied to a normal semiconductor device and a semiconductor device according to one embodiment.

[0097] In Figure 9, M1 represents a typical semiconductor device as shown in Figure 1, i.e., a semiconductor device in which the barrier layer 13 has not undergone the HPN process or HPN process. In Figure 9, M2 represents a semiconductor device having the same structure as in Figure 3, but with the barrier layer 23 having undergone the HPN process. In Figure 9, M3 represents a semiconductor device having the same structure as in Figure 3, but with the barrier layer 23 having undergone both the HPA process and the HPN process.

[0098] As shown in Figure 9, the resistance of the barrier layer 13 when a voltage is applied to the semiconductor element (M1) is greater than the resistance of the barrier layer 23 when a voltage is applied to the semiconductor element (M2). This result indicates that when the HPN process is applied to the barrier layer, the isometricity of the barrier layer is improved, thereby reducing the resistance of the barrier layer.

[0099] Furthermore, as shown in Figure 9, the resistance of the barrier layer 23 when a voltage is applied to the semiconductor element (M2) is greater than the resistance of the barrier layer 23 when a voltage is applied to the semiconductor element (M3). These results indicate that when both the HPA process and the HPN process are applied to the barrier layer, the isometricity of the barrier layer is improved compared to when only the HPN process is applied, and the resistance of the barrier layer is further reduced.

[0100] Figure 10 is a graph showing the resistance values ​​of metal electrodes measured when a voltage is applied to a typical semiconductor device and a semiconductor device according to one embodiment.

[0101] In Figure 10, M1 represents a typical semiconductor device as shown in Figure 1, i.e., a semiconductor device in which the barrier layer 13 has not undergone the HPN or HPA process. In Figure 10, M2 represents a semiconductor device having the same structure as in Figure 3, but with the barrier layer 23 having undergone the HPN process. In Figure 10, M3 represents a semiconductor device having the same structure as in Figure 3, but with the barrier layer 23 having undergone both the HPA and HPN processes.

[0102] As shown in Figure 10, the resistance of the metal electrode 14 when a voltage is applied to the semiconductor element (M1) is greater than the resistance of the metal electrode 25 when a voltage is applied to the semiconductor element (M2). These results indicate that when the HPN process is applied to the barrier layer, the isometricity of the metal electrode is improved, thereby reducing the resistance of the metal electrode.

[0103] Furthermore, as shown in Figure 10, the resistance of the metal electrode 25 when a voltage is applied to the semiconductor element (M2) is greater than the resistance of the metal electrode 25 when a voltage is applied to the semiconductor element (M3). These results indicate that when both the HPA process and the HPN process are applied to the barrier layer, the isometricity of the metal electrode is improved compared to when only the HPN process is applied to the barrier layer, resulting in a further reduction in the resistance of the metal electrode.

[0104] As described above, this specification has been explained with reference to the illustrative drawings, but the present invention is not limited to the embodiments and drawings disclosed herein, and various modifications can be made by someone of the ordinary skill. In addition, even if the effects of the configuration described herein are not explicitly stated and explained in the embodiments described herein, the effects that can be predicted by such configuration should also be recognized.

Claims

1. The step of forming an insulating layer; A step of forming a barrier layer on the insulating layer; A step in which the high-pressure annealing (HPA) process for the barrier layer is carried out in a chamber into which a reactive gas containing hydrogen is injected in an inert gas atmosphere, while maintaining the internal pressure of the chamber at 2 to 50 atmospheres; A step of performing a high-pressure nitriding (HPN) process on the barrier layer in a chamber into which a reactive gas containing nitrogen is injected in an inert gas atmosphere, while maintaining the internal pressure of the chamber at 2 to 50 atmospheres; and The step includes forming a metal electrode on the barrier layer that has undergone the HPA step and the HPN step, The HPA process and the HPN process are carried out sequentially. A method for manufacturing semiconductor devices.

2. When the HPN process is performed, the concentration of the reactive gas in the chamber is 5% or more. A method for manufacturing a semiconductor device according to claim 1.

3. During the HPN process, the internal temperature of the chamber is maintained at 200 to 1000°C. A method for manufacturing a semiconductor device according to claim 1.

4. When the HPA process is performed, the concentration of the reactive gas in the chamber is 5% or more. A method for manufacturing a semiconductor device according to claim 1.

5. During the HPA process, the internal temperature of the chamber is maintained at 200 to 1000°C. A method for manufacturing a semiconductor device according to claim 1.

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