Methods for converting numerical formats using scaling

Abstract

Instructions are executed to perform a scaling operation, a transforming operation, and a division operation. Executing the instructions includes scaling an input value in one format to provide a scaled result. The scaled result is transformed from one format to provide a transformed result in another format. The transformed result is divided into a plurality of portions, and one or more of the plurality of portions is placed at a selected location.

Description

[Technical Field]

[0001] One or more embodiments relate to facilitating processing within a computing environment, and more particularly to improving such processing. [Background technology]

[0002] Applications running within a computing environment provide a wide variety of operations used by diverse technologies, including but not limited to design, manufacturing, medical technology, automotive technology, and computer processing. These applications, often written in programming languages ​​such as COBOL, frequently perform complex calculations in executing their operations. These calculations, for example, involve power functions, exponential functions, or both, and often require data conversion from one format (e.g., binary-coded decimal) to another (e.g., hexadecimal floating-point), and vice versa.

[0003] An application performs various steps to convert from one format to another. For example, to convert from binary-coded decimal to hexadecimal floating-point, the application includes a step to convert the binary-coded decimal to an integer, and then the integer to a hexadecimal floating-point. Furthermore, each of these steps may include substeps. These conversions are time-consuming and affect the performance of the computing environment and the availability of computer resources. [Overview of the project]

[0004] The provision of computer program products that facilitate processing within a computing environment overcomes the shortcomings of prior art and brings additional advantages. A computer program product includes one or more computer-readable storage media and program instructions collectively stored in one or more computer-readable storage media for performing a method. This method includes executing instructions to perform scaling, transformation, and partitioning operations. Executing instructions includes scaling an input value in one form to provide a scaled result, transforming the scaled result from one form to provide the transformed result in another form, partitioning the transformed result into multiple parts, and placing one or more of the multiple parts in selected locations.

[0005] Using a single instruction to perform scaling, transformation, and partitioning operations improves performance and reduces resource utilization. Using a single, designed instruction to perform scaling, transformation, and partitioning operations allows certain tasks, such as scaling, transformation, and partitioning, to be performed far more efficiently than using a software paradigm. Scaling, transformation, and partitioning operations are performed much faster, reducing execution time and improving the performance of the processor, the system as a whole, or both.

[0006] In one example, one format is decimal format and the other is hexadecimal floating-point format. For example, the decimal format is binary-coded decimal format. Hexadecimal floating-point format offers improved precision, which is beneficial for various technologies, improving precision, performance, or both.

[0007] In one example, scaling involves determining a scale factor and using that scale factor to scale an input value and provide a scaled result. Determining a scale factor includes, for example, obtaining a scale value using an operand of an instruction and determining the scale factor using the scale value. Using a scale factor involves multiplying an input value by the scale factor to obtain a scaled result.

[0008] Scaling facilitates the conversion of a value from one format (e.g., decimal) to another format (e.g., hexadecimal floating-point) by, for example, separating specific digits of a number and indicating, for instance, the selected position within the number to be truncated or rounded.

[0009] In one example, splitting involves normalizing the transformed result to obtain a first normalized result, and then truncating the first normalized result to obtain one result in a shorter form of another form. In another example, splitting further involves subtracting one result from the transformed result to provide a difference, normalizing this difference to provide a second normalized result, and then truncating the second normalized result to obtain another result in a longer form of another form.

[0010] By dividing a hexadecimal floating-point number into smaller parts, the smaller parts may be used independently, or they may be summed up to provide a more accurate result, or both.

[0011] For example, placement includes placing one result in a portion of the selected location and another result in a different portion of the selected location. This portion of the selected location includes, for example, the first selected bit of the register specified by the instruction, and the other portion of the selected location includes the second selected bit of the register specified by the instruction.

[0012] In one example, in addition to the sign of one result, the signs of other results are also determined. The sign of one result and the signs of other results are arranged at selected positions.

[0013] Computer-implemented methods and systems related to one or more aspects are also described and claimed herein. Further, services related to one or more aspects are also described herein and may be claimed.

[0014] Additional features and advantages are realized through the technology described herein. Other embodiments and aspects are described in detail herein and are considered a part of the claimed aspects.

[0015] One or more aspects are specifically pointed out by way of example and distinctly claimed in the claims at the end of this specification. The foregoing content, as well as the objects, features, and advantages of one or more aspects, will become apparent from the following detailed description taken in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] [Figure 1A] FIG. 1 is a diagram illustrating an example of a computing environment for use incorporating one or more aspects of the present invention. [Figure 1B] FIG. 1B further shows details of the processor of FIG. 1A in accordance with one or more aspects of the present invention. [Figure 2] FIG. 2 is a diagram illustrating an example format of a Decimal Scale and Convert and Split to Hexadecimal Floating Point instruction in accordance with one or more aspects of the present invention. [Figure 3] FIG. 3 is a diagram illustrating an example of processing associated with execution of the Decimal Scale and Convert and Split to Hexadecimal Floating Point instruction in accordance with one or more aspects of the present invention. [Figure 4]This figure shows an example of the processing associated with the scaling operation of decimal scaling and hexadecimal floating-point conversion partitioning instructions according to one or more aspects of the present invention. [Figure 5] This figure shows an example of processing logic for performing the conversion operation of decimal scaling and hexadecimal floating-point conversion partitioning instructions according to one or more aspects of the present invention. [Figure 6] This figure shows an example of the processing associated with the partitioning operation of a decimal scaling and hexadecimal floating-point conversion partitioning instruction according to one or more aspects of the present invention. [Figure 7] This figure shows an example of the processing associated with the placement of decimal scaling and hexadecimal floating-point conversion partitioning instructions according to one or more aspects of the present invention. [Figure 8A] This figure shows an example of facilitating processing within a computing environment according to one or more aspects of the present invention. [Figure 8B] This figure shows an example of facilitating processing within a computing environment according to one or more aspects of the present invention. [Figure 9A] This figure shows another example of a computing environment for using one or more embodiments of the present invention. [Figure 9B] This figure shows an example of further details of the memory shown in Figure 9A, according to one or more embodiments of the present invention. [Figure 9C] This figure shows another example of further details of the memory in Figure 9A, according to one or more aspects of the present invention. [Figure 10A] This figure shows yet another example of a computing environment for using one or more embodiments of the present invention. [Figure 10B] This figure shows further details of the memory shown in Figure 10A, according to one or more embodiments of the present invention. [Figure 11] This figure shows one embodiment of a cloud computing environment according to one or more aspects of the present invention. [Figure 12]This figure shows an example of an abstract model layer according to one or more aspects of the present invention. [Modes for carrying out the invention]

[0017] According to aspects of the present invention, the ability to facilitate processing within a computing environment is provided. As one example, a single instruction (e.g., a single designed hardware machine instruction at a hardware / software interface) is provided to perform scaling, conversion, and partitioning operations. The instruction, referred herein as a decimal scaling and hexadecimal floating-point conversion and partitioning instruction, is part of a general-purpose processor instruction set architecture (ISA) that is programmatically dispatched on a processor such as a general-purpose processor (in another example, the instruction may be part of a dedicated processor, such as a coprocessor configured for a particular function).

[0018] As part of the execution of a single instruction (e.g., a decimal scaling and hexadecimal floating-point conversion and partitioning instruction), various operations are performed, including scaling input data using a scaling factor and providing scaled data, converting the scaled data from one format (e.g., binary-coded decimal) to another format (e.g., hexadecimal floating-point), and partitioning the result (e.g., a hexadecimal floating-point number) into multiple parts. Each part of the partitioned result may be used independently of the others, or selected parts may be combined to provide a more accurate result, or both. Each of these operations is performed as part of executing a single instruction, improving system performance, and reducing the use of system resources.

[0019] In one example, as shown, the conversion is from binary-coded decimal to hexadecimal floating-point. Binary-coded decimal is a binary encoding of a decimal number, where each decimal number is represented by a fixed number of bits (e.g., 4 bits or 8 bits). Hexadecimal floating-point is a format for encoding floating-point numbers. In one example, a hexadecimal floating-point number includes a sign bit, an exponent (e.g., 7 bits), and a fractional part (e.g., 6 digits, 14 digits, or 28 digits). The exponent represents the signed exponent, obtained, for example, by adding 64 to the exponent value. The range of the exponent is from 0 to 127, which corresponds to the exponent range, for example, from -64 to +63. The magnitude of a hexadecimal floating-point number is the product of the fractional part and the number 16 raised to the power of the exponent represented by the exponent. This value will be positive or negative, depending on whether the sign bit is, for example, 0 or 1.

[0020] Hexadecimal floating-point numbers can be represented in several different forms, including short form (e.g., 32 bits), long form (e.g., 64 bits), and extended form (e.g., 128 bits). In each form, the first bit (e.g., the leftmost bit of the first form, bit 0) is the sign bit, the next selected number of bits (e.g., 7 bits) is the exponent, and in short and long forms, the remaining bits constitute the fractional part, which contains, for example, 6-digit or 14-digit hexadecimal numbers, respectively. In extended form, the fractional part is, for example, 28-digit fractional parts, and extended hexadecimal floating-point numbers consist of two long-form numbers called the upper and lower parts. The upper part is any long hexadecimal floating-point number. The fractional part of the upper part contains, for example, the leftmost 14 hexadecimal digits of the 28-digit fractional part, and the fractional part of the lower part contains, for example, the rightmost 14 hexadecimal digits of the 28-digit fractional part. The upper part of the exponent and sign are those of the extended hexadecimal floating-point number, while the lower part of the extended operand's sign and exponent are ignored.

[0021] One embodiment of a computing environment for using one or more aspects of the present invention is described with reference to Figure 1A. As an example, the computing environment is based on the z / Architecture® hardware architecture provided by International Business Machines Corporation (Armonk, New York). One embodiment of the z / Architecture hardware architecture is described in the published document “z / Architecture Principles of Operation,” IBM Publication No. SA22-7832-12, Thirteenth Edition, September 2019, which is incorporated herein by reference in its entirety. However, the z / Architecture hardware architecture is only one exemplary architecture, and other architectures or other types of computing environments of International Business Machines Corporation or other entities, or both, may include or use one or more aspects of the present invention. z / Architecture and IBM are trademarks or registered trademarks of International Business Machines Corporation in at least one jurisdiction.

[0022] Referring to Figure 1A, the computing environment 100 includes, for example, a computer system 102, shown in the form of a general-purpose computing device. The computer system 102 may include, but is not limited to, one or more processors or processing units 104 (e.g., central processing units (CPUs)), memory 106 (e.g., also called system memory, main memory, primary memory, central memory, or storage), and one or more input / output (I / O) interfaces 108, all coupled to one or more via one or more buses or other connections 110 or both.

[0023] Bus 110 represents one or more of several types of bus structures, including memory buses or memory controllers, peripheral buses, accelerated graphics ports, and processor or local buses using any of the various bus architectures. Examples of such architectures include, but are not limited to, ISA (Industry Standard Architecture), MCA (MicroChannel Architecture), EISA (Enhanced ISA), VESA (Video Electronics Standards Association) local buses, and PCI (Peripheral Component Interconnects).

[0024] Memory 106 may include a cache 112, such as a shared cache, which may be coupled to the local cache 114 of the processor 104. Furthermore, memory 106 may include one or more programs or applications 116 and at least one operating system 118. An exemplary operating system is the z / OS(R) operating system provided by International Business Machines Corporation (Armonk, New York). z / OS is a trademark or registered trademark of International Business Machines Corporation in at least one jurisdiction. Other operating systems provided by International Business Machines Corporation or other entities, or both, may be used. Memory 106 may include one or more computer-readable program instructions 120 configured to perform functions of embodiments of the present invention.

[0025] The computer system 102 may communicate with one or more external devices 130, such as a user terminal, tape drive, pointing device, display, and one or more data storage devices 134, for example, via an I / O interface 108. The data storage device 134 may store one or more programs 136, one or more computer-readable program instructions 138, or data, or a combination thereof. The computer-readable program instructions may be configured to perform functions of embodiments of the present invention.

[0026] The computer system 102 may communicate with the network interface 132, for example, via the I / O interface 108, which enables the computer system 102 to communicate with one or more networks, such as a local area network (LAN), a general wide area network (WAN), or a public network (e.g., the Internet), or a combination thereof, thereby enabling communication with other computing devices or systems.

[0027] Computer system 102 may include, or be coupled to, removable / non-removable, volatile / non-volatile computer system storage media, or both. For example, computer system 102 may include, or be coupled to, a magnetic disk drive for reading and writing to a non-removable, non-volatile magnetic medium (typically called a “hard drive”), a removable, non-volatile magnetic disk (e.g., a “floppy disk”), or an optical disk drive for reading or writing to a removable, non-volatile optical disk such as a CD-ROM, DVD-ROM, or other optical medium, or a combination thereof. It should be understood that other hardware components or software components, or both, may be used with computer system 102. Examples include, but are not limited to, microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data archive storage systems.

[0028] Computer system 102 can be operated in a number of other general-purpose or dedicated computing system environments or configurations. Examples of well-known computing systems, environments, or configurations, or combinations thereof, that may be suitable for use with computer system 102 include, but are not limited to, personal computer (PC) systems, server computer systems, thin clients, thick clients, handheld or laptop devices, microprocessor systems, microprocessor-based systems, set-top boxes, programmable consumer electronics, network PCs, microcomputer systems, mainframe computer systems, and distributed cloud computing environments that include any of these systems or devices.

[0029] In one example, a processor (e.g., processor 104) includes several functional components used to execute instructions. As shown in Figure 1B, these functional components include, for example, an instruction fetch component 150 for fetching instructions to be executed, an instruction decode unit 152 for decoding the fetched instructions and obtaining the operands of the decoded instructions, one or more instruction execution components 154 for executing the decoded instructions, a memory access component 156 for accessing memory to execute the instructions if necessary, and a write-back component 158 ​​for providing the results of the executed instructions. One or more of these components may access one or more registers 160 in instruction processing, or use registers 160, or both. Furthermore, one or more of the components may include, or be able to access, at least some of, one or more other components used in performing scaling, conversion, or splitting operations, or combinations thereof, of, for example, decimal scaling and hexadecimal floating-point conversion and splitting instructions (or other operations that may use one or more aspects of the present invention), as described herein, according to one or more aspects of the present invention. One or more other components include, for example, a scaling component, a conversion component, and a splitting component (or one or more other components) 170.

[0030] In accordance with aspects of the present invention, instructions referred to herein as decimal scaling and hexadecimal floating-point conversion and partitioning instructions are provided to perform scaling, conversion, and partitioning operations for converting a number from one format (e.g., decimal) to another format (e.g., hexadecimal floating-point) as part of executing a single instruction.

[0031] One embodiment of a decimal scaling and hexadecimal floating-point conversion / partition instruction used to perform scaling, conversion, and partitioning operations is described with reference to Figure 2. The instruction is executed, in one example, using a general-purpose processor (e.g., processor 104). In the description herein, a specific location of a field, a specific field, or a specific size, or a combination thereof (e.g., a specific byte or bit, or both), is indicated. However, other locations, fields, or sizes, or combinations thereof, may be provided. Furthermore, setting a bit to a specific value (e.g., 1 or 0) may be specified, but this is merely an example. In other examples, a bit may be set to a different value, such as the opposite value or another value. Many variations are possible.

[0032] In one example, the decimal scaling and hexadecimal floating-point conversion and partition instructions have a VRR-b form that indicates vector registers and register operations, along with extended operation codes (opcodes). In one embodiment, the decimal scaling and hexadecimal floating-point conversion and partition instructions are part of a vector function that provides, for example, a fixed-size vector containing 1 to 16 elements. Each vector contains data that is manipulated by the vector instructions defined in this function. In one embodiment, if the vector consists of multiple elements, each element is processed in parallel with the other elements. In one example, instruction completion does not occur until all elements have been processed. In other embodiments, elements are processed partially in parallel, sequentially, or both.

[0033] In one embodiment, there are 32 vector registers, and other types of registers can be mapped to the quadrants of the vector registers. For example, a register file, which is an array of processor registers in a central processing unit (e.g., processor 104), may contain 32 vector registers, each with a length of 128 bits. Sixteen floating-point registers, each with a length of 64 bits, can overlap with the vector registers. Therefore, as an example, if floating-point register 2 is changed, vector register 2 is also changed. Other mappings of other types of registers are also possible.

[0034] For example, within storage, vector data appears in the same left-to-right order as other data formats. Bits of the data format, numbered 0-7, form a byte at the leftmost (smallest numbered) byte position in storage, bits 8-15 form a byte at the next consecutive positions, and so on. In yet another example, vector data may appear in a different order within storage, such as right-to-left.

[0035] As shown in Figure 2, in one example, the decimal scaling and hexadecimal floating-point conversion partition instruction 200 contains multiple fields, each field having a subscript associated with it. The subscript associated with a field in the instruction indicates the operand to which that field applies. For example, the subscript 1 associated with vector register V1 indicates that the register specified using V1 contains the first operand, and so on. The operand length of a register is one register, for example, 128 bits.

[0036] In one embodiment, the decimal scaling and hexadecimal floating-point conversion and partition instruction 200 includes operation code (opcode) fields 202a, 202b (e.g., bits 0-7 and 40-47) indicating scaling, conversion, and partition operations where the input data is, for example, a decimal number (e.g., binary-coded decimal) and the output is, for example, a hexadecimal floating-point value; a first vector register (V1) field 204 (e.g., bits 8-11) used to specify a first vector register; a second vector register (V2) field 206 (e.g., bits 12-15) used to specify a second vector register; a third vector register (V3) field 208 (e.g., bits 16-19) used to specify a third vector register; and a register extension bit (RXB) field 210 (e.g., bits 36-39), each of which is described below. In one embodiment, each field is separate and independent of the others, but in other embodiments, two or more fields may be combined. Further information regarding these fields is described below.

[0037] In one embodiment, the vector register (V1) field 204 is used to indicate a vector register that stores a first operand. The first operand is the result of scaling a decimal number to a hexadecimal floating-point value and then splitting the hexadecimal floating-point value into multiple (e.g., two) operands. The second operand is contained in a vector register specified using the vector register (V2) field 206 and is, for example, a signed packed decimal number (e.g., a binary-coded decimal, with 31 digits and a sign), which is then scaled using an unsigned integer contained in a third operand contained in a vector register specified using the vector register (V3) field 208.

[0038] In one example, vector register fields 204, 206, and 208 are each used with the RXB field 210 to specify a vector register. For example, the RXB field 210 contains the most significant bit of the operand specified by the vector register. Bits of register specifications not specified by the instruction become spare and are set to 0. The most significant bit is concatenated to the left of, for example, a 4-bit register specification in a vector register field to create a 5-bit vector register specification.

[0039] In one example, the RXB field contains four bits (for example, bits 0-3), each bit defined as follows: 0 - The most significant bit of the first vector register specification of the instruction (e.g., bits 8-11). 1 - The most significant bit of the second vector register specification of the instruction (e.g., bits 12-15) (if any). 2 - The most significant bit of the third vector register specification of the instruction (e.g., bits 16-19) (if any). 3 - The most significant bit of the fourth vector register specification of the instruction (e.g., bits 32-35) (if any). Each bit is set to either 0 or 1 depending on the register number, for example, by the assembler. For example, for registers 0-15, the bits are set to 0, and for registers 16-31, the bits are set to 1, and so on.

[0040] In one embodiment, each RXB bit is an extension bit for a specific position in an instruction that includes one or more vector registers. For example, bit 0 of RXB is an extension bit for positions 8-11, which are assigned to, for example, V1. Specifically, for vector registers, the register containing the operand is specified using a 4-bit field of the register field, for example, by adding the corresponding register extension bit (RXB) as the most significant bit. For example, if the 4-bit field is 0110 and the extension bit is 0, then the 5-bit field 00110 indicates register number 6. In a further embodiment, the RXB field includes an additional bit, and for each vector or position, two or more bits are used as extensions.

[0041] In the execution of one embodiment of the decimal scaling and hexadecimal floating-point conversion and splitting instruction, the second operand is scaled and converted to a hexadecimal floating-point number using an unsigned integer at a selected position of the third operand (e.g., byte element 7). The second operand is multiplied by a scaling factor equal to, for example, 10, which is equal to the byte element 7 of the third operand. The scaled result is converted to, for example, a hexadecimal floating-point value and split into, for example, two hexadecimal floating-point operands using normalization and truncation. As an example, the two hexadecimal floating-point operands are placed in the register of the first operand.

[0042] Further details of one embodiment of processing based on the execution of decimal scaling and hexadecimal floating-point conversion and partitioning instructions, according to one or more aspects of the present invention, are described with reference to Figures 3-7. In one example, a processor such as a general-purpose processor 104 is used to execute the instructions. In one example, processor hardware is used to execute the instructions. The hardware may be located within or coupled to the processor for the purpose of receiving instructions from the processor, and the processor, for example, retrieves, decodes, and sets instructions for execution on the hardware. Other variations are possible.

[0043] Referring to Figure 3, first, instructions such as decimal scaling and hexadecimal floating-point conversion partitioning instructions are obtained (e.g., fetched, received, provided, etc.) (300) and executed (310). This execution includes, for example, obtaining the second and third operands of the instruction (312). The second operand is, for example, a signed packed decimal obtained from a location specified by the instruction (e.g., a vector register) (e.g., using the V2 field 206), and the third operand is, for example, an unsigned integer obtained from a location specified by the instruction (e.g., a vector register) (e.g., using the V3 field 208). In one example, the unsigned integer is located at byte element 7 of the third operand.

[0044] The second operand (e.g., a signed packed decimal obtained using V2) is scaled using an unsigned integer in, for example, byte element 7 of the third operand (e.g., obtained using V3), and the scaled result is obtained (314).

[0045] A scaled result, which is in one format (e.g., a decimal number such as binary-coded decimal), is converted to a converted result in another format (316). For example, a scaled decimal number is converted to a hexadecimal floating-point number. The converted result is divided into multiple parts. For example, a hexadecimal floating-point number is divided into multiple (e.g., two) hexadecimal floating-point operands (318), and one or more of those operands (e.g., two operands) are placed in the position of the first operand (e.g., a register specified using V1) (320). Further details regarding scaling, conversion, division, and placement are illustrated with reference to Figures 4-6.

[0046] First, with reference to Figure 4, one embodiment of performing scaling of the second operand (314 in Figure 3) is described. In one example, a value called the scale value is obtained for a selected portion of the third operand (e.g., byte element 7) (stored in a vector register specified using V3) (400). A determination is made as to whether the value is valid (410). For example, a determination is made as to whether the value has a default relationship to a pre-selected value (e.g., is it less than a pre-selected value such as 8, for example?). If the value is invalid, the process terminates, for example with an error. However, if the value is valid, the process proceeds to determine a scale factor using the value. For example, the scale factor is equal to 10 raised to the power of (415). The second operand is multiplied by the scale factor to obtain the scaled result (420). In one example, since the second operand is a signed packed decimal, scaling by a power of 10 is equivalent to shifting the digits to the left. Scaling facilitates the conversion of signed packed decimal numbers to hexadecimal floating-point numbers.

[0047] Next, the scaled result, which is in one format (e.g., decimal format), is converted to a converted result, which is in another format (e.g., hexadecimal floating-point format) (Figure 3, 316). This conversion can be performed using multiple techniques. In one example, to convert a decimal number to a hexadecimal number, the following is performed:

[0048] Divide a decimal number by 16 and find the quotient and remainder.

[0049] The remainder multiplied by 16 becomes a single hexadecimal digit, starting from the rightmost digit.

[0050] Divide the quotient by 16 to find the other quotient and remainder.

[0051] This process starts at 16 times the remainder and is repeated until the quotient becomes 0.

[0052] The above technique is used for converting decimal numbers to hexadecimal numbers, but other techniques may also be used. In one example, hardware logic is used to improve the speed at which processing is executed and facilitate the conversion.

[0053] One example of hardware logic used to perform the conversion is described with reference to FIG. 5. Referring to FIG. 5, in one example, a binary coded decimal 500 is input to the logic. Starting from the leftmost digit of the binary coded decimal, up to 4 digits of the binary coded decimal are selected (510). The selected digits are input to a counter tree 520, which multiplies each digit using a redundant digit format and equations. In one example, this multiplication is performed by shifting the numerical value, and each multiplication by a power of 2 results in a shift of the numerical value.

[0054] One example of an equation used by the counter tree is as follows. First, (X'+Y') is set to 0, represents the value resulting from the previous loop in the counter tree, and A, B, C, D are the digits of a binary coded decimal (BCD) numerical value.

[0055] New total=X+Y=(X'+Y')×10000+A×1000+B×100+C×10+D

[0056] =(X'+Y')×(2 13 +2 11 -2 8 +2 4 )

[0057] +A×(2 9 +2 8 +2 7 +2 6 +2 5 +2 3 )

[0058] +B×(2 6 +2 5 +2 2 )

[0059] +C×(23 +2 1 )

[0060] +D

[0061] The process loops within the counter tree until all digits of the BCD number have been processed. The output of the counter tree 520 is fed into a 2:1 adder 530, which provides the intermediate converted result (e.g., an intermediate hexadecimal floating-point number) in a non-redundant format. The output of the adder 530 is fed into a hex normalize, update exponent logic 540, which is used to normalize the adder's output and update the exponent to provide the hexadecimal floating-point number. For example, normalization involves shifting all leading zeros to the right of the radix to the left to remove those digits and decreasing the exponent by one for each shift.

[0062] This specification describes one specific example of the above process for an 8-digit BCD number. In the following example, since the actual values ​​of X and Y are implementation-specific (for example, X and Y may be different values ​​but still have the same sum), Z, which is implementation-independent, is used. Thus, Z = X + Y, Z' = X' + Y', and Z' is initialized to 0. Furthermore, in this example, BCD = 32610423, and therefore initially A = 3, B = 2, C = 6, D = 1.

[0063] formula Hexadecimal value

[0064] Z=0×(2 13 +2 11 -2 8 +2 4 ) Z=x0

[0065] +3 × (2 9 +2 8 +2 7 +2 6 +2 5 +2 3 ) +xBB8

[0066] +2 × (2 6 +2 5 +2 2 ) +xC8

[0067] +6 × (2 3 +2 1 ) +x3C

[0068] +1 +x1

[0069] Z = 0 + 3000 + 200 + 60 + 1 = 3261 Z = xCBD

[0070] Next, A=0, B=4, C=2, D=3.

[0071] Z = 3261 × (2 13 +2 11 -2 8 +2 4 ) Z=1F196D0

[0072] +0 × (2 9 +2 8 +2 7 +2 6 +2 5 +2 3 ) +x0

[0073] +4 × (2 6 +2 5 +2 2 ) +x190

[0074] +2 × (2 3 +2 1 ) +x14

[0075] +3 +x3

[0076] Z=32610000+400+20+3=32610423 Z=x1F19877

[0077] A hexadecimal floating-point number (also referred herein to as the converted result) is divided into multiple parts, such as two hexadecimal floating-point operands (318 in Figure 3). For example, a hexadecimal floating-point number is divided using normalization and truncation, as further illustrated with reference to Figure 6. In one embodiment, the hexadecimal floating-point number (also referred to as the converted result) is normalized to obtain a first normalized result (600). The first normalized result is truncated into a hexadecimal floating-point short form, which is called a short truncated result or upper result (610). As an example, the fractional part of the hexadecimal floating-point number (i.e., the digits after the exponent) is normalized (e.g., leading zeros are removed) to provide the first normalized result, and then, since it is in short form, all digits after six digits are truncated, for example.

[0078] The shorter, truncated result is subtracted from the transformed result to obtain the difference (620). As described herein, the difference is normalized to obtain a second normalized result (630), and the second normalized result is truncated into a hexadecimal long form called the lower result (for example, truncating the last digits, e.g., 14 digits, because it is a long form) (640). The upper and lower results are two hexadecimal floating-point operands resulting from the transformation and decomposition. In one example, if the lower result is equal to 0, the lower result is forced to be a true 0.

[0079] One or more of the results are placed at the position of the first operand. In one example, the upper and lower results are placed at the position of the first operand, as will be further explained with reference to Figure 7 (320 in Figure 3). In one embodiment, the result of the upper hexadecimal floating-point short form is converted to hexadecimal long form. For example, the short result is placed at bits 0 to 31 of the position of the first operand (e.g., the vector register specified by V1), and bits 32 to 63 of the position of the first operand are set to 0 (700). The lower result in hexadecimal floating-point long form is placed, for example, at bits 64 to 127 of the same position (e.g., the same vector register) (710).

[0080] In one example, the signs of the upper and lower results are determined (720). For example, the sign of the upper result is equal to the sign code of the second operand, except when the second operand is negative 0, in which case the upper result is set to 0 with a positive sign. The sign of the lower result is equal to the sign of the upper result, except when the lower result is forced to be true 0, and the upper result is non-zero and negative. The determined signs are placed in the position of the first operand (730). For example, bit 0 is set to the sign of the upper result and bit 64 is set to the sign of the lower result.

[0081] In one example, the validity of the digits and sign of the second operand is checked. If the validity check fails, a general operand data exception is recognized.

[0082] While various fields and registers for decimal scaling and hexadecimal floating-point conversion and partitioning instructions have been described, one or more embodiments of the present invention may use more or fewer, or both, fields or registers of other sizes, or combinations thereof. Many variations are possible. For example, implicit registers may be used instead of explicitly specified registers or fields or both in the instruction, or explicitly specified registers or fields or both may be used instead of implicit registers or fields or both, or combinations thereof. Other variations are also possible.

[0083] As described herein, in one aspect, a single instruction (e.g., a single designed machine instruction in a hardware / software interface, e.g., a decimal scaling and hexadecimal floating-point conversion / decomposition instruction) is provided to perform scaling a decimal number to provide a scaled decimal number, converting a scaled decimal number to a hexadecimal floating-point number, and splitting a hexadecimal floating-point number into multiple hexadecimal floating-point numbers. This instruction is a hardware instruction defined in an instruction set architecture (ISA), for example, that directly converts a value in one form (e.g., decimal) to a value in another form (e.g., hexadecimal floating-point). This conversion is a direct conversion from decimal to hexadecimal floating-point, rather than, for example, converting from decimal to integer and then from integer to hexadecimal floating-point. For example, it is faster and more efficient than a program that performs binary-coded decimal multiplication or shift, converts binary-coded decimal numbers to integers, converts integers to hexadecimal floating-point numbers, and retains enough digits to obtain the high-precision short-precision hexadecimal floating-point and the low-precision long-precision hexadecimal floating-point numbers. The complexity of the program associated with performing scaling, conversion, and partitioning operations is reduced. Furthermore, the performance of the operation (and therefore the processor) is improved. Execution of hardware instructions reduces execution time and improves performance.

[0084] Performance is improved by using a single instruction instead of multiple instructions to perform operations such as scaling, transformation, and partitioning, thereby eliminating the need for multiple traverses of hardware / software interfaces. Furthermore, by executing processing as part of a single instruction, the processing remains within the processing unit performing the operation (e.g., a floating-point unit) without requiring updates to the processor's register file registers (i.e., arrays of processor registers used to store data between memory and function units (e.g., floating-point units)) before completing the operation. This improves execution time and reduces the use of processor resources.

[0085] In one example, a hexadecimal floating-point number can be divided into smaller parts (e.g., a short upper hexadecimal floating-point number and a long lower hexadecimal floating-point number), where the smaller parts may be used independently, or multiple smaller parts may be summed together to provide a more accurate result, or both.

[0086] One or more aspects of the present invention are closely related to computer technology and facilitate processing within computers, thereby improving their performance. At a minimum, performance in a computing environment is improved by reducing complexity, decreasing resource usage, and increasing processing speed by using a single designed machine instruction to perform scaling of decimal numbers (e.g., binary-coded decimal) to obtain scaled decimal numbers, converting scaled decimal numbers to hexadecimal floating-point numbers, and dividing hexadecimal floating-point numbers into multiple parts. The data or instructions, or both, can be used in many technical fields such as computer processing, medical processing, design, automotive technology, and manufacturing. These technical fields are improved by reducing execution time through optimization in data conversion.

[0087] When processing within a computing environment relates to one or more aspects of the present invention, further details of one embodiment that facilitates such processing are described with reference to Figures 8A-8B.

[0088] Referring to Figure 8A, in one embodiment, instructions are executed to perform scaling, transformation, and splitting operations (800). Executing the instructions includes, for example, scaling an input value in one format to provide a scaled result (802), transforming the scaled result from one format to provide a transformed result in another format (804), splitting the transformed result into multiple parts (806), and placing one or more of the multiple parts in selected locations (808). By performing at least the scaling, transformation, and splitting operations using a single instruction, performance is improved and resource utilization is reduced.

[0089] In one example, one format is decimal and the other is hexadecimal floating-point (820). In another example, the decimal format is binary-coded decimal (822). Hexadecimal floating-point format offers improved precision, which is beneficial for various technologies, improving precision, performance, or both.

[0090] In one example, scaling involves determining a scale factor (830) and using the scale factor to scale an input value to provide a scaled result (832). Determining a scale factor involves, for example, obtaining a scale value using an operand of an instruction (834) and using the scale value to determine a scale factor (836). The input value is multiplied by the scale factor to obtain a scaled result (838).

[0091] Scaling facilitates the conversion of a value from one format (e.g., decimal) to another format (e.g., hexadecimal floating-point) by, for example, separating specific digits of a number and indicating, for instance, the selected position within the number to be truncated or rounded.

[0092] Referring to Figure 8B, in one example, splitting includes normalizing the transformed result to obtain a first normalized result (850), and truncating the first normalized result to obtain one result in another short form (852). In another example, splitting further includes subtracting one result from the transformed result to provide a difference (854), normalizing this difference to provide a second normalized result (856), and truncating the second normalized result to obtain another result in another long form (858).

[0093] By dividing a hexadecimal floating-point number into smaller parts, the smaller parts may be used independently, or they may be summed up to provide a more accurate result, or both.

[0094] For example, placement includes placing one result in a portion of the selected location (860) and placing another result in a different portion of the selected location (862). This portion of the selected location includes, for example, the first selected bit of the register specified by the instruction (864), and the other portion of the selected location includes the second selected bit of the register specified by the instruction (866).

[0095] In one example, the sign of one result is determined (867), the sign of another result is determined (868), and the signs of one result and the other result are placed in the selected position (870).

[0096] Other variations and embodiments are possible.

[0097] Aspects of the present invention can be used in many types of computing environments. Another example of a computing environment for incorporating and using one or more aspects of the present invention is described with reference to Figure 9A. As an example, the computing environment in Figure 9A is based on the z / Architecture(R) hardware architecture provided by International Business Machines Corporation (Armonk, New York). However, the z / Architecture hardware architecture is only one exemplary architecture. Furthermore, the computing environment may be based on other architectures, including but not limited to the Intel(R) x86 architecture, other architectures from International Business Machines Corporation, or architectures from other companies, or combinations thereof. Intel is a trademark or registered trademark of Intel Corporation or its subsidiaries in the United States and other countries.

[0098] In one example, the computing environment 10 includes a central electronics complex (CEC) 11. The central electronics complex 11 includes multiple components, such as one or more processors (also called central processing units (CPUs)) 13 and memory 12 (also called system memory, main memory, primary memory, central memory, or storage) coupled to an input / output (I / O) subsystem 14.

[0099] The I / O subsystem 14 may be part of the central electronic circuit complex or it may be separate from the central electronic circuit complex. The I / O subsystem 14 directs the flow of information between the main memory 12 and the input / output control unit 15 and input / output (I / O) devices 16 which are coupled to the central electronic circuit complex.

[0100] Many types of I / O devices may be used. One particular type is a data storage device 17. The data storage device 17 can store one or more programs 18, one or more computer-readable program instructions 19, or data, or a combination thereof. The computer-readable program instructions may be configured to perform functions of embodiments of the present invention.

[0101] The central electronic circuit complex 11 may include, or be coupled to, a removable / non-removable, volatile / non-volatile computer system storage medium, or both. For example, the central electronic circuit complex 11 may include, or be coupled to, a magnetic disk drive for reading and writing to a non-removable, non-volatile magnetic medium (typically called a “hard drive”), a removable, non-volatile magnetic disk (e.g., a “floppy disk”), or an optical disk drive for reading and writing to a removable, non-volatile optical disk such as a CD-ROM, DVD-ROM, or other optical medium, or a combination thereof, or both. It should be understood that other hardware components or software components, or both, may be used in conjunction with the central electronic circuit complex 11. Examples include, but are not limited to, microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data archive storage systems.

[0102] Furthermore, the central electronic circuit complex 11 can be operated in a number of other general-purpose or dedicated computing system environments or configurations. Examples of well-known computing systems, environments, or configurations, or combinations thereof, suitable for use with the central electronic circuit complex 11 include, but are not limited to, personal computer (PC) systems, server computer systems, thin clients, thick clients, handheld or laptop devices, microprocessor systems, microprocessor-based systems, set-top boxes, programmable consumer electronics, network PCs, minicomputer systems, mainframe computer systems, and distributed cloud computing environments that include any of these systems or devices.

[0103] The central electronic circuit complex 11 provides support for logical partitioning or virtualization or both in one or more embodiments. In one embodiment, as shown in Figure 9B, the memory 12 includes, for example, one or more logical partitions 20, a hypervisor 21 that manages the logical partitions, and processor firmware 22. One example of the hypervisor 21 is the Processor Resource / System Manager (PR / SM™) provided by International Business Machines Corporation (Armonk, New York). As used herein, firmware includes, for example, the microcode of the processor. Firmware includes, for example, hardware-level instructions or data structures or both used in the implementation of higher-level machine code. In one embodiment, firmware includes, for example, microcode containing trusted software, or proprietary code typically provided as microcode specific to the underlying hardware that controls the operating system's access to the system hardware. PR / SM is a trademark or registered trademark of International Business Machines Corporation in at least one jurisdiction.

[0104] Each logical partition 20 can function as a separate system. That is, each logical partition can be independently reset and run a guest operating system 23, such as the z / OS(R) operating system provided by International Business Machines Corporation (Armonk, New York), or other control code 24, such as coupling facility control code (CFCC), and operate with different programs 25. An operating system or application program running within a logical partition appears to have access to the entire system, but in reality, only a portion of it is available. While the z / OS operating system is provided as an example, other operating systems provided by International Business Machines Corporation or other companies, or both, may be used according to one or more aspects of the present invention.

[0105] Memory 12 is coupled to the CPU 13 (Figure 9A), which is a physical processor resource allocated to the logical partition. For example, a logical partition 20 includes one or more logical processors, each of which represents all or part of the physical processor resource 13 dynamically allocated to the logical partition.

[0106] In yet another embodiment, the central electronics complex provides support for virtual machines (with or without logical partitioning). As shown in Figure 9C, the memory 12 of the central electronics complex 11 includes, for example, one or more virtual machines 26, a virtual machine manager (such as a hypervisor 27) that manages the virtual machines, and processor firmware 28. One example of a hypervisor 27 is the z / VM(R) hypervisor provided by International Business Machines Corporation (Armonk, New York). A hypervisor is sometimes referred to as a host. z / VM is a trademark or registered trademark of International Business Machines Corporation in at least one jurisdiction.

[0107] The central electronic circuit complex's support for virtual machines allows for the operation of numerous virtual machines 26, each virtual machine 26 running a different program 29 and capable of running a guest operating system 30, such as the Linux(R) operating system. Each virtual machine 26 can function as a separate system; that is, each virtual machine can be reset independently, run a guest operating system, and run a different program. An operating system or application program running within a virtual machine appears to have access to the entire system, but in reality, only a portion of it is available. While z / VM and Linux are provided as examples, other virtual machine managers and / or operating systems may be used according to one or more aspects of the present invention. The registered trademark Linux(R) is used in accordance with a sublicense from the Linux Foundation (exclusive licensee of Linus Torvalds, the worldwide trademark owner).

[0108] Another embodiment of a computing environment for using one or more aspects of the present invention is described with reference to Figure 10A. In this example, the computing environment 36 includes, for example, a native central processing unit (CPU) 37, memory 38, and one or more input / output devices or interfaces 39, coupled to one or more buses 40 or other connections or both. For example, the computing environment 36 may include a PowerPC(R) processor provided by International Business Machines Corporation (Armonk, New York), an HP Superdome with an Intel(R) Itanium(R) II processor provided by Hewlett-Packard Corporation (Palo Alto, California), or other machines or combinations based on architectures provided by International Business Machines Corporation, Hewlett-Packard Corporation, Intel Corporation, Oracle Corporation, or other companies, or a combination thereof. PowerPC is a trademark or registered trademark of International Business Machines Corporation in at least one jurisdiction. Itanium is a trademark or registered trademark of Intel Corporation or its subsidiaries in the United States and other countries.

[0109] The native central processing unit 37 includes one or more native registers 41, such as one or more general-purpose registers or one or more dedicated registers or both, used during processing within the environment. These registers contain information representing the state of the environment at any particular point in time.

[0110] Furthermore, the native central processing unit 37 executes instructions and code stored in memory 38. In one particular example, the central processing unit executes emulator code 42 stored in memory 38. This code allows a computing environment configured on one architecture to emulate another architecture. For example, the emulator code 42 allows machines based on architectures other than the z / Architecture hardware architecture (such as PowerPC processors or HP Superdome servers) to emulate the z / Architecture hardware architecture and execute software and instructions developed based on the z / Architecture hardware architecture.

[0111] Further details relating to the emulator code 42 are described with reference to Figure 10B. The guest instructions 43 stored in memory 38 include software instructions developed to run on architectures other than the native CPU 37 architecture (e.g., those that interact with machine instructions). For example, the guest instructions 43 are designed to run on a processor based on the z / Architecture hardware architecture, but are instead emulated on the native CPU 37, which may be, for example, an Intel Itanium II processor. In one example, the emulator code 42 includes an instruction fetch routine 44 for retrieving one or more guest instructions 43 from memory 38 and for optionally providing local buffering of the retrieved instructions. The emulator code 42 also includes an instruction translation routine 45 for determining the type of guest instruction retrieved and for translating the guest instruction into one or more corresponding native instructions 46. This translation includes, for example, identifying the function performed by the guest instruction and selecting a native instruction to perform that function.

[0112] Furthermore, the emulator code 42 includes an emulation control routine 47 for triggering the execution of a native instruction. The emulation control routine 47 may cause the native CPU 37 to execute a native instruction routine that emulates one or more already obtained guest instructions, and upon completion of such execution, return control to the instruction fetch routine to emulate the acquisition of the next guest instruction or group of guest instructions. The execution of the native instruction 46 may include reading data from memory 38 into a register, storing data back into memory from the register, or performing any kind of arithmetic or logical operation determined by the translation routine.

[0113] For example, each routine is implemented in software stored in memory and executed by the native central processing unit 37. In other examples, one or more routines or operations are implemented in firmware, hardware, software, or any combination thereof. Registers of the emulated processor can be emulated by using the registers 41 of the native CPU or by using locations in memory 38. In embodiments, the guest instruction 43, the native instruction 46, and the emulator code 42 may reside in the same memory or may be distributed across different memory devices.

[0114] One instruction to be emulated is a decimal scaling and conversion partitioning instruction described herein in accordance with an aspect of the present invention.

[0115] The computing environments described herein are merely examples of available computing environments. Other environments may be used, including, but not limited to, undivided environments, divided environments, cloud environments, or emulated environments, or combinations thereof, and embodiments are not limited to any one of these environments. Various examples of computing environments are described herein, but one or more embodiments of the present invention may be used with many types of environments. The computing environments provided herein are merely examples.

[0116] Each computing environment can be configured to include one or more embodiments of the present invention.

[0117] One or more embodiments may relate to cloud computing.

[0118] While this disclosure includes a detailed description of cloud computing, it should be understood that implementations of the teachings presented herein are not limited to cloud computing environments. Embodiments of the present invention may be implemented in combination with any other type of computing environment that is currently known or may be developed in the future.

[0119] Cloud computing is a service delivery model that enables convenient, on-demand network access to a shared pool of configurable computing resources (e.g., networks, network bandwidth, servers, processing, memory, storage, applications, virtual machines, and services), allowing these resources to be provisioned and released quickly with minimal administrative effort or interaction with service providers. This cloud model may include at least five features, at least three service models, and at least four deployment models.

[0120] The features are as follows:

[0121] On-demand self-service: Cloud users can unilaterally and automatically provision computing power, such as server time and network storage, as needed, without requiring human interaction with service providers.

[0122] Broad network access: The capabilities of the cloud are available over a network and can be accessed using standard mechanisms, thus facilitating use by heterogeneous thin-client or thick-client platforms (e.g., mobile phones, laptops, and PDAs).

[0123] Resource Pool: A provider's computing resources are pooled and served to multiple users using a multi-tenant model. Various physical and virtual resources are dynamically allocated and reallocated as needed. There is a sense of location independence, and users typically have neither control nor know the exact location of the resources served, although at a higher level of abstraction, they may be able to specify a location (e.g., country, state, or data center).

[0124] Rapid Adaptability: Cloud capabilities can be provisioned quickly and flexibly, sometimes automatically, scale out rapidly, and be released quickly to scale in rapidly. The capacity available for provisioning often appears to the user as if they can purchase any amount at any time without limit.

[0125] Measured Services: Cloud systems leverage metering capabilities to automatically control and optimize resource usage at an appropriate level of abstraction for each type of service (e.g., storage, processing, bandwidth, and active user accounts). Resource usage can be monitored, controlled, and reported, providing transparency to both service providers and users.

[0126] The service model is as follows:

[0127] SaaS (Software as a Service): The capability provided to the user is the use of the provider's applications running on cloud infrastructure. These applications can be accessed from various client devices via thin client interfaces such as web browsers (e.g., web-based email). Users do not manage or control the underlying cloud infrastructure, including the network, servers, operating system, storage, or individual application functions, except for the possibility of making limited user-specific application configuration settings.

[0128] PaaS (Platform as a Service): The ability provided to the user is to deploy applications created or acquired by the user, using programming languages ​​and tools supported by the provider, onto a cloud infrastructure. The user does not manage or control the underlying cloud infrastructure, including the network, servers, operating system, or storage, but can control the configuration of the deployed application and, in some cases, the application hosting environment.

[0129] IaaS (Infrastructure as a Service): The capabilities provided to the user are the provisioning of processing, storage, networking, and other basic computing resources, allowing the user to deploy and run any software, including operating systems and applications. The user does not manage or control the underlying cloud infrastructure, but can control the operating system, storage, and deployed applications, and in some cases, has limited control over selected network components (e.g., host firewalls).

[0130] The deployment model is as follows:

[0131] Private Cloud: This cloud infrastructure is operated solely for the organization. It can be managed by this organization or a third party and can reside on-premises or off-premises.

[0132] Community Cloud: This cloud infrastructure is shared by multiple organizations and supports specific communities that share common interests (e.g., missions, security requirements, policies, and compliance considerations). It can be managed by these organizations or third parties and can reside on-premises or off-premises.

[0133] Public Cloud: This cloud infrastructure is available for use by general users or large industry groups and is owned by the organization that sells the cloud service.

[0134] Hybrid Cloud: This cloud infrastructure is a combination of two or more clouds (private, community, or public) that are joined together while retaining their own distinct entities, through standardized or proprietary technologies that enable the portability of data and applications (e.g., cloud bursting to adjust load balancing between clouds).

[0135] Cloud computing environments are service-oriented environments that emphasize statelessness, loose coupling, modularity, and semantic interoperability. At the heart of cloud computing is the infrastructure, which includes a network of interconnected nodes.

[0136] Referring here to Figure 11, an exemplary cloud computing environment 50 is shown. As illustrated, the cloud computing environment 50 includes one or more cloud computing nodes 52 that can communicate with local computing devices used by cloud users (e.g., a personal digital assistant (PDA) or mobile phone 54A, a desktop computer 54B, a laptop computer 54C, or an automotive computer system 54N, or a combination thereof). The nodes 52 can communicate with each other. The nodes 52 can be physically or virtually grouped within one or more networks into a private cloud, community cloud, public cloud, or hybrid cloud, or a combination thereof, as described herein (not illustrated). This allows the cloud computing environment 50 to provide an infrastructure, platform, or SaaS, or a combination thereof, that does not require cloud users to maintain resources on their local computing devices. The types of computing devices 54A-N shown in Figure 11 are intended for illustrative purposes only, and it is understood that the computing node 52 and the cloud computing environment 50 can communicate with any type of computer-controlled device via any type of network or network-addressable connection (e.g., a connection using a web browser) or both.

[0137] Referring now to Figure 12, a set of functional abstraction layers provided by the cloud computing environment 50 (Figure 11) is shown. It should be understood in advance that the components, layers, and functions shown in Figure 12 are intended to be illustrative only and that embodiments of the present invention are not limited thereto. The following layers and corresponding functions are provided as illustrated:

[0138] The hardware and software layer 60 includes hardware components and software components. Examples of hardware components include a mainframe 61, RISC (Reduced Instruction Set Computer) architecture-based servers 62, 63, blade servers 64, storage devices 65, and networks and network components 66. In some embodiments, software components include network application server software 67 and database software 68.

[0139] The virtualization layer 70 includes an abstraction layer that can provide virtual entities such as virtual servers 71, virtual storage 72, virtual networks 73 including virtual private networks, virtual applications and operating systems 74, and virtual clients 75.

[0140] For example, the management layer 80 may provide the following functions: Resource provisioning 81 dynamically procures computing and other resources used to perform tasks within the cloud computing environment. Measurement and pricing 82 tracks the costs of using resources within the cloud computing environment and sends invoices or bills for the use of those resources. For example, those resources may include application software licenses. Security verifies the identities of cloud users and tasks and protects data and other resources. The user portal 83 provides users and system administrators with access to the cloud computing environment. Service level management 84 allocates and manages cloud computing resources to meet required service levels. Service Level Agreement (SLA) planning and execution 85 prepares and procures cloud computing resources in advance of anticipated future demands in accordance with SLAs.

[0141] Workload Layer 90 provides examples of capabilities available in a cloud computing environment. Examples of workloads and capabilities provided by this layer include mapping and navigation 91, software development and lifecycle management 92, virtual classroom education delivery 93, data analysis processing 94, transaction processing 95, and scaling, transformation, and partitioning processing 96.

[0142] Aspects of the present invention may be systems, methods, or computer program products, or combinations thereof, at any possible level of technical detail of integration. A computer program product may include a computer-readable storage medium containing computer-readable program instructions for causing a processor to perform aspects of the present invention.

[0143] A computer-readable storage medium can be a tangible device capable of holding and storing instructions for use by an instruction execution device. A computer-readable storage medium may be, but is not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination thereof. A non-exclusive list of more specific examples of computer-readable storage media includes portable floppy disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM) or flash memory, static random access memory (SRAM), compact disc read-only memory (CD-ROM), digital versatile disk (DVD), memory sticks, floppy disks, mechanically encoded devices such as punched cards or grooved structures on which instructions are recorded, and any appropriate combination thereof. When used herein, computer-readable storage media should not be interpreted as transient signals themselves, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmitting media (e.g., light pulses passing through optical fiber cables), or electrical signals transmitted through wires.

[0144] The computer-readable program instructions described herein may be downloaded from a computer-readable storage medium to each computing device / processing device, or to an external computer or external storage device via a network (e.g., the Internet, a local area network, a wide area network, or a wireless network, or a combination thereof). This network may include copper transmission cables, optical transmission fibers, wireless transmitters, routers, firewalls, switches, gateway computers, or edge servers, or a combination thereof. A network adapter card or network interface within each computing device / processing device receives computer-readable program instructions from the network and transfers those computer-readable program instructions for storage on a computer-readable storage medium within each computing device / processing device.

[0145] The computer-readable program instructions for performing the operation of the present invention may be assembler instructions, instruction-set-architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state-setting data, configuration data for integrated circuits, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk(R) and C++, and procedural programming languages ​​such as the C programming language or similar programming languages. The computer-readable program instructions may be executed as a whole on the user's computer, partially as a standalone software package on the user's computer, partially on the user's computer and a remote computer, or entirely on a remote computer or a server. In the latter scenario, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection may be to an external computer (for example, via the Internet using an Internet Service Provider). In some embodiments, to carry out aspects of the present invention, electronic circuits including, for example, programmable logic circuits, field-programmable gate arrays (FPGAs), or programmable logic arrays (PLAs) can be customized by executing computer-readable program instructions using state information of computer-readable program instructions.

[0146] Aspects of the present invention will be described herein by reference to flowcharts or block diagrams, or both, of methods, apparatuses (systems), and computer program products, according to embodiments of the present invention. It will be understood that each block in a flowchart or block diagram, or both, and any combination of blocks contained in a flowchart or block diagram, or both, are implemented by computer-readable program instructions.

[0147] These computer-readable program instructions may be provided to a computer or other programmable data processing device processor to create a machine, so that instructions executed via the processor of the computer or other programmable data processing device may create means to perform functions / operations specified in one or more blocks of a flowchart or block diagram or both. These computer-readable program instructions may be stored on a computer-readable storage medium containing instructions that include a product containing instructions to perform modes of functions / operations specified in one or more blocks of a flowchart or block diagram or both, and may be used to instruct a computer, a programmable data processing device, or other device, or a combination thereof, to function in a particular manner.

[0148] Computer-readable program instructions may be read into a computer, another programmable data processing device, or other device so that instructions executed on a computer, another programmable device, or other device perform functions / operations specified in one or more blocks of a flowchart or block diagram, or both, thereby causing a series of operable steps to be executed on a computer, another programmable device, or other device that generates a computer implementation process.

[0149] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagram may represent a module, segment, or portion of instructions comprising one or more executable instructions for implementing a defined logical function. In some alternative implementations, the functions shown in the blocks may occur in a different order than that shown in the figures. For example, two consecutively shown blocks may actually be implemented as a single step, executed simultaneously, executed substantially simultaneously in a way that partially or completely overlaps in time, or possibly in reverse order, depending on the functions they contain. Note also that each block in the block diagram or flowchart diagram, or both, and any combination of blocks contained in the block diagram or flowchart diagram, or both, is implemented by a dedicated hardware-based system that performs a defined function or operation, or a combination of dedicated hardware and computer instructions.

[0150] In addition to the above, one or more aspects may be provided, presented, deployed, managed, or serviced by a service provider that provides management of the customer's environment. For example, a service provider may create, maintain, or support computer code or computer infrastructure, or both, that runs one or more aspects for one or more customers. In return, the service provider may receive payment from the customer, for example, under a subscription or fee agreement or both. As an additional or alternative, the service provider may receive payment from the sale of advertising content to one or more third parties.

[0151] In one aspect, an application may be deployed to perform one or more embodiments. As one example, the deployment of an application includes providing a computer infrastructure that functions to perform one or more embodiments.

[0152] In a further embodiment, a computing infrastructure may be deployed that includes integrating computer-readable code into a computing system, such that the code combined with the computing system can execute one or more embodiments.

[0153] In yet another aspect, a process for integrating a computing infrastructure may be provided, which includes integrating computer-readable code into a computer system. The computer system comprises a computer-readable medium, the computer medium including one or more embodiments. The code combined with the computer system can perform one or more embodiments.

[0154] Although various embodiments have been described above, these are merely examples. For example, computing environments of other architectures may be used to incorporate one or more embodiments, to use one or more embodiments, or both. Furthermore, various instructions or operations may be used. Furthermore, different types of registers or different registers, or both, may be used. Many variations are possible.

[0155] Various embodiments are described herein. Furthermore, many modifications are possible without departing from the spirit of the embodiments of the present invention. It should be noted that each embodiment or feature and its variations described herein can be combined with any other embodiment or feature, in particular, as long as they do not contradict each other.

[0156] Furthermore, other types of computing environments can benefit and be used. For example, a data processing system could be used that includes at least two processors, directly or indirectly coupled to memory elements via a system bus, suitable for storing, executing, or both program code. These memory elements include, for example, local memory used during the actual execution of program code, bulk storage, and cache memory for temporarily storing at least some program code to reduce the number of times the code must be retrieved from bulk storage during execution.

[0157] Input / output devices or I / O devices (including, but not limited to, keyboards, displays, pointing devices, DASDs, tapes, CDs, DVDs, thumb drives, and other storage media) can be connected to the system directly or through an intermediary I / O controller. Network adapters may be connected to the system, allowing data processing systems to be connected to other data processing systems or remote printers or storage devices through an intermediary private or public network. Modems, cable modems, and Ethernet(R) cards are just a few of the types of network adapters that can be used.

[0158] The terms used herein are intended solely to describe specific embodiments and are not intended to be limiting. Where used herein, the singular forms “a,” “an,” and “the” are intended to include the plural form unless otherwise explicitly indicated in the context. It will be further understood that the terms “equipped with” or “possessing” or both, as used herein, indicate the presence of a described function, integer, step, operation, element, or component, or a combination thereof, but do not exclude the presence or addition of one or more other functions, integers, steps, operations, elements, components, or groups thereof, or combinations thereof.

[0159] All means or steps and functional elements within the following claims, along with their corresponding structures, materials, actions, and equivalents, are intended to include, if any, any structures, materials, or actions for performing a function in combination with other claimed elements when specifically claimed. Descriptions of one or more embodiments are presented for illustrative and explanatory purposes, but are not intended to be exhaustive and are not limited to the disclosed forms. Many modifications and variations will be apparent to those skilled in the art. Embodiments have been selected and described to best illustrate various aspects and practical applications, and to enable others skilled in the art to understand the diverse embodiments with various modifications suitable for a particular intended use.

Claims

1. A computer program product which is one or more computer-readable storage media for facilitating processing within a computing environment, wherein the computer program product comprises collectively stored program instructions, and the program instructions are transmitted to a computer. To execute instructions for scaling, transforming, and splitting operations, and to cause the execution of such instructions, To scale input values ​​in one format and provide the scaled result, The scaled result is converted from one format to another format, and the converted result is provided in another format. The converted result is divided into multiple parts, This includes arranging one or more of the aforementioned plurality of parts at a selected position, The aforementioned division involves normalizing the transformed result to obtain a first normalized result. The first normalized result is truncated to obtain a single result in the other short form, Subtracting the one result from the converted result provides the difference, The aforementioned difference is normalized to provide a second normalized result, A computer program product further comprising truncating the second normalized result to obtain another result in the other long form.

2. The computer program product according to claim 1, wherein one of the formats is a decimal format and the other format is a hexadecimal floating-point format.

3. The computer program product according to claim 2, wherein the decimal format is binary-coded decimal format.

4. The scaling mentioned above Determining the scale factor, A computer program product according to any one of claims 1 to 3, comprising using the scaling factor to scale the input value and providing the scaled result.

5. Determining the scale factor is Obtaining a scale value using the operand of the aforementioned instruction, This includes determining the scale coefficient using the scale value, The computer program product according to claim 4, wherein using the scaling factor includes multiplying the input value by the scaling factor to obtain the scaled result.

6. The arrangement described above is Placing the aforementioned one result in the portion of the selected position, The computer program product according to claim 1, further comprising arranging the other results in another portion of the selected location.

7. The computer program product according to claim 6, wherein the portion of the selected position includes a first selected bit of the register specified by the instruction, and the other portion of the selected position includes a second selected bit of the register specified by the instruction.

8. Executing the aforementioned instruction means Determining the sign of the aforementioned result, Determining the sign of the other results mentioned above, The computer program product according to claim 6, further comprising arranging the reference numerals for one result and the reference numerals for the other result at the selected positions.

9. A computer system for facilitating processing within a computing environment, wherein the computer system is Memory and The computer system comprises a processor that communicates with the memory, and is configured to perform a method, wherein the method is This includes executing instructions for performing scaling, transformation, and splitting operations, and executing such instructions is To scale input values ​​in one format and provide the scaled result, The scaled result is converted from one format to another format, and the converted result is provided in another format. The converted result is divided into multiple parts, This includes arranging one or more of the aforementioned plurality of parts at a selected position, The aforementioned division involves normalizing the transformed result to obtain a first normalized result. The first normalized result is truncated to obtain a single result in the other short form, Subtracting the one result from the converted result provides the difference, The aforementioned difference is normalized to provide a second normalized result, A computer system further comprising truncating the second normalized result to obtain another result in the other long form.

10. The scaling mentioned above Determining the scale factor, The computer system according to claim 9, comprising using the scaling factor to scale the input value and providing the scaled result.

11. The arrangement described above is Placing the aforementioned one result in the portion of the selected position, The computer system according to claim 9, further comprising arranging the other results in another portion of the selected location.

12. A method for facilitating processing within a computing environment through computer information processing, wherein the method is This includes executing instructions for performing scaling, transformation, and splitting operations, and executing such instructions is To scale input values ​​in one format and provide the scaled result, The scaled result is converted from one format to another format, and the converted result is provided in another format. The converted result is divided into multiple parts, This includes arranging one or more of the aforementioned plurality of parts at a selected position, The aforementioned division involves normalizing the transformed result to obtain a first normalized result. The first normalized result is truncated to obtain a single result in the other short form, Subtracting the one result from the converted result provides the difference, The aforementioned difference is normalized to provide a second normalized result, A method further comprising truncating the second normalized result to obtain another result in the other long form.

13. The scaling mentioned above Determining the scale factor, The method according to claim 12, comprising using the scaling factor to scale the input value and providing the scaled result.

14. The arrangement described above is Placing the aforementioned one result in the portion of the selected position, The method according to claim 12, further comprising arranging the other results in another part of the selected position.

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