Integrated circuit security using programmable switches

Abstract

To provide a security mechanism for providing a security mechanism for computer chips using programmable switches.SOLUTION: In the security mechanism, a user sets each of programmable switches included in a computer chip, receives a security key, identifies programmable switches (PSs) that must be "open" to cause the computer chip to function, and identifies PSs that must be "closed" to cause the computer chip to function; in response to identifying a set of PSs that must be "open" to cause the computer chip to function, the user applies reset pulses to each of the PSs, and disconnects using electronic fuses; if all of the PSs are set to "open" or "closed" according to the security key, and the electronic fuses are opened for all of the PSs, then power is removed from the computer chip.SELECTED DRAWING: Figure 8

Description

[[Technical Field]]

[0001] The present invention relates generally to the field of integrated circuits (i.e., computer chips, or simply chips), and more specifically to providing a security mechanism for computer chips using programmable switches. [[Background Art]]

[0002] Computer chips have revolutionized the world. These chips are used in many consumer products, from indoor robotic vacuum cleaners to outdoor robotic lawn mowers. Improvements in chip manufacturing methods have led to evolution from the first portable calculators that could only perform basic mathematical functions to today's cutting-edge smartphones that can be held and operated in one hand. Global computer chip sales are expected to exceed 400 billion US dollars this year. Given this lucrative market, companies need ways to protect their chip designs from being copied by competitors. [[Summary of the Invention]] [[Means for Solving the Problem]]

[0003] One embodiment of the present invention includes a method for providing a security mechanism for a computer chip using programmable switches. In one embodiment, a security key associated with a plurality of programmable switches provided in an integrated circuit is received. The plurality of programmable switches are configured to make the plurality of programmable switches conductive. Based on the received security key, a reset pulse is applied to a first set of the programmable switches included in the plurality of programmable switches.

[0004] According to one perspective, a method is provided which includes: receiving a security key associated with a plurality of programmable switches provided in an integrated circuit by one or more computer processors; setting the plurality of programmable switches to be conductive by one or more computer processors; and applying a reset pulse to a first set of programmable switches included in the plurality of programmable switches by one or more computer processors based on the received security key.

[0005] According to another perspective, a programmable switch is provided, the programmable switch comprising: a first electrode and a second electrode, wherein the first electrode and the second electrode are separated by a phase change material on a first surface; a first heater on the first side of the phase change material; and a second heater on the second side of the phase change material, wherein the first heater and the second heater are separated by the phase change material on a second surface perpendicular to the first surface and face each other.

[0006] In other words, a method is provided which comprises forming a plurality of non-volatile logic devices in a row with vias and wires during a back-end-of-line manufacturing process of a functional integrated circuit, wherein each non-volatile logic device comprises two electrodes separated by a phase-change material and two heaters positioned on two opposing sides of the phase-change material; forming a lock circuit electrically connected to the two heaters of the plurality of non-volatile logic devices, wherein the lock circuit is electrically isolated from the back-end-of-line wiring of the functional integrated circuit; and changing the state of the phase-change material by passing an electric current through each of the two heaters.

[0007] Preferred embodiments of the present invention are merely illustrative and will be described with reference to the following drawings. [Brief explanation of the drawing]

[0008] [Figure 1] Figure 1 illustrates a cross-section of a computer chip showing possible locations of programmable switches (PS) according to one embodiment of the present invention. [Figure 2] Figure 2 illustrates a three-dimensional (3D) structure of PS according to one embodiment of the present invention. [Figure 3] Figure 3 illustrates a top view of a PS, associated circuitry, and chip circuitry according to one embodiment of the present invention. [Figure 4] Figure 4 illustrates a top view of a PS and the current flow in various circuits according to one embodiment of the present invention. [Figure 5A] Figure 5A illustrates a top view of PS, current flow in various circuits, and formation of amorphous regions according to one embodiment of the present invention. [Figure 5B] Figure 5B illustrates a top view of PS, current flow in various circuits, and the formation of multiple amorphous regions according to one embodiment of the present invention. [Figure 6] Figure 6 illustrates Figure 5A and its associated logical table according to one embodiment of the present invention. [Figure 7A] Figure 7A illustrates a simplified process flow diagram for manufacturing PS according to one embodiment of the present invention. [Figure 7B] Figure 7B illustrates a simplified process flow diagram for manufacturing PS according to one embodiment of the present invention. [Figure 7C] Figure 7C illustrates a simplified process flow diagram for manufacturing PS according to one embodiment of the present invention. [Figure 7D] Figure 7D illustrates a simplified process flow diagram for manufacturing PS according to one embodiment of the present invention. [Figure 8]Figure 8 illustrates a flowchart illustrating a security mechanism for a computer chip using a PS, according to one embodiment of the present invention. [Modes for carrying out the invention]

[0009] Embodiments of the present invention recognize that many companies worldwide manufacture computer chips. In some cases, companies manufacture their own chips, while in others, a first company subcontracts the manufacture or electrical testing of those chips to a second company. Today, the intellectual property contained in such chips can be protected by using a logic lock method. In this specification, additional logic circuits are inserted between existing functional logic circuits. The inputs to these additional logic circuits are treated as keys, and without the keys, the chip will not function as intended. The logic lock method has several drawbacks: (i) valuable chip space (real estate) is occupied by the additional logic circuits; (ii) the additional logic circuits consume power; and (iii) the additional logic circuits may cause delays in the operation of the functional logic circuits. A protection method is needed that can protect the chip and overcome these drawbacks.

[0010] Embodiments of the present invention recognize an approach to providing a security mechanism to a computer chip using programmable switches (PS). In one embodiment, any number of PS are inserted into the standard functional logic circuit of the chip. The PS is composed of a phase change material (PCM). In the crystalline state, the PCM has high conductivity, and the PS is considered "closed." In the amorphous state, the PCM has high resistance (i.e., low conductance), and the PS is considered "open." The state of the PCM can be controlled by proximity heaters manufactured as part of the PS. By requiring that some PS be "closed" and others be "open" for the chip to function properly, a security key can be designed within the chip that does not require extra space (real estate), does not require constant power, and does not affect the performance of the chip. The use of this security key improves integrated circuit (i.e., computer chip) technology by providing a simple protection mechanism to prevent intellectual property from being stolen.

[0011] References in this specification to “one embodiment,” “an embodiment,” “exemplary embodiment,” etc., indicate that while the described embodiments may include certain features, structures, or characteristics, not all embodiments may necessarily include those features, structures, or characteristics. Furthermore, such phrases do not necessarily refer to the same embodiment. Moreover, where certain features, structures, or characteristics are described in relation to an embodiment, it is presented that any influence of such features, structures, or characteristics in relation to other embodiments, whether explicitly stated or not, is within the knowledge of those skilled in the art.

[0012] For the purposes of the following description in this specification, the terms “above,” “right,” “left,” “vertical,” “horizontal,” “top,” “bottom,” “on top,” “below,” and their derivatives should refer to structures and methods disclosed as oriented in the drawings. The terms “superimposed,” “top,” “located on top,” or “located at the top” mean that a first element, e.g., a first structure, is located on a second element, e.g., a second structure, and an intervening element, e.g., an interface structure, may be located between the first and second elements. The term “direct contact” means that a first element, e.g., a first structure, and a second element, e.g., a second structure, are connected at the interface of the two elements without an intermediate conductive, insulating, or semiconductor layer.

[0013] Where used herein, an element referred to as singular may also be considered plural. In the following examples, the word "X" refers to both a single "X" and two or more "X"s, such as "programmable switch," "PS," and "via."

[0014] The present invention will be described in detail below with reference to the accompanying drawings.

[0015] Figure 1 is an exemplary cross-section of a complementary metal-oxide semiconductor (CMOS) computer chip, commonly referred to as 100, according to one embodiment of the present invention. Figure 1 is merely an example of one implementation and does not imply any limitation on other embodiments that may be implemented. Many modifications to the illustrated embodiment can be made by those skilled in the art without departing from the scope of the present invention as described in the claims.

[0016] Generally, CMOS chips are manufactured in two parts: a front-end-of-line (FEOL) and a back-end-of-line (BEOL). Typically, in the FEOL process, each device (e.g., transistors, capacitors, resistors, etc.) is patterned on the silicon base. The BEOL process involves forming the metal interconnect layer of the chip. The BEOL includes contacts, an insulating layer, metal levels, and bonding sites for connecting the chip to the package. In a preferred embodiment of the present invention, the PS is manufactured in the BEOL.

[0017] In one embodiment, section 100 comprises an M3 metal 102 (where M3 refers to layer 4 of the chip), a dielectric 104, an M3 / M2 via 106, a dielectric 108, a programmable switch (PS) 110, an M2 metal 112, an M2 / M1 via 114, a dielectric 116, a dielectric 118, an M1 metal 120, an M1 / FET via 122 (where FET is a field-effect transistor), an FET gate 124, an FET source 126A, an FET drain 126B, and silicon 128. The combination of the FET source 126A, the FET gate 124, and the FET drain 126B constitutes one FET. In one embodiment, the balance of structures constituting section 100, other than the PS 110, is included in currently manufactured computer chips.

[0018] In one embodiment, the FET gate 124 is disposed on a base layer made of silicon 128. The FET source 126A and the FET drain 126B are doped regions in the silicon 128 and are adjacent to the FET gate 124. A dielectric 118 is deposited over the silicon and the FET. A hole (i.e., a via) is formed in the dielectric 118 and filled with tungsten or another suitable material to form the M1 / FET via 122 (i.e., the interconnection between the M1 metal 120 and one of the FET source 126A and the FET drain 126B). Chemical mechanical planarization (CMP) is used to remove excess material of the M1 / FET via 122 on the dielectric 118. A dielectric 116 is deposited over the device and patterned to form a trench in which the M1 metal 120 is deposited, thereby forming the overall first-layer circuit. CMP is then used to remove excess M1 metal 120 on the dielectric 116. This process is repeated for the remaining metal layers of the structure. A discussion of how the PS 110 is manufactured is provided later in this specification in the discussion of FIGS. 7A to 7D.

[0019] The M3 metal 102, M2 metal 112, and M1 metal 120 are generally made of one of copper and aluminum. The M3 / M2 via 106, M2 / M1 via 114, and M1 / FET via 122 are respectively holes in the dielectric 108, dielectric 116, and dielectric 118, and are filled with tungsten to provide electrical connection between layers. The dielectric 108, dielectric 116, and dielectric 118 are materials that provide electrical insulation between parts of the structure. Silicon dioxide (SiO2) or any material with a low dielectric constant is generally used as a dielectric material in chip manufacturing. The FET source 126A, FET gate 124, and FET drain 126B are three terminals constituting a FET device, which is a transistor that uses an electric field to control the flow of current in a channel connecting the FET source 126A and the FET drain 126B. FETs are generally formed of silicon-based channels, but other materials, for example, silicon germanium alloys and III-V semiconductors, can also be used.

[0020] Figure 2 illustrates a three-dimensional structure of a PS, generally designated 200, in accordance with one embodiment of the present invention. Figure 2 is merely an illustration of one implementation, and does not imply any limitation with respect to different embodiments that may be implemented. Many modifications to the illustrated embodiments can be made by those skilled in the art without departing from the scope of the present invention as set forth in the claims.

[0021] In one embodiment, the PS 200 comprises a phase change material (PCM) 202, heaters 204 and 205, a spacer sidewall 206, and a hard mask 208. The PCM 202 can be in one or two of the following states: a crystalline state and an amorphous state. In the crystalline state, the PCM 202 is conductive. In the amorphous state, the PCM 202 is nonconductive. Examples of PCM 202 include, but are not limited to, germanium antimony telluride (Ge2Sb2Te5), germanium telluride (GeTe), antimony telluride (Sb2Te3), GaSb (gallium antimony), etc. In this embodiment, germanium telluride is used for the PCM 202. Heaters 204 and 205 are resistance heaters (i.e., devices that generate heat when current flows through them). For example, heaters 204 and 205 can be made of tantalum nitride (TaN). Heaters 204 and 205 face each other on opposite sides of the PCM 202, as shown in Figure 2. Generally, the surfaces containing heaters 204 and 205 are perpendicular to the main surface of the PCM 202. Heaters 204 and 205 are electrically insulated from the PCM 202 and thermally coupled to the PCM 202 by spacer sidewalls 206. Thus, spacer sidewalls 206 are both electrical insulators and thermal conductors. Examples of spacer sidewalls 206 include, but are not limited to, aluminum nitride (AlN) and hexagonal boron nitride (hex-BN). In this embodiment, aluminum nitride is used for spacer sidewalls 206. A hard mask 208 is used to define (i.e., etch) the PCM 202 during the manufacturing process. The hard mask 208 also serves as a “stop layer” during a chemical mechanical planarization (CMP) process, which is carried out so that the heaters 204, 205, spacer sidewalls 206, and the top of the hard mask 208 are all at roughly the same level (i.e., on the same plane).

[0022] Figure 3 illustrates a top view of a PS, commonly referred to as 300, according to one embodiment of the present invention. Figure 3 is merely an example of one implementation and does not imply any limitation on other embodiments that may be implemented. Many modifications to the illustrated embodiment can be made by those skilled in the art without departing from the scope of the present invention as described in the claims.

[0023] In one embodiment, the PS 300 comprises the PCM 202, heater 204, heater 205, and spacer sidewall 206 as previously described. The PS 300 also includes the following new features: PS input 302A, PS output 302B (these are two electrodes separated by the PCM 202), heater 204 input 304A, heater 204 output 304B, heater 205 input 305A, and heater 205 output 305B. PS input 302A, PS output 302B, heater 204 input 304A, heater 204 output 304B, heater 205 input 305A, and heater 205 output 305B are current-carrying wiring (i.e., electrode) inputs. Note that the input and output currents do not have inherent directionality. However, in this embodiment, current flows to heater 204 along heater 204 input 304A and flows out of heater 204 along heater 204 output 304B. Similarly, in one embodiment, current flows to heater 205 along heater 205 input 305A and flows out of heater 205 along heater 205 output 305B. The conductivity of PS 202 (i.e., switching open or closed), i.e., controlling the current flowing through PS 202, is controlled by how heaters 204 and 205 are heated or cooled, or heated and cooled. PS input 302A and PS output 302B are part of the functional logic circuit of the chip. Heater 204 input 304A, heater 204 output 304B, heater 205 input 305A, and heater 205 output 305B are dedicated circuits for heaters 204 and 205, and these circuits are independent of the functional logic circuit of the device. The PS input 302A and PS output 302B can be any of the M1 metal 120, M2 metal 112, M3 metal 102, M1 / FET via 122, M2 / M1 via 114, and M3 / M2 via 106 shown in Figure 1.

[0024] Figure 4 illustrates a PS commonly referred to as 400 and shows a top view of PS 300 of Figure 3, illustrating the current flow in the PS and the current flow in the functional logic circuit comprising PS 300, according to one embodiment of the present invention. Figure 4 is merely an example of one implementation and does not imply any limitation on other embodiments that may be implemented. Many modifications to the illustrated embodiments can be made by those skilled in the art without departing from the scope of the present invention as described in the claims.

[0025] In one embodiment, current is carried to the PS 300 along the PS input 302A, as shown by current flow 402A, the current flows through the PCM 202 (i.e., part of the PS 300), and the current flows out of the PCM 202 along the PS output 302B (as shown by current flow 402B). Current flows 402A and 402B are part of the operating current of the computer chip. Here, when the PS 300 is "closed", current can pass through the programmable switch, as shown by current flows 402A and 402B. When the PS 300 is "open", no current flows through either current flow 402A or current flow 402B. As indicated by current flow 404A, current is carried to heater 204 along heater input 304A (therefore heater 204 heats PCM 202), and the current leaving heater 204 flows along heater output 304B (as indicated by current flow 404B). As indicated by current flow 405A, current is carried to heater 205 along heater input 305A (therefore heater 205 heats PCM 202), and the current out of heater 205 flows along heater output 305B (as indicated by current flow 405B).

[0026] In one embodiment, when PCM 202 is initially in a crystalline state and current flows 404A and 405A are reset pulses, the crystalline region in PCM 202 changes state and becomes amorphous. The reset pulse is a current flow (i.e., a pulse) that raises the temperature of the PCM above its melting point and subsequently quenches the PCM (i.e., a rapid decrease in current resulting in rapid cooling). Rapid cooling does not give the PCM enough time to crystallize, resulting in an amorphous region. This process is also known as "melt-quench". When PCM 202 is initially in an amorphous state and current flows 404A and 405A are set pulses, the amorphous region in PCM 202 changes state and becomes crystalline. The set pulse is a current flow that raises the temperature of the PCM above its crystallization temperature and subsequently slowly decreases the temperature of the PCM. This setting process changes the PCM from an amorphous state to a crystalline state. As one example, in the case of Ge2Sb2Te5 (germanium antimonitorl alloy), the crystallization temperature is approximately 160°C and the melting point is approximately 600°C. As another example, the melting points of antimony telluride (Sb2Te3) and germanium telluride (GeTe) are approximately 620°C and 725°C, respectively.

[0027] Figure 5A illustrates a PS commonly referred to as 500, showing the PS 300 of Figure 3, the associated circuit, and the current flow of Figure 4, as well as the amorphous region of the PCM, according to one embodiment of the present invention. Figure 5A is merely an example of one implementation and does not imply any limitation on other embodiments that may be implemented. Many modifications to the illustrated embodiments can be made by those skilled in the art without departing from the scope of the present invention as described in the claims.

[0028] In one embodiment, when a current flow 404A (reset current pulse) flows through the heater 204 (i.e., the current flows in along the heater 204 input 304A and out along the heater 204 output 304B), the heater 204 emits a thermal pulse, causing the structure of the PCM 202 to begin forming an amorphous region 502 adjacent to the heater 204. Thus, when the heater 204 heats up (caused by the current flow 404A), an amorphous region 502 adjacent to the heater 204 is formed in the PCM 202. Since the amorphous region 502 in the PCM 202 does not extend across the entire width of the PCM 202, the current flow 402A can still flow through the PCM 202 (i.e., a portion of the PCM 202 remains crystalline and therefore highly conductive, and the PS maintains a "closed" state).

[0029] Figure 5B illustrates PS 500 and PS 550, commonly referred to as PS 500, according to one embodiment of the present invention, and showing a second amorphous region. Figure 5B is merely an example of one implementation and does not imply any limitation on other embodiments that may be implemented. Many modifications to the illustrated embodiments can be made by those skilled in the art without departing from the scope of the present invention as described in the claims.

[0030] In one embodiment, the amorphous region 502 is formed as described above. Similarly, the current flow 405A (which is also the reset current pulse) flows through the heater 205 (i.e., the current flows in along the heater 205 input 305A and out along the heater 205 output 305B), providing a thermal pulse to the heater 205 and consequently forming the amorphous region 552 in the PCM 202. Here, the amorphous region 502 and the amorphous region 552 merge, so the current path through the crystalline portion of the PCM 202 is unavailable, and the PS is now "open".

[0031] Therefore, by utilizing set and reset pulses with appropriate programmable switches, each PS can be individually "closed" or "open" according to a security key. When the security key is followed, the chip functions properly. If the security key is not followed precisely, the chip will not function.

[0032] Figure 6 illustrates a PS commonly referred to as 600, which is the PS 400 of Figure 4 having a single amorphous region 552. PS 600 will be used in the discussion of how a PS can function as a logic device implementing the NAND truth table 602 included in Figure 6.

[0033] In one embodiment, the initial state of the PCM 202 is crystalline and therefore conductive. When no current flows through heaters 204 and 205 (i.e., both current flows 404A and 405A are zero), the PCM 202 remains sufficiently crystalline and the PS 600 remains conductive. This is shown in NAND truth table 602, where both "input" 404A and "input" 405A are "0" and "output" 402B is "1" (i.e., PS 600 is conductive). When current flow 404A is zero and current flow 405A is a reset pulse, a single amorphous region is formed in the PCM 202. This is shown in NAND truth table 602, where "input" 404A is "0" (i.e., no current) and "input" 405A is "1" (i.e., reset puree). In this situation, an amorphous region 552 is formed adjacent to the heater 205. If the pulse is reversed (i.e., input 404A is 1 and input 405A is 0), the amorphous region 552 will not be formed and will be replaced by an amorphous region PCM 202 adjacent to the heater 204 (not shown in Figure 6 but shown in Figure 5A). In either case, the PS 600 will maintain conductivity as shown in the NAND truth table 602 (i.e., one of inputs 404A and 405A is 0 and the other is 1, resulting in output 402B being 1, indicating that the PS is closed). Finally, when both current flows 404A and 405A are reset pulses, an amorphous region 552 is formed adjacent to heater 205, and another amorphous region is formed adjacent to heater 204 (not shown in Figure 6 but shown in Figure 5B). Due to the merging of the two amorphous regions, PS 600 becomes nonconductive, and PS is open. This is shown in NAND truth table 602 that both "input" 404A and "input" 405A are "1" and the corresponding "output" 402B is "0".

[0034] Figures 7A to 7D illustrate a simplified diagram of the formation of the PS. In Figure 7A, the phase-change material (i.e., PCM 202) is deposited in a gap formed within the existing metal layer (i.e., M2 metal 112). The excess PCM 202 can be removed using photolithography and reactive ion etching (RIE), leaving only the PCM 202. An insulating material, which is both a good thermal conductor and a poor electrical conductor, is blanket-deposited, and the spacer sidewall 206 is formed from the insulating material using the reactive ion etching process. Note that the hard mask 208 used to define the PCM 202 remains on top of the PCM 202.

[0035] In Figure 7B, dielectric 702 (corresponding to dielectric 116 in Figure 1) is the material deposited on top of the PS structure. The upper surface of dielectric 702 is planarized using a chemical mechanical planarization (CMP) process, which results in the upper surface of dielectric 702 and the upper surface of hard mask 208 being in the same plane.

[0036] In Figure 7C, trenches in the dielectric 702 are created on both sides of the PCM 202 by an etching process. This simply involves removing a portion of the dielectric 702 adjacent to the spacer sidewall 206.

[0037] In Figure 7D, heaters 204 and 205 are formed by filling previously created trenches with a resistant material, such as tantalum nitride (TaN). The entire structure is then planarized again using a CMP process, resulting in all top surfaces of the structure's features being identical.

[0038] Figure 8 is a flowchart of workflow 800 illustrating a methodology for a user to "unlock" a computer chip protected by an arbitrary number of programmable switches. In one embodiment, workflow 800 is performed by a user with access to the appropriate security key.

[0039] In one embodiment, in step 802, the user “configures” the device. In other words, the user configures each of several programmable switches (PS) provided in the computer chip (i.e., integrated circuit). In one embodiment, the actual programming of each PS on the chip (there may be many programmable switches) is generally performed by another circuit on the chip. In some embodiments, the circuit may comprise a state machine or microcontroller that receives a security key from the user, as described later, and configures the device via one or more computer processors. In one embodiment, the user configures each PS by using a set pulse for each PS that crystallizes the phase change material (PCM) within the PS to form a conductive structure. In another embodiment, the user heats the entire chip to a temperature higher than the crystallization temperature of the PCM and then cools the chip to ambient room temperature. This process configures all PS to be conductive. After the device (i.e., computer chip) is configured, all PS are conductive, but the chip is non-functional. Furthermore, a "configured" programmable switch is conductive and allows current to flow, and is therefore considered "closed" (similar to a light switch where the light turns on when "closed" (i.e., in the "on" position) and turns off when "open" (i.e., in the "off" position)). For example, in the case of a chip with 300 PSs, all 300 would be "configured" to be closed.

[0040] In one embodiment, the user receives a security key in step 804. In other words, the user receives or obtains a security key associated with a computer chip. According to one embodiment, the security key defines which PSs should be "open" and which should be "closed" for the chip to function correctly. The security key is provided by a chip designer, which may also be a chip manufacturer. In this example, the security key states that for the device to function, a first set of 300 PSs should remain "closed," while a second set of 300 PSs should be "open" (i.e., made non-conductive).

[0041] According to one embodiment, in step 806, the user identifies a programmable switch that must be "open" for the device to function. In other words, the user identifies from the security key a list of PSs that must be reset to be non-conductive by changing the state of the PCM from crystalline to amorphous. This identification can be done by the user entering the security key, and the microcontroller identifies the various PSs and further programs the PSs as needed. In an example, of 300 programmable switches (i.e., "1" to "300"), the PSs associated with odd numbers must be "open" (i.e., PS numbers "1", "3", "5", ..., "297", and "299").

[0042] In one embodiment, in step 808, the user identifies a programmable switch that must be "closed" for the device to function. In other words, the user identifies from the security key a list of PSs that must be set to be conductive by changing the state of the PCM from amorphous to crystalline. Here, since the device was "set" in a previous step, no action is required from the user regarding this list of PSs that must be "set". It would be important to know which PSs should be "set" (i.e., closed) when the initial state of each PS is unknown and the user has not performed the "set" step for the device. In the example, of the 300 programmable switches (i.e., "1" to "300"), the PSs associated with even numbers need to be "closed" (i.e., PS numbers "2", "4", "6", ..., "298", and "300"). Generally, the positions of the programmable switches would be completely random rather than "odd" and "even" as used in this example.

[0043] According to one embodiment, in step 810, a reset pulse is applied to the appropriate programmable switch. In other words, in response to identifying a set of PSs that must be "open" for the device to function, the user applies a reset pulse to each of the PSs. In one embodiment, the reset pulse changes the state of the PCM from crystalline (and conductive) to amorphous (and non-conductive). Once completed, each of the PSs is "open". In the example, the reset pulse is applied to each of the odd-numbered PSs.

[0044] In one embodiment, in step 812, the pin associated with each PS is disconnected using an electronic fuse. In other words, each PS is electrically isolated from its associated input pin. According to one embodiment, the user provides an input current exceeding a threshold that “overloads” an electronic fuse incorporated in the wiring (i.e., circuit) associated with each PS, thus causing an electrical opening in the wiring. As a result of disconnecting the pin from the associated PS, each PS can no longer be “set” or “reset” (i.e., “closed” or “opened”). The device is set to function permanently (assuming the PS is “opened” or “closed” according to the security key). According to another embodiment, the use of an electronic fuse is optional (i.e., it is not necessary to include an electronic fuse in the wiring associated with the PS), and the operation of the programmable switch is not affected by not including the electronic fuse. In an example, the user overloads each of the electronic fuses associated with each of the 300 PS by inputting a current exceeding a threshold.

[0045] In one embodiment, power is removed from all programmable switches in step 814. In other words, if all PSs are set to "open" or "closed" according to the security key, and the electronic fuse is open for all PSs (if equipped in such a way), then no power is required for the PSs to function, and therefore power is removed from the devices (i.e., the PSs will remain in that state until a set pulse is applied for sufficiently amorphous PCMs, or a reset pulse for sufficiently crystalline PCMs).

[0046] Several advantages are offered by using a phase-change material to implement the programmable switch. Firstly, the PS can be opened and closed multiple times according to the security key, unless the electronic fuse is opened. For example, a chip manufacturer may manufacture a chip, electrically test the chip in-house, disable the chip, send the chip for visual inspection by a non-trusted company, receive the chip, activate the chip, electrically test it again in-house, disable the chip, send the chip to another non-trusted company for identification marking, receive the chip, activate the chip, and then continue packaging the chip into a module.

[0047] A second advantage of using PCM is that it does not require electrical probing of the chip to disable it. Probing can also cause unintended damage to the chip, so simply annealing the chip at a temperature above the crystallization temperature of the PCM causes all the PS to crystallize and become conductive, rendering the chip unusable.

[0048] A third advantage of PS is that any level of metal can be placed within the chip. Figure 1 shows PS insertions in M3 metal 102, M2 metal 112, M1 metal 120, M3 / M2 via 106, M2 / M1 via 114, and M1 / FET via 122. Furthermore, PS requires less chip "space" (real estate) compared to the area required by logic clocks, which require additional logic circuits to be inserted between existing logic circuits.

[0049] The fourth advantage of PS is that, once set to "open" or "closed," PS will maintain that state without power. This is because PS forms non-volatile memory (i.e., it does not require a constant power to maintain memory). This differs from current logic clock schemes, which require power to function properly.

[0050] A fifth advantage of PS is that, based on the selection of the PCM, the period during which the PS remains "open" can be controlled (i.e., the lifetime of the integrated circuit can be controlled). This duration is the average time (i.e., operating time or lifetime) it takes for the phase-change material to spontaneously (i.e., naturally) transition (i.e., return) to a more stable crystalline phase after remaining in the amorphous phase. This retention time depends on the ambient temperature and the composition of the material (i.e., the specific PCM selected for the application). This time can be adjusted from at least 10 years to several minutes. The ability to control this retention time allows manufacturers to keep the chip functional for a specific lifespan, after which the chip may cease to function.

[0051] The terms used herein are for the sole purpose of describing specific embodiments and are not intended to limit the invention. Where used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural form unless the context clearly indicates otherwise. Where used herein, the words “comprises” or “comprising” or any combination thereof specify the existence of a described feature, integer, process, operation, element, or component or combination thereof, but it will be further understood that they do not exclude the existence or addition of one or more other features, integers, processes, operations, elements, components, or combinations thereof, or combinations thereof.

[0052] Embodiments of a PCM-based PS that enables and disables a chip, a process for manufacturing a PS, and a method for "unlocking" a disabled chip (these are illustrative and not limiting) have been described, but it should be noted that modifications and variations can be made by those skilled in the art in light of the above teachings. Therefore, it should be understood that modifications can be made to specific embodiments of the disclosed invention that fall within the scope of the invention outlined by the appended claims.

[0053] One embodiment of the present invention is as follows: [Section 1] Receiving security keys associated with multiple programmable switches within an integrated circuit by one or more computer processors; The plurality of programmable switches are configured by one or more computer processors to make the plurality of programmable switches conductive; and, Based on the received security key, one or more computer processors apply reset pulses to a first set of programmable switches included in the plurality of programmable switches. A method that includes this. [Section 2] The method according to item 1, wherein the plurality of programmable switches comprise a set of non-volatile logic devices. [Section 3] The plurality of programmable switches are configured by one or more computer processors to make the plurality of programmable switches conductive. Heating the integrated circuit to a temperature higher than the crystallization temperature of the phase change material contained in the plurality of programmable switches using one or more computer processors; and, The aforementioned integrated circuit is cooled to ambient room temperature by one or more computer processors. The method described in item 1, including the method described in item 1. [Section 4] The method according to item 1, wherein the integrated circuit becomes inoperable by setting the plurality of programmable switches provided within the integrated circuit. [Section 5] The method according to item 1, wherein applying the reset pulse to the first set of programmable switches opens the programmable switches and makes them non-conductive. [Section 6] The aforementioned security key, It consists of the first set of programmable switches and the second set of programmable switches; Define the first set of programmable switches among the plurality of programmable switches that are required to be open for the integrated circuit to function; and, A second set of programmable switches from the plurality of programmable switches that are required to be closed in order for the integrated circuit to function is further defined. The method described in item 1. [Section 7] Disconnecting the pins associated with the plurality of programmable switches by one or more computer processors; and, The power is removed from the aforementioned multiple programmable switches by one or more computer processors. The method described in item 1, further comprising: [Section 8] Disconnecting the pins associated with the aforementioned multiple programmable switches by one or more computer processors is: Inputting a current exceeding a threshold using one or more computer processors overloads the electronic fuses associated with the plurality of programmable switches, thereby creating an electrical open circuit in the wiring associated with the plurality of programmable switches. The method described in paragraph 7, including the method described in paragraph 7. [Section 9] The lifespan of the integrated circuit can be controlled based on the selection of the phase change material constituting the plurality of programmable switches and the ambient temperature at which the integrated circuit will operate; and, The lifetime of the integrated circuit is the operating time of the integrated circuit until the phase-change material naturally returns from an amorphous state to a more stable crystalline state. The method described in item 1. [Section 10] A programmable switch, A first electrode and a second electrode, wherein the first electrode and the second electrode are separated by a phase change material on a first surface; The first heater on the first side of the phase change material; and, The second heater on the second side of the phase change material, wherein the first heater and the second heater are separated by the phase change material on a second surface perpendicular to the first surface and face each other. The programmable switch is provided with the above. [Section 11] The programmable switch according to item 10, wherein applying an electric current to both the first heater and the second heater causes a change in the state of the phase-change material. [Section 12] The programmable switch according to claim 11, wherein the applied current is a reset pulse, and the change of the phase-change material to the state is from crystalline to amorphous. [Section 13] The programmable switch according to item 11, wherein the applied current is a set pulse, and the change in the state of the phase-change material is from amorphous to crystalline. [Section 14] The reset pulse, A current pulse is used to raise the temperature of the phase change material to a temperature higher than its melting point, followed by a first cooling process that forms an amorphous region in the phase change material; and, Known as a melt quench, The programmable switch described in item 12. [Section 15] The programmable switch according to item 13, wherein the set pulse is a current pulse that raises the temperature of the phase change material above its crystallization temperature, and thereafter a second cooling is performed to produce a sufficiently crystallized phase change material. [Section 16] A programmable switch according to paragraph 10, which changes the state of the phase-change material such that the conductivity between the first electrode and the second electrode conforms to a NAND truth table by applying a combination of currents input to the first heater and the second heater. [Section 17] During the backend obline manufacturing process of a functional integrated circuit, a plurality of non-volatile logic devices are formed in a row with vias and wires, wherein each of the plurality of non-volatile logic devices is Two electrodes separated by a phase-change material; and, Two heaters are positioned on two opposing sides of the phase change material. It is equipped with; To form a lock circuit electrically connected to the two heaters of the plurality of non-volatile logic devices, wherein the lock circuit is electrically isolated from the back-end obline wiring of the functional integrated circuit; and, By passing an electric current through each of the two heaters, the state of the phase-change material is changed. A method that includes this. [Section 18] The two electrodes and the wire are made of copper; and, The via is made of tungsten. The method described in paragraph 17, including the method described in paragraph 17. [Section 19] The method according to claim 17, wherein the phase change material is selected from the group consisting of germanium antimony telluride, germanium telluride, antimony telluride, and gallium antimony. [Section 20] The two heaters mentioned above, This is a resistance heater that generates heat based on the current flowing through each of the two heaters; It is electrically insulated from the aforementioned phase change material; and, Thermally bonded to the aforementioned phase change material, The method described in item 17.

Claims

1. A programmable switch, A first electrode and a second electrode, wherein the first electrode and the second electrode are separated by a phase change material on a first surface; A first heater on the first side of the phase change material; and, The second heater on the second side of the phase change material, where the first heater and the second heater are separated by the phase change material on a second surface perpendicular to the first surface and face each other. It is equipped with, A first reset current pulse is passed through the first heater to form a first amorphous region adjacent to the first heater within the phase change material, wherein the first amorphous region is smaller than the width of the phase change material. A second reset current pulse is passed through the second heater to form a second amorphous region adjacent to the second heater within the phase change material, wherein the second amorphous region is smaller than the width of the phase change material. The overlap between the second amorphous region and the first amorphous region blocks the flow of current through the crystalline portion of the phase change material. The first heater and the second heater, A resistance heater that generates heat based on the current flowing through the first heater and the second heater; It is electrically insulated from the aforementioned phase change material; and, Thermally bonded to the aforementioned phase change material, The aforementioned programmable switch.

2. The programmable switch according to claim 1, wherein applying an electric current to both the first heater and the second heater causes a change in the state of the phase-change material.

3. The programmable switch according to claim 2, wherein the applied current is a reset pulse, and the change of the phase-change material to the state is from crystalline to amorphous.

4. The programmable switch according to claim 2, wherein the applied current is a set pulse, and the change in the state of the phase-change material is from amorphous to crystalline.

5. The reset pulse, A current pulse is used to raise the temperature of the phase change material to a temperature higher than its melting point, and thereafter, a first cooling is performed to form an amorphous region in the phase change material; and, Known as a melt quench, The programmable switch according to claim 3.

6. The programmable switch according to claim 4, wherein the set pulse is a current pulse that raises the temperature of the phase change material above its crystallization temperature, and thereafter a second cooling is performed to produce a sufficiently crystallized phase change material.

7. A programmable switch according to claim 1, wherein the state of the phase-change material is changed by applying a combination of currents input to the first heater and the second heater such that the conductivity between the first electrode and the second electrode conforms to a NAND truth table.

8. A method, said method is During the backend obline manufacturing process of a functional integrated circuit, a plurality of non-volatile logic devices are formed in a row with vias and wires, wherein each of the plurality of non-volatile logic devices is Two electrodes separated by a phase-change material; and, A first heater and a second heater are positioned on two opposing sides of the phase change material. It is equipped with; To form a lock circuit electrically connected to the first heater and the second heater of the plurality of non-volatile logic devices, wherein the lock circuit is electrically isolated from the back-end obline wiring of the functional integrated circuit; and, By passing an electric current through the first heater and the second heater, the state of the phase-change material is changed. Includes, By passing the aforementioned current, A first reset current pulse is passed through the first heater to form a first amorphous region adjacent to the first heater within the phase change material, wherein the first amorphous region is smaller than the width of the phase change material, and A second reset current pulse is passed through the second heater to form a second amorphous region adjacent to the second heater within the phase change material, wherein the second amorphous region is smaller than the width of the phase change material. This is carried out by the overlapping of the second amorphous region and the first amorphous region, thereby blocking the flow of current through the crystalline portion of the phase change material. The first heater and the second heater, A resistance heater that generates heat based on the current flowing through the first heater and the second heater; It is electrically insulated from the aforementioned phase change material; and, Thermally bonded to the aforementioned phase change material, The aforementioned method.

9. The two electrodes and the wire are made of copper; and, The via is made of tungsten. The method according to claim 8, including the method described in claim 8.

10. The method according to claim 8, wherein the phase change material is selected from the group consisting of germanium antimony telluride, germanium telluride, antimony telluride, and gallium antimony.

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