Semiconductor devices and semiconductor modules

Abstract

To provide a semiconductor device capable of varying a gate-source parasitic capacitance, as required, without changing a device design.SOLUTION: A semiconductor device 10A includes: a semiconductor substrate 11; a transistor that is formed on the semiconductor substrate 11; an insulation layer 12 provided on the semiconductor substrate 11; a source pad 41 formed on a front surface 12A of the insulation layer 12 and electrically connected to a source electrode; a drain pad formed on the front surface 12A of the insulation layer 12 and electrically connected to a drain electrode; a gate pad formed on the front surface 12A of the insulation layer 12 and connected to a gate electrode; a specified pad 47 formed on the front surface 12A of the insulation layer 12; and a capacitor 60. The capacitor 60 is includes a source-side electrode 61 electrically connected to a source electrode of the transistor, and a specified electrode 62 electrically connected to the specified pad 47 and disposed facing the source-side electrode 61.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device and a semiconductor module. [Background Art]

[0002] Semiconductor devices in which a transistor such as a GaN transistor is formed are generally known (see, for example, Patent Document 1). [Prior Art Documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2017-37967 [Summary of the Invention] [Problem to be Solved by the Invention]

[0004] When a transistor is used for high-speed switching operation, such as in an inverter circuit constituted by a bridge circuit and a non-isolated synchronous rectification converter circuit, the drain-source voltage of the transistor changes steeply. When the drain-source voltage changes steeply, the gate-source voltage of the transistor rises, which may cause erroneous turn-on, that is, so-called self-turn-on, in which an off-state transistor is erroneously turned on.

[0005] Self-turn-on refers to when a steep voltage is applied between the drain and source of an off-state transistor, the gate-drain parasitic capacitance C gd and the gate-source parasitic capacitance C gs expressed as a ratio C gd / C gs , in accordance with which a gate voltage exceeding a threshold voltage is applied to the gate-source parasitic capacitance C gs , thereby turning on the transistor. This is the phenomenon described.

[0006] In a semiconductor device having transistors formed therein, as a method for suppressing self-turn-on, the gate-source parasitic capacitance C gs is increased to make the above ratio C gd / C gs smaller. On the other hand, when the gate-source parasitic capacitance C gs is increased, the amount of charge required for gate driving increases, resulting in a decrease in power supply efficiency. Therefore, it is preferable to selectively apply a semiconductor device designed with an increased gate-source parasitic capacitance C gs to portions where self-turn-on is likely to occur. However, in this case, it is necessary to prepare a plurality of types of semiconductor devices designed to have different gate-source parasitic capacitances C gs . Means for Solving the Problem

[0007] A nitride semiconductor device according to one aspect of the present disclosure includes: a semiconductor substrate; a transistor formed on the semiconductor substrate and including a source electrode, a drain electrode, and a gate electrode; an insulating layer provided on the semiconductor substrate; a source pad formed on a surface of the insulating layer and electrically connected to the source electrode; a drain pad formed on the surface of the insulating layer and electrically connected to the drain electrode; a gate pad formed on the surface of the insulating layer and connected to the gate electrode; a specific pad formed on the surface of the insulating layer; and a capacitor including a source-side electrode electrically connected to the source electrode, and a specific electrode electrically connected to the specific pad and disposed opposite the source-side electrode. Effect of the Invention

[0008] According to the present disclosure, the gate-source parasitic capacitance of the semiconductor device can be changed as needed without changing the design of the semiconductor device. Brief Description of the Drawings

[0009] [Figure 1] FIG. 1 is a schematic plan view of the semiconductor device according to the first embodiment. [Figure 2] Figure 2 is a schematic cross-sectional view of a portion of the semiconductor device cut along the F2-F2 line in Figure 1. [Figure 3] Figure 3 is a detailed, enlarged view of section F3 in Figure 1. [Figure 4] Figure 4 is an enlarged view of section F4 in Figure 3. [Figure 5] Figure 5 is a schematic cross-sectional view of a portion of the semiconductor device cut along the F5-F5 line in Figure 4. [Figure 6] Figure 6 is a schematic cross-sectional view of a portion of the semiconductor device cut along the line F6-F6 in Figure 4. [Figure 7] Figure 7 is a schematic cross-sectional view of a portion of the semiconductor device cut along the line F7-F7 in Figure 1. [Figure 8] Figure 8 is a schematic plan view of the semiconductor module according to the first embodiment. [Figure 9] Figure 9 is a schematic cross-sectional view of a part of the semiconductor device of the second embodiment. [Figure 10] Figure 10 is a schematic plan view of a semiconductor device according to the third embodiment. [Figure 11] Figure 11 is a schematic plan view of the modified semiconductor module. [Figure 12] Figure 12 is a schematic cross-sectional view of a portion of the modified semiconductor device. [Modes for carrying out the invention]

[0010] Hereinafter, embodiments of semiconductor devices and semiconductor modules in this disclosure will be described with reference to the attached drawings. For the sake of simplicity and clarity, the components shown in the drawings are not necessarily depicted to a consistent scale. Furthermore, hatching lines may be omitted in cross-sectional views for easier understanding. The accompanying drawings are merely illustrative of embodiments of this disclosure and should not be considered limiting.

[0011] The following detailed description includes apparatus, systems, and methods that embody exemplary embodiments of the Disclosure. This detailed description is for illustrative purposes only and is not intended to limit the embodiments of the Disclosure or the application and use of such embodiments.

[0012] <First Embodiment> The configuration of the semiconductor device and semiconductor module of the first embodiment will be described with reference to Figures 1 to 8.

[0013] [Material structure of semiconductor devices] Figure 1 shows a schematic planar structure of the semiconductor device 10A according to the first embodiment. In this disclosure, the term "planar view" refers to viewing the semiconductor device 10A in the Z direction of the mutually orthogonal XYZ axes shown in Figure 1. For convenience, in the semiconductor device 10A shown in Figure 1, the +Z direction is defined as up, the -Z direction as down, the +X direction as right, and the -X direction as left.

[0014] As shown in Figure 1, the semiconductor device 10A includes a semiconductor substrate 11, a transistor T (not shown) formed on the semiconductor substrate 11, and an insulating layer 12 provided on the semiconductor substrate 11. For example, a silicon (Si) substrate can be used as the semiconductor substrate 11. Alternatively, a silicon carbide (SiC) substrate, a gallium nitride (GaN) substrate, or a sapphire substrate can be used instead of the Si substrate. The thickness of the semiconductor substrate 11 can be, for example, 200 μm or more and 1500 μm or less.

[0015] In the following explanation, unless explicitly stated otherwise, thickness refers to the dimension along the Z direction in Figure 1. Hereafter, unless explicitly stated otherwise, "plan view" refers to viewing the semiconductor substrate 11 from above in the thickness direction, that is, viewing the semiconductor device 10A from above along the Z axis.

[0016] The insulating layer 12 may be made of a material containing, for example, one of silicon nitride (SiN), silicon dioxide (SiO2), silicon oxynitride (SiON), alumina (Al2O3), AlN, and aluminum oxynitride (AlON). In one example, the insulating layer 12 is formed of a material containing SiN.

[0017] The semiconductor device 10A includes, in a plan view, an active region A1 located in the central part of the semiconductor substrate 11, and a frame-shaped peripheral region A2 located on the outer edge of the semiconductor substrate 11 that surrounds the active region A1. The active region A1 is the region where the transistor T is formed, and the peripheral region A2 is the region where the transistor T is not formed.

[0018] [Transistor Details] Figure 2 is a cross-sectional view showing an example of the schematic cross-sectional structure of a transistor T obtained by cutting the semiconductor device 10A along the cross-sectional indicator line F2-F2 in Figure 1. Note that some hatching lines have been omitted for clarity of the drawing. Also, the insulating layer 12 placed on top of the transistor T is not shown.

[0019] As shown in Figure 2, transistor T is a high electron mobility transistor (HEMT) using a nitride semiconductor. Transistor T includes a buffer layer 14 formed on a semiconductor substrate 11, an electron transport layer 16 formed on the buffer layer 14, and an electron supply layer 18 formed on the electron transport layer 16.

[0020] The buffer layer 14 may be made of any material that can suppress wafer warping and cracking caused by mismatch in thermal expansion coefficients between the semiconductor substrate 11 and the electron transport layer 16. The buffer layer 14 may also include one or more nitride semiconductor layers. For example, the buffer layer 14 may include at least one of the following: an aluminum nitride (AlN) layer, an aluminum gallium nitride (AlGaN) layer, and a grated AlGaN layer having a different aluminum (Al) composition. For example, the buffer layer 14 may be made of a single film of AlN, a single film of AlGaN, a film having an AlGaN / GaN superlattice structure, a film having an AlN / AlGaN superlattice structure, or a film having an AlN / GaN superlattice structure.

[0021] In one example, the buffer layer 14 may include a first buffer layer which is an AlN layer formed on the semiconductor substrate 11, and a second buffer layer which is an AlGaN layer formed on the AlN layer (first buffer layer). The first buffer layer may be, for example, an AlN layer with a thickness of 200 nm, and the second buffer layer may be, for example, a grated AlGaN layer with a thickness of 300 nm. In order to suppress leakage current in the buffer layer 14, impurities may be introduced into a part of the buffer layer 14 to make the area other than the surface region of the buffer layer 14 semi-insulating. In this case, the impurities may be, for example, carbon (C) or iron (Fe). The impurity concentration may be, for example, 4 × 10⁻⁶. 16 cm -3 This can be done.

[0022] The electron transport layer 16 is made of a nitride semiconductor. The electron transport layer 16 may be, for example, a GaN layer. The thickness of the electron transport layer 16 can be, for example, 0.5 μm or more and 2 μm or less. In order to suppress leakage current in the electron transport layer 16, an impurity may be introduced into a part of the electron transport layer 16 to make the area other than the surface layer of the electron transport layer 16 semi-insulating. In this case, the impurity is, for example, C. The concentration of the impurity is, for example, 4 × 10⁻⁶. 16 cm -3It can be as described above. That is, the electron transit layer 16 can include a plurality of GaN layers with different impurity concentrations, for example, a C-doped GaN layer and an undoped GaN layer. In this case, the C-doped GaN layer is formed on the buffer layer 14. The C-doped GaN layer can have a thickness of 0.5 μm or more and 2 μm or less. The C concentration in the C-doped GaN layer is 5×10 17 cm -3 or more and 9×10 19 cm -3 or less. The undoped GaN layer is formed on the C-doped GaN layer. The undoped GaN layer can have a thickness of 0.05 μm or more and 0.4 μm or less. The undoped GaN layer is in contact with the electron supply layer 18. In one example, the electron transit layer 16 includes a C-doped GaN layer with a thickness of 0.4 μm and an undoped GaN layer with a thickness of 0.4 μm. The C concentration in the C-doped GaN layer is about 2×10 19 cm -3 .

[0023] The electron supply layer 18 has a larger band gap than the electron transit layer 16. The electron supply layer 18 may be, for example, an AlGaN layer. In nitride semiconductors, the higher the Al composition, the larger the band gap. Therefore, the electron supply layer 18 which is an AlGaN layer has a larger band gap than the electron transit layer 16 which is a GaN layer. In one example, the electron supply layer 18 is Al x Ga 1-x N. In other words, the electron supply layer 18 can be said to be an Al x Ga 1-x N layer, where x satisfies 0 < x < 0.4, more preferably 0.1 < x < 0.3. The electron supply layer 18 can have a thickness of, for example, 5 nm or more and 20 nm or less.

[0024] The electron travel layer 16 and the electron supply layer 18 have different lattice constants in the bulk region. Therefore, the junction between the electron travel layer 16 and the electron supply layer 18 is a lattice-mismatched junction. Due to the spontaneous polarization of the electron travel layer 16 and the electron supply layer 18, and the piezoelectric polarization caused by the compressive stress applied to the heterojunction portion of the electron travel layer 16, the energy level of the conduction band of the electron travel layer 16 near the heterojunction interface between the electron travel layer 16 and the electron supply layer 18 becomes lower than the Fermi level. As a result, a two-dimensional electron gas (2DEG) 20 spreads in the electron travel layer 16 at a position close to the heterojunction interface between the electron travel layer 16 and the electron supply layer 18 (for example, at a distance of about several nanometers from the interface).

[0025] The electron supply layer 18 has a larger band gap than the electron travel layer 16. The electron supply layer 18 may be, for example, an AlGaN layer. In nitride semiconductors, the higher the Al composition, the larger the band gap. Therefore, the electron supply layer 18 which is an AlGaN layer has a larger band gap than the electron travel layer 16 which is a GaN layer. In one example, the electron supply layer 18 is Al x Ga 1-x N. In other words, the electron supply layer 18 is an Al x Ga 1-x N layer, where x satisfies 0 < x < 0.4, more preferably 0.1 < x < 0.3. The electron supply layer 18 may have a thickness of, for example, not less than 5 nm and not more than 20 nm.

[0026] The transistor T further includes a gate layer 22 formed on the electron supply layer 18, a gate electrode 24 formed on the gate layer 22, and an insulating layer 26 covering the electron supply layer 18, the gate layer 22, and the gate electrode 24. The insulating layer 26 has a source opening 26A and a drain opening 26B provided on both sides of the gate layer 22 in the X direction in plan view. The X direction can also be referred to as the separation direction of the source opening 26A and the drain opening 26B.

[0027] The gate layer 22 has a smaller band gap than the electron supply layer 18 and is composed of a nitride semiconductor containing acceptor-type impurities. The gate layer 22 can be composed of any material having a smaller band gap than the electron supply layer 18, which is, for example, an AlGaN layer. In one example, the gate layer 22 is a GaN layer (p-type GaN layer) doped with acceptor-type impurities. The acceptor-type impurities can include at least one of zinc (Zn), magnesium (Mg), and carbon. The maximum concentration of acceptor-type impurities in the gate layer 22 is, for example, 1 × 10⁻⁶. 18 cm -3 The above 1 x 10 20 cm -3 The following applies:

[0028] As described above, the inclusion of acceptor-type impurities in the gate layer 22 raises the energy levels of the electron transport layer 16 and the electron supply layer 18. Therefore, in the region directly below the gate layer 22, the energy level of the conduction band of the electron transport layer 16 near the heterojunction interface between the electron transport layer 16 and the electron supply layer 18 is approximately the same as or higher than the Fermi level. Consequently, under zero bias conditions where no voltage is applied to the gate electrode 24, 2DEG20 is not formed in the electron transport layer 16 in the region directly below the gate layer 22. On the other hand, 2DEG20 is formed in the electron transport layer 16 in regions other than the region directly below the gate layer 22.

[0029] Thus, the presence of the acceptor-type impurity-doped gate layer 22 depletes 2DEG20 in the region directly beneath the gate layer 22. As a result, normally-off operation of transistor T is achieved. When an appropriate on-voltage is applied to the gate electrode 24, a channel of 2DEG20 is formed in the electron transport layer 16 in the region directly beneath the gate electrode 24, thus enabling conduction between the source and drain.

[0030] The cross-sectional shape of the gate layer 22 is not particularly limited. For example, the gate layer 22 may have a rectangular, trapezoidal, or ridge-shaped cross-section in the XZ plane shown in Figure 1.

[0031] The gate electrode 24 is composed of one or more metal layers. In one example, the gate electrode 24 is a titanium nitride (TiN) layer. Alternatively, the gate electrode 24 may be composed of a first metal layer formed of a Ti-containing material and a second metal layer laminated on the first metal layer and formed of a TiN-containing material. The gate electrode 24 can form a Schottky junction with the gate layer 22. The gate electrode 24 may be formed in a region smaller than the gate layer 22 in a plan view. The gate electrode 24 may have a thickness of, for example, 50 nm to 200 nm.

[0032] The insulating layer 26 is formed on the electron supply layer 18. It can also be said that the insulating layer 26 covers the electron supply layer 18. The insulating layer 26 is a part of the insulating layer 12 provided on the semiconductor substrate 11. In other words, the insulating layer 26 is the portion located in the active region A1 of the insulating layer 12. The insulating layer 26 can also be described as a passivation layer. The insulating layer 26 has a portion that covers the gate layer 22 and the gate electrode 24.

[0033] Each of the source opening 26A and the drain opening 26B is separated from the gate layer 22. The gate layer 22 is located between the source opening 26A and the drain opening 26B. In the X direction, the gate layer 22 is positioned closer to the source opening 26A than to the drain opening 26B. In other words, the distance between the gate layer 22 and the drain opening 26B in the X direction is longer than the distance between the gate layer 22 and the source opening 26A in the X direction.

[0034] The transistor T further includes a source electrode 28 in contact with the electron supply layer 18 through a source opening 26A, and a drain electrode 30 in contact with the electron supply layer 18 through a drain opening 26B.

[0035] The source electrode 28 and the drain electrode 30 are composed of one or more metal layers (for example, Ti, Al, AlCu, TiN, etc.). The source electrode 28 and the drain electrode 30 are in ohmic contact with the 2DEG20 through the source opening 26A and the drain opening 26B, respectively.

[0036] The transistor T further includes a field plate electrode 31 formed on the insulating layer 26. The field plate electrode 31 extends at least partially into the region between the gate layer 22 and the drain electrode 30 in a plan view. The field plate electrode 31 is separated from the drain electrode 30. Thus, the field plate electrode 31 includes, for example, an end 31A located between the drain electrode 30 (drain opening 26B) and the gate layer 22 in a plan view.

[0037] The field plate electrode 31 is electrically connected to the source electrode 28. As an example, in the example shown in Figure 2, the field plate electrode 31 is continuous with the source electrode 28. In this case, the field plate electrode 31 is integrally formed with the source electrode 28. Of the integrally formed electrodes, the source electrode 28 may include at least a portion embedded in the source opening 26A of the insulating layer 26, and the field plate electrode 31 may include the remaining portion. The field plate electrode 31 plays a role in mitigating electric field concentration near the ends of the gate electrode 24 when zero bias is applied and no gate voltage is applied to the gate electrode 24.

[0038] Here, Figure 3 is a detailed enlarged view of section F3 in Figure 1, and Figure 4 is an enlarged view of section F4 in Figure 3. In Figure 4, the portion embedded in the source opening 26A of the source electrode 28, the portion embedded in the drain opening 26B of the drain electrode 30, and the gate electrode 24 are shown as transparent.

[0039] As shown in Figure 4, the source electrode 28, drain electrode 30, and gate electrode 24 each extend along the Y direction in a plan view. More specifically, the cross-sectional structure of the HEMT shown in Figure 2 is formed continuously in the Y direction. Multiple such HEMT structures are formed in both the X and Y directions. Although not shown in Figure 4, both ends of the gate electrode 24 protrude from the active region A1 and are located in the peripheral region A2. Furthermore, as shown in Figures 5 and 6, the electron supply layer 18 is not formed in the peripheral region A2, and an insulating layer 12 is formed in contact with the electron transport layer 16. In Figures 5 and 6, the semiconductor substrate 11, buffer layer 14, and electron transport layer 16 are shown together as a single layer.

[0040] Furthermore, in this embodiment, in a plan view, the Y direction, which is the direction in which the source electrode 28, drain electrode 30, and gate electrode 24 extend, is the first direction, and the X direction, which is perpendicular to the Y direction, is the second direction. Hereafter, the Y direction may be referred to as the first direction, and the X direction as the second direction.

[0041] [Source pad, drain pad, gate pad, and their surrounding structures] As shown in Figure 1, the semiconductor device 10A includes a source pad 41, a drain pad 42, and a gate pad 43, which are formed on the surface 12A of the insulating layer 12. The source pad 41, drain pad 42, and gate pad 43 can be made of any conductive material, for example, including at least one of copper (Cu), aluminum (Al), AlCu alloy, tungsten (W), titanium (Ti), and titanium nitride (TiN).

[0042] The source pad 41 is an electrode pad electrically connected to the source electrode 28 of the transistor T. The source pad 41 is positioned in the peripheral region A2 on the surface 12A of the insulating layer 12, adjacent to the active region A1 on the +X direction side of the active region A1. In a plan view, the source pad 41 is rectangular in shape and extends in the Y direction. The formation area of ​​the source pad 41 in the Y direction is approximately equal to the formation area of ​​the active region A1 in the Y direction.

[0043] The drain pad 42 is an electrode pad electrically connected to the drain electrode 30 of the transistor T. The drain pad 42 is located in the peripheral region A2 on the surface 12A of the insulating layer 12, adjacent to the active region A1 on the -X side of the active region A1. In plan view, the drain pad 42 is rectangular in shape and extends in the Y direction. The formation area of ​​the drain pad 42 in the Y direction is approximately equal to the formation area of ​​the active region A1 in the Y direction. The source pad 41 and the drain pad 42 are arranged separated in the X direction with the active region A1 in between.

[0044] The gate pad 43 is an electrode pad electrically connected to the gate electrode 24 of the transistor T. The gate pad 43 includes a first gate pad 43A and a second gate pad 43B.

[0045] The first gate pad 43A is positioned in the peripheral region A2 on the surface 12A of the insulating layer 12, adjacent to the active region A1 and on the +Y direction side of the active region A1. Furthermore, the first gate pad 43A is positioned closer to the drain pad 42 than to the source pad 41. In the example shown in Figure 1, the first gate pad 43A is positioned on the +Y direction side of the drain pad 42. Note that the first gate pad 43A is spaced apart from the drain pad 42.

[0046] The second gate pad 43B is positioned in the peripheral region A2 on the surface 12A of the insulating layer 12, adjacent to the active region A1 and on the -Y direction side of the active region A1. Furthermore, the second gate pad 43B is positioned closer to the drain pad 42 than to the source pad 41. In the example shown in Figure 1, the second gate pad 43B is positioned on the -Y direction side of the drain pad 42. The second gate pad 43B is spaced apart from the drain pad 42. The first gate pad 43A and the second gate pad 43B are spaced apart in the Y direction, with the drain pad 42 in between.

[0047] The first gate pad 43A and the second gate pad 43B are rectangular in shape in a plan view, extending in the X direction. The first gate pad 43A and the second gate pad 43B protrude more than the drain pad 42 in the -X direction. The first gate pad 43A and the second gate pad 43B protrude more than the drain pad 42 in the +X direction.

[0048] As shown in Figures 1 and 3, the semiconductor device 10A includes a plurality of source wires 44 extending from the source pad 41, a plurality of drain wires 45 extending from the drain pad 42, and gate wires 46 extending from the gate pad 43. In Figure 1, the source wires 44 and drain wires 45 are not shown.

[0049] Each source wire 44 extends in the X direction from the edge of the source pad 41 on the active region A1 side (the edge on the -X direction side) toward the drain pad 42. Each source wire 44 is provided spanning the peripheral region A2 and the active region A1, and the tip of each source wire 44 is located in the active region A1. Multiple source wires 44 are arranged at equal intervals in the Y direction. Each source wire 44 is formed integrally with the source pad 41.

[0050] Each drain wire 45 extends in the X direction from the edge of the drain pad 42 on the active region A1 side (the edge on the +X direction side) toward the source pad 41. Each drain wire 45 is provided spanning the peripheral region A2 and the active region A1, and the tip of each drain wire 45 is located in the active region A1. Multiple drain wires 45 are arranged at equal intervals in the Y direction. In addition, in the active region A1, multiple source wires 44 and multiple drain wires 45 are arranged alternately along the Y direction. Multiple source wires 44 and multiple drain wires 45 are arranged at intervals in the Y direction. Each drain wire 45 is formed integrally with the drain pad 42.

[0051] As shown in Figure 1, the gate wiring 46 includes a first gate wiring 46A and a second gate wiring 46B. The first gate wiring 46A and the second gate wiring 46B connect the first gate pad 43A and the second gate pad 43B. The first gate wiring 46A and the second gate wiring 46B as a whole are arranged in a frame shape surrounding the active region A1, the source pad 41, and the drain pad 42.

[0052] The first gate wiring 46A is positioned in the peripheral region A2 on the surface 12A of the insulating layer 12, on the side of the drain pad 42 in the -X direction. The first gate wiring 46A extends in the Y direction from the portion of the first gate pad 43A that protrudes in the -X direction more than the drain pad 42 toward the portion of the second gate pad 43B that protrudes in the -X direction more than the drain pad 42.

[0053] The second gate wiring 46B extends in a U-shape on the surface 12A of the insulating layer 12, surrounding the active region A1 and the source pad 41. One end of the second gate wiring 46B is connected to the first gate pad 43A, and the other end is connected to the second gate pad 43B. The gate wiring 46 is formed integrally with the gate pad 43.

[0054] Here, Figure 5 is a cross-sectional view showing an example of a schematic cross-sectional structure obtained by cutting the semiconductor device 10A along the cross-sectional indicator line F5-F5 in Figure 4. Figure 6 is a cross-sectional view showing an example of a schematic cross-sectional structure obtained by cutting the semiconductor device 10A along the cross-sectional indicator line F6-F6 in Figure 4. In Figures 4 and 5, the cross-sectional structure of transistor T is shown in a simplified form compared to the cross-sectional structure in Figure 2.

[0055] As shown in Figures 4 and 5, the source wiring 44 has a portion 44A that overlaps with the source electrode 28 in the Z direction. In the portion 44A where the source wiring 44 and the source electrode 28 overlap, vias Vs are formed in the insulating layer 12 located between the source wiring 44 and the source electrode 28, penetrating the insulating layer 12 and electrically connecting the source wiring 44 and the source electrode 28.

[0056] As shown in Figures 4 and 6, the drain wiring 45 has a portion 45A that overlaps with the drain electrode 30 in the Z direction. In the portion 45A where the drain wiring 45 and the drain electrode 30 overlap, a via Vd is formed in the insulating layer 12 located between the drain wiring 45 and the drain electrode 30, penetrating the insulating layer 12 and electrically connecting the drain wiring 45 and the drain electrode 30.

[0057] As shown in Figures 4-6, the outer periphery of the active region A1 is provided with a rectangular frame-shaped first outer periphery guard ring 51 and a second outer periphery guard ring 52 that surround the central part of the active region A1.

[0058] An example of the first outer peripheral guard ring 51 includes a semiconductor layer 51A provided in contact with the electron supply layer 18, a first conductive layer 51B provided in contact with the semiconductor layer 51A, and a second conductive layer 51C embedded in the insulating layer 12 on the first conductive layer 51B. The semiconductor layer 51A is made of, for example, the same material as the gate layer 22. The first conductive layer 51B is made of, for example, the same material as the gate electrode 24. The second conductive layer 51C is made of, for example, the same material as one or both of the source electrode 28 and the drain electrode 30.

[0059] The second outer peripheral guard ring 52 is provided to surround the first outer peripheral guard ring 51, on the outer peripheral side of the active region A1, compared to the first outer peripheral guard ring 51. An example of the second outer peripheral guard ring 52 is a conductive layer provided in contact with the electron supply layer 18. The second outer peripheral guard ring 52 is made of the same material as, for example, one or both of the source electrode 28 and the drain electrode 30.

[0060] Figure 7 is a cross-sectional view showing an example of a schematic cross-sectional structure obtained by cutting the semiconductor device 10A along the cross-sectional indicator line F7-F7 in Figure 1. In Figure 7, the structure of the insulating layer 12 is shown in a simplified manner. As shown in Figure 7, a protective film 48 is provided on the surface 12A of the insulating layer 12. The protective film 48 is formed to cover the surface (top surface) on the side of the semiconductor device 10A where each pad is formed. The protective film 48 also has portions that expose part or all of each pad, including the source pad 41, drain pad 42, gate pad 43, and specific pads 47, which will be described later.

[0061] In the example shown in Figure 7, the protective film 48 covers the second gate wiring 46B located between the specific pad 47 and the source pad 41, and the surface 12A of the insulating layer 12. The protective film 48 may also have portions that partially cover the upper surface of the specific pad 47 and portions that partially cover the upper surface of the source pad 41. The protective film 48 can be made of an insulating material such as polyimide. Note that the protective film 48 is not shown in figures other than Figure 7.

[0062] [Specific pads and capacitors] As shown in Figures 1 and 7, the semiconductor device 10A includes a specific pad 47 formed on the surface 12A of the insulating layer 12 and a capacitor 60. The specific pad 47 and the capacitor 60 are located in the peripheral region A2.

[0063] In the example shown in Figure 1, the specific pad 47 is positioned on the surface 12A of the insulating layer 12, in the peripheral region A2, closer to the source pad 41 than to the gate pad 43. Furthermore, the specific pad 47 is positioned on the surface 12A of the insulating layer 12, with the second gate wiring 46B in between, and is positioned alongside the source pad 41 on the +Y direction side of the source pad 41.

[0064] An example of a specific pad 47 is square in plan view. Alternatively, the specific pad 47 may have a shape other than a square in plan view, such as a rectangle, circle, or ellipse. An example of the width of the specific pad 47 in the X direction is narrower than the width of the source pad 41 in the X direction. The width of the specific pad 47 in the X direction may be wider than the width of the source pad 41 in the X direction, or it may be approximately equal to the width of the source pad 41 in the X direction.

[0065] The capacitor 60 includes a source electrode 61 electrically connected to a source electrode 28, and a specific electrode 62 electrically connected to a specific pad 47 and positioned opposite the source electrode 61. The source electrode 61 is composed of a source pad 41 electrically connected to the source electrode 28. The potential of the source electrode 61 of the capacitor 60 is the source potential.

[0066] As shown in Figure 7, the specific electrode 62 is a third conductive layer L1 formed on the back surface 12B of the insulating layer 12. The insulating layer 12 includes a front surface 12A and a back surface 12B located on the opposite side of the front surface 12A. The front surface 12A of the insulating layer 12 is the surface facing the +Z direction (top surface) of the insulating layer 12, and is the surface located on the opposite side from the semiconductor substrate 11. The back surface 12B of the insulating layer 12 is the surface facing the -Z direction, i.e., the semiconductor substrate 11 side (bottom surface).

[0067] The third conductive layer L1 can be made of any conductive material including at least one of copper (Cu), aluminum (Al), AlCu alloy, tungsten (W), titanium (Ti), and titanium nitride (TiN). One example of the third conductive layer L1 is made of the same material as the gate electrode 24, for example, titanium nitride (TiN). In this case, the third conductive layer L1 can be formed by patterning it simultaneously with the gate electrode 24. Another example of the third conductive layer L1 is made of the same material as one or both of the source electrode 28 and the drain electrode 30, for example, AlCu alloy. In this case, the third conductive layer L1 can be formed by patterning it simultaneously with one or both of the source electrode 28 and the drain electrode 30.

[0068] As shown in Figures 1 and 7, the specific electrode 62 includes a facing portion 62A positioned opposite the source pad 41 with the insulating layer 12 in between, and a connecting portion 62B for connecting the facing portion 62A and the specific pad 47.

[0069] In the example shown in Figure 1, the opposing portion 62A is rectangular in shape in a plan view, extending in the Y direction along the source pad 41. The width of the opposing portion 62A in the X direction is narrower than the width of the source pad 41 in the X direction. The width of the opposing portion 62A in the X direction may also be wider than the width of the source pad 41 in the X direction. In this case, in a plan view, the opposing portion 62A protrudes from the source pad 41 in one or both directions in the X direction. Also, in a plan view, the position of the tip of the opposing portion 62A (the end opposite to the specific pad 47) may be a position that protrudes from the source pad 41 in the Y direction, or it may be a position that overlaps with the source pad 41. Furthermore, the shape of the opposing portion 62A in a plan view does not have to be rectangular.

[0070] The connecting portion 62B extends from the opposing portion 62A in the +Y direction, and a part of it is located below the specific pad 47. The specific electrode 62, including the opposing portion 62A and the connecting portion 62B, is provided so as to straddle both the source pad 41 and the specific pad 47. The connecting portion 62B has a portion that overlaps with the specific pad 47 in the Z direction. In the portion where the connecting portion 62B and the specific pad 47 overlap, a via V1 is formed in the insulating layer 12 located between the connecting portion 62B and the specific pad 47, penetrating the insulating layer 12 and electrically connecting the connecting portion 62B and the specific pad 47.

[0071] The potential of the specific electrode 62 of the capacitor 60 is equal to the potential of the specific pad 47 and changes depending on the voltage applied to the specific pad 47. Furthermore, as will be described in detail later, the specific pad 47 is electrically connected to the gate pad 43 as needed. In this case, the specific electrode 62 is electrically connected to the gate electrode 24 via the specific pad 47 and the gate pad 43. Therefore, the potential of the specific electrode 62 in this case is the gate potential.

[0072] The source electrode 61 includes a portion 41A of the source pad 41 that faces the opposing portion 62A of the specific electrode 62. The opposing portion 41A may be a part of the source pad 41 or the entire source pad 41. If the entire source pad 41 is the opposing portion 41A, the opposing portion 62A of the specific electrode 62 is formed to be the same size as or larger than the source pad 41 in a plan view and is positioned to face the entire source pad 41. Furthermore, as described above, the source pad 41 is electrically connected to the source electrode 28 through vias Vs formed in the insulating layer 12.

[0073] The capacitor 60 includes a portion 62A of a specific electrode 62 formed by a third conductive layer L1, a source-side electrode 61 which is a source pad 41, and an insulating layer 12 interposed between the portion 62A and the source pad 41. The capacitor 60 forms a capacitance between the portion 62A and the source pad 41. Hereinafter, the capacitance of the capacitor 60 will be referred to as the specific capacitance C spIt should be written as follows.

[0074] Specific capacity C sp This can be calculated using the following formula (1). C sp =ε × (S / d) ... (1) In equation (1), S is the area of ​​contact between the source electrode 61 and the specific electrode 62. d is the inter-electrode distance between the source electrode 61 and the specific electrode 62. ε is the relative permittivity of the insulating layer 12 interposed between the source electrode 61 and the specific electrode 62. Therefore, the specific capacitance C sp This can be changed by changing one or more of the opposing area S, the distance between electrodes d, and the relative permittivity ε of the insulating layer 12. The relative permittivity ε of the insulating layer 12 can be changed by changing the type of insulating layer 12.

[0075] The opposing surface area S is, for example, 0.02 mm². 2 More than 0.4mm 2 The following applies: The above-mentioned opposing area S is the area of ​​the portion 41A facing the opposing portion 62A of the specific electrode 62 in the source pad 41 in a plan view. The electrode distance d is, for example, 50 nm or more and 3000 nm or less. In this embodiment, the electrode distance d is equal to the thickness of the insulating layer 12 in the peripheral region A2.

[0076] [Semiconductor Modules] Referring to Figure 8, an example of the configuration of a semiconductor module 100 equipped with a semiconductor device 10A will be described. Figure 8 is a schematic plan view mainly showing the wiring structure of the semiconductor module 100.

[0077] The semiconductor module 100 comprises a die pad 101, a semiconductor device 10A mounted on the die pad 101, and a sealing resin 102 that seals the semiconductor device 10A. The die pad 101 is formed in the shape of a rectangular plate. The die pad 101 is made of, for example, copper (Cu) or a copper-containing alloy. The sealing resin 102 is made of, for example, an insulating resin material such as epoxy resin, acrylic resin, or phenolic resin.

[0078] The semiconductor module 100 includes a source lead 103, a drain lead 104, and a gate lead 105 that are partially exposed from the encapsulating resin 102. The source lead 103 is integrally formed with the die pad 101.

[0079] The semiconductor module 100 also includes a source wire 106, a drain wire 107, and a gate wire 108. The source wire 106 connects the die pad 101 to the source pad 41. The drain wire 107 connects the drain lead 104 to the drain pad 42. The gate wire 108 connects the gate lead 105 to the gate pad 43 (first gate pad 43A). Each of the source wire 106, drain wire 107, and gate wire 108 is sealed with a sealing resin 102.

[0080] Furthermore, the semiconductor module 100 includes a specific wire 109 that connects a specific pad 47 and a gate pad 43 (first gate pad 43A). The specific wire 109 is sealed with a sealing resin 102. Note that the specific wire 109 is an optional component and can be omitted if necessary.

[0081] The source wire 106, drain wire 107, gate wire 108, and specific wire 109 are bonding wires formed by a wire bonding apparatus, and are made of conductors such as gold (Au), Al, or Cu. In this embodiment, each wire is made of the same material (e.g., Cu). However, at least one of the wires may be made of a different material from the others.

[0082] [Effect] Next, the operation of the semiconductor device 10A of the first embodiment will be described. The semiconductor device 10A includes a capacitor 60 which includes a source electrode 61 and a specific electrode 62 which faces the source electrode 61 across an insulating layer 12. The source electrode 61 of the capacitor 60 is a source pad 41 which is electrically connected to a source electrode 28. The specific electrode 62 of the capacitor 60 is electrically connected to a specific pad 47. The semiconductor device 10A which includes the capacitor 60 with the above configuration has a first application form in which the specific pad 47 and the gate pad 43 are not electrically connected, and a second application form in which the specific pad 47 and the gate pad 43 are electrically connected.

[0083] In the first application embodiment, the specific pad 47 and the gate pad 43 are electrically disconnected. More specifically, the specific pad 47 is electrically disconnected from the other electrode pads so that it is at zero potential (floating state). As a result, the potential of the source electrode 61 of the capacitor 60 becomes the source potential, and the potential of the specific electrode 62 of the capacitor 60 becomes zero potential. In this case, the specific capacitance C of the capacitor 60 sp This is the gate-source parasitic capacitance C of the semiconductor device 10A. gs It does not affect the gate-source parasitic capacitance C. gs This represents the capacitance that does not involve capacitor 60, i.e., the original capacitance based on the structure of semiconductor device 10A (hereinafter referred to as the basic capacitance).

[0084] In the second application embodiment, the specific pad 47 and the gate pad 43 are electrically connected by a specific wire 109. As a result, the potential of the source electrode 61 of the capacitor 60 becomes the source potential, and the potential of the specific electrode 62 of the capacitor 60 becomes the gate potential. In this case, the specific capacitance C of the capacitor 60 sp This represents the capacitance generated between the gate electrode 24 and the source electrode 28. In other words, it is the specific capacitance C of the capacitor 60. sp However, the gate-source parasitic capacitance C of semiconductor device 10A gs This is added to the gate-source parasitic capacitance C. gs This refers to the specific capacitance C of capacitor 60. spThis amount makes it larger than the basic capacity. In other words, in the second application form, the gate-source parasitic capacity C gs This becomes larger than the first application form.

[0085] Thus, the semiconductor device 10A has a gate-source parasitic capacitance C gs This can take two different application forms. Therefore, according to the configuration of this embodiment, the gate-source parasitic capacitance of the semiconductor device 10A can be changed by selecting whether or not to connect a specific pad 47 and a gate pad 43 as needed, without changing the design of the semiconductor device 10A.

[0086] Gate-source parasitic capacitance C gs The second application mode, in which the second application mode is relatively large, can be selectively used, for example, in parts where self-turn-on is likely to occur. On the other hand, the gate-source parasitic capacitance C gs The first application form, in which the first application form is relatively small, can be selectively used, for example, in parts where self-turn-on is less likely to occur and improving power efficiency is a priority.

[0087] As an example, consider applying semiconductor device 10A to the high-side switch and low-side switch in a non-isolated synchronous rectifier converter circuit. In a non-isolated synchronous rectifier converter circuit, self-turn-on is more likely to occur in the low-side switch than in the high-side switch. Therefore, as the low-side switch, a gate-source parasitic capacitance C is used. gs A semiconductor device 10A of the second application form, in which the second application form is relatively large, is adopted. And, as a high-side switch, gate-source parasitic capacitance C gs A semiconductor device 10A of the first application form, which has a relatively small size, is adopted.

[0088] As a result, in a low-side switch, the gate-source parasitic capacitance C gs Because this is larger than the normal capacity, the occurrence of self-turn-on can be suppressed. On the other hand, in a high-side switch, the gate-source parasitic capacitance C gsSince this is a normal capacitance, the semiconductor device 10A can perform at its full power efficiency. Thus, the gate-source parasitic capacitance C of the semiconductor device 10A applied to low-side and high-side switches. gs This allows for both differentiating the two components and standardizing the semiconductor device 10A applied to the low-side switch and the high-side switch.

[0089] [effect] The semiconductor device 10A of the first embodiment provides the following advantages. (1-1) The semiconductor device 10A includes a semiconductor substrate 11, a transistor T formed on the semiconductor substrate 11 and including a source electrode 28, a drain electrode 30, and a gate electrode 24, an insulating layer 12 provided on the semiconductor substrate 11, a source pad 41 formed on the surface 12A of the insulating layer 12 and electrically connected to the source electrode 28, a drain pad 42 formed on the surface 12A of the insulating layer 12 and electrically connected to the drain electrode 30, a gate pad 43 formed on the surface 12A of the insulating layer 12 and connected to the gate electrode 24, a specific pad 47 formed on the surface 12A of the insulating layer 12, and a capacitor 60. The capacitor 60 includes a source-side electrode 61 electrically connected to the source electrode 28, and a specific electrode 62 electrically connected to the specific pad 47 and positioned opposite the source-side electrode 61.

[0090] In this configuration, when manufacturing a semiconductor module 100 equipped with the device, it is possible to choose whether or not to connect a specific pad 47 and a gate pad 43. If the specific pad 47 and the gate pad 43 are not connected, the gate-source parasitic capacitance C of the semiconductor device 10A is gs This becomes the basic capacitance. On the other hand, when a specific pad 47 and a gate pad 43 are connected, the gate-source parasitic capacitance C gs This is the capacitance of capacitor 60 (specific capacitance C). sp The capacitance becomes larger than the basic capacitance by the amount of ( ). In this way, the gate-source parasitic capacitance can be changed by the user making the above selection as needed, without changing the design of the semiconductor device 10A.

[0091] And in this configuration, the gate-source parasitic capacitance C gs A large gate-source parasitic capacitance C is desirable for semiconductor devices. gs This configuration is applicable to both semiconductor devices where a small gate-source parasitic capacitance C is desired. gs This is useful when standardizing different semiconductor devices.

[0092] (1-2) The specific electrode 62 includes an opposing portion 62A positioned opposite the source pad 41 with a portion of the insulating layer 12 in between. The source-side electrode 61 is composed of the source pad 41 and includes a portion 41A that faces the opposing portion 62A on the source pad 41.

[0093] This configuration allows the capacitor 60 to be placed between the source pad 41 and the semiconductor substrate 11. Therefore, the increase in size of the semiconductor device 10A caused by the presence of the capacitor 60 can be suppressed. Furthermore, with this configuration, the specific capacitance C of the capacitor 60 can be adjusted by adjusting the formation range of the opposing portion 62A of the specific electrode 62. sp This allows for easy adjustment. Furthermore, this configuration makes it easier to increase the facing area S between the source electrode 61 and the specific electrode 62 compared to a configuration in which the capacitor 60 is provided in a part of the semiconductor device 10A other than the area between the source pad 41 and the semiconductor substrate 11 (see the description of Figure 12 below).

[0094] (1-3) The specific electrode 62 includes a connecting portion 62B for electrically connecting the opposing portion 62A and the specific pad 47. In a plan view, the specific electrode 62 is provided so as to straddle both the source pad 41 and the specific pad 47. With this configuration, the specific electrode 62 of the capacitor 60, which is located between the source pad 41 and the semiconductor substrate 11, can be easily connected to the specific pad 47.

[0095] (1-4) The semiconductor device 10A is provided with a via V1 that penetrates the insulating layer 12 between the connection portion 62B and the specific pad 47, and electrically connects the connection portion 62B and the specific pad 47. With this configuration, the specific electrode 62 of the capacitor 60, which is located between the source pad 41 and the semiconductor substrate 11, can be connected to the specific pad 47 with a simple structure.

[0096] (1-5) The opposing portion 62A is formed on the back surface 12B of the insulating layer 12. With this configuration, the entire thickness of the insulating layer 12 located between the source pad 41 and the semiconductor substrate 11 can be used for the capacitor 60, thus the specific capacitance C of the capacitor 60 sp It can be made larger.

[0097] (1-6) On the surface 12A of the insulating layer 12, the specific pad 47 is positioned closer to the source pad 41 than the gate pad 43. With this configuration, because the specific pad 47 is positioned closer to the source pad 41, it is easier to connect the specific electrode 62 of the capacitor 60, which is located between the source pad 41 and the semiconductor substrate 11, to the specific pad 47. In addition, it is possible to suppress the enlargement and complexity of the shape of the connection portion 62B of the specific electrode 62.

[0098] (1-7) On the surface 12A of the insulating layer 12, the gate pad 43 is positioned closer to the drain pad 42 than to the source pad 41. With this configuration, since the gate pad 43 is positioned away from the source pad 41, space is created in the peripheral region A2 where a specific pad 47 can be placed near the source pad 41. Therefore, it is easy to place the specific pad 47 close to the source pad 41.

[0099] (1-8) The transistor T comprises an electron transport layer 16 made of a nitride semiconductor, an electron supply layer 18 formed on the electron transport layer 16 and made of a nitride semiconductor having a larger band gap than the electron transport layer 16, a gate layer 22 formed on a part of the electron supply layer 18 and made of a nitride semiconductor containing acceptor-type impurities, a gate electrode 24 formed on the gate layer 22, and a source electrode 28 and a drain electrode 30 in contact with the electron supply layer 18. The gate layer 22 is located on the electron supply layer 18 between the source electrode 28 and the drain electrode 30.

[0100] In this configuration, the transistor T (HEMT) has a faster electron movement speed compared to other transistors, making it prone to self-turn-on when applied as a high-speed switching element. Therefore, in the semiconductor device 10A where transistor T is a HEMT, the gate-source parasitic capacitance C is due to the capacitor 60. gs By increasing this value, the effect of suppressing self-turn-on becomes more pronounced.

[0101] (1-9) The semiconductor module 100 comprises a semiconductor device 10A and a sealing resin 102 for sealing the semiconductor device 10A. With this configuration, a semiconductor module 100 comprising the semiconductor device 10A is obtained.

[0102] (1-10) The semiconductor module 100 includes a specific wire 109 that connects a specific pad 47 and a gate pad 43. According to this configuration, the gate-source parasitic capacitance C of the semiconductor device 10A is... gs This can be increased. Therefore, the occurrence of self-turn-on in semiconductor device 10A can be suppressed.

[0103] (1-11) A specific pad 47 of the semiconductor module 100 is electrically disconnected from the gate pad 43. According to this configuration, the gate-source parasitic capacitance C of the semiconductor device 10A is... gsHowever, this is not increased by the capacitor 60 provided in the semiconductor device 10A. Therefore, the semiconductor device 10A can suppress the decrease in power efficiency caused by the capacitor 60.

[0104] <Second Embodiment> The semiconductor device 10B of the second embodiment differs from the first embodiment in the configuration of the specific electrode 62 in the capacitor 60. The other configurations are the same as those of the first embodiment. In the following, the same components as in the first embodiment will not be described, and the components that differ from the first embodiment will be described.

[0105] Figure 9 is a schematic cross-sectional view of a part of the semiconductor device 10B according to the second embodiment. Figure 9 shows a portion corresponding to the portion shown in Figure 7 in the first embodiment. As shown in Figure 9, a third conductive layer L1 is formed on the back surface 12B of the insulating layer 12. A fourth conductive layer L2 is formed inside the insulating layer 12, which is located between the source pad 41 and the semiconductor substrate 11, and is embedded within the insulating layer 12. A via V2 is formed in the insulating layer 12, which is located between the third conductive layer L1 and the fourth conductive layer L2, and penetrates the insulating layer 12 to electrically connect the third conductive layer L1 and the fourth conductive layer L2.

[0106] In this embodiment, the opposing portion 62A of the specific electrode 62 is formed by the fourth conductive layer L2. In other words, the opposing portion 62A is an embedded conductive layer embedded within the insulating layer 12. The connecting portion 62B of the specific electrode 62 is formed by the third conductive layer L1 and via V2.

[0107] Therefore, the capacitor 60 includes a portion 62A of a specific electrode 62 formed by the fourth conductive layer L2, a source-side electrode 61 which is a source pad 41, and an insulating layer 12 interposed between the portion 62A and the source pad 41. In this case, a portion of the insulating layer 12 in the thickness direction, that is, the portion located between the upper surface 12S of the insulating layer 12 and the fourth conductive layer L2, constitutes the capacitor 60. The capacitor 60 then forms capacitance between the portion 62A and the source pad 41.

[0108] Furthermore, the connecting portion 62B formed by the third conductive layer L1 is provided so as to span both the opposing portion 62A formed by the fourth conductive layer L2 and the specific pad 47 in a plan view. The connecting portion 62B is electrically connected to the specific pad 47 via V1, similar to the first embodiment.

[0109] The third conductive layer L1 can be made of any conductive material including at least one of copper (Cu), aluminum (Al), AlCu alloy, tungsten (W), titanium (Ti), and titanium nitride (TiN). An example of the third conductive layer L1 is made of the same material as the gate electrode 24, for example, titanium nitride (TiN). In this case, the third conductive layer L1 can be formed by patterning it simultaneously with the gate electrode 24.

[0110] The fourth conductive layer L2 can be made of any conductive material including, for example, at least one of copper (Cu), aluminum (Al), AlCu alloy, tungsten (W), titanium (Ti), and titanium nitride (TiN). An example of the fourth conductive layer L2 is made of the same material as one or both of the source electrode 28 and the drain electrode 30, for example, an AlCu alloy. In this case, the fourth conductive layer L2 can be formed by patterning one or both of the source electrode 28 and the drain electrode 30 at the same time.

[0111] [effect] As described above, the semiconductor device 10B of the second embodiment provides the same effects as the semiconductor device 10A of the first embodiment, except for the effects described in (1-5). Furthermore, the semiconductor device 10B of the second embodiment provides the following effects.

[0112] (2-1) The opposing portion 62A is an embedded conductive layer (fourth conductive layer L2) embedded within the insulating layer 12. With this configuration, when other layers such as wiring layers are provided on the back surface 12B of the insulating layer 12 located between the source pad 41 and the semiconductor substrate 11, it is possible to place the opposing portion 62A in areas that overlap with other layers in a plan view. Therefore, the design flexibility of the opposing portion 62A is improved.

[0113] <Third Embodiment> The semiconductor device 10C of the third embodiment differs from the first embodiment in the arrangement of the specific pads 47 and the configuration of the specific electrodes 62 in the capacitor 60. The other configurations are the same as those of the first embodiment. Below, the components that are the same as those of the first embodiment will not be described, and the components that differ from those of the first embodiment will be described.

[0114] As shown in Figure 10, the specific pad 47 of the semiconductor device 10C includes a first specific pad 47A and a second specific pad 47B formed on the surface 12A of the insulating layer 12, spaced apart from each other. In one example shown in Figure 10, the first specific pad 47A and the second specific pad 47B are located on the surface 12A of the insulating layer 12 in the peripheral region A2, closer to the source pad 41 than to the gate pad 43.

[0115] On the surface 12A of the insulating layer 12, the first specific pad 47A and the second specific pad 47B are arranged spaced apart in the Y direction in which the source pad 41 extends, and are positioned on either side of the source pad 41. More specifically, the first specific pad 47A is positioned on the surface 12A of the insulating layer 12, with the second gate wiring 46B in between, and is located alongside the source pad 41 on the +Y direction side of the source pad 41. The second specific pad 47B is positioned on the surface 12A of the insulating layer 12, with the second gate wiring 46B in between, and is located alongside the source pad 41 on the -Y direction side of the source pad 41. In the example shown in Figure 10, the first gate pad 43A and the first specific pad 47A of the gate pad 43 are arranged side by side in the X direction. The second gate pad 43B and the second specific pad 47B of the gate pad 43 are arranged side by side in the X direction.

[0116] An example of the first specific pad 47A and the second specific pad 47B is square in shape when viewed from above. The specific pad 47 may also have a shape other than a square when viewed from above, such as a rectangle, circle, or ellipse.

[0117] An example of the width in the X direction of the first specific pad 47A and the second specific pad 47B is that it is narrower than the width in the X direction of the source pad 41. The width in the X direction of the first specific pad 47A and the second specific pad 47B may be wider than the width in the X direction of the source pad 41, or it may be approximately equal to the width in the X direction of the source pad 41. The width in the X direction of the first specific pad 47A and the width in the X direction of the second specific pad 47B may be the same or may be different from each other.

[0118] The capacitor 60 of the semiconductor device 10C includes a first capacitor 60A and a second capacitor 60B. The first capacitor 60A includes a first source-side electrode 61A electrically connected to the source electrode 28, and a first specific electrode 62C electrically connected to the first specific pad 47A and positioned opposite the first source-side electrode 61A. The first source-side electrode 61A is composed of a source pad 41 electrically connected to the source electrode 28. The potential of the first source-side electrode 61A of the first capacitor 60A is the source potential. The first specific electrode 62C may have the same configuration as in the first embodiment, or the same configuration as in the second embodiment.

[0119] The first specific electrode 62C includes a first opposing portion 62A1 positioned opposite the source pad 41 with the insulating layer 12 in between, and a first connecting portion 62B1 for connecting the first opposing portion 62A1 and the first specific pad 47A. In one example shown in Figure 10, the first opposing portion 62A1 is rectangular in shape in a plan view, extending in the Y direction along the source pad 41.

[0120] The first connecting portion 62B1 extends from the first opposing portion 62A1 in the +Y direction, and a part of it is located below the first specific pad 47A. The first specific electrode 62C, including the first opposing portion 62A1 and the first connecting portion 62B1, is provided so as to straddle both the source pad 41 and the first specific pad 47A in a plan view.

[0121] The first connection portion 62B1 has a portion that overlaps with the first specific pad 47A in the Z direction. In the portion where the first connection portion 62B1 and the first specific pad 47A overlap, a via V1 is formed in the insulating layer 12 located between the first connection portion 62B1 and the first specific pad 47A, which penetrates the insulating layer 12 and electrically connects the first connection portion 62B1 and the first specific pad 47A.

[0122] The first source-side electrode 61A includes a first opposing portion 41A1 that faces the first opposing portion 62A1 of the first specific electrode 62C in the source pad 41. The first opposing portion 41A1 is a part of the source pad 41.

[0123] The first capacitor 60A includes a first opposing portion 62A1 of the first specific electrode 62C, a first source-side electrode 61A which is a source pad 41, and an insulating layer 12 interposed between the first opposing portion 62A1 and the source pad 41. The first capacitor 60A forms capacitance between the first opposing portion 62A1 and the source pad 41.

[0124] The second capacitor 60B includes a second source-side electrode 61B electrically connected to the source electrode 28, and a second specific electrode 62D electrically connected to the second specific pad 47B and positioned opposite the second source-side electrode 61B. The second source-side electrode 61B is composed of a source pad 41 electrically connected to the source electrode 28. In other words, the first source-side electrode 61A and the second source-side electrode 61B are composed of a common source pad 41. The potential of the second source-side electrode 61B of the second capacitor 60B is the source potential. The second specific electrode 62D may have the same configuration as in the first embodiment, or the same configuration as in the second embodiment.

[0125] The second specific electrode 62D includes a second opposing portion 62A2 positioned opposite the source pad 41 with the insulating layer 12 in between, and a second connecting portion 62B2 for connecting the second opposing portion 62A2 and the second specific pad 47B. The first opposing portion 62A1 of the first specific electrode 62C and the second opposing portion 62A2 of the second specific electrode 62D are positioned in areas that do not overlap with each other in a plan view.

[0126] The second connecting portion 62B2 extends from the second opposing portion 62A2 in the -Y direction, and a portion of it is located below the second specific pad 47B. The second specific electrode 62D, including the second opposing portion 62A2 and the second connecting portion 62B2, is provided so as to straddle both the source pad 41 and the second specific pad 47B in a plan view.

[0127] The second connection portion 62B2 has a portion that overlaps with the second specific pad 47B in the Z direction. In the portion where the second connection portion 62B2 and the second specific pad 47B overlap, a via V1 is formed in the insulating layer 12 located between the second connection portion 62B2 and the second specific pad 47B, penetrating the insulating layer 12 and electrically connecting the second connection portion 62B2 and the second specific pad 47B.

[0128] The second source-side electrode 61B includes a second opposing portion 41A2 that faces the second opposing portion 62A2 of the second specific electrode 62D in the source pad 41. The second opposing portion 41A2 is a part of the source pad 41. The first opposing portion 41A1 of the first source-side electrode 61A and the second opposing portion 41A2 of the second source-side electrode 61B are arranged in areas that do not overlap with each other in a plan view.

[0129] The second capacitor 60B includes a second opposing portion 62A2 of the second specific electrode 62D, a second source-side electrode 61B which is the source pad 41, and an insulating layer 12 interposed between the second opposing portion 62A2 and the source pad 41. The second capacitor 60B forms a capacitance between the second opposing portion 62A2 and the source pad 41.

[0130] The capacitance of the first capacitor 60A (hereinafter referred to as the first specific capacitance C) sp1 It shall be stated as follows: ) and the capacitance of the second capacitor 60B (hereinafter, the second specific capacitance C sp2 It is stated as follows.) can be set arbitrarily. For example, the first specific capacity C sp1 This is the second specific capacity C sp2 It may be larger than the second specific capacity C sp2 It may be smaller than the second specific capacity C sp2 It may be the same as the first specific capacity C. sp1 The second specific capacity C sp2 If it is greater than, the ratio of these capacities (C sp1 / C sp2 For example, ) is between 2 and 100.

[0131] 1st specific capacity C sp1This can be changed by changing one or more of the following: the opposing area S1 between the first source-side electrode 61A (source pad 41) and the first specific electrode 62C, the inter-electrode distance d1 between the first source-side electrode 61A (source pad 41) and the first specific electrode 62C, and the relative permittivity ε of the insulating layer 12. The second specific capacitance C sp2 This can be changed by changing one or more of the following: the facing area S2 between the second source-side electrode 61B (source pad 41) and the second specific electrode 62D, the inter-electrode distance d2 between the second source-side electrode 61B (source pad 41) and the second specific electrode 62D, and the relative permittivity ε of the insulating layer 12. Therefore, by making the facing areas of the first capacitor 60A and the second capacitor 60B different, making the inter-electrode distances different, and combinations thereof, the first specific capacitance C can be changed. sp1 and the second specific capacity C sp2 The relative size can be adjusted.

[0132] The opposing areas can be made different, for example, by making the shape of the first opposing portion 62A1 of the first specific electrode 62C and the shape of the second opposing portion 62A2 of the second specific electrode 62D different. The distance between the electrodes can be made different, for example, by making the position of the first opposing portion 62A1 and the second opposing portion 62A2 different in the Z direction. For example, the first opposing portion 62A1 is configured to be placed on the back surface 12B of the insulating layer 12 (opposing portion 62A of the first embodiment), and the second opposing portion 62A2 is configured to be embedded in the insulating layer 12 (opposing portion 62A of the second embodiment).

[0133] In one example shown in Figure 10, by making the opposing area of ​​the first capacitor 60A larger than the opposing area of ​​the second capacitor 60B, the first specific capacitance C sp1 The second specific capacity C sp2 It has become larger than that.

[0134] More specifically, the first specific electrode 62C and the second specific electrode 62D are each formed in a rectangular shape extending in the Y direction in a plan view. The first opposing portion 62A1 of the first specific electrode 62C and the second opposing portion 62A2 of the second specific electrode 62D are arranged to be aligned in the X direction in the area overlapping with the source pad 41. The Y-direction length of the first opposing portion 62A1 of the first specific electrode 62C is the same as the Y-direction length of the second opposing portion 62A2 of the second specific electrode 62D.

[0135] The X-direction length of the first opposing portion 62A1 of the first specific electrode 62C is longer than the X-direction length of the second opposing portion 62A2 of the second specific electrode 62D. Therefore, the opposing area between the first specific electrode 62C and the second source-side electrode 61B (source pad 41) is larger than the opposing area between the second specific electrode 62D and the second source-side electrode 61B (source pad 41). As a result, the first specific capacitance C sp1 The second specific capacity C sp2 It is larger than that. The distance between electrodes and the relative permittivity of the insulating layer 12 are the same in the first capacitor 60A and the second capacitor 60B.

[0136] The plan view shapes and arrangements of the first opposing portion 62A1 and the second opposing portion 62A2 are set as appropriate so that the opposing areas of the first specific electrode 62C and the opposing areas of the second specific electrode 62D have an arbitrary relative size relationship. For example, the lengths of the first opposing portion 62A1 and the second opposing portion 62A2 in the X direction may be the same, while their lengths in the Y direction may be different. Also, the plan view shapes of the first opposing portion 62A1 and the second opposing portion 62A2 may be shapes other than rectangles, such as L-shapes. Furthermore, the arrangement of the first opposing portion 62A1 and the second opposing portion 62A2 may be changed; for example, they may be arranged so that they are aligned in the Y direction.

[0137] When manufacturing a semiconductor module 100 equipped with the semiconductor device, the semiconductor device 10C electrically connects specific pads 47 (first specific pad 47A and second specific pad 47B) to gate pads 43 as needed. For example, the first specific pad 47A is connected to the first gate pad 43A by a specific wire 109, and the second specific pad 47B is connected to the second gate pad 43B by a specific wire 109. Alternatively, the first specific pad 47A may be connected to the second gate pad 43B, or the second specific pad 47B may be connected to the first gate pad 43A.

[0138] [Effect] Next, the operation of the semiconductor device 10C of the third embodiment will be described. The semiconductor device 10C, similar to the first embodiment, has a first application form in which the specific pads 47 (first specific pad 47A and second specific pad 47B) and the gate pad 43 are not electrically connected, and a second application form in which the specific pads 47 and the gate pad 43 are electrically connected. Furthermore, the semiconductor device 10C has a second application form in which there are multiple application forms in which the method of connecting the gate pad 43 to the first specific pad 47A and the second specific pad 47B differs.

[0139] Firstly, gate pad 43 is connected to the first specific pad 47A, and gate pad 43 is not connected to the second specific pad 47B. In this case, the gate-source parasitic capacitance C gs This is the first specific capacitance C of the first capacitor 60A. sp1 This will result in a larger capacity than the base capacity.

[0140] Secondly, gate pad 43 and the first specific pad 47A are disconnected, and gate pad 43 and the second specific pad 47B are connected. In this case, the gate-source parasitic capacitance C gs This is the second specific capacitance C of the second capacitor 60B. sp2 This will result in a larger capacity than the base capacity.

[0141] Third, the gate pad 43 is connected to both the first specific pad 47A and the second specific pad 47B. For example, the first gate pad 43A is connected to the first specific pad 47A, and the second gate pad 43B is connected to the second specific pad 47B, respectively. Alternatively, one of the first gate pad 43A and the second gate pad 43B is connected to one of the first specific pad 47A and the second specific pad 47B, and the first specific pad 47A is connected to the second specific pad 47B. In this case, the gate-source parasitic capacitance C gs is the first specific capacitance C of the first capacitor 60A sp1 and the second specific capacitance C of the second capacitor 60B sp2 becomes larger than the basic capacitance by the total sum thereof.

[0142] As described above, the semiconductor device 10C can take a plurality of application modes with different gate-source parasitic capacitances C gs as a second application mode in which the specific pad 47 and the gate pad 43 are electrically connected. Therefore, according to the configuration of the present embodiment, the gate-source parasitic capacitance of the semiconductor device 10C can be changed in multiple steps as needed without changing the design of the semiconductor device 10C. Specifically, by selecting whether or not to connect each of the first specific pad 47A and the second specific pad 47B to the gate pad 43, the gate-source parasitic capacitance of the semiconductor device 10C can be changed in multiple steps.

[0143] [Effect] As described above, according to the semiconductor device 10C of the third embodiment, the same effects as those of the semiconductor device 10A of the first embodiment are obtained. Further, according to the semiconductor device 10C of the third embodiment, the following effects are obtained.

[0144] (3-1) The specific pad 47 includes a first specific pad 47A and a second specific pad 47B that are not electrically connected to each other. The capacitor 60 includes a first capacitor 60A and a second capacitor 60B. The first capacitor 60A comprises a first source-side electrode 61A electrically connected to the source electrode 28 and a first specific electrode 62C electrically connected to the first specific pad 47A and positioned opposite the first source-side electrode 61A. The second capacitor 60B comprises a second source-side electrode 61B electrically connected to the source electrode 28 and a second specific electrode 62D electrically connected to the second specific pad 47B and positioned opposite the second source-side electrode 61B.

[0145] In this configuration, when manufacturing a semiconductor module 100 equipped with the device, it is possible to select whether or not to connect the gate pad 43 to the first specific pad 47A, and whether or not to connect the gate pad 43 to the second specific pad 47B. As a result, as a second application form in which the gate pad 43 and specific pads 47 are connected, there are three possible configurations: one in which only the first specific pad 47A is connected to the gate pad 43, one in which only the second specific pad 47B is connected to the gate pad 43, and one in which both the first specific pad 47A and the second specific pad 47B are connected to the gate pad 43. This allows the user to make the above selections as needed without changing the design of the semiconductor device 10C, thereby enabling multi-stage changes in gate-source parasitic capacitance, including a second application form in which the specific pads 47 and the gate pad 43 are electrically unconnected. Thus, finer adjustment of gate-source parasitic capacitance becomes possible.

[0146] (3-2) The first specific electrode 62C includes a first opposing portion 62A1 positioned opposite the source pad 41 with a portion of the insulating layer 12 in between. The first source-side electrode 61A is formed by the source pad 41 and includes a first opposed portion 41A1 on the source pad 41 that faces the first opposing portion 62A1. The second specific electrode 62D includes a second opposing portion 62A2 positioned opposite the source pad 41 with a portion of the insulating layer 12 in between. The second source-side electrode 61B is formed by the source pad 41 and includes a second opposed portion 41A2 on the source pad 41 that faces the second opposing portion 62A2.

[0147] This configuration allows the first capacitor 60A and the second capacitor 60B to be placed between the source pad 41 and the semiconductor substrate 11. Therefore, the increase in size of the semiconductor device 10C caused by the provision of the first capacitor 60A and the second capacitor 60B can be suppressed.

[0148] (3-3) Capacitance of the first capacitor 60A (First specific capacitance C sp1 ) is the capacitance of the second capacitor 60B (second specific capacitance C sp2 It is larger than ).

[0149] This configuration allows for different gate-source parasitic capacitances between a configuration where only the first specific pad 47A is connected to the gate pad 43 and a configuration where only the second specific pad 47B is connected to the gate pad 43. Therefore, the gate-source parasitic capacitance of the semiconductor device 10C can be varied in multiple stages.

[0150] (3-4) The area of ​​contact between the first source electrode 61A and the first specific electrode 62C is larger than the area of ​​contact between the second source electrode 61B and the second specific electrode 62D. With this configuration, the capacitance of the first capacitor 60A can be made larger than that of the second capacitor 60B by simply adjusting the planar shape of the first facing portion 62A1 of the first specific electrode 62C and the second facing portion 62A2 of the second specific electrode 62D.

[0151] (3-5) On the surface 12A of the insulating layer 12, the first specific pad 47A and the second specific pad 47B are arranged with the source pad 41 in between.

[0152] This configuration facilitates the connection between the first specific electrode 62C and the first specific pad 47A, and between the second specific electrode 62D and the second specific pad 47B. Furthermore, it prevents the first connection portion 62B1 of the first specific electrode 62C and the second connection portion 62B2 of the second specific electrode 62D from becoming larger and more complex.

[0153] (3-6) The first specific pad 47A and the second specific pad 47B are arranged at a distance from each other in the Y direction in which the source pad 41 extends, in a plan view. The gate pad 43 includes, in a plan view, a first gate pad 43A arranged alongside the first specific pad 47A in the X direction, and a second gate pad 43B arranged alongside the second specific pad 47B in the X direction.

[0154] With this configuration, two gate pads 43 are provided, and these two gate pads 43 (first gate pad 43A and second gate pad 43B) can be positioned close to the first specific pad 47A and the second specific pad 47B, respectively. Therefore, when connecting the gate pads 43 and specific pads 47 using a specific wire 109, by adopting a method of connecting the first gate pad 43A to the first specific pad 47A and the second gate pad 43B to the second specific pad 47B, the specific wire 109 connecting the gate pads 43 and specific pads 47 can be shortened.

[0155] <Example of changes> Each of the above embodiments can be modified as follows, for example. Each of the above embodiments and the following modifications can be combined with each other as long as no technical inconsistencies arise. In the following modifications, parts common to each of the above embodiments are denoted by the same reference numerals as in the above embodiments, and their descriptions are omitted.

[0156] The configuration for connecting the specific pad 47 and the gate pad 43 is not limited to a configuration using the specific wire 109. For example, the semiconductor module 100 may have a configuration that does not include the specific wire 109 connecting the specific pad 47 and the gate pad 43, such as a chip-size package. Figure 11 shows an example of a configuration in which the specific pad 47 and the gate pad 43 are connected without using the specific wire 109.

[0157] Figure 11 is a plan view, seen from the mounting board 200 side, showing a semiconductor device 10A surface-mounted on a mounting board 200 such as a printed circuit board. In Figure 11, the mounting board 200 is shown with a dashed line so that the semiconductor device 10A is visible through it.

[0158] The mounting substrate 200 has a mounting surface on which the semiconductor device 10A is mounted. A first substrate wiring 201, a second substrate wiring 202, and a third substrate wiring 203 are formed on the mounting surface of the mounting substrate 200. The first substrate wiring 201 has a portion located on the mounting surface of the mounting substrate 200 that faces the source pad 41 of the semiconductor device 10A. The second substrate wiring 202 has a portion located on the mounting surface of the mounting substrate 200 that faces the drain pad 42 of the semiconductor device 10A.

[0159] The third substrate wiring 203 has a first portion 203A located on the mounting surface of the mounting substrate 200, facing the first gate pad 43A of the semiconductor device 10A, and a second portion 203B located facing the specific pad 47. In this case, the specific pad 47 and the first gate pad 43A (gate pad 43) are electrically connected through the third substrate wiring 203 provided on the mounting substrate 200 side.

[0160] In the semiconductor device 10B of the second embodiment, the connection portion 62B of the specific electrode 62 may be the same fourth conductive layer L2 as the opposing portion 62A. In the semiconductor device 10C of the third embodiment, the capacitor 60 may have three or more capacitors.

[0161] The capacitor 60 may be configured separately from the source electrode 61. Furthermore, the capacitor 60 may be located in a portion other than the area between the source pad 41 and the semiconductor substrate 11.

[0162] For example, the capacitor 60 in one modified example shown in Figure 12 is configured to form capacitance between a specific pad 47 and a semiconductor substrate 11. In this modified example, the specific electrode 62 is made up of the specific pad 47, and the source-side electrode 61 is made up of a third conductive layer L1. The source-side electrode 61 has a source-facing portion 61C that faces the specific pad 47 across the insulating layer 12, and a source-connecting portion 61D that extends from the source-facing portion 61C. A part of the source-connecting portion 61D is located below the source pad 41. In the portion where the source-connecting portion 61D and the source pad 41 overlap in the Z direction, a via V3 is formed in the insulating layer 12 located between the source-connecting portion 61D and the source pad 41 to electrically connect the source-connecting portion 61D and the source pad 41. In this case, the capacitor 60 forms capacitance between the specific electrode 62 and the specific pad 47.

[0163] Furthermore, in the above modified example, the source-side electrode 61, which is composed of the third conductive layer L1, may be replaced with a source-side electrode 61 composed of the fourth conductive layer L2 (see Figure 9) embedded in the insulating layer 12.

[0164] Alternatively, the capacitor 60 may be configured to form capacitance between the third conductive layer L1 and the fourth conductive layer L2. In this case, one of the third conductive layer L1 and the fourth conductive layer L2 constitutes a specific electrode 62 that is electrically connected to the specific pad 47, and the other constitutes a source-side electrode 61 that is electrically connected to the source electrode 28.

[0165] Furthermore, the capacitor 60 may be an external capacitor mounted on the source pad 41 and the specific pad 47 outside the insulating layer 12. In this case, of the two electrodes constituting the external capacitor, the electrode connected to the source pad 41 becomes the source electrode 61, and the electrode connected to the specific pad 47 becomes the specific electrode 62.

[0166] With respect to the electrode pads, the source pad 41, drain pad 42, gate pad 43, and specific pad 47, their planar shape, number, and arrangement on the surface 12A of the insulating layer 12 are not limited to the above embodiment.

[0167] Regarding the first application embodiment in which the specific pad 47 and the gate pad 43 are electrically disconnected, instead of leaving the specific pad 47 at no potential (floating state), the specific pad 47 may be electrically connected to the source pad 41 by a wire or the like. In this case, the potential of the specific pad 47 and the specific electrode 62 becomes the source potential.

[0168] In each of the above embodiments, the transistor T is a HEMT using a nitride semiconductor, but any transistor can be used as the transistor T in the semiconductor device of each embodiment.

[0169] As used in this disclosure, the term “on” includes both the meanings of “on” and “above” unless the context clearly indicates otherwise. Therefore, the expression “the first layer is formed on the second layer” is intended to mean that in one embodiment the first layer may be in contact with and directly positioned on the second layer, while in other embodiments the first layer may be positioned above the second layer without contact. In other words, the term “on” does not preclude structures in which another layer is formed between the first and second layers.

[0170] The Z direction used in this disclosure does not necessarily have to be vertical, nor does it have to perfectly coincide with the vertical. Therefore, the various structures provided in this disclosure (for example, the structures shown in Figures 2 and 3) are not limited to the Z direction "up" and "down" being the same as the Z direction "up" and "down" being the same as the vertical. For example, the X direction may be vertical, or the Y direction may be vertical.

[0171] The terms "first," "second," "third," etc., used in this disclosure are used simply to distinguish between the subjects and do not rank them. <Note> The technical concepts that can be grasped from this disclosure are described below. Note that, not as an attempt to limit the scope but to aid understanding, the components described in the appendices are denoted by the corresponding reference numerals of the components in the embodiments. The reference numerals are provided as examples to aid understanding, and the components described in each appendice should not be limited to those indicated by the reference numerals.

[0172] [Note 1] Semiconductor substrate (11) and A transistor (T) is formed on the semiconductor substrate and includes a source electrode (28), a drain electrode (30), and a gate electrode (24), An insulating layer (12) provided on the semiconductor substrate (11), A source pad (41) is formed on the surface (12A) of the insulating layer (12) and electrically connected to the source electrode (28), A drain pad (42) is formed on the surface (12A) of the insulating layer (12) and is electrically connected to the drain electrode (30), A gate pad (43) is formed on the surface (12A) of the insulating layer (12) and connected to the gate electrode (24), A specific pad (47) formed on the surface (12A) of the insulating layer (12), A semiconductor device (10A, 10B, 10C) comprising a source-side electrode (61) electrically connected to the source electrode (28), and a capacitor (60) including a specific electrode (62) electrically connected to the specific pad (47) and positioned opposite the source-side electrode (61).

[0173] [Note 2] The specified electrode (62) includes opposing portions (62A, 62A1, 62A2) that are positioned opposite the source pad (41) with a portion of the insulating layer (12) in between. The source-side electrode (61) is composed of the source pad (47), and the semiconductor device (10A, 10B, 10C) described in Appendix 1 includes a opposed portion (41A, 41A1, 41A2) that faces the opposing portion (62A, 62A1, 62A2) of the source pad (47).

[0174] [Note 3] The specific electrode (62) further includes connecting parts (62B, 62B1, 62B2) for electrically connecting the opposing parts (62A, 62A1, 62A2) and the specific pad (47), The semiconductor device (10A, 10B, 10C) described in Appendix 2 is provided such that the specific electrode (62) spans both the source pad (41) and the specific pad (47) when viewed from the thickness direction of the semiconductor substrate (11).

[0175] [Note 4] A semiconductor device (10A, 10B, 10C) is provided, as specified in Appendix 3, which has vias (V1) that penetrate the insulating layer (12) between the connection portion (62B, 62B1, 62B2) and the specific pad (47) and electrically connects the connection portion (62B, 62B1, 62B2) and the specific pad (47).

[0176] [Note 5] The opposing portions (62A, 62A1, 62A2) are formed on the back surface of the insulating layer (12A), and the semiconductor device (10A, 10C) is as described in any one of appendices 2 to 4.

[0177] [Note 6] The semiconductor device (10B, 10C) described in any one of the appendices 2 to 4, wherein the opposing portions (62A, 62A1, 62A2) are embedded conductive layers (L2) embedded within the insulating layer (12).

[0178] [Note 7] The semiconductor device described in Appendix 1, wherein the source-side electrode (61) is provided separately from the source pad (47).

[0179] [Note 8] The specified pad (47) includes a first specified pad (47A) and a second specified pad (47B) formed on the surface (12A) of the insulating layer (12) at a distance from each other. The capacitor (60) includes a first capacitor (60A) and a second capacitor (60B), The first capacitor (60A) is, The source side electrode (61) comprises a first source side electrode (61A) electrically connected to the source electrode (28), The specified electrode (62) comprises a first specified electrode (62C) which is electrically connected to the first specified pad (47A) and is positioned opposite the first source side electrode (61A), The second capacitor (60B) is, The source side electrode (61) comprises a second source side electrode (61B) electrically connected to the source electrode (28), A semiconductor device (10C) according to any one of the appendices 1 to 7, comprising the specified electrode (62) which is electrically connected to the second specified pad (47B) and is positioned opposite the second source side electrode (61B).

[0180] [Note 9] The first specific electrode (62C) includes a first opposing portion (62A1) that is positioned opposite the source pad (41) with a portion of the insulating layer (12) in between, The first source-side electrode (61A) is composed of the source pad (47) and includes a first opposing portion (41A1) that faces the first opposing portion of the source pad (41), The second specific electrode (62D) includes a second opposing portion (62A2) that is positioned opposite the source pad with a portion of the insulating layer in between, The semiconductor device (10C) described in Appendix 8, wherein the second source-side electrode (61B) is composed of the source pad (47) and includes a second opposing portion (41A2) facing the second opposing portion (62A2) of the source pad (41).

[0181] [Note 10] A semiconductor device (10C) as described in Appendix 7 or Appendix 9, wherein the capacitance of the first capacitor (60A) is greater than the capacitance of the second capacitor (60B).

[0182] [Note 11] The semiconductor device (10C) according to Appendix 8 or Appendix 10, wherein the area of ​​contact between the first source electrode (61A) and the first specific electrode (62C) is greater than the area of ​​contact between the second source electrode (61B) and the second specific electrode (62D).

[0183] [Note 12] A semiconductor device (10C) according to any one of appendices 8 to 11, wherein the first specific pad (47A) and the second specific pad (47B) are arranged on the surface (12A) of the insulating layer (12) with the source pad (41) in between.

[0184] [Note 13] The first specific pad (47A) and the second specific pad (47B) are arranged spaced apart in the first direction (Y direction) in which the source pad (41) extends, as viewed from the thickness direction (Z direction) of the semiconductor substrate (11). The gate pad (43) is A first gate pad (43A) is arranged alongside the first specific pad (47A) in a second direction (X direction) that is perpendicular to the first direction (Y direction) when viewed from the thickness direction (Z direction) of the semiconductor substrate (11), A semiconductor device (10C) according to any one of appendices 8 to 12, comprising a second gate pad (43B) arranged alongside the second specific pad (47B) in the second direction (X direction).

[0185] [Note 14] A semiconductor device (10A, 10B, 10C) according to any one of appendices 1 to 13, wherein the specific pad (47) is located closer to the source pad (41) than the gate pad (43) on the surface (12A) of the insulating layer (12).

[0186] [Note 15] A semiconductor device (10A, 10B, 10C) according to any one of appendices 1 to 14, wherein the gate pad (43) is positioned closer to the drain pad (42) than the source pad (41) on the surface (12A) of the insulating layer (12).

[0187] [Note 16] The aforementioned transistor (T) is An electron transport layer (16) made of nitride semiconductor, An electron supply layer (18) is formed on the electron transport layer (16) and is made of a nitride semiconductor having a larger band gap than the electron transport layer (16), A gate layer (22) is formed on a portion of the electron supply layer (18) and is made of a nitride semiconductor containing acceptor-type impurities, The gate electrode (24) formed on the gate layer, The electron supply layer (18) is in contact with the source electrode (28) and the drain electrode (30), The semiconductor device (10A, 10B, 10C) according to any one of appendices 1 to 15, wherein the gate layer (22) is located on the electron supply layer (18) between the source electrode (28) and the drain electrode (30).

[0188] [Note 17] A semiconductor device (10A, 10B, 10C) according to any one of appendices 1 to 16, comprising: an active region (A1) on which a plurality of transistors (T) are formed; a peripheral region (A2) surrounding the active region (A1); and the source pad (41) and the drain pad (42) arranged in the peripheral region (A2) so as to sandwich the active region (A1).

[0189] [Note 18] Multiple source wires (44) extending from the source pad (41) toward the drain pad (42), The system comprises a plurality of drain wires (45) extending from the drain pad (42) toward the source pad (41), The plurality of source wires (44) and the plurality of drain wires (45) are arranged alternately along the first direction (Y direction), The source electrode (28) is connected to the source wiring (44), The semiconductor device (10A, 10B, 10C) described in any one of appendices 1 to 17, wherein the drain electrode (30) is connected to the drain wiring (45).

[0190] [Note 19] Die pad (101) and, A semiconductor device (10A, 10B, 10C) described in any one of appendices 1 to 18, mounted on the die pad (101), A semiconductor module (100) comprising a sealing resin (102) for sealing the semiconductor devices (10A, 10B, 10C).

[0191] [Note 20] A semiconductor module (100) as described in Appendix 19, comprising a specific wire (109) connecting the specific pad (47) and the gate pad (43).

[0192] [Note 21] The semiconductor module (100) described in Appendix 18 or Appendix 19, wherein the specified pad (47) is electrically disconnected from the gate pad (43).

[0193] [Note 22] Source lead (103), drain lead (104), and gate lead (105), A source wire (106) connects the source lead (103) and the source pad (41), A drain wire (107) connects the drain lead (104) and the drain pad (42), A semiconductor module (100) according to any one of appendices 18 to 21, comprising a gate wire (108) connecting the gate lead (105) and the gate pad (43). [Explanation of Symbols]

[0194] A1... Active area A2…peripheral area D…Distance between electrodes L1...Third conductive layer L2…4th conductive layer T...transistor Vd, Vs, V1, V2, V3... Via 10A, 10B, 10C… Semiconductor equipment 11… Semiconductor substrates 12…Insulating layer 12A…Surface 12B…Reverse side 14…Buffer layer 16…Electronic transport layer 18...electron supply layer 20...2DEG (Two-Dimensional Electron Gas) 22...Gate layer 24… Gate 26…Insulating layer 26A…Source opening 26B...Drain opening 28…Source electrode 30…Drain electrode 31…Field plate electrode 31A...end 41…Sourcepad 41A…Opposed part 41A1...First opposed part 41A2…Second opposed part 42... Drain pad 43…Gate pad 43A...Gate pad #1 43B... Second gate pad 44…Source wiring 44A... Overlapping parts 45... Drain wiring 45A... overlapping part 46…Gate wiring 46A…First gate wiring 46B...Second gate wiring 47...Specific pad 47A...First specific pad 47B...Second specific pad 48...Protective film 51…First outer perimeter guard ring 51A... Semiconductor layer 51B...first conductive layer 51C…Second conductive layer 52…Second outer perimeter guard ring 60…Capacitor 60A…First Capacitor 60B…Second capacitor 61…Source side electrode 61A...First source side electrode 61B...Second source side electrode 61C... Source opposite section 61D...Source connection section 62…Specific electrode 62A... Opposite section 62A1...First opposing section 62A2…Second opposing part 62B…Connecting portion 62B1…First connecting portion 62B2…Second connecting portion 62C…First specific electrode 62D…Second specific electrode 63…Embedded conductive layer 100…Semiconductor module 101…Die pad 102…Sealing resin 103…Source lead 104…Drain lead 105…Gate lead 106…Source wire 107…Drain wire 108…Gate wire 109…Specific wire 200…Mounting substrate 201…First substrate wiring 202…Second substrate wiring 203…Third substrate wiring 203A…First portion 203B…Second portion

Claims

1. Semiconductor substrate and A transistor formed on the semiconductor substrate, including a source electrode, a drain electrode, and an electrode, An insulating layer provided on the semiconductor substrate, A source pad formed on the surface of the insulating layer and electrically connected to the source electrode, A drain pad formed on the surface of the insulating layer and electrically connected to the drain electrode, A gate pad formed on the surface of the insulating layer and connected to the gate electrode, A specific pad formed on the surface of the insulating layer, A capacitor comprising a source-side electrode electrically connected to the source electrode, and a specific electrode electrically connected to the specific pad and positioned opposite the source-side electrode, The specified electrode includes a facing portion that is positioned opposite the source pad with a part of the insulating layer in between, A semiconductor device comprising the source-side electrode, the source pad, and a portion of the source pad facing the opposing portion.

2. The specific electrode further includes a connecting portion for electrically connecting the opposing portion and the specific pad, The semiconductor device according to claim 1, wherein the specific electrode is provided so as to span both the source pad and the specific pad when viewed from the thickness direction of the semiconductor substrate.

3. The semiconductor device according to claim 2, further comprising a via provided through the insulating layer between the connection portion and the specific pad, which electrically connects the connection portion and the specific pad.

4. The semiconductor device according to claim 1, wherein the opposing portion is formed on the back surface of the insulating layer.

5. The semiconductor device according to claim 1, wherein the opposing portion is an embedded conductive layer embedded within the insulating layer.

6. Semiconductor substrate and A transistor formed on the semiconductor substrate, including a source electrode, a drain electrode, and an electrode, An insulating layer provided on the semiconductor substrate, A source pad formed on the surface of the insulating layer and electrically connected to the source electrode, A drain pad formed on the surface of the insulating layer and electrically connected to the drain electrode, A gate pad formed on the surface of the insulating layer and connected to the gate electrode, A specific pad formed on the surface of the insulating layer, A capacitor comprising a source-side electrode electrically connected to the source electrode, and a specific electrode electrically connected to the specific pad and positioned opposite the source-side electrode, The specified pad includes a first specified pad and a second specified pad formed on the surface of the insulating layer at a distance from each other. The capacitor includes a first capacitor and a second capacitor, The first capacitor is The source side electrode comprises a first source side electrode electrically connected to the source electrode, The specified electrode comprises a first specified electrode electrically connected to the first specified pad and positioned opposite the first source side electrode, The second capacitor is The source electrode comprises a second source electrode electrically connected to the source electrode, A semiconductor device comprising the specified electrode, the second specified electrode which is electrically connected to the second specified pad and is positioned opposite the second source side electrode.

7. The first specific electrode includes a first opposing portion that is positioned opposite the source pad with a part of the insulating layer in between, The first source-side electrode includes a first opposing portion that faces the first opposing portion in the source pad, The second specific electrode includes a second opposing portion that is positioned opposite the source pad with a portion of the insulating layer in between, The semiconductor device according to claim 6, wherein the second source electrode includes a second opposing portion that faces the second opposing portion in the source pad.

8. The semiconductor device according to claim 6, wherein the capacitance of the first capacitor is greater than the capacitance of the second capacitor.

9. The semiconductor device according to claim 7, wherein the area of ​​contact between the first source electrode and the first specific electrode is greater than the area of ​​contact between the second source electrode and the second specific electrode.

10. The semiconductor device according to claim 6, wherein the first specific pad and the second specific pad are arranged on the surface of the insulating layer, sandwiching the source pad.

11. The first specific pad and the second specific pad are arranged spaced apart in the first direction in which the source pad extends, as viewed from the thickness direction of the semiconductor substrate. The aforementioned gate pad is A first gate pad is arranged alongside the first specific pad in a second direction perpendicular to the first direction when viewed from the thickness direction of the semiconductor substrate, The semiconductor device according to claim 6, further comprising: a second gate pad arranged alongside the second specific pad in the second direction.

12. The semiconductor device according to claim 1, wherein the specific pad is positioned closer to the source pad than the gate pad on the surface of the insulating layer.

13. The semiconductor device according to claim 1, wherein the gate pad is positioned closer to the drain pad than the source pad on the surface of the insulating layer.

14. The aforementioned transistor is An electron transport layer composed of a nitride semiconductor, An electron supply layer formed on the electron transport layer and composed of a nitride semiconductor having a larger band gap than the electron transport layer, A gate layer formed on a portion of the electron supply layer and composed of a nitride semiconductor containing acceptor-type impurities, The gate electrode formed on the gate layer, The electron supply layer comprises the source electrode and the drain electrode in contact with the electron supply layer, The semiconductor device according to claim 1, wherein the gate layer is located on the electron supply layer between the source electrode and the drain electrode.

15. A semiconductor device according to any one of claims 1 to 14, A semiconductor module comprising a sealing resin for sealing the semiconductor device.

16. The semiconductor module according to claim 15, further comprising a specific wire connecting the specific pad and the gate pad.

17. The semiconductor module according to claim 15, wherein the specified pad is electrically disconnected from the gate pad.

18. Source lead, drain lead, and gate lead, A source wire connecting the source lead and the source pad, A drain wire connecting the drain lead and the drain pad, The semiconductor module according to claim 15, further comprising a gate wire connecting the gate lead and the gate pad.

Images