Signal processing device and signal processing system

Abstract

To provide a technique which allows for simply communicating data with two devices.SOLUTION: A signal processing apparatus 20 includes a first terminal 202 to which one of a clock signal and a data signal is inputted, a second terminal 204 to which the other of the clock signal and the data signal is inputted, a storage unit 250 in which address maps defining addresses to which data writing is permitted and addresses to which data writing is prohibited are set, a designation unit 220 which designates an address map set in the storage unit, and a processing unit 240 which writes data based on the data signal into the storage unit in accordance with the address map designated by the designation unit. The designation unit designates a first address map when the clock signal is inputted to the first terminal and the data signal is inputted to the second terminal, and designates a second address map different from the first address map when the data signal is inputted to the first terminal and the clock signal is inputted to the second terminal.SELECTED DRAWING: Figure 4

Description

Technical Field

[0001] The present disclosure relates to a signal processing device and a signal processing system. Background Art

[0002] Conventionally, communication buses that transmit and receive data using a clock signal line and a data signal line are known. An example of such a communication bus is the I2C (Inter-Integrated Circuit) bus. Prior Art Documents Patent Documents

[0003] Patent Document 1 Japanese Unexamined Patent Application Publication No. 2014-153822 Summary of the Invention Problem to be Solved by the Invention

[0004] However, when connecting a plurality of devices to such a communication bus, it is necessary to assign identifiers to these devices. In order to assign these identifiers, it is necessary to prepare external terminals or preconfigure a non-volatile memory or the like built into the device. For this reason, it has not been possible to simply transmit and receive data with a plurality of devices.

[0005] The present disclosure has been made in view of such circumstances, and one exemplary object thereof is to provide a signal processing device and a signal processing system that enable simple communication with two devices. Means for Solving the Problem

[0006] One aspect of the present disclosure is a signal processing device. The signal processing device includes a first terminal to which one of a clock signal and a data signal is input, a second terminal to which the other of the clock signal and the data signal is input, a storage unit in which an address map is set that defines addresses where data writing is permitted and addresses where data writing is prohibited, a designation unit that designates the address map set in the storage unit, and a processing unit that writes data based on the data signal to the storage unit according to the address map designated by the designation unit. The designation unit designates a first address map when a clock signal is input to the first terminal and a data signal is input to the second terminal, and designates a second address map different from the first address map when a data signal is input to the first terminal and a clock signal is input to the second terminal.

[0007] Another aspect of the present disclosure is a signal processing system. The signal processing system comprises a first signal processing device and a second signal processing device, each configured with the above-described signal processing device. The first signal processing device is configured such that a data signal is input to a first terminal of the first signal processing device and a clock signal is input to a second terminal of the first signal processing device. The second signal processing device is configured such that a clock signal is input to a first terminal of the second signal processing device and a data signal is input to a second terminal of the second signal processing device.

[0008] Furthermore, any combination of the above components, as well as any conversion of the expressions of this disclosure between methods, apparatus, systems, recording media, computer programs, etc., are also valid as aspects of this disclosure. [Effects of the Invention]

[0009] This disclosure provides a signal processing device and a signal processing system that enable easy communication between two devices. [Brief explanation of the drawing]

[0010] [Figure 1] Figure 1 shows a signal processing system for reference purposes. [Figure 2] Figure 2 is a diagram illustrating the signal transmission and reception flow in a signal processing system related to a reference example. [Figure 3] Figure 3 shows the configuration of a signal processing system according to one embodiment of the present disclosure. [Figure 4] Figure 4 is a functional block diagram of the signal processing device according to the same embodiment. [Figure 5] Figure 5(a) shows a first address map according to the same embodiment. Figure 5(b) shows a second address map according to the same embodiment. [Figure 6] Figure 6 illustrates an example of the operation of the signal processing system according to the same embodiment. [Figure 7] Figure 7 shows the two signal processing devices viewed from the master device according to the same embodiment. [Figure 8] Figure 8(a) shows a first address map relating to a modified example. Figure 8(b) shows a second address map relating to a modified example. [Figure 9] Figure 9 shows the address maps set in the first signal processing device and the second signal processing device according to the application example. [Figure 10] Figure 10(a) is a diagram illustrating the communication flow when data is written to the memory unit of the signal processing device. Figure 10(b) is a diagram illustrating the communication flow when data is read from the memory unit of the signal processing device. [Modes for carrying out the invention]

[0011] (overview) This section outlines some exemplary embodiments of the present disclosure. This outline is intended to provide a basic understanding of the embodiments and to simplify some concepts of one or more embodiments, serving as a prelude to the more detailed descriptions that follow. It is not intended to limit the scope of the invention or disclosure. This outline is not a comprehensive overview of all possible embodiments, nor is it intended to identify essential elements of all embodiments or to delineate the scope of some or all aspects. For convenience, “one embodiment” may be used to refer to one or more embodiments (examples or variations) disclosed herein.

[0012] A signal processing device according to one embodiment includes: a first terminal to which one of a clock signal and a data signal is input; a second terminal to which the other of the clock signal and the data signal is input; a storage unit in which an address map is set that defines addresses where data writing is permitted and addresses where data writing is prohibited; a designation unit that designates the address map set in the storage unit; and a processing unit that writes data based on the data signal to the storage unit according to the address map designated by the designation unit. The designation unit designates a first address map when a clock signal is input to the first terminal and a data signal is input to the second terminal, and designates a second address map different from the first address map when a data signal is input to the first terminal and a clock signal is input to the second terminal.

[0013] In this configuration, the signal processing unit writes data according to one of two specified address maps. By using two such signal processing units, it becomes possible to write data according to each address map, thus simplifying communication between the two signal processing units.

[0014] In one embodiment, when a clock signal is input to a first terminal and a data signal is input to a second terminal, the signal processing apparatus may further comprise: a first detection unit that detects the start of communication based on the clock signal and the data signal; and a second detection unit that detects the start of communication based on the clock signal and the data signal when a data signal is input to the first terminal and a clock signal is input to the second terminal. The specifying unit may specify a first address map when the first detection unit detects a start, and may specify a second address map when the second detection unit detects a start. This enables more appropriate specification of an address map.

[0015] In one embodiment, each of the first address map and the second address map may include a first address and a second address. The first address may be an address that permits data writing and reading in the first address map, where data writing and reading are performed, and an address that prohibits data writing and reading in the second address map, where data writing and reading are not performed. The second address may be an address that prohibits data writing and reading in the first address map, where data writing and reading are not performed, and an address that permits data writing and reading in the second address map, where data writing and reading are performed. This makes it possible to more reliably perform appropriate signal transmission and reception with two signal processing apparatuses.

[0016] In one embodiment, each of the first address map and the second address map may include a first address, a second address, and a write address to which data can be written. The first address may permit writing of data to the write address in the first address map, and may prohibit writing of data to the write address in the second address map. The second address may prohibit writing of data to the write address in the first address map, and may permit writing of data to the write address in the second address map.

[0017] In one embodiment, the signal processing device may further include an output control unit that causes data written to a storage unit to be output from a first terminal or a second terminal in accordance with an address map specified by a specifying unit. This enables easy reception of data from two signal processing devices.

[0018] A signal processing device according to another embodiment includes a first signal processing device and a second signal processing device each configured as the above signal processing device. The first signal processing device is arranged such that a data signal is input to a first terminal of the first signal processing device, and a clock signal is input to a second terminal of the first signal processing device. The second signal processing device is arranged such that the clock signal is input to a first terminal of the second signal processing device, and the data signal is input to a second terminal of the second signal processing device. With this configuration, it is possible to easily transmit and receive data to and from the two signal processing devices.

[0019] In one embodiment, the data signal may be configured such that data is written to a storage unit of the first signal processing device in accordance with the first address map, and data is written to a storage unit of the second signal processing device in accordance with the second address map. This enables writing data to the two signal processing devices through one communication.

[0020] (Reference Example) Figure 1 shows a signal processing system 9 according to an example. As shown in Figure 1, the signal processing system 9 according to the example comprises a master device 90, a communication bus 92, a first slave device 94a, and a second slave device 94b. The master device 90 communicates with the first slave device 94a and the second slave device 94b via the communication bus 92.

[0021] The first slave device 94a and the second slave device 94b each perform various signal processing operations according to the input signals. The first slave device 94a has a data signal terminal 942a, a clock signal terminal 944a, and an identifier terminal 946a. The second slave device 94b also has a data signal terminal 942b, a clock signal terminal 944b, and an identifier terminal 946b. The first slave device 94a and the second slave device 94b are assigned identifiers using external terminals. Specifically, the first slave device 94a is assigned an identifier from an external terminal via the identifier terminal 946a, and the second slave device 94b is assigned an identifier from an external terminal via the identifier terminal 946b.

[0022] The communication bus 92 is connected to the master device 90, the first slave device 94a, and the second slave device 94b, and is used as a signal transmission path between the master device 90 and the first slave device 94a and the second slave device 94b. The communication bus 92 has a clock signal line 920 and a data signal line 922.

[0023] The clock signal line 920 is connected to the master device 90, the clock signal terminal 944a of the first slave device 94a, and the clock signal terminal 944b of the second slave device 94b. The clock signal from the master device 90 is transmitted to the first slave device 94a and the second slave device 94b through the clock signal line 920.

[0024] The data signal line 922 is connected to the master device 90, the data signal terminal 942a of the first slave device 94a, and the data signal terminal 942b of the second slave device 94b. Data signals from the master device 90 are transmitted to the first slave device 94a and the second slave device 94b via the data signal line 922. Conversely, data from the first slave device 94a or the second slave device 94b is transmitted to the master device 90 via the data signal line 922.

[0025] Referring to Figure 2, the signal transmission and reception flow in the signal processing system 9 of the reference example will be explained. The master device 90 transmits start information 960 indicating the start of communication, followed by slave address information 962 identifying the slave device to be communicated with. The slave device corresponding to this slave address information 962 (the first slave device 94a or the second slave device 94b) becomes able to communicate with the master device 10.

[0026] The master device 90 transmits instruction information 964, which instructs the slave device to write data, following the slave address information 962. The master device 10 then transmits sub-address information 966,968 to which the data will be written, followed by data 970 representing the data to be written, and finally transmits stop information 972 indicating the end of communication. The slave device communicating with the master device 10 transmits acknowledgment information 980,982,984,986 to the master device 10 as needed. The slave device then performs internal signal processing based on the information transmitted from the master device 10 (sub-address information 966,968 and data 970) and writes the data to its internal memory.

[0027] Generally, when multiple devices are connected to a communication bus, in order to communicate with any of these devices, it is necessary to make the target device aware that it has been selected for communication. In the signal processing system 9 of the reference example, identifiers (slave addresses) that identify the first slave device 94a and the second slave device 94b are used to make the slave devices aware that they are the target of communication. In the reference example, external terminals are provided to assign identifiers to each slave device. These external terminals need to be placed on the circuit board on which the slave devices are mounted, and their maintenance is burdensome. Alternatively, identifiers can be assigned to the slave devices using non-volatile memory built into the slave devices. However, in this case, the settings of the non-volatile memory must be configured in advance according to the slave device.

[0028] (Embodiment) Preferred embodiments will be described below with reference to the drawings. The same or equivalent components, members, and processes shown in each drawing will be denoted by the same reference numeral, and redundant explanations will be omitted as appropriate. Furthermore, in this specification and the drawings, multiple components having substantially the same functional configuration may be distinguished by adding a different alphabet after the same reference numeral. However, if there is no need to particularly distinguish between multiple components having substantially the same functional configuration, only the same reference numeral will be used for each of the multiple components. For example, when the first signal processing device 20a and the second signal processing device 20b are not particularly distinguished, they will simply be referred to as "signal processing device 20".

[0029] Furthermore, the embodiments are illustrative and not limiting to the disclosure and invention, and not all features or combinations thereof described in the embodiments are necessarily essential to the disclosure and invention.

[0030] Figure 3 shows the configuration of a signal processing system 1 according to one embodiment of the present disclosure. The signal processing system 1 according to this embodiment comprises a master device 10, a communication bus 12, a first signal processing device 20a, and a second signal processing device 20b.

[0031] The master device 10 transmits and receives various information with the first signal processing unit 20a and the second signal processing unit 20b. Specifically, the master device 10 transmits clock signals and data signals to the first signal processing unit 20a and the second signal processing unit 20b, and receives various data from the first signal processing unit 20a and the second signal processing unit 20b.

[0032] The first signal processing device 20a and the second signal processing device 20b perform various signal processing, and both devices have substantially the same configuration. The first signal processing device 20a has a first terminal 202a (Port A) and a second terminal 204a (Port B), and transmits and receives signals with the master device 10 through these terminals. The second signal processing device 20b has a first terminal 202b (Port A) and a second terminal 204b (Port B), and transmits and receives signals with the master device 10 through these terminals.

[0033] The communication bus 12 is connected to the master device 10, the first signal processing device 20a, and the second signal processing device 20b, and functions as a transmission path for sending and receiving data between the master device 10 and the first signal processing device 20a and the second signal processing device 20b. The communication bus 12 has a clock signal line 120 and a data signal line 122.

[0034] The clock signal line 120 is connected to the master device 10, the first terminal 202a of the first signal processing device 20a, and the second terminal 204b of the second signal processing device 20b. The clock signal line 120 transmits the clock signal from the master device 10 to the first signal processing device 20a through the first terminal 202a, and transmits the clock signal from the master device 10 to the second signal processing device 20b through the second terminal 204b.

[0035] The data signal line 122 is connected to the master device 10, the second terminal 204a of the first signal processing device 20a, and the first terminal 202b of the second signal processing device 20b. The data signal line transmits data signals from the master device 10 to the first signal processing device 20a through the second terminal 204a, and transmits data signals from the master device 10 to the second signal processing device 20b through the first terminal 202b. In addition, data from the first signal processing device 20a or the second signal processing device 20b is transmitted to the master device 10 through the data signal line 122.

[0036] Figure 4 is a functional block diagram of a signal processing device 20 according to one embodiment of the present disclosure. As shown in Figure 4, the signal processing device 20 according to this embodiment includes a processing unit 200, a first terminal 202, a second terminal 204, a storage unit 250, and an output control unit 260.

[0037] The first terminal 202 receives signals from an external device and outputs signals to an external device. For example, the first terminal 202 receives a clock signal or a data signal from the master device 10. Specifically, depending on the connection status between the first signal processing device 20a and the communication bus 12, either a clock signal or a data signal is input to the first terminal 202. The signal input to the first terminal 202 is transmitted to the first detection unit 210, the second detection unit 212, and the discrimination unit 230. The first terminal 202 can also output data stored in the storage unit 250 to the outside, for example.

[0038] The second terminal 204 receives signals from an external device and outputs signals to an external device. For example, the second terminal 204 receives a clock signal or a data signal from the master device 10. Specifically, the second terminal 204 receives either a clock signal or a data signal depending on the connection status between the first signal processing device 20a and the communication bus 12. More specifically, when a clock signal is input to the first terminal 202, a data signal is input to the second terminal 204. Also, when a data signal is input to the first terminal 202, a clock signal is input to the second terminal 204. The signal input to the second terminal 204 is transmitted to the first detection unit 210, the second detection unit 212, and the discrimination unit 230. The second terminal 204 can also output data stored in the storage unit 250 to the outside, for example.

[0039] The processing unit 200 performs various processes. The processing unit 200 may include a CPU (Central Processing Unit), RAM (Random Access Memory), and ROM (Read Only Memory). The functions of the processing unit 200 according to this embodiment are realized by the cooperation of the first detection unit 210, the second detection unit 212, the designation unit 220, the discrimination unit 230, and the signal processing unit 240.

[0040] The first detection unit 210 detects the start and stop of communication based on the clock signal and data signal input to the first terminal 202 and the second terminal 204. The first detection unit 210 transmits a signal Ss1 indicating the detection result to the designation unit 220, the discrimination unit 230, and the output control unit 260.

[0041] In this embodiment, the first detection unit 210 detects start and stop when a clock signal is input to the first terminal 202 and a data signal is input to the second terminal 204. The method by which the first detection unit 210 detects start and stop is not particularly limited, and it may detect the start and stop of communication based on various known protocols. For example, in the case of the I2C protocol, the first detection unit 210 detects the start and stop of communication in accordance with the change in the data signal when the clock signal is high. Specifically, the first detection unit 210 may detect a start when the data signal changes from high to low while the clock signal is high, and detect a stop when the data signal changes from low to high while the clock signal is high.

[0042] The second detection unit 212 detects the start and stop of communication based on the clock signal and data signal input to the first terminal 202 and the second terminal 204. The second detection unit 212 transmits a signal Ss2 indicating the detection result to the designation unit 220, the discrimination unit 230, and the output control unit 260.

[0043] In this embodiment, the second detection unit 212 detects the start and stop of communication when a data signal is input to the first terminal 202 and a clock signal is input to the second terminal 204. The method by which the second detection unit 212 detects the start and stop is not particularly limited, and it may detect the start and stop of communication based on various known protocols. For example, in the case of the I2C protocol, the second detection unit 212 may detect the start and stop of communication in accordance with the change in the data signal when the clock signal is high, similar to the first detection unit 210.

[0044] The designation unit 220 designates an address map based on the signals input to the first terminal 202 and the second terminal 204. The address map defines addresses where data writing is permitted and addresses where data writing is prohibited, more specifically, addresses where data writing and reading are permitted and addresses where data writing and reading are prohibited. Specifically, the designation unit 220 designates a first address map when a clock signal is input to the first terminal 202 and a data signal is input to the second terminal 204. Also, the designation unit 220 designates a second address map different from the first address map when a data signal is input to the first terminal 202 and a clock signal is input to the second terminal 204. The designation unit 220 sets the designated address map in the storage unit 250.

[0045] The discrimination unit 230 distinguishes between a clock signal and a data signal from the signals transmitted from the first terminal 202 and the second terminal 204. At this time, the discrimination unit 230 may use the start detection results from the first detection unit 210 and the second detection unit 212. Based on the discrimination result, the discrimination unit 230 transmits the clock signal CLK and the data signal D1 to the signal processing unit 240.

[0046] The signal processing unit 240 performs various signal processing. Specifically, the signal processing unit 240 writes data to the storage unit 250. Based on the data signal D1 transmitted from the discrimination unit 230, it obtains sub-address information Sad and data D2, accesses the storage unit 250 based on the sub-address information Sad, and writes data D2 to the storage unit 250. At this time, the signal processing unit 240 writes the data to the storage unit 250 according to the address mapping set in the storage unit 250.

[0047] The storage unit 250 stores various types of data. In this embodiment, the storage unit 250 is composed of registers and memory, etc. The storage unit 250 is configured with an address map that defines addresses to which data writing is permitted and addresses to which data writing is prohibited.

[0048] The output control unit 260 controls the output of data. Specifically, it reads data stored in the storage unit 250 and outputs the read data from the first terminal 202 or the second terminal 204. In this embodiment, the output control unit 260 causes data to be output from the first terminal 202 or the second terminal 204 according to the address map specified by the designation unit 220. Specifically, the output control unit 260 selects a terminal to output the read data according to the address map specified by the designation unit 220 and causes the data to be output from the selected terminal.

[0049] For example, the output control unit 260 may select a terminal to output the read data based on the detection results of the first detection unit 210 and the second detection unit 212. Specifically, when the first detection unit 210 detects a start (when the first address map is specified), the output control unit 260 outputs data from the second terminal 204. Also, when the second detection unit 212 detects a start (when the second address map is specified), the output control unit 260 outputs data from the first terminal 202. However, if the address to be read is one for which reading of the address map is prohibited, the output control unit 260 cannot read data from that address and therefore does not output data from either terminal.

[0050] Referring to Figures 5(a) and 5(b), the address maps set in the storage unit 250 in this embodiment will be described. Figure 5(a) is a diagram showing the first address map 300 according to this embodiment, and Figure 5(b) is a diagram showing the second address map 310 according to this embodiment.

[0051] As shown in Figure 5(a), the first address map 300 includes two address areas 302 and 304. Address area 302 includes subaddresses from 0x00 to 0x7F, and data writing is permitted and data is written to these subaddresses in response to access by the signal processing unit 240. Address area 304 includes subaddresses from 0x80 to 0xFF, and data writing is prohibited and data is not written to these subaddresses in response to access by the signal processing unit 240.

[0052] As shown in Figure 5(b), the second address map 310 includes two address areas 312 and 314. Address area 312 includes subaddresses from 0x00 to 0x7F, and data writing is prohibited from these subaddresses depending on the access of the signal processing unit 240, so no data is written. Address area 314 includes subaddresses from 0x80 to 0xFF, and data writing is permitted from these subaddresses depending on the access of the signal processing unit 240, so data is written.

[0053] In this embodiment, an example is described in which the address map is divided in half into an address area where data is written and an address area where data is not written. However, the way the address area is divided is not limited to this. For example, the address map may be configured such that addresses where data is written and addresses where data is not written alternately. Alternatively, the address map may be configured such that one of the address areas where data is written or the other where data is not written is larger than the other.

[0054] Thus, in this embodiment, the sub-addresses (0x00 to 0x7F) that allow data writing in the first address map 300 are the same as the sub-addresses that prohibit data writing in the second address map 310. On the other hand, the addresses (0x80 to 0xFF) that prohibit data writing in the first address map 300 are the same as the addresses that allow data writing in the second address map 310.

[0055] The signal processing unit 240 writes data according to such an address map. For example, if the first address map 300 is set in the storage unit 250, the signal processing unit 240 can write data to address area 302, but cannot write data to address area 304. On the other hand, if the second address map 310 is set in the storage unit 250, it cannot write data to address area 312, but can write data to address area 314.

[0056] Referring to Figure 6, an example of the operation of a signal processing system 1 according to one embodiment of this disclosure will be described. The operation flow of the signal processing system 1 will be described below in accordance with the flowchart shown in Figure 6.

[0057] First, the master device 10 transmits a clock signal and a data signal to the first signal processing device 20a and the second signal processing device 20b, respectively (S101, S103). The operation of the first signal processing device 20a will be described below, followed by the operation of the second signal processing device 20b.

[0058] The first signal processing device 20a receives the clock signal and data signal transmitted from the master device 10 (S105). Specifically, the clock signal is input to the first terminal 202a of the first signal processing device 20a, and the data signal is input to the second terminal 204a of the first signal processing device 20a.

[0059] Next, the first signal processing device 20a detects the start of communication based on the clock signal and the data signal (S107). Here, the first detection unit 210 of the first signal processing device 20a detects the start of communication based on the clock signal and the data signal.

[0060] Next, the first signal processing device 20a specifies the first address map based on the start detection result (S109). Here, since the first detection unit 210 detected a start, the designation unit 220 of the first signal processing device 20a specifies the first address map from the first address map and the second address map, and sets the first address map in the storage unit 250.

[0061] Next, the first signal processing device 20a distinguishes between a clock signal and a data signal (S111). Specifically, the discrimination unit 230 of the first signal processing device 20a distinguishes between a clock signal and a data signal based on the signals input to the first terminal 202a and the second terminal 204a.

[0062] Next, the first signal processing unit 20a processes data based on the data signal determined in S111 according to the first address map. At this time, the signal processing unit 240 can write data to sub-addresses 0x00 to 0x7F. However, the signal processing unit 240 cannot write data to sub-addresses 0x80 to 0xFF.

[0063] Next, the operation of the second signal processing device 20b will be described. The second signal processing device 20b receives the clock signal and data signal transmitted from the master device 10 (S115). Specifically, the data signal is input to the first terminal 202b of the second signal processing device 20b, and the clock signal is input to the second terminal 204b of the second signal processing device 20b.

[0064] Next, the second signal processing device 20b detects the start of communication based on the clock signal and the data signal (S117). Here, the second detection unit 212 of the second signal processing device 20b detects the start of communication based on the clock signal and the data signal.

[0065] Next, the second signal processing device 20b specifies the second address map based on the start detection result (S119). Here, since the second detection unit 212 of the second signal processing device 20b has detected a start, the designation unit 220 of the second signal processing device 20b specifies the second address map from the first address map and the second address map, and sets the second address map in the storage unit 250. Thus, in this embodiment, the first signal processing device 20a and the second signal processing device 20b set different address maps in the storage unit 250.

[0066] Next, the second signal processing device 20b distinguishes between a clock signal and a data signal. Specifically, the discrimination unit 230 of the second signal processing device 20b distinguishes between a clock signal and a data signal based on the signals input to the first terminal 202b and the second terminal 204b.

[0067] Next, the second signal processing unit 20b processes data based on the data signal according to the second address map (S123). At this time, the signal processing unit 240 cannot write data to the sub-addresses 0x00 to 0x7F. However, the signal processing unit 240 can write data to the sub-addresses 0x80 to 0xFF.

[0068] Therefore, when the master device 10 specifies a subaddress in the range of 0x00 to 0x7F, data is written to the first signal processing device 20a. On the other hand, when the master device 10 specifies a subaddress in the range of 0x80 to 0xFF, data is written to the second signal processing device 20b. When reading data, the master device 10 can receive read data from the subaddress range of 0x00 to 0x7F in the first signal processing device 20a, and read data from the subaddress range of 0x80 to 0xFF in the second signal processing device 20b.

[0069] The above describes an example of the operation of the signal processing system 1 according to this embodiment. However, the steps shown in Figure 6 do not necessarily have to be executed in the order shown. Multiple steps may be executed simultaneously or in parallel, and the order of each step may be changed as needed.

[0070] According to the signal processing system 1 of this embodiment, the master device 10 can communicate with two signal processing devices 20 having substantially identical configurations. In this embodiment, the connections of the first terminal 202 and the second terminal 204 of the first signal processing device 20a and the second signal processing device 20b to the clock signal line 120 and the data signal line 122 are reversed. This allows the address maps set for each signal processing device 20 to be different, and signal processing can be performed according to the address map. Therefore, as in the reference example described above, there is no need to prepare external terminals or pre-set non-volatile memory, and the master device 10 can easily communicate with the two signal processing devices 20 by adjusting the connections of the first signal processing device 20a and the second signal processing device 20b.

[0071] Figure 7 shows the view of the two signal processing devices 20 from the master device 10 according to this embodiment. In reality, as described above, two signal processing devices 20, the first signal processing device 20a and the second signal processing device 20b, are connected to the communication bus 12. However, these signal processing devices 20 are assigned the same identifier, and the master device 10 can communicate with the two signal processing devices 20 using the same identifier. Therefore, as shown in Figure 7, the master device 10 can communicate with the first signal processing device 20a and the second signal processing device 20b as if it were communicating with a single signal processing device 30 that has been assigned that identifier.

[0072] (modified version) In the above embodiment, an example was described in which an address map is used that separates data read / write addresses from data not read / written addresses. In the modified example, the first address map and the second address map share data read / write addresses, but include addresses that determine whether or not to allow access to those addresses. Other configurations and operations of the modified example are the same as in the above embodiment. Note that the configurations of the above embodiment and the modified example may be combined in any way.

[0073] Figure 8(a) shows a modified version of the first address map 320, and Figure 8(b) shows a modified version of the second address map 330.

[0074] The first address map 320 includes an unlock address 322, a lock address 324, and a read / write area 326. The read / write area 326 consists of subaddresses from 0x02 to 0xFF on which data is read and written. The unlock address 322 is a subaddress of 0x00 that permits access to the read / write area 326, and the lock address 324 is a subaddress of 0x01 that prohibits access to the read / write area 326.

[0075] If the first address map 320 is set in the storage unit 250, the signal processing unit 240 accesses either the unlock address 322 or the lock address 324 and processes the data according to the accessed address. Specifically, if the signal processing unit 240 accesses the unlock address 322, it permits access to the read / write area 326 and writes data to the read / write area 326. If the signal processing unit 240 accesses the lock address 324, it prohibits access to the read / write area 326. If the signal processing unit 20 is unable to read data from the read / write area 326 when access to the read / write area 326 is prohibited, it may output a signal Hiz to indicate this.

[0076] The second address map 330 includes a lock address 332, an unlock address 334, and a read / write area 336. The read / write area 336 consists of addresses from 0x02 to 0xFF where data is read and written, and is the same address as the write area 326 of the first address map 320. The lock address 332 is the address 0x00 which prohibits access to the read / write area 336, and the unlock address 334 is the address 0x01 which prohibits access to the read / write area 336. Thus, in the second address map 330, the lock address and unlock address are the opposite of those in the first address map 320.

[0077] If the second address map 330 is set in the storage unit 250, the signal processing unit 240 accesses the lock address 332 or unlock address 334 of the second address map 330 and processes the data according to the accessed address. Specifically, if the signal processing unit 240 accesses the lock address 332, access to the read / write area 336 is prohibited, and data cannot be written to the read / write area 326. The signal processing unit 20 prohibits access to the read / write area 326. If the signal processing unit 240 accesses the unlock address 334, access to the read / write area 326 is permitted, and data can be written to the read / write area 326. If the signal processing unit 20 is unable to read data from the read / write area 326 when access to the read / write area 326 is prohibited, it may output a signal Hiz to indicate this.

[0078] In this way, by reversing the addresses of the unlock address and the lock address in the first address map 320 and the second address map 330, the master device 10 can communicate with the two signal processing devices 20 in the same manner as in the above embodiment.

[0079] Furthermore, regarding the read / write areas 326 and 336 of the modified address map, as explained with reference to Figure 5, some addresses may be designated as address areas where data can be read and written, while other addresses may be designated as address areas where data cannot be read or written.

[0080] (Examples of application) The above embodiment mainly describes an example in which the master device 10 sends and receives data with either the first signal processing device 20a or the second signal processing device 20b in a single communication. The application example describes an example in which the master device 10 sends and receives signals with both the first signal processing device 20a and the second signal processing device 20b in a single communication. The other configurations and operations of the application example are the same as those of the above embodiment described with reference to Figures 3 and 4, etc. The configurations of the above embodiment, modified examples and application examples may be combined in any way.

[0081] Figure 9 shows the address maps set in the first signal processing device 20a and the second signal processing device 20b in the application example. In the address map of the first signal processing device 20a, subaddress (N) is set to setting A, and subaddress (N+1) is disabled. On the other hand, in the address map of the second signal processing device 20b, subaddress (N) is disabled, and subaddress (N+1) is set to setting A. Here, setting A is a setting that allows reading and writing of data at that address.

[0082] Figure 10(a) is a diagram illustrating the communication flow when data is written to the storage unit 250 of the signal processing device 20. The master device 10 transmits start information 400 to indicate the start of communication, and then transmits slave address information 402 which includes an instruction to write data. This slave address information 402 allows both the first signal processing device 20a and the second signal processing device 20b to recognize the communication.

[0083] Next, the master device 10 transmits write data 406 for subaddress (N). The data transmitted next is sent as write data 408 for the address following subaddress (N), i.e., subaddress (N+1), and finally, stop information 410 indicating the end of communication is transmitted. In response, the first signal processing device 20a writes data to subaddress (N), and the second signal processing device 20b writes data to subaddress (N+1).

[0084] Thus, in the first signal processing device 20a and the second signal processing device 20b, sub-address (N) and sub-address (N+1) are set to opposite settings, A and disabled. This allows the master device 10 to transmit data to the first signal processing device 20a and the second signal processing device 20b in a single communication by transmitting data to be written to two consecutive sub-addresses (i.e., sub-addresses (N) and (N+1)).

[0085] Figure 10(b) is a diagram illustrating the communication flow when data is read from the storage unit 250 of the signal processing device 20. The master device 10 transmits start information 420 to indicate the start of communication, and then transmits slave address information 422 which includes an instruction to read data. This slave address information 422 allows both the first signal processing device 20a and the second signal processing device 20b to recognize the communication.

[0086] Next, the first signal processing device 20a reads the data written to subaddress (N) and transmits the read data 424 to the master device 10. At this time, the first signal processing device 20a does not read the data at subaddress (N+1) and may output the signal Hiz. The second signal processing device 20b reads the data written to subaddress (N+1) and transmits the read data 426 to the master device 10. At this time, the second signal processing device 20b does not read the data at subaddress (N) and may output the signal Hiz. After that, stop information indicating the end of communication is transmitted, and the communication ends.

[0087] As shown in this application example, the signal processing system 1 according to this disclosure makes it possible to write and read data to two signal processing devices 20 in a single communication.

[0088] (supplement) While the embodiments described herein have been explained using specific terminology, this explanation is merely illustrative to aid understanding and does not limit the scope of this disclosure or the claims. The scope of the present invention is defined by the claims. Furthermore, not only the embodiments described herein, but also embodiments, examples, and modifications not described herein are included in the scope of the present invention.

[0089] (Note) The technology disclosed herein can be understood in one respect as follows:

[0090] (Item 1) A first terminal to which either the clock signal or the data signal is input, A second terminal to which the other of the clock signal and the data signal is input, A storage unit in which an address map is set that defines addresses where data writing is permitted and addresses where data writing is prohibited, A designation unit that specifies the address map to be set in the storage unit, The system includes a processing unit that writes data based on the data signal to the storage unit according to the address map specified by the designation unit, The designation unit designates a first address map when the clock signal is input to the first terminal and the data signal is input to the second terminal, and designates a second address map different from the first address map when the data signal is input to the first terminal and the clock signal is input to the second terminal. Signal processing device.

[0091] (Item 2) A first detection unit detects the start of communication based on the clock signal and the data signal when the clock signal is input to the first terminal and the data signal is input to the second terminal, The system further includes a second detection unit that detects the start of communication based on the clock signal and the data signal when a data signal is input to the first terminal and a clock signal is input to the second terminal, The designation unit specifies the first address map when the first detection unit detects a start, and specifies the second address map when the second detection unit detects a start. The signal processing device described in item 1.

[0092] (Item 3) Each of the first address map and the second address map includes the first address and the second address, The first address is an address in the first address map where data writing and reading are permitted and data writing and reading are performed, and an address in the second address map where data writing and reading are prohibited and data writing and reading are not performed. The second address is an address in the first address map where data writing and reading are prohibited and no data is written or read, and an address in the second address map where data writing and reading are permitted and data is written or read. A signal processing device as described in item 1 or 2.

[0093] (Item 4) Each of the first address map and the second address map includes a first address, a second address, and a write address to which data can be written. The first address allows writing data to the write address in the first address map, and prohibits writing data to the write address in the second address map. The above-mentioned second address prohibits writing data to the write address in the above-mentioned first address map, and permits writing data to the write address in the above-mentioned second address map. A signal processing device as described in item 1 or 2.

[0094] (Item 5) The system further includes an output control unit that causes the data written to the storage unit to be output from the first terminal or the second terminal according to the address map specified by the designation unit. A signal processing device described in any one of items 1 to 4.

[0095] (Item 6) A first signal processing device and a second signal processing device are each configured with a signal processing device described in any one of items 1 to 5, The first signal processing device is arranged such that the data signal is input to a first terminal of the first signal processing device and the clock signal is input to a second terminal of the first signal processing device. The second signal processing device is arranged such that the clock signal is input to the first terminal of the second signal processing device and the data signal is input to the second terminal of the second signal processing device. Signal processing system.

[0096] (Item 7) The data signal is configured such that data is written to the storage unit of the first signal processing device according to the first address map, and data is written to the storage unit of the second signal processing device according to the second address map. The signal processing system described in item 6. [Explanation of Symbols]

[0097] 1 Signal processing system, 20 Signal processing device, 202 First terminal, 204 Second terminal, 210 First detection unit, 212 Second detection unit, 220 Designation unit, 230 Discrimination unit, 240 Signal processing unit, 250 Storage unit, 260 Output control unit.

Claims

1. A first terminal to which either a clock signal or a data signal is input, A second terminal to which the other of the clock signal and the data signal is input, A storage unit in which an address map is set that defines addresses where data writing is permitted and addresses where data writing is prohibited, A designation unit that specifies the address map to be set in the storage unit, The system includes a processing unit that writes data based on the data signal to the storage unit according to the address map specified by the designation unit, The designation unit designates a first address map when the clock signal is input to the first terminal and the data signal is input to the second terminal, and designates a second address map different from the first address map when the data signal is input to the first terminal and the clock signal is input to the second terminal. Signal processing device.

2. A first detection unit detects the start of communication based on the clock signal and the data signal when the clock signal is input to the first terminal and the data signal is input to the second terminal, The system further includes a second detection unit that detects the start of communication based on the clock signal and the data signal when a data signal is input to the first terminal and a clock signal is input to the second terminal, The designation unit designates the first address map when the first detection unit detects a start, and the designation unit designates the second address map when the second detection unit detects a start. The signal processing apparatus according to claim 1.

3. Each of the first address map and the second address map includes the first address and the second address, The first address is an address in the first address map where data writing and reading are permitted and data writing and reading are performed, and an address in the second address map where data writing and reading are prohibited and data writing and reading are not performed. The second address is an address in the first address map where data writing and reading are prohibited and no data is written or read, and an address in the second address map where data writing and reading are permitted and data is written or read. The signal processing apparatus according to claim 1.

4. Each of the first address map and the second address map includes a first address, a second address, and a write address to which data can be written. The first address allows writing data to the write address in the first address map, and prohibits writing data to the write address in the second address map. The second address prohibits writing data to the write address in the first address map, and permits writing data to the write address in the second address map. The signal processing apparatus according to claim 1.

5. The system further includes an output control unit that causes the data written to the storage unit to be output from the first terminal or the second terminal according to the address map specified by the designation unit. The signal processing apparatus according to claim 1.

6. A first signal processing device and a second signal processing device, each configured with the signal processing device described in claim 1, The first signal processing device is arranged such that the data signal is input to a first terminal of the first signal processing device and the clock signal is input to a second terminal of the first signal processing device. The second signal processing device is configured such that the clock signal is input to the first terminal of the second signal processing device and the data signal is input to the second terminal of the second signal processing device. Signal processing system.

7. The data signal is configured such that data is written to the storage unit of the first signal processing device according to the first address map, and data is written to the storage unit of the second signal processing device according to the second address map. The signal processing system according to claim 6.

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