Device chip manufacturing method

Abstract

To provide a manufacturing method of a device chip, capable of etching a wafer with a bump without corrosion when dividing the wafer with the bump into an individual device chip.SOLUTION: A manufacturing method of a device chip includes at least: a first coating step 1001 of applying a liquid-like resin onto a wafer front surface, and coating the wafer front surface including a bump with a first protection film by a spin coat; a second coating step 1002 of coating an upper surface of the first protection film including the bump with a second protection film that is different from the first protection film by a plasma; a division step 1004 of dividing a wafer by a plasma etching into an individual device chip along a division schedule line; and a removal step 1005 of removing the first and second protection films.SELECTED DRAWING: Figure 2

Description

[[Technical Field]]

[0001] The present invention relates to a method for manufacturing a device chip. [[Background Art]]

[0002] A wafer having a plurality of devices such as ICs (Integrated Circuits) and LSIs (Large Scale Integrations) formed on the front surface thereof is ground on the back surface to have a predetermined thickness, then divided into individual device chips by a cutting apparatus, and used in electrical equipment such as mobile phones and personal computers.

[0003] In recent years, when mounting a device chip on a predetermined mounting substrate, a mounting technique called flip chip bonding has been put into practical use in order to save space in the area required for mounting.

[0004] In flip chip bonding, a plurality of projecting electrodes called bumps having a height of about 10 μm to 100 μm are formed via a wiring layer formed in a region partitioned by a plurality of planned dividing lines on the front surface (hereinafter, such a wafer is simply referred to as a bumped wafer), the wafer is divided into individual device chips along the planned dividing lines, and these projecting electrodes are opposed to electrodes formed on a mounting substrate and directly bonded, which is a mounting technique. The projecting electrodes function as terminals of the device chip.

[0005] Here, in recent years, as one of methods for dividing a wafer into individual device chips, a technique of dividing by a plasma etching method has been developed and put into practical use (see, for example, Patent Document 1).

[0006] Furthermore, during plasma etching, a technique has been developed and put into practical use in which a water-soluble protective film is coated on the wafer surface by spin coating, the water-soluble resin protective film in the region of the planned dividing lines is removed by laser irradiation, and plasma etching is performed using the water-soluble protective film as a mask (see, for example, Patent Document 2). [[Prior Art Documents]] [[Patent Documents]]

[0007] [Patent Document 1] Japanese Patent Publication No. 2006-108428 [Patent Document 2] Japanese Patent Publication No. 2016-207737 [Overview of the project] [Problems that the invention aims to solve]

[0008] However, when a water-soluble resin protective film is applied to the surface of a bumped wafer by spin coating, there is a problem that the tip region of the bump is not covered by the water-soluble resin protective film, especially when the bump is about 100 μm high.

[0009] If plasma etching is performed without a water-soluble resin protective film covering the tip region of the bump, the tip region of the bump will corrode, resulting in a deterioration of its electrical properties.

[0010] The object of the present invention is to provide a method for manufacturing device chips that allows for etching of a bumped wafer into individual device chips without corroding the bumps. [Means for solving the problem]

[0011] To solve the above-mentioned problems and achieve the objective, the present invention provides a method for manufacturing a device chip, which divides a wafer having a plurality of bumps formed in a region demarcated by a plurality of division lines on its surface into individual device chips along the division lines, comprising: a first coating step of applying a liquid resin to the wafer surface and coating the wafer surface, including the bumps, with a first protective film by spin coating; and a second coating step of coating the upper surface of the first protective film, including the bumps, with a second protective film different from the first protective film by plasma. After the second coating process A division step of dividing the wafer into individual device chips along the planned division line by plasma etching, After the division process The process comprises at least a removal step of removing the first protective film and the second protective film. The second coating process and the splitting process are carried out using the same plasma etching apparatus. It is characterized by the following:

[0012] This invention Device chip manufacturing method This is a method for manufacturing a device chip, which divides a wafer having a plurality of bumps formed in a region demarcated by a plurality of division lines on its surface into individual device chips along the division lines, comprising at least: a first coating step of applying a liquid resin to the wafer surface and coating the wafer surface, including the bumps, with a first protective film by spin coating; a second coating step of coating the upper surface of the first protective film, including the bumps, with a second protective film different from the first protective film by plasma; a division step of dividing the wafer into individual device chips along the division lines by plasma etching after the second coating step; and a removal step of removing the first protective film and the second protective film after the division step. The process includes a mask forming step, which is performed after the second coating step and before the division step, in which a laser beam is irradiated along the division line to remove the first protective film and the second protective film in the region corresponding to the division line to form a mask, The second coating step and the splitting step are characterized by being carried out using the same plasma etching apparatus. In the method for manufacturing the device chip, the second protective film is formed by a plasma-treated gas containing fluorinated carbon radicals. That's fine. [Effects of the Invention]

[0013] This invention offers the advantage of being able to etch a bumped wafer into individual device chips without corroding the bumps. [Brief explanation of the drawing]

[0014] [Figure 1] Figure 1 is a schematic perspective view showing an example of a wafer to be processed by the device chip manufacturing method according to Embodiment 1. [Figure 2] Figure 2 is a flowchart showing the flow of the manufacturing method for a device chip according to Embodiment 1. [Figure 3] Figure 3 is a schematic side view showing a partial cross-section of the first coating step of the device chip manufacturing method shown in Figure 2. [Figure 4] Figure 4 is a schematic cross-sectional view showing a portion of the wafer after the first coating step of the device chip manufacturing method shown in Figure 2. [Figure 5] Figure 5 is a schematic cross-sectional view showing an example of the configuration of a plasma etching apparatus used to perform the second coating step and the splitting step of the device chip manufacturing method shown in Figure 2. [Figure 6] Figure 6 is a schematic cross-sectional view showing a portion of the wafer after the second coating step of the device chip manufacturing method shown in Figure 2. [Figure 7]FIG. 7 is a side view schematically showing, in partial cross-section, a mask forming step in the method of manufacturing the device chip shown in FIG. 2. [Figure 8] FIG. 8 is a cross-sectional view schematically showing a part of a wafer after the mask forming step in the method of manufacturing the device chip shown in FIG. 2. [Figure 9] FIG. 9 is a cross-sectional view schematically showing a dividing step in the method of manufacturing the device chip shown in FIG. 2. [Figure 10] FIG. 10 is a cross-sectional view schematically showing a removing step in the method of manufacturing the device chip shown in FIG. 2. [Figure 11] FIG. 11 is a cross-sectional view schematically showing a part of a wafer to be processed in the method of manufacturing a device chip according to Embodiment 2. [Figure 12] FIG. 12 is a flowchart showing the flow of the method of manufacturing a device chip according to Embodiment 2. [Figure 13] FIG. 13 is a side view schematically showing, in partial cross-section, a removing step in the method of manufacturing a device chip according to a modified example of Embodiment 1 and Embodiment 2. DETAILED DESCRIPTION OF THE INVENTION

[0015] Modes (embodiments) for carrying out the present invention will be described in detail with reference to the drawings. The present invention is not limited by the content described in the following embodiments. In addition, the constituent elements described below include those that can be easily conceived by those skilled in the art and those that are substantially the same. Furthermore, the configurations described below can be combined as appropriate. In addition, various omissions, substitutions, or changes can be made to the configuration without departing from the gist of the present invention.

[0016] [Embodiment 1] A method of manufacturing a device chip according to Embodiment 1 of the present invention will be described based on the drawings. FIG. 1 is a perspective view schematically showing an example of a wafer to be processed in the method of manufacturing a device chip according to Embodiment 1. FIG. 2 is a flowchart showing the flow of the method of manufacturing a device chip according to Embodiment 1.

[0017] (wafer) The device chip manufacturing method according to Embodiment 1 is a method for processing the wafer 1 shown in Figure 1. In Embodiment 1, the wafer 1 to be processed in the device chip manufacturing method is a disc-shaped semiconductor wafer with silicon or the like as the substrate 2. As shown in Figure 1, devices 5 are formed in each region of the wafer 1 that are demarcated by a plurality of division lines 4 on the surface 3.

[0018] Device 5 is, for example, an integrated circuit such as an IC (Integrated Circuit) or LSI (Large Scale Integration), or various types of memory (semiconductor memory device). In Embodiment 1, device 5 also includes conductive spherical bumps 6 connected to electrodes of a wiring layer, etc. That is, wafer 1 has a plurality of bumps 6 formed in regions demarcated by a plurality of division lines 4 on its surface 3. In Embodiment 1, the bumps 6 are formed in a spherical shape with a diameter of about 100 μm. That is, the height of the bumps 6 from the surface 3 is about 100 μm.

[0019] Wafer 1 is divided into individual device chips 10 along the division line 4. Each device chip 10 includes a portion of the substrate 2 and a device 5. In Embodiment 1, wafer 1 is divided into device chips 10, each device 5 having bumps 6, which are mounted on the mounting substrate using a mounting technique called flip-chip bonding. In Embodiment 1, the surface of the division line 4 and the surface of the device 5 lie on the same plane.

[0020] (Method of manufacturing device chips) The device chip manufacturing method according to Embodiment 1 is a method of dividing wafer 1 into individual device chips 10 along a division line 4. The device chip manufacturing method according to Embodiment 1 is also a method of dividing wafer 1 into device chips 10 by plasma etching, or so-called plasma dicing. As shown in Figure 2, the device chip manufacturing method comprises a first coating step 1001, a second coating step 1002, a mask formation step 1003, a division step 1004, and a removal step 1005.

[0021] (First coating process) Figure 3 is a schematic side view showing a partial cross-section of the first coating step of the device chip manufacturing method shown in Figure 2. Figure 4 is a schematic cross-sectional view showing a part of the wafer after the first coating step of the device chip manufacturing method shown in Figure 2. The first coating step 1001 is a step in which liquid resin 25 is applied to the surface 3 of the wafer 1 and a first protective film 11 is coated on the surface 3 of the wafer 1, including the bumps 6, by spin coating.

[0022] In Embodiment 1, the first coating step 1001 involves first attaching the central part of a disc-shaped tape 8, which has a larger diameter than the wafer 1, to the back surface 7 of the wafer 1, and then attaching an annular frame 9, whose inner diameter is larger than the outer diameter of the wafer 1, to the outer edge of the tape 8. In Embodiment 1, the tape 8 is an adhesive tape comprising a base material made of a resin having non-adhesive properties and flexibility, and an adhesive layer laminated on the base material and made of a resin having adhesive properties and flexibility, wherein the adhesive layer is attached to the wafer 1 and the frame 9, or a sheet consisting only of a base material made of a thermoplastic resin without an adhesive layer and which is heat-pressed to the wafer 1 and the frame 9.

[0023] In Embodiment 1, in the first coating step 1001, the back surface 7 side of the wafer 1 is placed on the holding surface 22 of the spinner table 21 of the spin coater 20 shown in Figure 3 via tape 8, the back surface 7 side of the wafer 1 is held in place by suction on the holding surface 22 via tape 8, and the frame 9 is clamped by clamp parts 23 provided around the spinner table 21. In Embodiment 1, in the first coating step 1001, the spin coater 20 applies liquid resin 25 to the center of the surface 3 of the wafer 1 from the coating nozzle 24 above the wafer 1 while rotating the spinner table 21 around its axis, as shown in Figure 3. The liquid resin 25 applied to the surface 3 of the wafer 1 is then spread to the outer edge of the wafer 1 by the centrifugal force generated by the rotation of the spinner table 21, covering the entire surface 3 of the wafer 1.

[0024] Thus, in Embodiment 1, the first coating step 1001 is performed by so-called spin coating, in which liquid resin 25 is supplied and applied to the wafer 1 held on a spinner table 21 that rotates around its axis. In Embodiment 1, the first coating step 1001 is performed by drying the liquid resin 25 to form a first protective film 11 that covers the surface 3 of the wafer 1, as shown in Figure 4.

[0025] In Embodiment 1, the liquid resin 25 is, for example, a liquid water-soluble resin such as polyvinyl alcohol (PVA) or polyvinylpyrrolidone (PVP) (for example, HogoMax®, manufactured by Disco Corporation). However, in the present invention, the liquid resin 25 may also be a liquid resin that constitutes a resist used in the photolithography process. Furthermore, the liquid resin 25 is resistant to the plasma-generated etching gas used in the splitting process 1004.

[0026] The first protective film 11, formed on the entire surface 3 of the wafer 1 after the liquid resin 25 dries, is made of the aforementioned liquid resin 25 and is therefore made of a material that is resistant to the plasma-generated etching gas used in the splitting process 1004. In addition, in Embodiment 1, since bumps 6 are formed on the surface 3 of the wafer 1, the liquid resin 25 is not applied to the upper end of the bumps 6, and as shown in Figure 4, the first protective film 11 does not cover the upper end of the bumps 6, leaving the upper end of the bumps 6 exposed.

[0027] (Plasma etching equipment) Next, the plasma etching apparatus 30 that performs the second coating step 1002 and the splitting step 1004 will be described based on the drawings. Figure 5 is a schematic cross-sectional view showing an example of the configuration of a plasma etching apparatus that performs the second coating step and the splitting step of the device chip manufacturing method shown in Figure 2. As shown in Figure 5, the plasma etching apparatus 30 includes a holding table 31, a gas ejection head 32, a rectangular parallelepiped chamber 33 that houses the holding table 31 and the gas ejection head 32, and a control unit (not shown).

[0028] In Embodiment 1, the plasma etching apparatus 30 is a capacitively coupled plasma (CCP) system as shown in Figure 5. However, the present invention is not limited to this. For example, it may be an inductively coupled plasma (ICP) system in which high-frequency power for plasma generation is applied to a dielectric coil, and the etching gas is converted into plasma through interaction with the magnetic field formed on the dielectric coil. Alternatively, it may be an electron cyclotron resonance (ECR) system in which plasma is generated by utilizing the cyclotron resonance of electrons with a combination of microwaves of predetermined wavelengths.

[0029] Chamber 33 has a processing space 331 formed inside where plasma etching is performed. Chamber 33 has an opening 333 for loading and unloading wafers 1 and an opening / closing door 334 on one side wall 332 that opens and closes the opening 333. The opening / closing door 334 opens and closes the opening 333 by raising and lowering it with an opening / closing mechanism (not shown) consisting of an air cylinder or the like.

[0030] Furthermore, the chamber 33 has an exhaust port 337 formed in its bottom wall 336, which connects the inside and outside of the chamber 33. An exhaust device 338, such as a vacuum pump, is connected to the exhaust port 337.

[0031] The holding table 31 has a top surface that is formed flat horizontally to form a holding surface 311 for holding the wafer 1, and is made of a dielectric material such as ceramic. The holding table 31 is supported from below by a support member 312 whose lower end is fixed to the bottom wall 336 of the chamber 33. An electrode 315 is embedded inside the holding table 311, arranged parallel to the holding surface 311 and connected to a matching unit 313 and a bias high-frequency power supply 314. The electrode 315 is a so-called electrostatic chuck (ESC) that, when a voltage is applied from the bias high-frequency power supply 314 via the matching unit 313, generates a dielectric polarization phenomenon between the holding surface 311 and the wafer 1 on the holding surface 311, and holds the wafer 1 on the holding surface 311 by electrostatic attraction force generated by the polarization of the charge.

[0032] A water passage (not shown) is formed inside the holding table 31, and the holding table 31 is cooled from the inside to a predetermined temperature by cooling water circulating through the water passage. In addition, a heat transfer gas such as He gas flows at a predetermined pressure between the holding surface 311 and the wafer 1 held by the holding surface 311 in order to improve the heat absorption efficiency of the wafer 1 by the cooling water. In Embodiment 1, the holding table 31 is a unipolar electrostatic chuck as shown in Figure 5, but the present invention is not limited to this, and for example, a bipolar electrostatic chuck may also be used.

[0033] The gas ejection head 32 is mounted on the ceiling wall 339 of the chamber 33 via a bearing 321 so as to be able to move up and down, and faces the holding surface 311 of the holding table 31. The gas ejection head 32 is provided with a gas diffusion space 322, through which a gas inlet hole 323 passes over the upper part of the gas diffusion space 322, and through which multiple gas discharge holes 324 pass over the lower part of the gas diffusion space 322. Each gas discharge hole 324 opens toward the holding surface 311 of the holding table 31. The gas inlet hole 323 is connected to the first gas supply unit 34, the second gas supply unit 35, the third gas supply unit 36, and the fourth gas supply unit 37.

[0034] The first gas supply unit 34 supplies CF (fluorocarbon) gas, CH (hydrocarbon) gas, CN (cyanide) gas, CO (carbon oxide) gas, or CCl (carbon chloride) gas to the processing space 331 in the chamber 33 via the gas diffusion space 322 and gas discharge hole 324 of the gas ejection head 32. In Embodiment 1, the gas supplied by the first gas supply unit 34 is CF4 gas, but in the present invention, it is not limited to CF4 gas, but any CF gas, CH gas, CN gas, CO gas, or CCl gas may be used, for example, C4F8 gas.

[0035] The second gas supply unit 35 supplies etching gas to the processing space 331 in the chamber 33 via the gas diffusion space 322 and gas discharge hole 324 of the gas ejection head 32. In Embodiment 1, the etching gas supplied by the second gas supply unit 35 is SF6 gas, but the present invention is not limited to SF6 gas.

[0036] The third gas supply unit 36 ​​supplies oxygen (O2) gas to the processing space 331 in the chamber 33 via the gas diffusion space 322 and gas discharge hole 324 of the gas ejection head 32. The fourth gas supply unit 37 supplies inert gas to the processing space 331 in the chamber 33 via the gas diffusion space 322 and gas discharge hole 324 of the gas ejection head 32. In Embodiment 1, the inert gas supplied by the fourth gas supply unit 37 is argon (Ar) gas, but the present invention is not limited to argon gas.

[0037] A high-frequency power supply 326 is connected to the gas ejection head 32 via a matching circuit 325. High-frequency power is supplied from the high-frequency power supply 326 to the gas ejection head 32 via the matching circuit 325.

[0038] The control unit controls each component of the plasma etching apparatus 30 to cause the plasma etching apparatus 30 to perform plasma etching on the wafer 1. The control unit is a computer having a processing unit with a microprocessor such as a CPU (central processing unit), a storage device with memory such as ROM (read-only memory) or RAM (random access memory), and an input / output interface device. The processing unit of the control unit performs calculations according to the computer program stored in the storage device and outputs control signals for controlling the plasma etching apparatus 30 to each component of the plasma etching apparatus 30 via the input / output interface device.

[0039] Furthermore, the control unit is connected to a display unit, which consists of a liquid crystal display device that displays various information and images, and an input unit used by the operator to register processing details and other information. The input unit consists of at least one of the following: a touch panel provided on the display unit and an external input device such as a keyboard.

[0040] (Second coating process) Figure 6 is a schematic cross-sectional view showing a portion of the wafer after the second coating step of the device chip manufacturing method shown in Figure 2. The second coating step 1002 is a step in which a second protective film 12, which is different from the first protective film 11, is coated onto the upper surface of the first protective film 11, including the bumps 6, by plasma.

[0041] In Embodiment 1, in the second coating step 1002, the plasma etching apparatus 30 raises the gas ejection head 32 and lowers the opening / closing door 334 using an opening / closing mechanism to open the opening 333. In the second coating step 1002, the plasma etching apparatus 30 receives the wafer 1 coated with the first protective film 11 in the first coating step 1001 into the processing space 331 by a transport unit (not shown), and the back surface 7 of the wafer 1 is placed on the holding surface 311 of the holding table 31 via tape 8.

[0042] In the second coating step 1002, the plasma etching apparatus 30 raises the opening / closing door 334 using an opening / closing mechanism to close the opening 333, and depressurizes the processing space 331 inside the chamber 33 using an exhaust device 338. In the second coating step 1002, the plasma etching apparatus 30 lowers the gas ejection head 32 to a predetermined height, supplies CF4 gas from the first gas supply unit 34 into the processing space 331 inside the chamber 33, and supplies Ar gas from the fourth gas supply unit 37 into the processing space 331 inside the chamber 33.

[0043] Furthermore, in the second coating process 1002, the plasma etching apparatus 30 applies high-frequency power from the high-frequency power supply 326 to the gas ejection head 32 to generate a high-frequency electric field between the gas ejection head 32 and the holding table 31. In parallel with this, the plasma etching apparatus 30 applies a voltage from the bias high-frequency power supply 314 to the electrode 315 to generate a dielectric polarization phenomenon between the holding surface 311 of the holding table 31 and the wafer 1, and the wafer 1 is held and adsorbed on the holding surface 311 by the electrostatic adsorption force generated by the polarization of the charge.

[0044] The CF4 gas supplied from the first gas supply unit 34 and the Ar gas supplied from the fourth gas supply unit 37 are mixed and plasma-formed. The plasma-formed gas is then supplied to the wafer 1, and the CF radicals contained in the gas are deposited on the surface 3 side of the wafer 1. As a result, as shown in Figure 6, an insulating second protective film 12 containing carbon fluoride is formed on the upper end of the bump 6 on the surface 3 side of the wafer 1 and on the first protective film 11.

[0045] The second protective film 12, which contains fluorocarbon, is resistant to the plasma-generated etching gas used in the splitting process 1004. In Embodiment 1, the plasma etching apparatus 30 supplies CF4 gas from the first gas supply unit 34, and the second protective film 12 is composed of fluorocarbon. However, in the present invention, depending on the gas supplied from the first gas supply unit 34, it may be composed of hydrocarbon, cyanide, carbon oxide, or carbon chloride.

[0046] In the second coating step, the plasma etching apparatus 30 coats the wafer 1 with a second protective film 12, and then proceeds to the mask formation step 1003.

[0047] (Mask formation process) Figure 7 is a schematic side view showing a partial cross-section of the mask formation process of the device chip manufacturing method shown in Figure 2. Figure 8 is a schematic cross-sectional view showing a portion of the wafer after the mask formation process of the device chip manufacturing method shown in Figure 2. The mask formation process 1003 is a step that takes place after the second coating process 1002 and before the division process 1004, in which a laser beam 42 (shown in Figure 7) is irradiated along the division line 4 to remove the first protective film 11 and the second protective film 12 in the region corresponding to the division line 4 to form a mask 13 (shown in Figure 8).

[0048] In Embodiment 1, in the mask formation step 1003, the back surface 7 of the wafer 1 is held by suction to the holding surface of the chuck table via tape 8 in the laser processing apparatus 40 shown in Figure 7, and the frame 9 is clamped by clamps provided around the chuck table. In Embodiment 1, in the mask formation step 1003, the surface 3 of the wafer 1 is imaged with an imaging camera provided in the laser processing apparatus 40, and alignment is performed to align the planned division lines 4 of the wafer 1 with the focusing lens of the laser light irradiation unit 41.

[0049] In Embodiment 1, during the mask formation process 1003, the laser processing apparatus 40, as shown in Figure 8, moves the chuck table and the laser light irradiation unit 41 relative to each other along the division line 4, positions the focal point on the protective films 11 and 12 on the division line 4, and irradiates the protective films 11 and 12 on each division line 4 with laser light 42 of a wavelength that is absorbed by the protective films 11 and 12, thereby removing the protective films 11 and 12 on the division line 4. In Embodiment 1, during the mask formation process 1003, the laser processing apparatus 40 forms an opening 14 along the division line 4 in the protective films 11 and 12 over the entire length of each division line 4, thereby forming the protective films 11 and 12 on a mask 13 with the opening 14 formed as shown in Figure 8. The opening 14 exposes the division line 4, i.e., the surface 3 of the wafer 1, at its bottom.

[0050] (splitting process) Figure 9 is a schematic cross-sectional view showing the division process of the device chip manufacturing method shown in Figure 2. The division process 1004 is a process of dividing the wafer 1 into individual device chips 10 along the division line 4 by plasma etching.

[0051] In Embodiment 1, during the splitting process 1004, the plasma etching apparatus 30 raises the gas ejection head 32 and lowers the opening / closing door 334 using an opening / closing mechanism to open the opening 333. During the splitting process 1004, the plasma etching apparatus 30 receives the wafer 1, on which the mask 13 was formed in the mask formation process 1003, into the processing space 331 via a transport unit (not shown), and the back surface 7 of the wafer 1 is placed on the holding surface 311 of the holding table 31 via tape 8.

[0052] In the splitting process 1004, the plasma etching apparatus 30 raises the opening / closing door 334 using an opening / closing mechanism to close the opening 333, and depressurizes the processing space 331 inside the chamber 33 using an exhaust device 338. In the splitting process 1004, the plasma etching apparatus 30 lowers the gas ejection head 32 to a predetermined height and supplies SF6 gas as etching gas into the processing space 331 of the chamber 33 from the second gas supply unit 35.

[0053] In addition, during the splitting process 1004, the plasma etching apparatus 30 applies high-frequency power from the high-frequency power supply 326 to the gas ejection head 32 to generate a high-frequency electric field between the gas ejection head 32 and the holding table 31, thereby plasmaizing the SF6 gas supplied from the second gas supply unit 35 as the etching gas. In parallel with this, the plasma etching apparatus 30 applies a voltage from the bias high-frequency power supply 314 to the electrode 315 to generate a dielectric polarization phenomenon between the holding surface 311 of the holding table 31 and the wafer 1, and the wafer 1 is held on the holding surface 311 by the electrostatic attraction force generated by the polarization of the charge.

[0054] In the splitting process 1004, plasma-enhanced SF6 gas is supplied to the wafer 1, etching the planned splitting lines 4 exposed through the opening 14 to form etching grooves 15, and the etching grooves 15 are advanced toward the back surface 7. In the splitting process, as shown in Figure 9, the plasma etching apparatus 30 causes the etching grooves 15 to reach the tape 8, splitting the wafer 1 into individual device chips 10, and then proceeds to the removal process 1005.

[0055] (Removal process) Figure 10 is a schematic cross-sectional view showing the removal process of the device chip manufacturing method shown in Figure 2. The removal process 1005 is the process of removing the mask 13, i.e., the first protective film 11 and the second protective film 12.

[0056] In Embodiment 1, during the removal step 1005, the plasma etching apparatus 30 stops supplying SF6 gas from the second gas supply unit 35 to the processing space 331 of the chamber 33 as etching gas, and instead supplies oxygen gas from the third gas supply unit 36 ​​to the processing space 331 of the chamber 33. As a result, the oxygen gas supplied from the third gas supply unit 36 ​​is converted into plasma.

[0057] In the removal step 1005, plasma-treated oxygen gas is supplied to the wafer 1 to ash and remove the mask 13. In the removal step, the plasma etching apparatus 30 removes the mask 13, i.e., the protective films 11 and 12, from the surface 3 of the wafer 1, as shown in Figure 10, and the manufacturing method of the device chip is completed.

[0058] In the device chip manufacturing method according to Embodiment 1 described above, in the first coating step 1001, the surface 3 of the wafer 1 is coated with a first protective film 11 using a liquid resin 25 by so-called spin coating, and then in the second coating step 1002, the surface 3 of the wafer 1 is coated with a second protective film 12 using plasma. For this reason, in the device chip manufacturing method according to Embodiment 1, the upper end of the bump 6 can also be coated with the second protective film 12.

[0059] As a result, the device chip manufacturing method according to Embodiment 1 has the effect of being able to etch the bumps 6 without corroding them when dividing the wafer 1 with bumps 6 into individual device chips 10 by etching.

[0060] [Embodiment 2] Next, the method for manufacturing a device chip according to Embodiment 2 will be described based on the drawings. Figure 11 is a schematic cross-sectional view showing a part of the wafer to be processed in the method for manufacturing a device chip according to Embodiment 2. Figure 12 is a flowchart showing the flow of the method for manufacturing a device chip according to Embodiment 2. Note that the same reference numerals are used for the same parts as in Embodiment 1 in Figures 11 and 12, and their descriptions are omitted.

[0061] As shown in Figure 11, the wafer 1 to be processed in the device chip manufacturing method according to Embodiment 2 has the planned division line 4 formed in a recessed groove from the surface 3. As shown in Figure 12, the device chip manufacturing method according to Embodiment 2 comprises a first coating step 1001, a second coating step 1002, a division step 1004, and a removal step 1005, but does not include a mask formation step 1003.

[0062] In the device chip manufacturing method according to Embodiment 2, when forming the first protective film 11 by applying liquid resin 25 by spin coating in the first coating step 1001, the liquid resin 25 flows outward along the division line 4 formed in the groove due to the centrifugal force of the rotation of the spinner table 21, and the first protective film 11 is not formed on the division line 4. For this reason, in the device chip manufacturing method according to Embodiment 2, etching grooves 15 can be formed on the division line 4 of the wafer 1 in the division step 1004 without performing the mask formation step 1003, thereby dividing the wafer 1 into individual device chips 10.

[0063] In the device chip manufacturing method according to Embodiment 2, in the first coating step 1001, the surface 3 of the wafer 1 is coated with a first protective film 11 by so-called spin coating, and in the second coating step 1002, the surface 3 of the wafer 1 is coated with a second protective film 12 by plasma. As a result, the upper end of the bump 6 can also be coated with the second protective film 12, and, similar to Embodiment 1, when the wafer 1 with the bump 6 is divided into individual device chips 10 by etching, the bump 6 can be etched without corrosion.

[0064] [Variation] Next, the manufacturing methods for device chips according to modified examples of Embodiment 1 and Embodiment 2 will be described based on the drawings. Figure 13 is a schematic side view showing a partial cross-section of the removal process of the manufacturing method for device chips according to modified examples of Embodiment 1 and Embodiment 2. Note that in Figure 13, the same reference numerals are used for the same parts as in Embodiment 1, and their descriptions are omitted.

[0065] In the modified device chip manufacturing method, in the removal step 1005, the second protective film 12 is removed by ashing with a plasma etching apparatus 30, similar to Embodiments 1 and 2, and then the first protective film 11 is removed with a cleaning apparatus 50 shown in Figure 13.

[0066] In the removal step 1005 of the modified version, when removing the first protective film 11, the cleaning device 50 shown in Figure 13 places the back surface 7 side of the wafer 1 on the holding surface 52 of the spinner table 51 via tape 8, holds the back surface 7 side of the wafer 1 on the holding surface 52 via tape 8, and clamps the frame 9 with clamp parts 53 provided around the spinner table 51. In the removal step 1005 of the modified version, when removing the first protective film 11, the cleaning device 50 rotates the spinner table 51 around its axis and supplies a cleaning solution, such as pure water, from a cleaning nozzle 54 above the wafer 1 to the center of the surface 3 of the wafer 1. The cleaning solution supplied to the surface 3 of the wafer 1 flows toward the outer edge of the wafer 1 due to the centrifugal force generated by the rotation of the spinner table 51, washing away the first protective film 11 from the surface 3 of the wafer 1.

[0067] In the modified device chip manufacturing method, in the first coating step 1001, the surface 3 of the wafer 1 is coated with a first protective film 11 by so-called spin coating, and in the second coating step 1002, the surface 3 of the wafer 1 is coated with a second protective film 12 by plasma. As a result, the upper end of the bump 6 can also be covered with the second protective film 12, and, similar to Embodiment 1, when the wafer 1 with the bump 6 is divided into individual device chips 10 by etching, the bump 6 can be etched without corrosion.

[0068] It should be noted that the present invention is not limited to the embodiments described above. That is, it can be implemented with various modifications without departing from the core principles of the present invention. [Explanation of Symbols]

[0069] 1 wafer 3 surface 4 planned division lines 6 Bump 10 device chips 11. First protective film 12. Second protective layer 13 masks 25 Liquid resin 1001 First coating process 1002 Second coating process 1003 Mask Forming Process 1004 Division process 1005 Removal process

Claims

1. A method for manufacturing a device chip, comprising dividing a wafer having multiple bumps formed in regions demarcated by multiple division lines on its surface into individual device chips along the division lines, A first coating step involves applying a liquid resin to the wafer surface and coating the wafer surface, including the bumps, with a first protective film by spin coating. A second coating step involves coating the upper surface of the first protective film, including the bump, with a second protective film different from the first protective film using plasma, A division step is performed after the second coating step, in which the wafer is divided into individual device chips along the planned division line by plasma etching, A removal step is performed after the dividing step to remove the first protective film and the second protective film, It consists of at least the following: A method for manufacturing a device chip, wherein the second coating step and the splitting step are performed using the same plasma etching apparatus.

2. A method for manufacturing a device chip, comprising dividing a wafer having multiple bumps formed in regions demarcated by multiple division lines on its surface into individual device chips along the division lines, A first coating step involves applying a liquid resin to the wafer surface and coating the wafer surface, including the bumps, with a first protective film by spin coating. A second coating step involves coating the upper surface of the first protective film, including the bump, with a second protective film different from the first protective film using plasma, A division step is performed after the second coating step, in which the wafer is divided into individual device chips along the planned division line by plasma etching, A removal step is performed after the dividing step to remove the first protective film and the second protective film, It consists of at least the following: The process includes a mask forming step, which is performed after the second coating step and before the division step, in which a laser beam is irradiated along the division line to remove the first protective film and the second protective film in the region corresponding to the division line to form a mask, A method for manufacturing a device chip, wherein the second coating step and the splitting step are performed using the same plasma etching apparatus.

3. The method for manufacturing a device chip according to claim 1 or claim 2, wherein the second protective film is formed by a plasma-formed gas containing fluorinated carbon radicals.

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