Semiconductor memory devices

Abstract

To suppress reduction in data processing performance during mask write processing in a semiconductor memory device.SOLUTION: A semiconductor memory devices 100, 100A which can execute a mask write process includes: a plurality of banks B0-B7 comprising a data recording unit 30 on which write data is recorded and an ECC code recording unit 40 on which error correction codes corresponding to the write data are recorded; sense amplifiers SA for reading / writing data to / from the banks; an ECC code generation unit 22 which generates the error correction codes; an error correction unit 21 which corrects an error of the data using the error correction codes; first buses MRB, RR, LRB connecting the sense amplifiers and the error correction unit and transferring the data output from the sense amplifiers to the error correction unit; and second buses MWB, WR, LWB connecting the ECC code generation unit and the sense amplifiers and transferring the data output from the ECC code generation unit to the sense amplifiers.SELECTED DRAWING: Figure 1

Description

[[Technical Field]]

[0001] The present disclosure relates to a semiconductor memory device. [[Background Art]]

[0002] As a semiconductor memory device, for example, a Dynamic Random Access Memory (DRAM) that includes an ECC (Error Check and Correct) function and autonomously performs data error correction processing may be used. Also, there is known a DRAM having an ECC function that enables a masked write processing of rewriting only part of data when writing data to a semiconductor memory device (Patent Document 1). In the semiconductor memory device described in Patent Document 1, a plurality of masked write processes targeting different banks to which data is to be written are pipelined, thereby suppressing a decrease in data processing performance of the semiconductor memory device. [[Prior Art Documents]] [[Patent Documents]]

[0003] [[Patent Document 1]] US Patent Application Publication No. 2022 / 0245031A1 Specification [[Summary of the Invention]] [[Problem to be Solved by the Invention]]

[0004] However, when a plurality of masked write processes targeting the same bank to be accessed are continuously executed, the next masked write process cannot be executed until after the previous series of processes is completed, which causes a problem that data processing performance decreases. [[Means for Solving the Problem]]

[0005] The present disclosure can be implemented in the following modes.

[0006] According to one embodiment of this disclosure, (100, 100A) is provided. This semiconductor memory device is a semiconductor memory device (100, 100A) capable of performing mask write processing to rewrite data with a data length smaller than a preset data access unit, and comprises a plurality of banks (B0 to B7) having a data recording unit (30) on which write data is recorded and an ECC code recording unit (40) on which an error correction code corresponding to the write data is recorded; a sense amplifier (SA) provided in each of the plurality of banks for reading and writing data to each of the banks; an ECC code generation unit (22) for generating the error correction code; an error correction unit (21) for performing error correction of data using the error correction code; a first bus (MRB, RR, LRB) connecting each of the sense amplifiers and the error correction unit and transmitting data output from each of the sense amplifiers to the error correction unit; and a second bus (MWB, WR, LWB) connecting the ECC code generation unit and each of the sense amplifiers and transmitting data output from the ECC code generation unit to each of the sense amplifiers.

[0007] This type of control device includes a first bus and a second bus, allowing for parallel execution of data output from the sense amplifier to the error correction unit and data input from the ECC code generation unit to the sense amplifier within the same bank. Therefore, even when multiple mask write operations are performed consecutively for the same bank, if the columns to be accessed are different, the next mask write operation can be executed in parallel without waiting for the previous mask write operation to finish, thereby suppressing a decrease in data processing performance. [Brief explanation of the drawing]

[0008] [Figure 1] This is an explanatory diagram showing the schematic configuration of a semiconductor memory device according to the first embodiment. [Figure 2] This is a flowchart showing the procedure for mask light processing in the first embodiment. [Figure 3] This is a flowchart showing the procedure for mask light processing in the first embodiment. [Figure 4] This is a timing chart showing an example of operation in the semiconductor memory device of the first embodiment. [Figure 5] This is an explanatory diagram showing the schematic configuration of a semiconductor memory device according to the second embodiment. [Figure 6] This is a flowchart showing the procedure for mask light processing in the second embodiment. [Figure 7] This is a flowchart showing the procedure for mask light processing in the second embodiment. [Figure 8] This is a flowchart showing the procedure for mask light processing in the second embodiment. [Figure 9] This is a timing chart showing an example of operation in the semiconductor memory device of the second embodiment. [Modes for carrying out the invention]

[0009] A. First Embodiment: A-1.Device configuration: The semiconductor memory device 100 in this embodiment reads and writes data in response to requests from the arithmetic unit 200, such as a CPU or GPU (Graphics Processing Unit). In this embodiment, the semiconductor memory device 100 is configured as LPDDR4 (Low Power DDR4) and is configured to perform mask write processing in addition to normal data writing write processing. "Mask write processing" is a process in which a portion of the data read in a data access unit predetermined in the specifications of the semiconductor memory device 100 is overwritten with newly input data of a smaller data length than the said access unit and written back. In the following description, the command issued by the arithmetic unit 200 to request mask write processing will also be called a "mask write command".

[0010] In the following description, data with a data length smaller than the data access unit will also be referred to as "mask data." Data whose portion is overwritten by the mask data will also be referred to as "data to be overwritten." Furthermore, the bit sequence of the data to be overwritten by the mask data will also be referred to as the "part to be overwritten." In this embodiment, the mask data includes address information indicating the address of the storage area where the data to be overwritten is held, and information indicating which bit sequence of the data to be overwritten will be designated as the part to be overwritten.

[0011] As shown in Figure 1, the semiconductor memory device 100 of this embodiment includes an input / output circuit 10, an input / output bus IOB, a plurality of banks B0 to B7, an ECC calculation circuit 20, a main read bus MRB, and a main write bus MWB. In addition to the above configuration, the semiconductor memory device 100 also includes a clock generation circuit and various decoders, but these are the same as those of a typical LPDDR4, so they are not shown in Figure 1.

[0012] The input / output circuit 10 controls the input and output of data to and from the arithmetic unit 200. More specifically, the input / output circuit 10 inputs and outputs data according to a clock signal supplied from outside the semiconductor memory device 100, or a clock signal generated by a clock generation circuit (not shown) in the semiconductor memory device 100. In this embodiment, the input / output circuit 10 has a data bus inversion (DBI) function. If the data input from the arithmetic unit 200 is bit-inverted, the input / output circuit 10 restores the original data by bit-inverting it again. In this way, when transmitting data containing many "0"s, which consume more power than "1", the DBI processing using the DBI function can be performed, thereby suppressing power consumption during data transmission. Note that the semiconductor memory device 100 does not necessarily have a DBI function.

[0013] Banks B0 to B7 each contain a memory area ST, a sense amplifier SA, a read register RR, a write register WR, a local read bus LRB, and a local write bus LWB. The memory area ST is formed by arranging memory cells, which are memory elements, in a matrix. Of banks B0 to B7, the memory areas ST of banks B0 to B3 function as data recording units 30 that hold written data written from the arithmetic unit 200. Of banks B0 to B7, the memory areas ST of banks B4 to B7 function as ECC code recording units 40 that hold ECC codes generated by the ECC code generation unit 22 (described later) in correspondence with the data written to the data recording units 30.

[0014] The sense amplifier SA is connected to the memory area ST and performs data reading from and writing to the memory area ST. More specifically, when reading data from the memory area ST in accordance with a command issued from the arithmetic unit 200, the sense amplifier SA reads the data held in the memory cell specified by the row address selected by the row decoder (not shown) according to the address specified by the received active command. On the other hand, when writing data to the memory area ST in accordance with a command issued from the arithmetic unit 200, the sense amplifier SA writes the data held in the memory cell specified by the row address specified when the active command was issued, according to the received precharge command.

[0015] The read register RR is connected to the sense amplifier SA via the local read bus LRB and to the ECC calculation circuit 20 via the main read bus MRB. When the sense amplifier SA outputs data outside its bank, the read register RR temporarily holds the data output from the sense amplifier SA via the local read bus LRB and outputs the data to the ECC calculation circuit 20 via the main read bus MRB.

[0016] The write register WR is mutually connected to the sense amplifier SA via the local write bus LWB, and is mutually connected to the ECC arithmetic circuit 20 via the main write bus MWB. When inputting data to the sense amplifier SA from outside the bank, the write register WR temporarily holds data input from the ECC arithmetic circuit 20 via the main write bus MWB, and inputs the data to the sense amplifier SA via the local write bus LWB. Data output from the sense amplifier SA to the read register RR via the local read bus LRB and data input from the write register WR to the sense amplifier SA via the local write bus LWB can each be executed in parallel with each other.

[0017] The ECC arithmetic circuit 20 is mutually connected to the input / output circuit 10 via the input / output bus IOB. The ECC arithmetic circuit 20 includes an error correction unit 21 and an ECC code generation unit 22.

[0018] The error correction unit 21 is mutually connected to each of the read registers RR included in each bank via the main read bus MRB. As described above, in the semiconductor memory device 100, a data transmission path that connects the sense amplifier SA and the error correction unit 21 to each other is formed by each local read bus LRB included in each bank, each read register RR included in each bank, and the main read bus MRB. In the following description, such a data transmission path is also referred to as a "first bus". When reading data from the data recording unit 30, the error correction unit 21 also reads an ECC code corresponding to the read data from the ECC code recording unit 40, and if an error occurs in the read data, corrects the error using the ECC code. The error correction unit 21 selects a bank serving as a read source of the read data and a bank serving as a read source of the ECC code according to the bank address specified by the received mask write command.

[0019] The ECC code generation unit 22 is connected to each of the write registers WR included in each bank via the main write bus MWB. As such, in the semiconductor memory device 100, the local write buses LWB included in each bank, the write registers WR included in each bank, and the main write bus MWB form a data transmission path connecting the sense amplifiers SA and the ECC code generation unit 22 to each other. In the following description, such a data transmission path is also referred to as a "second bus". The ECC code generation unit 22 generates an error correction code (ECC code) corresponding to write data when writing data to the data recording unit 30. The ECC code generation unit 22 selects a bank to which write data is to be written and a bank to which the ECC code is to be written according to the bank address specified by the received mask write command.

[0020] In the mask write process described above, the ECC code generation unit 22 receives the data to be rewritten and the mask data, and rewrites the portion to be rewritten in the data to be rewritten with the mask data. In the present embodiment, this process is performed by inputting the data to be rewritten and the mask data into a multiplexer (not shown) included in the ECC code generation unit 22.

[0021] A-2. Mask Write Process: When a mask write command is issued from the arithmetic device 200, the semiconductor memory device 100 executes the mask write process shown in FIG. 2 and FIG. 3. In the present embodiment, when banks to be accessed are different from each other, or when the banks to be accessed are the same as each other but columns to be accessed are different from each other, the semiconductor memory device 100 can execute a plurality of mask write processes in parallel.

[0022] In step S10 shown in FIG. 2, the semiconductor memory device 100 receives a mask write command from the arithmetic device 200. Thereafter, as shown in FIG. 2, the semiconductor memory device 100 executes the processes of steps S10, S20, S30, S40 and the processes of steps S22, S32, S42, S52, S62 in parallel.

[0023] In step S20, the semiconductor memory device 100 receives mask data from the arithmetic unit 200 in the input / output circuit 10.

[0024] In step S30, the semiconductor memory device 100 performs the above-described DBI processing on the mask data in the input / output circuit 10.

[0025] In step S40, the semiconductor memory device 100 transmits mask data from the input / output circuit 10 to the ECC code generation unit 22.

[0026] In step S22, the semiconductor memory device 100 reads the data to be rewritten and the corresponding ECC code from the storage area ST to the sense amplifier SA. More specifically, the semiconductor memory device 100 reads the data to be rewritten from the data recording unit 30 of the bank specified by the mask write command among banks B0 to B3 to the sense amplifier SA connected to the data recording unit 30. The semiconductor memory device 100 also reads the ECC code from the ECC code recording unit 40 of banks B4 to B7, which holds the ECC code generated in accordance with the data to be rewritten, to the sense amplifier SA connected to the ECC code recording unit 40. Note that the bank where the data to be rewritten is held and the bank where the ECC code is held are different from each other, so the above processes are executed independently in each bank.

[0027] In step S32, the semiconductor memory device 100 transmits the data to be rewritten and the ECC code from the sense amplifier SA to the read register RR via the local read bus LRB. Similar to step S22 described above, this process is performed independently in each bank.

[0028] In step S42, the semiconductor memory device 100 transmits the data to be rewritten and the ECC code from the read register RR to the error correction unit 21 via the main read bus MRB.

[0029] In step S52, the semiconductor memory device 100 performs error correction on the data to be rewritten using ECC code in the error correction unit 21.

[0030] In step S62, the semiconductor memory device 100 transmits the data to be rewritten from the error correction unit 21 to the ECC code generation unit 22.

[0031] After the completion of steps S40 and S62, in step S70 shown in Figure 3, the semiconductor memory device 100 generates rewritten data by replacing the portion of the data to be rewritten with mask data in the error correction unit 21.

[0032] In step S80, the semiconductor memory device 100 generates an ECC code corresponding to the rewrite data in the ECC code generation unit 22.

[0033] In step S90, the semiconductor memory device 100 transmits rewrite data and ECC code from the ECC code generation unit 22 to the write register WR via the main write bus MWB.

[0034] In step S100, the semiconductor memory device 100 transmits rewrite data and ECC code from the write register WR to the sense amplifier SA via the local write bus LWB.

[0035] In step S110, the semiconductor memory device 100 writes the rewrite data and ECC code from the sense amplifier SA to the storage area ST, respectively. With this, the semiconductor memory device 100 completes the mask write process.

[0036] A more detailed explanation will be given with reference to an example of a timing chart in Figure 4, which shows the semiconductor memory device 100 of this embodiment when multiple mask write processes are executed in parallel. In Figure 4, the horizontal axis shows the elapsed time in terms of clock cycles CLK, and the hatched rectangular areas indicate that each element constituting the semiconductor memory device 100 shown on the vertical axis is used for the clock interval indicated by the rectangular area.

[0037] Figure 4 shows the cases where mask write commands MWR1 to MWR4 are received at clock speeds CLK0, 8, 16, and 24, respectively. In other words, the semiconductor memory device 100 receives one mask write command per cycle, with clock speed 8 being considered one cycle. Mask write commands MWR1 to MWR4 are commands that request mask write operations where the banks to be accessed are the same, but the columns to be accessed are different.

[0038] As described above, the semiconductor memory device 100 of this embodiment has a local read bus LRB and a local write bus LWB, so that data output from the sense amplifier SA to the read register RR via the local read bus LRB and data input from the write register WR to the sense amplifier SA via the local write bus LWB can be performed in parallel with each other. Therefore, as shown in the clock cycles CLK28 to 32 in Figure 4, the semiconductor memory device 100 can perform write and read operations in parallel at the sense amplifier SA even within the same bank. In the case of a mask write command that requests mask write processing for different banks, the sense amplifier SA where the write operation is performed and the sense amplifier SA where the read operation is performed are different, so the write and read operations at each sense amplifier SA can be performed in parallel.

[0039] In contrast, in a semiconductor memory device where a single bus extending from the sense amplifier branches off to connect to the read register and the write register respectively, within the same bank, data output from the sense amplifier to the read register and data input from the write register cannot be performed while one process is running. Therefore, in a semiconductor memory device with such a configuration, it is necessary to delay the reception of subsequent mask write commands so that the write and read operations in the sense amplifier do not run in parallel, which degrades the data processing performance during mask write operations. The semiconductor memory device 100 of this embodiment avoids this problem, thereby suppressing the degradation of data processing performance during the execution of multiple mask write operations.

[0040] As described above, the semiconductor memory device 100 of the first embodiment includes a first bus and a second bus, so that in the same bank, the output of data from the sense amplifier SA to the error correction unit 21 and the input of data from the ECC code generation unit 22 to the sense amplifier SA can be executed in parallel. For this reason, even when multiple mask write operations are performed consecutively for the same banks to be accessed, if the columns to be accessed are different, the next mask write operation can be executed in parallel without waiting for the completion of the previous mask write operation, thereby suppressing a decrease in data processing performance.

[0041] B. Second Embodiment: The semiconductor memory device 100A of the second embodiment differs from the semiconductor memory device 100 of the first embodiment in that it includes buffers BF1 to BF3, as shown in Figure 5. Furthermore, the semiconductor memory device 100A of the second embodiment differs from the semiconductor memory device 100 of the first embodiment in that, in the mask writing process, it executes steps S12 and S14 shown in Figure 8, as shown in Figure 6, and steps S120 is executed in parallel with steps S90 to S110, as shown in Figure 7. The device configuration and other procedures in the mask writing process of the semiconductor memory device 100A of the second embodiment are the same as those of the semiconductor memory device 100 of the first embodiment, so the same components and procedures are denoted by the same reference numerals, and their detailed descriptions are omitted.

[0042] As shown in Figure 5, the semiconductor memory device 100A further includes buffers BF1 to BF3, a buffer write bus BWB, and a buffer read bus BRB. In this embodiment, the number of buffers BF1 to BF3, "3," corresponds to the number of cycles required from the start to the end of the mask write process described above, "4," minus 1. Note that the number of buffers is not limited to three, and four or more may be provided.

[0043] Buffers BF1 to BF3 are each connected to the ECC code generation unit 22 via the buffer write bus BWB and the buffer read bus BRB. Buffers BF1 to BF3 store buffer data input from the ECC code generation unit 22 via the buffer write bus BWB. "Buffer data" refers to information output when the ECC code generation unit 22 writes rewrite data to the sense amplifier SA, including the rewrite data and the destination bank address and column address of the rewrite data. By storing buffer data in the buffers, the rewrite data related to the most recent mask write process can be used in the next mask write process even before the writing back of the rewrite data to the data recording unit 30 by the mask write process is completed. Details of this effect will be described later.

[0044] Buffers BF1 to BF3 output buffer data to the ECC code generation unit 22 via the buffer read bus BRB.

[0045] Buffers BF1 to BF3 store buffer data until a predetermined number of clock cycles have elapsed since the buffer data was stored, and then erase the stored buffer data. In this embodiment, buffers BF1 to BF3 erase the stored buffer data after 3 cycles have elapsed. After 3 cycles have elapsed since the buffer data was stored, the writing of the rewritten data by the mask write process back to the data recording unit 30 is completed. Therefore, when the next mask write process is executed, the rewritten data related to the most recent mask write process stored in the data recording unit 30 can be used, and there is no need to use the data stored in the buffers. The predetermined number of cycles until buffer data is erased, "3", corresponds to the number of buffers BF1 to BF3, "3".

[0046] In the mask write process of the second embodiment shown in Figures 6 to 8, as shown in Figure 6, after step S10, in parallel with steps S20, S30, and S40, in step S12 shown in Figure 8, the semiconductor memory device 100A determines whether or not an address matching buffer exists. An "address matching buffer" refers to a buffer among buffers BF1 to BF3 in which the write destination bank address and write destination column address held as buffer data match the write destination address of the target data of the received mask write command. If an address matching buffer does not exist (step S12: No), the semiconductor memory device 100A sequentially executes the processes from step S22 onwards, similar to the first embodiment, and reads the data to be rewritten from the data recording unit 30 to the ECC code generation unit 22, similar to the first embodiment.

[0047] If an address matching buffer exists (step S12: Yes), the semiconductor memory device 100A transmits the rewrite data held in the address matching buffer to the ECC code generation unit 22 (step S14). Subsequently, in step S70 shown in Figure 7, the semiconductor memory device 100 uses the data read from the address matching buffer as the data to be rewritten, and the ECC code generation unit 22 generates new rewrite data.

[0048] Following step S80 shown in Figure 7, and in parallel with steps S90 to S110, in step S120, the semiconductor memory device 100A writes buffer data to one of buffers BF1 to BF3. The semiconductor memory device 100A selects the buffer from buffers BF1 to BF3 from which data was read in step S14, and overwrites the buffer data held in that buffer with new buffer data including the rewrite data. If the buffer data held in that buffer has been erased due to the passage of time as described above, new buffer data including the rewrite data is written to the now empty buffer.

[0049] The following will be explained in more detail with reference to an example of a timing chart in Figure 9, which shows the semiconductor memory device 100A of the second embodiment when multiple mask write processes are executed in parallel. The horizontal axis shows the elapsed time in clock cycles CLK, and the rectangular areas shown with hatching or cross-hatching indicate that each element constituting the semiconductor memory device 100A shown on the vertical axis is used for the clock interval indicated by the rectangular area. Note that the rectangular areas shown with hatching indicate that they are used in the mask write process related to the mask write command MWR5, and the rectangular areas shown with cross-hatching indicate that they are used in the mask write process related to the mask write command MWR6.

[0050] Figure 9 shows the cases where mask write commands MWR5 and MWR6 are received at clock speeds CLK0 and CLK8, respectively. Mask write commands MWR5 and MWR6 are commands that request mask write processing for the same bank and column to be accessed.

[0051] In the mask write process related to the mask write command MWR5, the data to be rewritten is read from the memory area ST to the sense amplifier SA at CLK4-8. Subsequently, the data to be rewritten is transmitted to the ECC code generation unit 22 after transmission via the local read bus LRB, transmission via the main read bus MRB, and error correction in the error correction unit 21. Furthermore, after the processing in the ECC code generation unit 22 is completed, buffer data is output from the ECC code generation unit 22 at CLK20 in parallel with the output of the rewritten data to the sense amplifier SA, and the buffer data is stored in buffer BF1. In Figure 9, the buffer data stored in buffer BF1 at CLK20-26 is indicated by a hatched rectangular area as the buffer data related to the mask write command MWR5.

[0052] In the mask write process for the mask write command MWR6, buffer data for the mask write command MWR6, which has the same access target address as the mask write command MWR5, is stored in buffer BF1. Therefore, the semiconductor memory device 100A omits the read operation in the sense amplifier SA, transmission via the local read bus LRB, transmission via the main read bus MRB, and error correction in the error correction unit 21, which are shown in the rectangular area without hatching enclosed by thick solid lines in Figure 9. Instead, at CLK22, it transmits the data to be rewritten from buffer BF1 to the ECC code generation unit 22 via the buffer read bus BRB. In this way, the semiconductor memory device 100A can execute the processing in the ECC code generation unit 22 using the buffer data stored in buffer BF1 before the writing back of the rewritten data related to the mask write command MWR5 to the data recording unit 30 is completed.

[0053] After processing in the ECC code generation unit 22 is completed, in parallel with the output of the rewritten data to the sense amplifier SA, at CLK28, the semiconductor memory device 100A rewrites buffer BF1 with new buffer data. In Figure 9, the rectangular area with cross-hatching indicates that the buffer data stored in buffer BF1 at CLK28-50 is the buffer data related to the mask write command MWR6. The buffer data stored in BF1 is erased at CLK52 after three cycles have elapsed.

[0054] In the mask write process corresponding to the mask write command MWR6, if a read operation is performed in the sense amplifier, indicated by the thick solid line, at CLK12, the mask write process will be executed based on older data before the completion of the mask write process corresponding to the mask write command MWR5, resulting in data inconsistency. Therefore, in semiconductor memory devices without a buffer, when performing multiple mask write operations on the same banks and columns to be accessed, it is necessary to delay receiving subsequent mask write commands so that the next mask write operation begins only after the write-back of the rewritten data from the previous mask write operation to the data recording unit is complete, in order to prevent data inconsistency. Consequently, in semiconductor memory devices with such a configuration, the data processing performance during mask write operations is reduced. According to the semiconductor memory device 100A of this embodiment, this problem can be avoided, and the reduction in data processing performance during the execution of multiple mask write operations can be further suppressed.

[0055] According to the semiconductor memory device 100A of the second embodiment described above, since it is equipped with buffers BF1 to BF3 for storing buffer data, when mask write operations are performed consecutively for the same banks and columns to be accessed, the next mask write operation can be performed using buffer data read from any of the buffers BF1 to BF3, even before the rewritten data is written back to the data recording unit 30 by the previous mask write operation. For this reason, even if the banks and columns to be accessed are the same, the next mask write operation can be performed in parallel without waiting for the completion of the previous mask write operation, further suppressing the deterioration of data processing performance.

[0056] C. Other embodiments: (C1) In the above embodiments, the semiconductor memory device 100 and semiconductor memory device 100A have a first bus formed by a local read bus LRB, a read register RR, and a main read bus MRB, and a second bus formed by a local write bus LWB, a write register WR, and a main write bus MWB, but the disclosure is not limited thereto. The sense amplifier SA and the error correction unit 21 may be directly connected by the main read bus MRB. In such a configuration, the main read bus MRB corresponds to the "first bus" in this disclosure. The sense amplifier SA and the ECC code generation unit 22 may also be directly connected by the main write bus MWB. In such a configuration, the main write bus MWB corresponds to the "second bus" in this disclosure. Semiconductor memory devices of such configurations also achieve the same effects as the above embodiments.

[0057] (C2) In the first embodiment described above, the effects of the semiconductor memory device 100 were explained using the example of a case in which multiple mask write operations are performed in which the banks to be accessed are the same and the columns to be accessed are different, but the disclosure is not limited thereto. Even when a write operation that only writes data is followed by a mask write operation in which the banks to be accessed in the write operation are the same and the columns to be accessed are different, the semiconductor memory device 100 will have the same effects as in the above embodiment. This is because even in such a case, the write operation by the write operation and the read operation by the mask write operation can be performed in parallel in the sense amplifier SA of the same bank.

[0058] (C3) In the second embodiment described above, the effects of the semiconductor memory device 100A were explained using the example of performing multiple mask write operations in which the banks and columns to be accessed are the same as those of each other, but the disclosure is not limited thereto. Even when a write operation that only writes data is followed by a mask write operation in which the banks and columns to be accessed in the write operation are the same as those of each other, the semiconductor memory device 100A will have the same effects as in the above embodiment. Even in such a case, after the completion of the write operation in the ECC code generation unit 22, buffer data is stored in the buffer, and before the writing of data by the write operation is completed, the mask write operation can be executed in parallel using the buffer data.

[0059] (C4) In the above embodiment, the data recording unit 30 and the ECC code recording unit 40 are implemented in memory areas ST that belong to different banks, but the disclosure is not limited thereto. The data recording unit 30 and the ECC code recording unit 40 may be implemented in memory areas ST that belong to the same bank. For example, 128 bits of data and an 8-bit ECC code corresponding to such data may be held in memory cells specified by the same row address in a memory area ST that belongs to the same bank, where the data unit specified by the row address and read to the sense amplifier SA is 136 bits or more. A semiconductor memory device of this form will also produce the same effects as the above embodiment. In addition, since reading and writing of corresponding data and ECC codes to the memory area ST can be achieved with a single read / write in one bank, a decrease in data processing performance can be suppressed compared to a form in which data and ECC codes are read and written in different banks.

[0060] This disclosure is not limited to the embodiments described above, and can be implemented in various configurations without departing from its spirit. For example, the technical features in each embodiment corresponding to the technical features in the embodiments described in the summary of the invention can be replaced or combined as appropriate in order to solve some or all of the above-described problems, or to achieve some or all of the above-described effects. Furthermore, if a technical feature is not described as essential in this specification, it can be deleted as appropriate. [Explanation of Symbols]

[0061] 21…Error correction unit, 22…ECC code generation unit, 30…Data recording unit, 40…ECC code recording unit, 100, 100A…Semiconductor memory device, B0~B7…Bank, LRB…Local read bus, LWB…Local write bus, MRB…Main read bus, MWB…Main write bus, RR…Read register, SA…Sense amplifier, WR…Write register

Claims

1. A semiconductor memory device (100, 100A) capable of performing a mask write operation to rewrite data with a data length smaller than a pre-set data access unit, A plurality of banks (B0 to B7) each having a data recording unit (30) on which write data is recorded, and an ECC code recording unit (40) on which an error correction code corresponding to the write data is recorded. A sense amplifier (SA) is provided in each of the aforementioned multiple banks for reading and writing data to each of the aforementioned banks, The ECC code generation unit (22) generates the error correction code, An error correction unit (21) that corrects errors in the data using the aforementioned error correction code, A first bus (MRB, RR, LRB) connects each of the sense amplifiers to the error correction unit and transmits the data output from each of the sense amplifiers to the error correction unit, A second bus (MWB, WR, LWB) connects the ECC code generation unit and each of the sense amplifiers, and transmits the data output from the ECC code generation unit to each of the sense amplifiers. Equipped with, Semiconductor memory device.

2. A semiconductor memory device according to claim 1, A plurality of buffers (BF1 to BF3) that store buffer data indicating the write data, the bank address to which the write data is written, and the column address to which the write data is written, further comprising a plurality of buffers provided in a number equal to or greater than the number of cycles required from the start to the end of the mask write process minus one, Each of the aforementioned buffers erases the buffer data after the buffer data has been stored in it and the same number of cycles as the number of buffers have elapsed. The semiconductor memory device, if an address matching buffer exists in which the write destination bank address and write destination column address stored in the buffer match the write destination address of the data to be masked, executes the masked write process using the written data read from the address matching buffer. If the address matching buffer does not exist, the mask write process is performed using the write data read from the sense amplifier in the bank indicated by the write destination address. Semiconductor memory device.

Images