Method for forming microvias with reduced diameter

Abstract

To provide a method and a non-transitory computer-readable medium for forming microvias for packaging applications.SOLUTION: A method includes depositing 110 a conductive seed layer 210 on a substrate 200, depositing 120 a first dielectric layer 220, patterning 130 the first dielectric layer 220 to form at least one via 230 having a diameter D, depositing 140 a conductive material 240 in the via 230 to form a pillar, depositing 150 the first dielectric layer 220 and the seed layer 210, and depositing 160 a second dielectric layer 250.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001]

[0001] Embodiments of the present disclosure generally relate to methods for forming microvias with reduced diameter and / or increased alignment. In particular, embodiments of the present disclosure relate to methods for forming copper pillars in redistribution layer (RDL) polymer dielectrics. Background Art

[0002]

[0002] RDL polymer dielectrics are used to redistribute high-density I / O from a chip onto a package substrate. Multilayer RDL is used to interconnect two or more chips. Using a semi-additive process (SAP), copper traces are fabricated in a planar two-dimensional manner. Successive layers are interconnected vertically by microvias.

[0003]

[0003] While the width and spacing of wiring continue to be miniaturized to less than 20 μm, microvia scaling is currently one of the biggest bottlenecks facing the industry. Miniaturizing copper lines without reducing via diameter reduces the wiring density per layer, thereby increasing the number of layers and raising the manufacturing cost of the package.

[0004]

[0004] Industry-standard dielectrics are typically epoxy dielectrics filled with silica filler. Such composite materials are typically used for their thermomechanical and electrical properties. While such composite dielectrics with smooth surfaces allow the fabrication of fine lines, forming small vias using any subtractive processing such as etching / lasering presents a major challenge due to potential non-uniformity of the bulk material.

[0005]

[0005] Microvias are typically formed by laser drilling. However, the diameter of laser-drilled microvias is manufacturing-limited to 20 μm in diameter. Mainly for cost and throughput reasons, it is difficult to scale down laser-drilled vias to below the 20 μm node.

[0006]

[0006] Therefore, there is a need for new methods of forming microvias, in particular, microvias with reduced diameter and improved placement accuracy. [Overview of the project]

[0007]

[0007] One or more embodiments of the present disclosure relate to a method for forming microvias. The method includes depositing a conductive seed layer on a substrate. A first dielectric layer is deposited. The first dielectric layer is patterned to form at least one via having a diameter. A conductive material is deposited in at least one via to form at least one conductive pillar having height. The first dielectric layer and the conductive seed layer are removed from the substrate. A second dielectric layer is deposited around at least one conductive pillar.

[0008]

[0008] Additional embodiments of the present disclosure relate to a method for forming microvias. This method includes depositing a copper seed layer on a substrate. A first copper layer is deposited on the copper seed layer. The first copper layer is patterned to form a first copper wire. A first dielectric layer is deposited on the first copper wire. The first dielectric layer is photosensitive. The first dielectric layer is patterned to form vias having a diameter. The vias are positioned above the first copper wire. Copper material is deposited in the vias to form copper pillars. The first dielectric layer and the copper seed layer are removed from the substrate. A second dielectric layer is deposited around and above the copper pillars. The second dielectric layer contains silica-filled epoxy. The second dielectric layer is planarized to expose the tops of the copper pillars. A second copper layer is deposited on the second dielectric layer and the copper pillars. The second copper layer is patterned to form a second copper wire.

[0009]

[0009] Further embodiments of the present disclosure relate to a non-transient computer-readable medium that, when executed by a controller of a processing system, includes instructions causing the processing system to perform: deposit a copper seed layer on a substrate; deposit a first dielectric layer; pattern the first dielectric layer to form vias having a diameter; deposit copper material in the vias to form copper pillars; etch the first dielectric layer and the copper seed layer from the substrate; and deposit a second dielectric layer around at least one conductive pillar.

[0010]

[0010] A more detailed description of the disclosure, which has been briefly summarized above, can be obtained by referring to the embodiments, some of which are shown in the accompanying drawings, so that the features of the disclosure described above can be understood in more detail. However, it should be noted that the accompanying drawings are merely illustrative of typical embodiments of the disclosure and should not be considered to limit the scope of the disclosure, as the disclosure may also allow for other equally valid embodiments. [Brief explanation of the drawing]

[0011] [Figure 1]

[0011] Exemplary processing methods according to one or more embodiments of the present disclosure are shown. [Figure 2]

[0012] An exemplary substrate in processing according to one or more embodiments of this disclosure is shown. [Figure 3]

[0013] An exemplary substrate in processing according to one or more embodiments of this disclosure is shown. [Figure 4]

[0014] An exemplary substrate in processing according to one or more embodiments of this disclosure is shown. [Figure 5]

[0015] An exemplary substrate in processing according to one or more embodiments of this disclosure is shown. [Figure 6A-6C]

[0016] This document shows exemplary devices formed by one or more embodiments of the present disclosure. [Figure 7]

[0017] This disclosure shows a processing system according to one or more embodiments of the present disclosure. [Modes for carrying out the invention]

[0012]

[0018] Before describing some exemplary embodiments of this disclosure, it should be understood that this disclosure is not limited to the details of the configuration or processing steps specified in the following description. Other embodiments of this disclosure are possible and can be implemented or performed in a variety of ways.

[0013]

[0019] As used herein and in the appended claims, the term “substrate” refers to a surface or part of a surface on which a process is performed. Those skilled in the art will also understand that when a substrate is referred to, unless otherwise explicitly stated in the context, it may refer to only a part of the substrate. Furthermore, when a deposition on a substrate is referred to, it may mean both a bare substrate and a substrate on which one or more films or features are deposited or formed.

[0014]

[0020] As used herein, “substrate” refers to any substrate or material surface formed on a substrate on which a film treatment is performed during a manufacturing process. For example, substrate surfaces on which treatment may be performed include, depending on the application, materials such as silicon, silicon oxide, strained silicon, silicon-on-insulator (SOI), carbon-doped silicon oxide, amorphous silicon, doped silicon, germanium, gallium arsenide, glass, sapphire, and any other materials such as metals, metal nitrides, metal alloys, and other conductive materials. A substrate includes, but is not limited to, a semiconductor wafer. A substrate can be exposed to a pretreatment process for polishing, etching, reduction, oxidation, hydroxylation, annealing, UV curing, electron beam (e-beam) curing, and / or baking of the substrate surface. In addition to film treatment directly on the surface of the substrate itself, any of the disclosed film treatment steps may be performed on an underlying layer formed on the substrate, as will be disclosed in more detail below, and the term “substrate surface” is intended to include such underlying layers as the context indicates. Therefore, for example, if a film / layer or partial film / layer is deposited on the substrate surface, the exposed surface of the newly deposited film / layer becomes the substrate surface.

[0015]

[0021] One or more embodiments of this disclosure relate to methods for forming microvias. Some embodiments of this disclosure provide microvias with reduced diameter compared to known processes. Some embodiments of this disclosure provide microvias with improved placement accuracy.

[0016]

[0022] Some embodiments of this disclosure advantageously provide microvias with reduced diameter. In some embodiments, the diameter of the microvia is 20 μm or less, 10 μm or less, or 5 μm or less. In some embodiments, the diameter of the microvia is 0.05 μm, 0.1 μm, 0.2 μm, 0.5 μm, 1 μm, or 2 μm or more. Theoretically, reducing the diameter makes it possible to increase the wiring density (IO / mm / layer) within RDLs without needing to increase the number of RDLs.

[0017]

[0023] Some embodiments of the present disclosure advantageously utilize apparatuses and / or processes that are well known in the art. Examples include, but are not limited to, physical vapor deposition (PVD), lithography, electrolytic copper deposition (ECD), and etching / chemical mechanical planarization (CMP). Without being bound by theory, it is believed that the use of known equipment and processes reduces resistance to adoption and increases the potential use of existing hardware.

[0018]

[0024] Some embodiments of the present disclosure advantageously provide microvias with improved overlay accuracy. Without being bound by theory, the improved overlay accuracy observed in some embodiments enables smaller capture pads. In some embodiments, no capture pad is used (i.e., a via-in-line process).

[0019]

[0025] Some embodiments of the present disclosure advantageously provide a semiconductor chipset with a reduced number of RDL layers. Without being bound by theory, the reduction in RDL layers lowers the manufacturing cost of the finished semiconductor chipset.

[0020]

[0026] Referring to FIGS. 1 and 2, an exemplary method 100 for forming a microvia is illustrated similarly to an exemplary substrate during processing. For the avoidance of doubt, the method illustrated in FIG. 1 includes several operations within dashed boxes. These operations are optional. Furthermore, it is within the scope of the present disclosure that some or all of any optional steps may be performed, or none of them may be performed.

[0021]

[0027] In the method, starting with operation 110, the method begins by depositing a conductive seed layer 210 on a substrate 200. In some embodiments, the substrate 200 is silicon. The substrate is shown in FIG. 2A, and the substrate having the conductive seed layer is shown in FIG. 2B. Electronic devices with letters in the figures are used to indicate the electronic device at various timings during processing. Alternative electronic devices formed by alternative or optional processes are indicated by a prime mark (e.g., B'). As used herein, a "conductive" seed layer refers to a seed layer of conductive material. The term "conductive" seed layer should not be understood to imply anything with respect to the electrical properties of the "conductive" seed layer. In some embodiments, the conductive seed layer 210 comprises copper. In some embodiments, the conductive seed layer 210 is continuous. In some embodiments, the conductive seed layer 210 has an average thickness ranging from 50 nm to 500 nm. In some embodiments not shown, a barrier layer is deposited on the substrate before depositing the conductive seed layer 210.

[0022]

[0028] In some embodiments, method 100 continues with optional operation 310. For reference, the substrate 200 processed by optional operations 310 and 320 is shown in FIG. 3 and denoted as device B''. Those skilled in the art will recognize that an electronic device with the same base letter may be substituted for any of the described methods. For example, a device denoted B'' can be substituted for the device denoted B in FIG. 2. In optional operation 310, a first conductive layer 350 is deposited on the conductive seed layer 210.

[0023]

[0029] In operation 320, the first conductive layer 350 is patterned by removing a portion of the first conductive layer 350 to form the conductive feature 360. In some embodiments, in operation 320, the first conductive layer 350 is patterned by removing a portion of the first conductive layer 350 to form the conductive feature 360. Those skilled in the art will recognize this as a subtractive patterning process. Alternatively, in some embodiments not shown, the first conductive layer 350 may be deposited by a patterning process, and the conductive feature 360 ​​may be formed on the first conductive layer 350. Those skilled in the art will recognize this as a semi-additive process (SAP). In some embodiments, the conductive feature 360 ​​is a conductive wire, trace, or capture pad. In some embodiments, the first conductive layer 350 and the conductive feature 360 ​​contain copper.

[0024]

[0030] When used in this context, “capture pad” is a pad of conductive material to which vias and / or pillars are expected to be connected. Conventionally, the inaccuracies of the laser drilling process have required larger capture pads to ensure that vias / pillars make reliable contact with the conductive wires. As described above, some embodiments of the present disclosure provide microvias with improved overlay accuracy, allowing for smaller capture pads or no capture pads at all. In some embodiments, vias are formed to make contact with the conductive wires without a capture pad.

[0025]

[0031] In some embodiments, the via 230 is formed within a tolerance at a predetermined xy position on the substrate 200. In some embodiments, the tolerance is 5 μm or less, 3 μm or less, 2 μm or less, 1 μm or less, 0.5 μm or less, or 0.25 μm or less from the predetermined xy position. In some embodiments, the tolerance is 50% or less, 20% or less, 10% or less, 5% or less, or 1% or less of the via diameter D from the predetermined xy position.

[0026]

[0032] Method 100 is continued in operation 120 by depositing a first dielectric layer 220. The first dielectric layer 220 can be deposited by any suitable method, including but not limited to atomic layer deposition (ALD), chemical vapor deposition (CVD), spin-on coating, hot roll lamination, vacuum lamination, and the like.

[0027]

[0033] In some embodiments, the first dielectric layer 220 includes a photosensitive dielectric material. In some embodiments, the first dielectric layer 220 includes a negative-type photoresist or a positive-type photoresist. In some embodiments, the first dielectric layer 220 includes a chemically amplified resist.

[0028]

[0034] In some embodiments not shown, a planarizing layer is deposited before the first dielectric layer 220. Independently, it is assumed that the first dielectric layer may not self-level or planarize above features in the substrate (e.g., conductive features 360). Therefore, in some embodiments, the planarizing layer is deposited on a substrate containing any conductive features to provide a horizontal surface for the deposition of the first dielectric layer 220. In some embodiments, the planarizing layer includes a dielectric layer. In some embodiments, the planarizing layer includes a parylene layer.

[0029]

[0035] Method 100 continues in operation 130 by patterning the first dielectric layer 220 to form at least one via 230 having a diameter D. In those embodiments, where the first dielectric layer 220 includes a photosensitive dielectric material, the first dielectric layer 220 may be patterned by a photolithography process. In some embodiments, operation 130 also removes any planarization layers exposed at the bottom of the via 230.

[0030]

[0036] Unlike conventional laser drilling, in the photolithography process, the diameter D of the via 230 is limited primarily by the resolution of the lithography process. As mentioned above, the reduction in diameter provided by some embodiments allows for higher wiring density in packaging applications.

[0031]

[0037] In some embodiments, the diameter D of the via 230 is 20 μm or less, 15 μm or less, 10 μm or less, 8 μm or less, 5 μm or less, 3 μm or less, 1 μm or less, or 0.5 μm or less. In some embodiments, the diameter D of the via 230 is in the range of 0.5 μm to 1 μm, 0.5 μm to 3 μm, 0.5 μm to 5 μm, 0.5 μm to 10 μm, 0.5 μm to 20 μm, 1 μm to 3 μm, 1 μm to 5 μm, 1 μm to 10 μm, 1 μm to 20 μm, 3 μm to 5 μm, 3 μm to 10 μm, or 3 μm to 20 μm.

[0032]

[0038] Method 100 continues in operation 140 by depositing conductive material 240 in via 230 to form pillars. In some embodiments, the conductive material includes copper. In some embodiments, the pillar height H is less than or equal to the thickness T of the first dielectric layer 220. In some embodiments, the pillar height H is greater than the thickness of the first dielectric material. In these embodiments, and any overburden deposited on the outside of via 230 can be removed. Any suitable removal process, including but not limited to planarization, can be used.

[0033]

[0039] Method 100 continues in operation 150 by depositing the first dielectric layer 220 and the seed layer 210. The removal process can be carried out by any suitable process.

[0034]

[0040] In some embodiments, the first dielectric layer 220 is removed by a wet etching process. In some embodiments, the wet etching process includes the use of an organic stripper. In some embodiments, the organic stripper includes N-methylpyrrolidone (NMP). In some embodiments, the wet etching process includes the use of an inorganic stripper. In some embodiments, the inorganic stripper may include hydroxides and amines. In some embodiments, the inorganic stripper includes sodium hydroxide or potassium hydroxide and tetramethylammonium hydroxide. In some embodiments, the wet etching process is carried out at a temperature in the range of 20°C to 50°C. In some embodiments, the wet etching process utilizes external forces, including but not limited to sonication or air agitation. Theoretically, the external forces in some embodiments are thought to improve mass flow and / or reaction rate to improve the removal of the first dielectric layer 220.

[0035]

[0041] In some embodiments, the seed layer 210 is removed by a wet etching process. In some embodiments, the wet etching process relies on the redox reaction of the seed layer 210. In some embodiments, the wet etching process includes the use of ferric chloride.

[0036]

[0042] In some embodiments, the first dielectric layer 220 and / or seed layer 210 are removed by a dry etching process. In some embodiments, the dry etching process includes the use of plasma. In some embodiments, the plasma is formed from oxygen and argon. In some embodiments, the plasma is formed from halogen and / or hydrogen gas.

[0037]

[0043] In some embodiments, if a barrier layer is present, the barrier layer may also be removed by operation 150. In some embodiments, if a planarization layer is present, the planarization layer may also be removed by operation 150.

[0038]

[0044] In some embodiments, method 100 further includes performing an ashing process. In some embodiments, the ashing process is performed after the removal of the first dielectric layer 220 and the seed layer 210. In some embodiments, the ashing process removes any organic residue from the substrate 200. In some embodiments, the ashing process includes exposing the substrate to a plasma generated from a mixture of O2 and argon. In some embodiments, the plasma has a power in the range of 250 W to 300 W, or 280 W. In some embodiments, the substrate is exposed to the plasma for a period ranging from 2 to 5 minutes.

[0039]

[0045] In some embodiments, bias power is supplied to the plasma. In some embodiments, bias power enables shorter reaction times. Theoretically, bias power is thought to provide direction to plasma species (ions, electrons, radicals, etc.) and help impart momentum to them. The increase in impact energy is thought to increase the reaction rate and the rate of removal of residues from the dielectric layer.

[0040]

[0046] Method 100 is continued in operation 160 by depositing a second dielectric layer 250. In some embodiments, the second dielectric layer 250 includes a redistribution layer (RDL) dielectric. In some embodiments, the RDL dielectric includes a polymer dielectric. In some embodiments, the polymer dielectric includes a filler. In some embodiments, the second dielectric layer 250 includes a silica-filled epoxy.

[0041]

[0047] The second dielectric layer 250 can be formed by any suitable process. In some embodiments, the second dielectric layer 250 is deposited by dry film lamination. In some embodiments, the second dielectric layer 250 is initially fluid during deposition. In some embodiments, the second dielectric layer can be cured.

[0042]

[0048] For example, in some embodiments, silica-filled epoxy is deposited by dry film lamination under vacuum at temperatures ranging from 90°C to 130°C. Theoretically, at these temperatures, the epoxy in the dielectric becomes fluid and conforms to the features of the underlying layer (e.g., wires / capture pads), and the lamination pressure planarizes the film on the top surface. Furthermore, the vacuum environment ensures there are no voids between the dielectric and the substrate / wire / pad. In some embodiments, after lamination, the second dielectric layer is cured at 180°C for a period ranging from 30 to 60 minutes. In some embodiments, the curing temperature is in the range of 150°C to 200°C.

[0043]

[0049] In some embodiments, the method continues with an arbitrary operation 410. For reference, a substrate 200 processed by an arbitrary operation 410 is shown in Figure 4. In some embodiments, the thickness of the second dielectric layer 250 is not strictly controlled during deposition in operation 160. In these embodiments, the thickness of the second dielectric layer 250 may exceed the pillar height H of the conductive material 240. In an arbitrary operation 410, the second dielectric layer 250 is planarized to expose the top of the conductive material 240. In some embodiments, the planarization process may be carried out by CMP or an etch-back process.

[0044]

[0050] After any operation 410, the top surface of the pillar and the second dielectric layer 250 are substantially coplanar. When used in this context, materials that are "substantially coplanar" have a surface area within + / - 50 nm.

[0045]

[0051] In some embodiments, method 100 is continued in optional operations 510 and 520. For reference, a substrate 200 processed by optional operations 510 and 520 is shown in Figure 5. In optional operation 510, a second conductive layer 550 is deposited on a second dielectric layer 250 and conductive pillars. In some embodiments, in operation 520, the second conductive layer 550 is patterned by removing a portion of the first conductive layer 550 to form conductive features 560. Those skilled in the art will recognize this as a subtractive patterning process. Alternatively, in some embodiments not shown, the second conductive layer 550 may be deposited by a patterning process, and the conductive features 560 may be formed on the second conductive layer 550. Those skilled in the art will recognize this as a semi-additive process (SAP). In some embodiments, the conductive features 560 are conductive wires, traces, or capture pads. In some embodiments, the second conductive layer 550 and the conductive features 560 contain copper.

[0046]

[0052] Referring to Figures 6A-6C, relevant embodiments of the completed devices are illustrated. In Figure 6A, device 610 includes at least two pillars 620A, 620B connecting two first copper wires 630A, 630B to one second copper wire 640. Alternatively, in Figure 6B, device 650 includes at least two pillars 660A, 660B connecting one first copper wire 670 to two second copper wires 680A, 680B. Finally, in Figure 6C, the embodiments of Figures 6A and 6B are combined to connect multiple first copper wires to multiple second copper wires in a "daisy-chain" configuration.

[0047]

[0053] Referring to Figure 7, further embodiments of the present disclosure relate to a processing system 900 for performing the methods described herein. Figure 7 shows a system 900 that may be used to process substrates according to one or more embodiments of the present disclosure. The system 900 may be referred to as a cluster tool. The system 900 includes a central transfer station 910 which contains a robot 912. The robot 912 is shown as a single-blade robot, but those skilled in the art will recognize that other robot 912 configurations are within the scope of the present disclosure. The robot 912 is configured to move one or more substrates between chambers connected to the central transfer station 910.

[0048]

[0054] At least one pre-cleaning / buffering chamber 920 is connected to the central transfer station 910. The pre-cleaning / buffering chamber 920 may include one or more of a heater, a radical source, or a plasma source. The pre-cleaning / buffering chamber 920 may be used as a holding area for individual semiconductor substrates or for a cassette of wafers to be processed. The pre-cleaning / buffering chamber 920 may perform a pre-cleaning process, or preheat substrates to be processed, or may simply be a staging area for a processing sequence. In some embodiments, there are two pre-cleaning / buffering chambers 920 connected to the central transfer station 910.

[0049]

[0055] In the embodiment shown in Figure 7, the pre-cleaning chamber 920 may act as a passage chamber between the factory interface 905 and the central transfer station 910. The factory interface 905 may include one or more robots 906 that move the substrate from the cassette to the pre-cleaning / buffering chamber 920. The robot 912 can then move the substrate from the pre-cleaning / buffering chamber 920 to other chambers in the system 900.

[0050]

[0056] The first processing chamber 930 may be connected to a central transfer station 910. The first processing chamber 930 may be configured as a deposit chamber and may be fluidly connected to one or more reactive gas sources to supply one or more flows of reactive gas to the first processing chamber 930. The substrate can be moved in and out of the processing chamber 930 by a robot 912 that passes through an isolation valve 914.

[0051]

[0057] The processing chamber 940 may also be connected to the central transfer station 910. In some embodiments, the processing chamber 940 includes a patterning chamber and is fluidly coupled to one or more reactive gas sources to supply a flow of reactive gas to the processing chamber 940 to perform an isotropic etching process. The substrate can be moved in and out of the processing chamber 940 by a robot 912 that passes through an isolation valve 914.

[0052]

[0058] In some embodiments, the processing chamber 960 is connected to a central transfer station 910 and configured to act as an etching or removal chamber. The processing chamber 960 may be configured to carry out one or more different epitaxial growth processes.

[0053]

[0059] In some embodiments, each of the processing chambers 930, 940, and 960 is configured to perform a different part of the processing method. For example, processing chamber 930 may be configured to perform a deposition process, processing chamber 940 may be configured to perform a patterning process, and processing chamber 960 may be configured to perform an etching / removal process. An experienced technician will recognize that the number and arrangement of the individual processing chambers of the tool can be varied, and the embodiment shown in Figure 7 represents only one possible configuration.

[0054]

[0060] In some embodiments, the processing system 900 includes one or more measurement stations. For example, the measurement stations may be located in the pre-wash / buffer chamber 920, in the central transfer station 910, or in any of the individual processing chambers 930, 940, 960. The measurement stations may be located anywhere within the system 900, allowing the substrate to be measured without removing it from the system 900.

[0055]

[0061] At least one controller 950 is connected to one or more of the central transfer station 910, pre-wash / buffer chamber 920, and processing chambers 930, 940, or 960. In some embodiments, there are multiple controllers 950 connected to individual chambers or stations, and a main control processor is connected to each of the individual processors to control the system 900. The controller 950 may be one of any form of general-purpose computer processor, microcontroller, microprocessor, etc., which can be used in industrial environments to control various chambers and subprocessors.

[0056]

[0062] At least one controller 950 may have a processor 952, a memory 954 connected to the processor 952, an input / output device 956 connected to the processor 952, and support circuits 958 for communication between various electronic components. The memory 954 may include one or more of temporary memory (e.g., random access memory) and non-temporary memory (e.g., storage).

[0057]

[0063] The processor's memory 954 or computer-readable medium may be one or more readily available memories (such as random access memory (RAM), read-only memory (ROM), floppy disks, hard disks, or any other form of local or remote digital storage). Memory 954 may hold an instruction set operable by the processor 952 to control the parameters and components of the system 900. Support circuits 958 are coupled to the processor 952 to support the processor in a conventional manner. These circuits may include, for example, caches, power supplies, clock circuits, input / output circuits, subsystems, etc.

[0058]

[0064] The process may generally be stored in memory as a software routine, which, when executed by a processor, causes a processing chamber to carry out the process of the present disclosure. This software routine may be stored and / or executed by a second processor (not shown) located remotely from the hardware controlled by the processor. Some or all of the methods of the present disclosure may also be implemented in hardware. Thus, the process may be implemented in software and executed by a computer system in hardware (e.g., application-specific integrated circuits or other types of hardware implementations) or in a combination of software and hardware. When executed by a processor, the software routine transforms a general-purpose computer into an application-specific computer (controller) that controls the operation of the chamber so that the process can be carried out.

[0059]

[0065] In some embodiments, the controller 950 has one or more configurations for executing individual processes or subprocesses to carry out the method. The controller 950 may be connected to and configured to operate intermediate components to perform the functions of the method. For example, the controller 950 may be connected to and configured to control one or more gas valves, actuators, motors, slit valves, pressure regulators, etc.

[0060]

[0066] The controller 950 in some embodiments has one or more configurations selected from the following: a configuration for moving a substrate on a robot between a plurality of processing chambers and a measurement station; a configuration for loading and / or unloading a substrate from the system; a configuration for depositing a conductive seed layer on the substrate; a configuration for depositing a first copper layer; a configuration for patterning the first copper layer; a configuration for depositing a first dielectric layer; a configuration for patterning the first dielectric layer; a configuration for depositing conductive material in vias; a configuration for removing the first dielectric layer; a configuration for depositing a second dielectric layer; a configuration for planarizing the second dielectric layer; a configuration for depositing a second copper layer; and / or a configuration for patterning the second copper layer.

[0061]

[0067] Throughout this specification, any reference to “one embodiment,” “a particular embodiment,” “one or more embodiments,” or “embodiment” means that any particular feature, structure, material, or property described in relation to an embodiment is included in at least one embodiment of this disclosure. Therefore, any phrases such as “in one or more embodiments,” “in a particular embodiment,” “in one embodiment,” or “in an embodiment” appearing in various places throughout this specification do not necessarily refer to the same embodiment of this disclosure. Furthermore, any particular feature, structure, material, or property may be combined in any optimal manner in one or more embodiments.

[0062]

[0068] While the disclosure herein is described with reference to specific embodiments, those skilled in the art will understand that the embodiments described are merely illustrative of the principles and uses of the disclosure. It will be apparent to those skilled in the art that various modifications and changes can be made to the methods and apparatus of the disclosure without departing from the spirit and scope of the disclosure. Accordingly, the disclosure may include modifications and changes within the scope of the appended claims and their equivalents.

Claims

1. A method for forming microvias, The method involves depositing a conductive seed layer on a substrate, wherein the conductive seed layer has an average thickness in the range of 50 nm to 500 nm. Depositing the first dielectric layer, The first dielectric layer is patterned to form at least one via having a diameter, Depositing a conductive material in at least one via to form at least one conductive pillar having height, Removing the first dielectric layer and the conductive seed layer from the substrate, After removing the first dielectric layer and the conductive seed layer, an ashing process is carried out. A second dielectric layer is deposited around the at least one conductive pillar. Includes, A method for patterning the first dielectric layer to form at least one via having a diameter, wherein the patterning of the first dielectric layer is such that the diameter of the at least one via is 0.05 μm or more and 20 μm or less.

2. Before depositing the first dielectric layer, a first conductive layer is deposited on the conductive seed layer, The first conductive layer is patterned to form a first conductive wire or capture pad. The method according to claim 1, further comprising:

3. Depositing the second dielectric layer having a thickness greater than the height of the at least one conductive pillar, The second dielectric layer is planarized to expose the top of at least one conductive pillar. The method according to claim 1, further comprising:

4. Depositing a second conductive layer on the second dielectric layer and the at least one conductive pillar, The second conductive layer is patterned to form a second conductive wire or capture pad. The method according to claim 1, further comprising:

5. The method according to claim 1, wherein the second dielectric layer includes an RDL polymer dielectric.

6. The method according to claim 5, wherein the RDL polymer dielectric comprises silica-filled epoxy.

7. The method according to claim 1, wherein the ashing process includes exposing the substrate to a plasma generated from a mixture of oxygen and argon.

8. The method according to claim 1, wherein the at least one via is formed within a tolerance at a predetermined x-y position, and the tolerance is 0.5 μm or less from the predetermined x-y position.

9. The method according to claim 1, wherein the at least one via is formed to contact a conductive wire without a capture pad.

10. Further comprising depositing a planarization layer before depositing the first dielectric layer, Patterning the first dielectric layer to form at least one via having a diameter includes removing the planarization layer at the bottom of the at least one via, The method according to claim 1, wherein removing the first dielectric layer and the conductive seed layer from the substrate includes removing the planarization layer from the substrate.

11. The method according to claim 10, wherein the planarization layer includes a dielectric layer.

12. The method according to claim 11, wherein the planarization layer includes a parylene layer.

13. Further comprising depositing a barrier layer on the substrate before depositing the conductive seed layer, The method according to claim 1, wherein removing the first dielectric layer and the conductive seed layer from the substrate includes removing the barrier layer from the substrate.

14. The method according to claim 1, wherein the conductive seed layer and the conductive material contain copper.

15. The method according to claim 1, wherein the ashing process comprises providing bias power to the plasma to provide directionality to the plasma species and increase the residual removal rate of the first dielectric layer.

16. A non-temporary computer-readable medium containing instructions, wherein when the instructions are executed by a controller of a processing system, the processing system causes the processing system to perform the method according to any one of claims 1 to 15.

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