Optical transmitter and timing adjustment method

Abstract

To make it possible to adjust timing for all segments during operation.SOLUTION: An optical transmitter includes: an optical modulator 121 having three or more segments 122 in series along one or both of two optical waveguides 126 of a Mach-Zehnder interferometer; a DSP 150 including an encoder that outputs two or more types of input bit data input to the segments 122 and multiple bits of bit data obtained by performing code conversion, for optical modulation of the optical modulator 121, of the input bit data to the segments 122; a switch 115 that can switch and output the bit data output by the encoder to a different segment 122; a delay adjustment unit 116a that adjusts an amount of delay between the segments 122; and a control unit 118. The control unit 118 instructs the switch 115 on the amount of delay of the delay adjustment unit 116a based on monitoring an optical signal of the optical modulator 121 in each of states 1 and 2 in which the bit data output by the encoder is switched to the different segments 122.SELECTED DRAWING: Figure 5

Description

Technical Field

[0001] The present invention relates to an optical transmitter and a timing adjustment method.

Background Art

[0002] A general optical transmitter for use in large-capacity transmission systems such as digital coherent transmission schemes and IM-DD (Intensity Modulation-Direct Detection) schemes converts a digital signal output from a DSP (Digital Signal Processor) into an electrical analog signal by means of an electrical DAC (Digital-to-Analog Converter), amplifies this electrical analog signal by an analog driver to generate a drive signal having an amplitude of several volts, and drives a traveling-wave optical modulator, thereby generating a multi-level optical modulation signal.

[0003] On the other hand, in order to reduce the power consumption of an optical transmitter, optical DAC (Digital-to-Analog Converter) technology has been researched as an architecture for generating a multi-level optical modulation signal by directly inputting a digital signal to a segmented optical modulator (an optical modulator having a plurality of phase shifters connected in multiple stages on an optical waveguide).

[0004] In optical DAC technology, a drive signal generated from a bit-wise digital signal corresponding to a symbol is amplified by a binary driver, and then input as-is to a segmented lumped-constant optical modulator, thereby optically converting a digital signal into an analog signal. For this reason, it eliminates the need to convert a digital signal into an analog signal using an electrical DAC and output a drive signal with large amplitude from a linear driver, and therefore reduction in power consumption is expected.

[0005] On the other hand, in an optical DAC, the optical modulator has a plurality of segments (phase shifters) and converts a digital signal into an analog signal in the optical domain. Therefore, in order to obtain good signal quality, appropriate timing adjustment between the optical signal propagating through the segments and the digital signal input from the binary driver is essential.

[0006] Factors that cause timing discrepancies between multiple segments of an optical DAC include: 1. Delays due to unequal wiring lengths of electrical signals between segments; 2. Delays in optical signal propagation between segments; and 3. Dynamic delay fluctuations due to temperature changes, etc. Of the above, 1. Unequal wiring lengths of electrical signals and 2. Optical signal propagation delays are expected to be fixed delay amounts and their timing adjusted through calibration at the factory or after equipment installation. Furthermore, during operation, for 3. Dynamic delay fluctuations due to temperature changes, etc., timing adjustment methods are needed for time-varying delay amounts such as voltage fluctuations and temperature fluctuations during equipment operation.

[0007] Prior art related to adjusting the delay amount includes, for example, a technique that detects the timing difference between the timing of the input drive signal and the optical propagation time between each segment for two segments arranged on the same optical waveguide by monitoring the output light of the optical modulator and using the amplitude value of the monitored signal. Another technique involves controlling the timing of the drive voltage applied to each of the multiple segments of the optical waveguide of the two arms within a Mach-Zehnder type segment optical modulator based on the intensity (average power) of the output light of the optical modulator. Prior art related to optical DACs includes a technique that divides the segments of the optical modulator according to the input bits, outputs the bit data from the least significant bit (LSB) to the most significant bit (MSB) to the corresponding multiple segments (phase shifter) of the optical waveguide, and outputs a multi-level optical signal. [Prior art documents] [Patent Documents]

[0008] [Patent Document 1] International Publication No. 2013 / 140482 [Patent Document 2] International Publication No. 2014 / 103231 [Patent Document 3] U.S. Patent No. 7787713 [Overview of the project] [Problems that the invention aims to solve]

[0009] When considering applying conventional segment optical modulator timing adjustment techniques to optical DAC transmitters, it is possible to adjust a fixed delay amount between two segments as an initial calibration. However, no effective means have been proposed for adjusting the timing between segments during equipment operation.

[0010] Conventional timing adjustment techniques determine the optimal delay based on the optical output when the same data sequence is input to a pair of segments. However, during optical DAC operation, different data is input to multiple segments. It was not possible to adjust the timing between segments receiving these different data sequences during equipment operation. For example, in a segment optical modulator used in an optical DAC transmitter, the most significant bit (MSB) and least significant bit (LSB) are separate segments within the optical modulator. During equipment operation, different data is input to each segment bit by bit, making it impossible to adjust the timing between, for example, the MSB segment and the LSB segment.

[0011] In one aspect, the present invention aims to enable timing adjustment of all segments during operation. [Means for solving the problem]

[0012] According to one aspect of the present invention, the optical transmitter is required to include: an optical modulator having three or more segments arranged in series along one or both of the two optical waveguides of a Mach-Zehnder interferometer; two or more types of input bit data input to the segments of the optical modulator; an encoder that outputs a plurality of bit data obtained by coding the input bit data for optical modulation of the optical modulator to the segments; a switch that can switch the bit data output by the encoder to different segments; a delay adjustment unit that adjusts the amount of delay between the segments; and a control unit that switches the bit data output by the encoder to different segments and instructs the amount of delay of the delay adjustment unit based on monitoring of the optical signal after optical modulation by the optical modulator. [Effects of the Invention]

[0013] According to one aspect of the present invention, the timing of all segments can be adjusted during operation, which is an advantage. [Brief explanation of the drawing]

[0014] [Figure 1A] Figure 1A is a block diagram showing an example of the functionality of a 3-bit input optical DAC provided in an optical transmitter according to the embodiment. [Figure 1B] Figure 1B shows an example configuration of an optical DAC according to the embodiment. [Figure 2] Figure 2 is an explanatory diagram of the factors that cause delay in an optical DAC. [Figure 3] Figure 3 is an explanatory diagram of an example of dynamic timing adjustment. [Figure 4A] Figure 4A is a diagram illustrating an example of waveform degradation due to the presence or absence of signal delay. (Part 1) [Figure 4B] Figure 4B is a diagram illustrating an example of waveform degradation due to the presence or absence of signal delay. (Part 2) [Figure 4C] Figure 4C is a diagram showing the relationship between the delay difference between segments with the same data input and the monitor optical power. [Figure 5]FIG. 5 is an explanatory diagram of an example of timing adjustment of an optical DAC according to the embodiment. [Figure 6] FIG. 6 is a diagram showing a hardware configuration example of a control unit of an optical DAC. [Figure 7] FIG. 7 is a functional block diagram showing a configuration example of the optical DAC according to the first embodiment. [Figure 8] FIG. 8 is a flowchart of a first timing adjustment processing example by the optical DAC according to the first embodiment. [Figure 9] FIG. 9 is a diagram showing a combination state of bits and segments in the first timing adjustment processing example according to the first embodiment. [Figure 10] FIG. 10 is a flowchart of a second timing adjustment processing example by the optical DAC according to the first embodiment. [Figure 11] FIG. 11 is a diagram showing a combination state of bits and segments in the second timing adjustment processing example according to the first embodiment. [Figure 12] FIG. 12 is a flowchart showing a first specific processing example of timing adjustment. [Figure 13] FIG. 13 is a flowchart showing a second specific processing example of timing adjustment. [Figure 14] FIG. 14 is a functional block diagram showing a configuration example of the optical DAC according to the second embodiment. [Figure 15] FIG. 15 is a circuit diagram showing a configuration example of a switch of the optical DAC according to the second embodiment. [Figure 16] FIG. 16 is a diagram showing a configuration example of a multi-stage array of switches of the optical DAC according to the second embodiment. [Figure 17] FIG. 17 is a flowchart of a first timing adjustment processing example by the optical DAC according to the second embodiment. [Figure 18A] FIG. 18A is a diagram showing a switching state of combinations of bits and segments in the first timing adjustment processing example according to the second embodiment. (Part 1) [Figure 18B] FIG. 18B is a diagram showing a switching state of combinations of bits and segments in the first timing adjustment processing example according to the second embodiment. (Part 2) [Figure 19]Figure 19 is a flowchart of Example 2 of the timing adjustment process using an optical DAC in Example 2. [Figure 20] Figure 20 shows the combination state of bits and segments in the timing adjustment process example 2 of Embodiment 2. [Figure 21] Figure 21 shows Example 3 of timing adjustment processing using an optical DAC in Example 2. [Figure 22] Figure 22 shows an example of switch switching timing detection using an optical DAC in Example 2. [Figure 23] Figure 23 shows an example configuration of a coherent optical DAC. [Modes for carrying out the invention]

[0015] Embodiments of the disclosed optical transmitter and timing adjustment method will be described in detail below with reference to the drawings.

[0016] (Overview of the timing adjustment method in the embodiment) Figure 1A is a block diagram showing an example of the functionality of a 3-bit input optical DAC provided in an optical transmitter according to this embodiment. The optical transmitter maps the transmission data to symbols using a multi-level modulation scheme such as QAM, inputs the bit-by-bit digital signals corresponding to the symbols into the segments (phase shifters) of the optical modulator, optically converts them from digital to analog, and outputs a modulated optical signal. In the case of digital coherent transmission, an IQ optical modulator is normally used to generate the optical transmission signal, but for the sake of simplifying the drawings, only the I-side optical modulator is shown in this embodiment of the present invention.

[0017] Figure 1A shows an optical DAC assuming a 3-bit input. The optical DAC 100 includes, for example, an electronic circuit 110 such as a DSP and an optical circuit 120 such as an optical modulator 121. The optical DAC 100 described in this embodiment outputs an optical signal based on two or more types of input bit data input to the segments of the optical modulator 121.

[0018] The optical modulator 121 has multiple segments (phase shifters) within a single Mach-Zehnder modulator. The specific segment is indicated by the code 122 in Figure 1B, but in Figure 1A, there are seven segments, indicated by the numbers of the input portion of the optical modulator 121. By inputting different digital (electrical signal) bit data from the electronic circuit 110 to the multiple segments of the optical modulator 121, the optical circuit 120 outputs a multi-level optical signal.

[0019] The optical DAC 100 in this embodiment controls the combination of the digital data of each bit input to the optical modulator 121 and the segment assigned to the input data. The optical DAC 100 then adjusts the timing of all segments during equipment operation (data transmission) by performing timing adjustments based on the optical signal monitoring results each time the data and segment combination is changed.

[0020] In the configuration example shown in Figure 1A, the electronic circuit 110 includes, for example, a framer 111, an FEC 112, a mapping unit 113, an encoder 114 for the optical DAC, a switch 115, a driver 116, an optical monitor unit 117, and a control unit 118.

[0021] The framer 111 stores the input data, such as the input packets, in an OTN (Optical Transport Network) and generates predetermined transmission data. The FEC 112 encodes the transmission data, adds parity bits for error correction, and outputs it to the mapping unit 113. The mapping unit 113 generates a symbol signal by mapping the transmission data onto the IQ plane according to a multi-level modulation scheme such as QAM, and outputs it to the optical DAC encoder 114.

[0022] The optical DAC encoder 114 performs data code conversion on the input symbol signal according to the segment configuration of the optical modulator 121. The optical DAC 100 shown in Figure 1A is an example of a 3-bit, 7-segment configuration. In this optical DAC 100, the optical modulator 121 has a total of 7 segments, with bit 0 of the LSB assigned to 1 segment, bit 1 to 2 segments, and bit 2 of the MSB to 4 segments. In response to this assignment, the optical DAC encoder 114 outputs 1 bit data for bit 0, 2 bit data for bit 1, and 4 bit data for bit 2.

[0023] The control unit 118 controls the switch 115 when adjusting the timing of each segment. The switch 115 can arbitrarily change the bit data of bits 0 to 2 output by the optical DAC encoder 114 and the assignment of segments #1 to 7 of the optical modulator that are assigned to that bit data. Based on the control of the control unit 118, the switch 115 changes the data and segment assignments. The control unit 118 performs timing adjustments based on the output optical signal of the optical modulator after the assignment changes.

[0024] The driver 116 includes a delay adjustment unit 116a and a binary driver array 116b. The delay adjustment unit 116a adjusts the timing between multiple segments 122 based on the control of the control unit 118. The binary driver array 116b outputs a drive signal (bit data) for each of the seven segments of the optical modulator 121.

[0025] Figure 1B is a diagram showing an example configuration of an optical DAC according to an embodiment. Figure 1B mainly shows an example configuration of the optical circuit 120, and the same reference numerals are used for components that are the same as those in Figure 1A. The functions of the framer 111 to the optical DAC encoder 114 described in Figure 1A can be realized, for example, using the DSP 150 shown in Figure 1B. The following explanation will refer to Figures 1A and 1B.

[0026] As shown in Figure 1B, the optical circuit 120 includes an optical waveguide 126 formed on a substrate. The optical modulator 121 of the optical circuit 120 includes a plurality of segments (phase shifters) 122, a demultiplexer 123, a multiplexer 124, and a DC phase shifter 125 provided along the optical waveguide 126.

[0027] The optical modulator 121 is, for example, a Mach-Zehnder modulator. The carrier wave emitted from the light source is split into two optical waveguides 126 by a demultiplexer 123 to form an interferometer. Multiple signal electrodes provided along the two optical waveguides 126 correspond to multiple segments 122. The light modulated in each segment 122 is combined by a multiplexer 124 and output as a modulated optical signal. A DC phase shifter 125 for DC bias control is provided in one of the optical waveguides 126 to control the operating point of the Mach-Zehnder interference.

[0028] The optical monitor unit 117 monitors the power of the optical signal output by the optical modulator 121 and outputs the monitoring results to the control unit 118. For example, the optical monitor unit 117 shown in Figure 1B includes a monitor PD (Photo Detector) 161 that converts the optical signal into an electrical signal, and a frequency filter 162 that extracts high-frequency components contained in the electrical signal. The power monitor 163 detects the optical power after the output of the frequency filter 162 and outputs it to the control unit 118. The output of the optical signal to the monitor PD 161 can be obtained using either the tap of the output of the multiplexer 124 or the output of the 2x2 multimode interference (MMI) coupler.

[0029] The control unit 118 controls the switch 115 and the delay adjustment unit 116a. The control unit 118 controls the switch 115 to change the combination of data and segment 122. For example, the switch 115 switches the most significant (MSB) four bits of bit 2 (a group of bits) output by the optical DAC encoder 114 to segments #4 to #7. By switching the switch 115, the output is sent to a different segment than before, for example, segments #1 to #4. In this way, the control unit 118 has the function of arbitrarily switching between multiple input bit data and the segment to which those input bits are assigned.

[0030] The control unit 118 then outputs the delay amount to be adjusted for segments #1 to #4 to the delay adjustment unit 116a based on the monitoring results of segments #1 to #4 after the switch 115 is switched. By repeating this process, timing adjustments are made for all segments 122 during equipment operation (data transmission).

[0031] The delay adjustment unit 116a can perform timing adjustment using a general-purpose delay adjustment method. For example, when the same bit data is output to the segment 122 to be adjusted, the delay adjustment unit 116a sweeps the delay amount for the segment 122 to be adjusted and determines the delay amount that maximizes the optical output. This minimizes the timing difference between segments 122 that have the same bit data input.

[0032] In this embodiment, it is assumed that the length of all segments 122, i.e., the length L of the signal electrode along the optical waveguide, is the same (the delay amount between all adjacent segments 122 is the same). The control unit 118 then changes the combination of data and segment 122 by controlling the switch 115.

[0033] Furthermore, in the 3-bit, 7-segment configuration example described for the optical DAC 100 above, the switch 115 switches the four outputs of bit 2 of the MSB, thereby switching more than half of the seven segments 122 of the optical modulator 121. This bit 2 can obtain a larger amplitude compared to the other bits 0 and 1 due to its four outputs, and its power can be easily detected by the frequency filter 162 of the optical monitor unit 117.

[0034] In this embodiment, the optical DAC 100 continuously performs timing adjustments each time the combination of the digital data of each bit input to each segment 122 of the optical modulator 121 and the assigned segment is switched by the switch 115. That is, the optical DAC 100 performs timing adjustments for multiple segments to which multiple bits of MSB data (bit by bit) that are the same data are input. The optical DAC 100 then switches the multiple bits of bit data (bit by bit) by the switch 115 and inputs them to multiple segments to which timing adjustments have not yet been performed. As a result, timing adjustments are performed between all segments in the background while the optical DAC 100 is in operation.

[0035] Furthermore, after the delay amount calibration (initialization) performed at the factory or during installation, the optical DAC 100 of this embodiment can dynamically adjust the delay amount of the optical signal in real time to track voltage fluctuations and temperature fluctuations caused by local heat sources during the operation of the optical transmitter.

[0036] (Existing technologies and their challenges) Figure 2 is an explanatory diagram of the factors causing delay in an optical DAC. Using Figure 2, we will explain existing technologies and their challenges regarding timing adjustment for delays occurring in optical DACs. The basic configuration of the optical DAC 200 shown in Figure 2 is the same as in the embodiment (Figure 1B).

[0037] The optical DAC 200 includes an optical modulator 211 composed of optical circuits, and a DSP 250, delay control circuit 215, and driver 216 composed of electronic circuits. The optical DAC 200 in Figure 2 shows, for example, an n-bit configuration example. The n-bit data from bit0 to bitn-1 output by the DSP 250 is connected to the corresponding segment 222 of the optical modulator 211 via signal wiring 220.

[0038] For illustrative purposes, let's assume that bit0 is a bit unit that outputs one bit data (1 lane), bit1 is a bit unit that outputs the same bit data with two bits (2 lanes), and bit2 is a bit unit that outputs the same bit data with four bits (4 lanes).

[0039] Signal delays in the optical signal occur between multiple segments 222 of the optical DAC 200 due to the following factors. (1) For the segments arranged on the optical waveguide 221 of the optical modulator 211, if we compare, for example, the leftmost segment assigned to bit 0 with the rightmost segment assigned to bit 2, the segment assigned to bit 2 will be delayed by the length of the optical waveguide as shown in the figure. This propagation delay occurs for each segment. The amount of propagation delay is proportional to the length of the optical waveguide, but for example, in the case of lengths on the order of several hundred μm to several millimeters, the amount of propagation delay will be several p seconds to tens of p seconds. (2) In the block diagram, the signal wiring 220 for electrical signals is shown to be the same length for each segment, but it is possible that the wiring lengths may be unequal for each segment during circuit implementation. If the wiring lengths are unequal, wiring delays may occur for each segment.

[0040] These propagation delays (1) and (2) are due to the principle of delay or design, and although the delay difference is relatively large, ranging from a few p-seconds to tens of p-seconds, they are fixed delays. Therefore, it is possible to correct the delay with the delay control circuit 215 during factory shipment or equipment installation. In order to obtain good signal quality as the optical signal to be transmitted, a delay control circuit 215 that performs appropriate timing adjustment is necessary.

[0041] (3) Variation in propagation delay due to temperature variations Since this (3) temperature variation is a real-time fluctuation, dynamic correction is required from a state where timing adjustment has already been made for the delay amounts in (1) and (2) above. Here, dynamic timing adjustment is required to track voltage fluctuations and temperature fluctuations (e.g., local heat sources) of the optical DAC200 during operation of the optical transmitter. For example, according to an electronic circuit simulator, the delay variation due to temperature fluctuations from -5°C to 95°C, assuming a certain drive circuit and delay circuit (no wiring, ideal state), was about 6 psec. Therefore, it is assumed that timing adjustment of a few p seconds is necessary for temperature fluctuations, etc. Also, since (3) temperature variation is a fluctuation during operation, data transmission cannot be stopped, and timing adjustment must be performed using the data being transmitted during operation.

[0042] Figure 3 is an explanatory diagram of an example of dynamic timing adjustment. Figure 3 shows an example of dynamic timing adjustment using existing technology in response to the temperature variation described above (3), and a 2-bit optical DAC200 is shown for the sake of simplicity in the explanation.

[0043] The optical output of the optical modulator 211 is detected by the monitor PD261 of the optical monitor unit 217, and the detected power is output to the control circuit 218. Based on the power of the detected optical signal, the control circuit 218 performs timing adjustment using the delay control circuit 215.

[0044] According to the configuration shown in Figure 3, even while the optical DAC 200 is operating, timing adjustment is possible between segments 222b and 222c, where the same data (MSB) bit 1 is input, even if different data (LSB) bit 0 is input to other segments 222a.

[0045] The timing adjustment during operation of this optical DAC will be explained using Figures 4A to 4C. Figures 4A and 4B are diagrams showing examples of waveform degradation due to the presence or absence of signal delay. Figure 4C is a diagram showing the relationship between the delay difference between segments with the same data input and the monitor optical power. In Figures 4A(a) and 4B(a), the horizontal axis is time and the vertical axis is amplitude, showing the change in the eye pattern when two bits, "bit 0" and "bit 1" in Figure 3, are input to an optical DAC with three segments in PAM4 (Pulse Amplitude Modulation 4) signal transmission.

[0046] Figure 4A(a) shows the signal waveform with adjusted timing between segments 222a, 222b, and 222c, resulting in nearly uniform eye apertures across the four levels. In contrast, Figure 4B(a) shows the signal waveform when there is a constant delay (timing difference) between segments 222b and 222c, demonstrating the degradation of the eye waveform.

[0047] Figures 4A(b) and 4B(b) show the frequency response of the optical output signal from the optical DAC200, which was detected by the monitor PD261 and converted into an electrical signal. The horizontal axis represents frequency, and the vertical axis represents optical power. Comparing Figure 4A(b) without a timing difference with Figure 4B(b) with a timing difference, it can be seen that the 20 GHz optical power component is reduced in Figure 4B(b). In other words, the optical power with frequency components corresponding to the timing difference between segments decreases.

[0048] Figure 4C shows the results of monitoring the 20GHz optical power component using a bandpass frequency filter, for example, against the delay difference between segment 222b and segment 222c and the output monitor component of the optical DAC 200. The monitor value is maximum when the delay difference between the two segments is 0, and adjustment is possible within a range of ±25p seconds. That is, by monitoring this value and sweeping the delay difference between segment 222b and segment 222c using the delay adjustment circuit 215, timing adjustment is possible by providing a delay amount that maximizes the monitor value. Incidentally, although the results of extracting the 20GHz optical power component using a bandpass frequency filter were explained here, it is possible to change the adjustment range of the delay amount by changing the value of the frequency extracted by this frequency filter. That is, increasing the frequency filter value narrows the adjustment range of the delay amount, making high-precision timing adjustment possible within a fine range, while decreasing the frequency filter value widens the adjustment range of the delay amount, making timing adjustment possible.

[0049] On the other hand, in this configuration, the timing of segment 222a, which receives LSB data, and segments 222b and 222c, which receive MSB data, cannot be adjusted. This is because timing adjustment using this method or conventional technology is constrained by data patterns, such as the input of identical data or inverted data to the segments to be adjusted.

[0050] During operation of the optical DAC200 shown in Figure 3, the bit data input to segment 222a of the LSB (bit0) and the bit data input to segments 222b and 222c of the MSB (bit1) are different data. Therefore, timing adjustment between segment 222a of the LSB and segments 222b and 222c of the MSB is not possible. Thus, with existing technology, timing adjustment for all segments of the optical DAC200 is not possible. Although Figure 3 illustrates a 2-bit example, the number of segments that cannot be adjusted with existing technology increases as the number of bits increases.

[0051] (Example of timing adjustment according to the embodiment) Figure 5 is an explanatory diagram of an example of timing adjustment for an optical DAC according to the embodiment. In response to the problems of existing technologies described in Figures 3 and 4A to C, the optical DAC 100 of the embodiment performs timing adjustment for all segments by switching the assignment of input bit data and multiple segments in the segment optical modulator during equipment operation (operation).

[0052] For example, the control unit 118 has a function to change the output path of the bit data driving each segment 122 (#1 to #7) using a switch 115, depending on whether it is state 1 (Figure 4A(a)) or state 2 (Figure 4A(b)). As a result, in state 1, the same data called MSB data is input to segments 122 #4 to #7, so timing adjustment can be performed on segments #4 to #7. In state 2, MSB data is input to segments 122 #1 to #4, so timing adjustment can be performed on segments #1 to #4. As shown in Figure 4, bit 2 of the most significant bit (MSB) occupies the majority of the segments (4 out of 7), so for example, the optical monitor unit 117 can monitor the optical power of a certain frequency component relative to the delay sweep, as shown in Figure 4C, and timing adjustment becomes possible.

[0053] (Example hardware configuration of the optical DAC control unit) Figure 6 shows an example of the hardware configuration of the control unit of the optical DAC. The control unit 118 of the optical DAC 100 shown in Figure 1 can be configured, for example, with the hardware shown in Figure 6.

[0054] For example, the control unit 118 includes a processor 601 such as a CPU (Central Processing Unit), a memory 602, a network IF 603, a recording medium IF 604, and a recording medium 605. Each component is connected by a bus 600.

[0055] Here, the processor 601 is a control unit that oversees the control of the entire control unit 118. The processor 601 may have multiple cores. The memory 602 includes, for example, ROM (Read Only Memory), RAM (Random Access Memory), and flash ROM. Specifically, for example, the flash ROM stores the control program, the ROM stores the application program, and the RAM is used as the work area of ​​the processor 601. The program stored in the memory 602 is loaded into the processor 601, causing the processor 601 to execute the coded process.

[0056] The network IF603 manages the interface between the network NW and the inside of the device, and controls the input and output of information to and from the outside of the device.

[0057] The recording medium IF604 controls the reading / writing of data to the recording medium 605 according to the control of the processor 601. The recording medium 605 stores the data written under the control of the recording medium IF604.

[0058] In addition to the components described above, the control unit 118 may also be configured to allow connection of, for example, an input device, a display, etc., via an interface (IF).

[0059] The processor 601 shown in Figure 6 can implement the functions of the control unit 118 shown in Figure 1 through program execution.

[0060] The hardware configuration shown in Figure 6 is not limited to the control unit 118 of the optical DAC 100, but can also function as the control unit of an optical transmitter having the optical DAC 100. In this case, the processor 601 shown in Figure 6 controls each function of the optical transmitter.

[0061] (Example 1) Figure 7 is a functional block diagram showing an example configuration of the optical DAC in Example 1. In the optical DAC 700 of Example 1, the function of the switch 115 that changes the combination of data and segments is placed within the DSP. In the optical DAC 700 of Example 1, an example configuration of 3 bits and 7 segments is shown, and the same reference numerals are used for components identical to those described above.

[0062] The optical DAC700 includes a DSP150, a driver116, an optical modulator121, an optical monitor unit117, and a control unit118.

[0063] The DSP150 includes a framer 111, an FEC 112, a mapping unit 113, an optical DAC encoder 114, a switch 115, and a serializer 711. The switch 115 is positioned after the optical DAC encoder 114 and can switch between outputting low-speed × n-lane data streams. For example, it outputs a 1Gbps × 64-lane data stream per lane. The number of lanes is determined by the ratio of the high-speed rate to the low-speed rate.

[0064] The serializer 711 converts (serializes) multiple (e.g., 64) slow data lines per lane into fast data and outputs them to seven lanes from bit0 to bit2. The serializer 711 outputs data at a high rate (e.g., 64 Gbaud) per lane, the same as the system's baud rate, to the driver 116.

[0065] In the first embodiment, the optical DAC 700 has a switch 115 located inside the DSP 150 and is controlled digitally, allowing data to be switched on a 1-symbol, 1-sample basis. The control unit 118 performs real-time timing adjustments during operation by repeatedly adjusting the timing of the 4 segments assigned to bit 2 and changing the combination of input bit data and segments by switching the switch.

[0066] (Example 1 of timing adjustment process in Example 1) Figure 8 is a flowchart of the timing adjustment process example 1 using the optical DAC in Embodiment 1. In timing adjustment process example 1, timing adjustment is performed in two different states, state 1 and state 2, as described above. Each process shown in Figure 8 is performed by the control unit 118 (CPU 601) controlling each function of the optical DAC 700.

[0067] Figure 9 is a diagram showing an example of the bit and segment combination state in Timing Adjustment Process Example 1 of Embodiment 1. Timing Adjustment Process Example 1 in Figure 8 will be explained with reference to Figure 9.

[0068] The control unit 118 continues to process the operations shown in Figure 8 in real time during operation, after the initial calibration of the optical transmitter, including the optical DAC 700 (pre-shipment or pre-adjustment at the device port) is completed and all settings, such as delay and bias status, have been adjusted. In the initial state, as shown as state 1 in Figure 9(a), the switch 115 assigns bit 0 (LSB) output by the DSP 150 to segment #1, bit 1 to segments #2 and #3, and bit 2 (MSB) to segments #4 to #7.

[0069] Then, in state 1, the control unit 118 can detect the delay amount of the MSB (bit 2) of the larger-amplitude higher-order bits by observing the output power of the optical monitor unit 117, which is the output of the optical modulator 121. The control unit 118 then adjusts the delay amounts of segments #4 to #7 using the delay adjustment unit 116a so that the monitor output power (optical output power of the specified frequency component) is maximized (step S801). Details of this timing adjustment process will be described later.

[0070] After performing the delay adjustment in step S801 for a certain period of time, the control unit 118 turns off the delay adjustment function of the delay adjustment unit 116a (step S802).

[0071] Next, the control unit 118 switches the bit and segment combination to state 2 shown in Figure 9(b) using switch 115 (step S803). In state 2, switch 115 switches to assign bit 2 (MSB) output by DSP 150 to segments #1 to #4. Segments #1 to #3 are segments whose timing was not adjusted in step S801. At this time, switch 115 assigns, for example, bit 0 (LSB) to segment #5, and bit 1 to segments #6 and #7.

[0072] Then, in state 2, the control unit 118 turns on the timing adjustment function by the delay adjustment unit 116a (step S804). Next, the control unit 118 can monitor segments #1 to #4 assigned to MSB (bit 2) by observing the output power at the optical monitor unit 117, which is the output of the optical modulator 121, and adjusts the delay amount of segments #1 to #4 by the delay adjustment unit 116a so that the monitor output power (optical output power of the specified frequency component) is maximized (step S805).

[0073] After performing the delay adjustment in step S805 for a certain period of time, the control unit 118 turns off the delay adjustment function of the delay adjustment unit 116a (step S806).

[0074] After this, the control unit 118 switches the bit and segment combination back to the original state 1 using the switch 115 (step S807), turns on the delay adjustment function by the delay adjustment unit 116a (step S808), and returns to the processing in step S801.

[0075] (Example 2 of timing adjustment process in Example 1) Figure 10 is a flowchart of the timing adjustment process example 2 using the optical DAC in Embodiment 1. In timing adjustment process example 2, delay adjustment is performed segment by segment. Each process shown in Figure 10 is performed by the control unit 118 (CPU 601) controlling each function of the optical DAC 700.

[0076] Figure 11 is a diagram showing the combination of bits and segments in the timing adjustment process example 2 of Embodiment 1. The timing adjustment process example 2 in Figure 10 will be explained with reference to Figure 11.

[0077] The control unit 118 continues to process the operations shown in Figure 10 in real time during operation, after the initial calibration of the optical transmitter, including the optical DAC 700 (pre-shipment or pre-adjustment at the device port) is completed and all settings, such as delay and bias status, have been adjusted. In the initial state, as shown in Figure 11(a), the switch 115 assigns bit 0 (LSB) output by the DSP 150 to segment #1, bit 1 to segments #2 and #3, and bit 2 (MSB) to segments #4 to #7 (State 1).

[0078] The control unit 118 then monitors segments #4 to #7 assigned to the MSB (bit 2) by observing the output power of the optical monitor unit 117, which is the output of the optical modulator 121. The delay adjustment unit 116a then adjusts the delay amount of segments #4 to #7 so that the monitor output power (optical output power of the specified frequency component) is maximized (step S1001). Details of this timing adjustment process will be described later.

[0079] After performing the delay adjustment in step S1001 for a certain period of time, the control unit 118 turns off the delay adjustment function of the delay adjustment unit 116a (step S1002).

[0080] Next, the control unit 118 switches the bit and segment combination to the state shown in Figure 11(b) using the switch 115 (step S1003). In this timing adjustment process example 2, the segments to which the MSB is assigned are swapped one by one. Here, the switch 115 switches the input data of segment #4 and segment #3 of bit2 (MSB) output by the DSP 150 (state 2). In this state, segments #1 to #3 are segments whose timing was not adjusted in step S1001.

[0081] Then, the control unit 118 turns on the delay adjustment function of the delay adjustment unit 116a (step S1004). Next, the control unit 118 monitors segments #3, #5, #6, and #7 assigned to the MSB (bit 2) by observing the output power of the optical monitor unit 117, which is the output of the optical modulator 121, and adjusts the delay amount of segment #3 using the delay adjustment unit 116a so that the monitor output power (optical output power of the specified frequency component) is maximized (step S1005).

[0082] After performing the delay adjustment in step S1005 for a certain period of time, the control unit 118 turns off the delay adjustment function of the delay adjustment unit 116a (step S1006).

[0083] Subsequently, the control unit 118 adjusts the timing for the next states 3 and 4 by swapping the MSB one by one for the bit and segment combinations, similar to the process described above (step S1007). In step S1007, the same process as in steps S1003 to S1006 is performed. For example, in the next state 3, the same process as in steps S1003 to S1006 is performed for the remaining unadjusted segment #2, switching the bit and segment combination and adjusting the delay of segments #2, #5 to #7. After this, in the next state 4, the same process as in steps S1003 to S1006 is performed for the remaining unadjusted segment #1, switching the bit and segment combination and adjusting the delay of segments #1, #5 to #7. After this, the control unit 118 returns to the process in step S1001.

[0084] In the timing adjustment process examples 1 and 2 of the above embodiment 1, the combination of bits and segments can be switched at any time using switch 115, and the timing adjustment time for the segment assigned to the MSB can be set to a predetermined time. In addition, during timing adjustment, when switch 115 is switched, one or more pairs (two segments) of segments are swapped, and a delay adjustment is performed for this pair of segments. Furthermore, the monitor may always be in the ON state, or it may be detected at regular intervals when the switch is switched. Moreover, the above delay adjustment process is just an example, and delay adjustment may be performed not only in the above delay adjustment process examples 1 and 2, but also in various other processes that change the combination of bits and segments.

[0085] (Specific example of timing adjustment process) Next, specific examples of timing adjustment processes will be explained using Figures 12 and 13. Here, specific examples of steps S801 and S805 of timing adjustment process example 1 (Figure 8) in Embodiment 1 above, and steps S1001 and S1005 of timing adjustment process example 2 (Figure 10) in Embodiment 2 above will be explained. These specific examples correspond to specific examples of delay amount adjustment explained using Figures 4A to 4C.

[0086] Figure 12 is a flowchart of a specific example of timing adjustment. For the sake of simplicity, this explanation describes the adjustment of the delay amount for four segments #4 to #7 of segment 122 that are assigned the same bit data (for example, bit 2 of the MSB).

[0087] First, in a certain state (for example, state 1), the control unit 118 fixes the switching path of the switch 115 and turns on the optical monitor unit 117 (step S1201). Next, the control unit 118 detects a change in the monitor value of the optical monitor unit 117 (step S1202). At this time, the control unit 118 detects a decrease from the maximum value (or an increase from the minimum value) as a change in the monitor value. Here, for example, the maximum value means that the timing between segments is in sync, and the delay difference between segments in Figure 4C is 0p seconds.

[0088] Next, the control unit 118 sweeps the delay amount for segment #4, which is the target of delay adjustment, in small intervals and fine-tunes it so that the monitor value at that time is the maximum (or minimum) (step S1203). Here, the control unit 118 performs control to sweep the delay amount after detecting a change in the monitor value.

[0089] After this, the control unit 118 sweeps the delay amount of the other segments #5, 6, and 7 in sequence over small intervals, and fine-tunes it so that the monitor value at that time is the maximum (or minimum) (step S1204).

[0090] Then, the control unit 118 continues monitoring to adjust to the maximum (or minimum) point (step S1205, see Figure 5C). During the period of continued monitoring, the control unit 118 returns to the process in step S1202 and continues processing until the switch 115 is flipped.

[0091] The control unit 118 then proceeds to the next step after a certain period of time has elapsed. This step transition corresponds to a change in the bit and segment combination by the switch 115, in which case the control unit 118 returns to processing step S1201.

[0092] Figure 13 is a flowchart of specific example 2 of timing adjustment. This specific example 2 is an example of adjusting the delay by sweeping the segment to be delayed in small intervals, using a certain segment as a reference. In Figure 13, for the sake of simplicity, we will explain the timing adjustment for four segments #4 to #7 of segment 122 that are assigned the same bit data (for example, bit 2 of the MSB).

[0093] First, in a certain state (for example, state 1), the control unit 118 fixes the switching path of the switch 115 and turns on the optical monitor unit 117 (step S1301). Next, the control unit 118 fixes the delay amounts of segments #4, #6, and #7, and for segment #5, which is the target of delay adjustment, sweeps the delay amount in small intervals and fine-tunes it so that the monitor value at this time is the maximum (or minimum) (step S1302).

[0094] Next, the control unit 118 fixes the delay amounts of segments #4, #5, and #7, and for segment #6, which is the target of delay adjustment, it sweeps the delay amount in small intervals and fine-tunes it so that the monitor value at this time is the maximum (or minimum) (step S1303).

[0095] Next, the control unit 118 fixes the delay amounts of segments #4, #5, and #6, and for segment #7, which is the target of delay adjustment, it sweeps the delay amount in small intervals and fine-tunes it so that the monitor value at this time is the maximum (or minimum) (step S1304).

[0096] Then, during the monitoring period, the control unit 118 returns to the process of step S1302 and continues to perform the process until the switch 115 is flipped.

[0097] The control unit 118 then proceeds to the next step after a certain period of time has elapsed. This step transition corresponds to a change in the bit and segment combination by the switch 115, in which case the control unit 118 returns to processing step S1301.

[0098] (Example 2) Figure 14 is a functional block diagram showing an example configuration of the optical DAC in Example 2. In the optical DAC 1400 of Example 2, the function of the switch that changes the input bit data and segment assignment is located outside the DSP. In the optical DAC 1400 of Example 2, an example configuration of 3 bits and 7 segments is shown, and the same reference numerals are used for components identical to those described above.

[0099] The optical DAC 1400 includes a DSP 150, a switch 1401, a driver 116, an optical modulator 121, an optical monitor unit 117, and a control unit 118.

[0100] The DSP150 includes a framer 111, an FEC 112, a mapping unit 113, an encoder 114 for the optical DAC, and a serializer 711.

[0101] Switch 1401 is positioned between the output of DSP 150 (serializer 711) and driver 116. Switch 1401 performs path switching for the seven lanes of bit0 to bit2 output by serializer 711. Here, serializer 711 outputs data to switch 1401 at a high rate equal to the system's baud rate per lane. Therefore, switch 1401 needs to be a circuit capable of rapidly switching the seven data and segment combinations of bit0 to bit2.

[0102] In Example 2, the optical DAC 1400 has a switch 1401 located outside the DSP 150, and the switch is turned on when the symbol (bit data) values ​​between different bit data, for example, bit0 and bit1, become the same. By repeatedly changing the combination of input bit data and assigned segment, real-time delay adjustment is performed during operation.

[0103] (Example of switch configuration in Example 2) Figure 15 is a circuit diagram showing an example of the switch configuration of the optical DAC in Embodiment 2. A requirement for realizing switch 1401 in high-speed data is that there should be no impact on the output waveform when switching. In this regard, Embodiment 2 switches the switch at high speed when different bit data, for example, symbols (bit data) between bit0 and bit1 occur at the same timing. For this reason, switch 1401 in Embodiment 2 is realized using a logic circuit that detects when input symbols between different bits that are to be swapped lanes by switching occur multiple times or more (for example, two times or more), and a switching unit that swaps bits and segments.

[0104] The switch 1401 includes a plurality of flip-flops (F / F) 1501 arranged between pairs of bit data, a comparison unit 1502, and a switching unit 1503.

[0105] The control unit 118 issues a bit data comparison instruction to the F / F1501 in the switch 1401 located in the two lanes to be swapped. The F / F1501 outputs the data for the preceding and succeeding steps in its own lane, and the data for the preceding and succeeding steps in the adjacent lane, to the comparison unit 1502.

[0106] In Figure 15, lane #1 has two F / F1501a and 1501b units. These two F / F1501a and F / F1501b units are input with a clock shift of one step, and each holds bit data that is shifted by one step. Lane #2 also has two F / F1501c and 1501d units. These two F / F1501c and 1501d units hold bit data that is shifted by one step, based on a clock shift of one step.

[0107] The comparison unit 1502 outputs a switching instruction to the switching unit 1503 when the four input data become identical. Similarly, for the other lanes, the unit compares the two lanes to be swapped and controls the switching.

[0108] For example, looking at lane #1 for bit0 and lane #2, one of the two lanes for bit1 in Figure 15, the bit data on lane #1 for bit0 is "110011...", and the bit data on lane #2 for bit1 is "100001...". In this way, during the operation of the optical transmitter, different bit data is continuously input between bits 0 and 1 of switch 1401 of the optical DAC 100 over time.

[0109] The comparison unit 1502 outputs a switching instruction to the switching unit 1503 when the bit data values ​​of the four F / F1501a to 1501d are the same, for example, when the bit data values ​​on lanes #1 and #2 are "00". As a result, the switching unit 1503 switches (swaps) the bit0 data to lane #2 and the bit1 data to lane #1 and outputs them. As explained using Figure 15, bits and segments can be swapped between pairs of lanes with different bit0 and bit1 values.

[0110] Figure 16 shows an example of a multi-stage array configuration of switches in the optical DAC of Embodiment 2. The numbered switches in Figure 16 correspond to the single-stage switches 1401 on the lane shown in Figure 15, and a single-stage switch 1401a swaps bit data between adjacent pairs of lanes. When swapping bit data in a total of 7 lanes of 3 bits 7 segments, as shown in Figure 16, 6 stages of switches 1401a to 1401f are arranged in multiple stages on the lane, and the bit data between adjacent lanes is sequentially swapped by switches 1401a to 1401f in each stage. The number of stages of switch 1401 is the total number of lanes minus 1.

[0111] In Figure 16, to output the bit data of bit0 to segment #7 (lane #7), switches 1401a to 1401f in each stage, arranged from the top to the bottom, perform bit data comparisons between adjacent bits and switch to the adjacent lane.

[0112] (Example 1 of timing adjustment process in Example 2) Figure 17 is a flowchart of the timing adjustment process example 1 using the optical DAC in Embodiment 2. In this timing adjustment process example 1, delay adjustment is performed in two states, state 1 and state 2. Therefore, the control unit 118 sequentially swaps the bit data between adjacent segments to change from state 1 to state 2. Each process shown in Figure 17 is performed by the control unit 118 (CPU 601) controlling each function of the optical DAC 1400.

[0113] Figures 18A and 18B show the switching state of bit and segment combinations in the timing adjustment process example 1 of Embodiment 2. The timing adjustment process example 1 of Figure 17 will be explained with reference to Figures 18A and 18B.

[0114] The control unit 118 continues to process the operations shown in Figure 17 in real time during operation, after the initial calibration of the optical transmitter, including the optical DAC 1400 (pre-shipment or pre-adjustment at the device port) is completed and all settings, such as delay and bias status, have been adjusted. In the initial state, as shown as state 1 in Figure 18A(a), the switch 1401 assigns bit 0 (LSB) output by the DSP 150 to segment #1, bit 1 to segments #2 and #3, and bit 2 (MSB) to segments #4 to #7.

[0115] Then, in state 1, the control unit 118 can monitor segments #4 to #7 assigned to the MSB (bit 2) by observing the output power of the optical monitor unit 117, which is the output of the optical modulator 121, and the delay amount of segments #4 to #7 is adjusted by the delay adjustment unit 116a so that the monitor output power (optical output power of the specified frequency component) is maximized (step S1701). The specific processing of the delay adjustment is the same as in Embodiment 1.

[0116] After performing the delay adjustment in step S1701 for a certain period of time, the control unit 118 turns off the delay adjustment function of the delay adjustment unit 116a (step S1702).

[0117] Next, the control unit 118 sequentially swaps bit data between adjacent lanes in order to switch the bit and segment combination to state 2 shown in Figure 18B(e) using the switch 1401. In the states shown in Figures 18A(a) to 18B(e), segments #1 to #3 are segments whose timing has not been adjusted in step S1701.

[0118] In Figures 18A and 18B, each bit data is assigned a sign, with one bit 0 being b01, two bits 1 being b11 and b12, and four bits 2 being b21 to b24. Note that Figures 18A(b) to 18B(e) only show the configuration of the optical modulator 121, and descriptions of the DSP 150, switch 1401, etc. are omitted.

[0119] First, as shown in Figure 18A(b), the control unit 118 swaps b12 and b21 using switch 1401 (step S1703). Next, the control unit 118 swaps b12 and b22 using switch 1401 (step S1704). Next, the control unit 118 swaps b12 and b23 using switch 1401 (step S1705). Next, the control unit 118 swaps b12 and b24 using switch 1401 (step S1706). In steps S1703 to S1706, the detection and swapping functions between segments are sequentially turned on to swap the segments, and then turned off after the swap.

[0120] This allows the system to switch the output state of bits 2 b21-b24 to lanes #3-#6, as shown in Figure 18A(c). In this case, bit 1 b12 will be output to lane #7.

[0121] Subsequently, the control unit 118 similarly swaps bit data between adjacent lanes for b11, i.e., swaps b11 with b21, b22, b23, and b24 in sequence until it reaches state 2 (step S1707). This results in the swapped state shown in Figure 18B(d).

[0122] Subsequently, the control unit 118 similarly swaps bit data between adjacent lanes for b01, i.e., swaps b01 with b21, b22, b23, and b24 in sequence until state 2 is reached (step S1708). This results in state 2 of the bit and segment combination shown in Figure 18B(e).

[0123] Then, in state 2, the control unit 118 turns on the delay adjustment function by the delay adjustment unit 116a (step S1709). Next, the control unit 118 performs an MSB (bit 2) monitor and observes the output power at the optical monitor unit 117, which is the output of the optical modulator 121, thereby enabling monitoring of segments #1 to #4 assigned to MSB (bit 2). The delay adjustment unit 116a then adjusts the delay amount of segments #1 to #4 so that the monitor output power (optical output power of the specified frequency component) is maximized (step S1710).

[0124] After performing the delay adjustment in step S1710 for a certain period of time, the control unit 118 returns the bit and segment combination to state 1. For this reason, the control unit 118 performs the swapping of bit data between adjacent lanes in reverse order.

[0125] The control unit 118 swaps the bit data between adjacent lanes for b01, i.e., swaps b01 with b24, b23, b22, and b21 in order (step S1711). After this, the control unit 118 swaps the bit data between adjacent lanes for b11, i.e., swaps b11 with b24, b23, b22, and b21 in order (step S1712). After this, the control unit 118 swaps the bit data between adjacent lanes for b12, i.e., swaps b12 with b24, b23, b22, and b21 in order (step S1713). As a result, state 1 of the bit and segment combination shown in Figure 18A(a) is obtained. Then, the control unit 118 returns to the process of step S1701.

[0126] (Example 2 of timing adjustment process in Example 2) Figure 19 is a flowchart of the timing adjustment process example 2 using the optical DAC in Embodiment 2. In this timing adjustment process example 2, timing adjustment is performed between adjacent segments. Each process shown in Figure 19 is performed by the control unit 118 (CPU 601) controlling the functions of the optical DAC 1400.

[0127] Figure 20 shows the combination of bits and segments in the timing adjustment process example 2 of Embodiment 2. The timing adjustment process example 2 in Figure 19 will be explained with reference to Figure 20.

[0128] The control unit 118 continues to process the operations shown in Figure 19 in real time during operation, after the initial calibration of the optical transmitter, including the optical DAC 1400 (pre-shipment or pre-adjustment at the device port) is completed and all settings, such as delay and bias status, have been adjusted. In the initial state, as shown as state 1 in Figure 20(a), the switch 1401 assigns bit 0 (LSB) output by the DSP 150 to segment #1, bit 1 to segments #2 and #3, and bit 2 (MSB) to segments #4 to #7.

[0129] Then, in state 1, the control unit 118 can monitor segments #4 to #7 assigned to the MSB (bit 2) by observing the output power of the optical monitor unit 117, which is the output of the optical modulator 121, and the delay amount of segments #4 to #7 is adjusted by the delay adjustment unit 116a so that the monitor output power (optical output power of the specified frequency component) is maximized (step S1901). The specific process for adjusting the delay amount is the same as in Embodiment 1.

[0130] After performing the delay adjustment in step S1901 for a certain period of time, the control unit 118 turns off the delay adjustment function of the delay adjustment unit 116a (step S1902).

[0131] Next, the control unit 118 switches bit data between adjacent lanes for bit and segment combinations using the switch 1401. First, the control unit 118 switches bit1's b12 and bit2's b21 as shown in Figure 20(b) (step S1903). In the state shown in Figure 20(b), segments #1 to #3 are segments with unadjusted delay amounts.

[0132] Then, the control unit 118 turns on the delay adjustment function of the delay adjustment unit 116a (step S1904). Next, the control unit 118 can monitor segments #3, #5 to #7 assigned to the MSB (bit 2) by observing the output power of the optical monitor unit 117, which is the output of the optical modulator 121, and adjusts the delay amount of segment #3 using the delay adjustment unit 116a so that the monitor output power (optical output power of the specified frequency component) is maximized (step S1905).

[0133] After performing the delay adjustment in step S1905 for a certain period of time, the control unit 118 turns off the delay adjustment function (step S1906) and switches bit 1 b12 and bit 2 b22 (step S1907).

[0134] Then, the control unit 118 turns on the delay adjustment function of the delay adjustment unit 116a (step S1908). Thereafter, in the same manner as above, the lane switching and delay adjustment are repeatedly performed for segments #2 and #1, whose delay amounts have not been adjusted, one segment at a time.

[0135] (Example 3 of timing adjustment process in Example 2) Figure 21 shows Example 3 of the timing adjustment process using the optical DAC in Example 2. In the above explanation, the switching (swapping) of bit and segment combinations between adjacent pairs of segments was described, but in this timing adjustment process Example 3, the switching of bit and segment combinations is performed between pairs of non-adjacent segments.

[0136] As shown in Figure 21, the bit data can be swapped between segments #1, #7, #2, #6, #3, and #5, with segment #4 as the center, to obtain the bit and segment combinations for state 1 and state 2. According to this timing adjustment process example 3, it can be easily constructed with just one stage switch 1401.

[0137] (Example of switch switching timing detection in Example 2) In the above description of Example 2, the control unit 118 of the optical DAC is configured to detect the timing at which symbols (bit data) become the same multiple times between different bits during operation. Assuming the bit data is a pseudo-random signal (PRBS: Pseudo-Random Binary Sequence), the frequency at which symbols become the same multiple times (twice in the explanation in Figure 15) between a pair of bits is sufficient.

[0138] Figure 22 shows an example of switch switching timing detection using an optical DAC in Example 2. Figure 22 shows the transmission data format, where the transmission data SD includes a training sequence (TS) with a header HS at the beginning, and a payload where the actual data is stored. For example, in typical digital coherent transmission, the transmission data SD consists of tens of thousands of symbols in total, and the TS consists of several hundred symbols.

[0139] In this case, if the transmitted data consists of tens of thousands of symbols at 64 Gbaud, the period is approximately on the order of several hundred nanoseconds. The optical DAC1400 can pre-prepare known signals that occur at intervals of several hundred nanoseconds to several microseconds and insert them into the transmitted data SD.

[0140] Furthermore, the optical DAC 1400 in Example 2 may insert a known signal that is continuous with any part of the TS. For example, it may be inserted into the training sequence.

[0141] (Example of a coherent optical DAC configuration) Figure 23 shows an example configuration of a coherent optical DAC. This optical DAC 2300 receives IQ data as input to the DSP 150 and has a symmetrical I-side circuit 2300I and a Q-side circuit 2300Q downstream of the DSP 150 to generate and output coherent light. The I-side circuit 2300I and the Q-side circuit 2300Q each include a switch 115 and a driver 116 (delay adjustment unit 116a, binary driver array 116b). In Figure 23, the same reference numerals are used for the same configuration as in Example 1 (Figure 1), but the configuration is also applicable to Example 2, and the switch 1401 from Example 2 may be used instead of the switch 115.

[0142] In the IQ configuration, the optical modulator 121 on the optical circuit side has three demultiplexers 123 at the optical input section. A two-way demultiplexer 123a splits the signal into I and Q sides, a demultiplexer 123b on the I side splits it into two more signals, and a demultiplexer 123c on the Q side splits it into two more signals. The optical output section has three multiplexers 124. A demultiplexer 124b on the I side combines two signals, a demultiplexer 124c on the Q side combines two signals, and these I and Q signals are combined by a multiplexer 124a to produce the optical output. A DC phase shifter 125 controls the phase of the I and Q sides with DC bias. A DC phase shifter 127 for bias control between I and Q is provided between multiplexers 124c and 124a.

[0143] As described above, by providing a pair of optical DACs, one on the I side and one on the Q side, as explained in Examples 1 and 2, a coherent optical transmitter can be configured. Furthermore, by providing the I-side circuit 2300I and the Q-side circuit 2300Q symmetrically on the optical DAC 2300, delay adjustment can be performed for both the I-side and Q-side of the coherent light.

[0144] The optical transmitter of the embodiment described above includes an optical modulator having three or more segments arranged in series along one or both of the two optical waveguides of a Mach-Zehnder interferometer; two or more types of input bit data (corresponding to an optical DAC) input to the segments of the optical modulator; an encoder that outputs multi-bit bit data to the segments obtained by coding the input bit data for optical modulation by the optical modulator; a switch that can switch the bit data output by the encoder to different segments; and a delay adjustment unit that adjusts the amount of delay between segments. The control unit of the optical DAC instructs the switch to switch the bit data output by the encoder to different segments and to adjust the amount of delay in the delay adjustment unit based on monitoring of the optical signal after optical modulation by the optical modulator. As a result, even when operating an optical transmitter in which bit data with different values ​​for each bit is continuously input, the delay can be adjusted by switching the switch to output delay-adjustable bit data to segments that have not yet undergone delay adjustment.

[0145] Furthermore, in the optical transmitter of this embodiment, the control unit controls the switch to switch bit data that outputs at least two or more identical data bits from among multiple bits to segments where delay adjustment has not been performed on a bit-by-bit basis. For example, the control unit controls the switch to switch multiple bit data of the MSB on a bit-by-bit basis. This makes it possible to easily perform delay adjustment between a pair of segments.

[0146] Furthermore, the optical transmitter in this embodiment may have a serializer that converts the encoder's output rate into baud rate data, and a switch may be placed before the serializer. In this case, the switch can be switched at a low rate before serialization.

[0147] Furthermore, the optical transmitter in this embodiment may have a serializer that converts the encoder's output rate into baud rate data, and a switch may be placed after the serializer. In this case, the switch switching configuration should be such that it corresponds to the high rate after serialization.

[0148] Furthermore, in the embodiment, the optical transmitter may have a control unit that performs delay adjustment between adjacent segments where delay adjustment has not been performed, in each of the different states before and after switching bit data to different segments bit by bit using a switch. In this way, by switching at the bit level with the same value, delay adjustment for all segments can be easily performed.

[0149] Furthermore, in the optical transmitter of this embodiment, the control unit may perform delay adjustment between adjacent segments where delay adjustment has not yet been performed while switching bit data to different segments bit by bit using a switch. In this way, when switching bit by bit, delay adjustment can be performed between the corresponding segments each time bit data is swapped, thereby performing delay adjustment for all segments.

[0150] Furthermore, in the embodiment, the optical transmitter may also output an instruction to a switch to swap the data between corresponding segments when the control unit detects that a predetermined number of different bit data input to a segment have the same value. This makes it easy to swap segments and allows for delay adjustment between segments that have output the same value.

[0151] Furthermore, in the optical transmitter of this embodiment, a predetermined number of consecutive identical values ​​may be inserted in advance as a known signal into a portion of the input transmission data, and the control unit may detect the predetermined number of consecutive identical values. For example, the known signal can be one inserted into the training sequence of the transmission data. This makes it easy to detect a state in which a predetermined number of different bits of bit data input to a segment have the same value using the known signal.

[0152] Furthermore, the optical transmitter of this embodiment may have an optical DAC that includes an optical modulator, an encoder, a switch, a delay adjustment unit, and a control unit in the I-side circuit and the Q-side circuit, respectively, and output coherent light. By providing the I-side circuit and the Q-side circuit symmetrically in the optical DAC, it becomes possible to adjust the delay of the I-side and Q-side of the coherent light.

[0153] With regard to the embodiments described above, the following additional information is disclosed.

[0154] (Note 1) An optical modulator having three or more segments arranged in series along one or both of the two optical waveguides of a Mach-Zehnder interferometer, Two or more types of input bit data are input to the segment of the optical modulator, An encoder that outputs multi-bit bit data obtained by coding the input bit data for optical modulation of the optical modulator to the segment, A switch capable of switching the bit data output by the encoder to different segments, A delay adjustment unit that adjusts the amount of delay between the segments, A control unit that switches the bit data output by the encoder to a different segment, and instructs the delay amount of the delay adjustment unit based on monitoring of the optical signal after optical modulation by the optical modulator, An optical transmitter characterized by having the following features.

[0155] (Note 2) The control unit controls the switch to switch the bit data that outputs at least two or more identical data from the plurality of bits to a segment where delay adjustment has not been performed on a bit-by-bit basis. The optical transmitter described in Appendix 1, characterized by the features described herein.

[0156] (Note 3) The control unit controls the switch to switch multiple bit data of the MSB on a bit-by-bit basis. The optical transmitter described in Appendix 2, characterized by the features described herein.

[0157] (Note 4) The serializer has a function that converts the output rate of the encoder into baud rate data. The optical transmitter according to Appendix 1, characterized in that the switch is placed before the serializer.

[0158] (Note 5) The encoder has a serializer that converts the output rate of the encoder into baud rate data, The optical transmitter according to Appendix 1, characterized in that the switch is located downstream of the serializer.

[0159] (Note 6) The control unit is, In each of the different states before and after switching the bit data to different segments on a bit-by-bit basis using the switch, delay adjustment is performed between adjacent segments where delay adjustment has not been performed. The optical transmitter described in Appendix 1, characterized by the features described herein.

[0160] (Note 7) The control unit is, During the process of switching the bit data to different segments on a bit-by-bit basis using the aforementioned switch, delay adjustment is performed between adjacent segments where delay adjustment has not yet been performed. The optical transmitter described in Appendix 1, characterized by the features described herein.

[0161] (Note 8) In Note 5, When the control unit detects that the bit data of different bits input to the segment has the same value for a predetermined number of consecutive times, it outputs an instruction to the switch to swap the data between the corresponding segments. An optical transmitter characterized by the features described above.

[0162] (Note 9) A predetermined number of consecutive identical values ​​are inserted in a portion of the input data for transmission as known signals. The control unit detects the predetermined number of consecutive identical values. The optical transmitter described in Appendix 8, characterized by the features described above.

[0163] (Note 10) The optical transmitter according to Note 9, characterized in that the known signal is inserted into the training sequence of the data to be transmitted.

[0164] (Note 11) An optical DAC having the optical modulator, the encoder, the switch, the delay adjustment unit, and the control unit respectively in the I-side circuit and the Q-side circuit, and outputting coherent light, as described in Note 1.

[0165] (Note 12) A timing adjustment method for an optical modulator having three or more segments arranged in series along one or both of the two optical waveguides of a Mach-Zehnder interferometer, and an optical transmitter that outputs an optical signal using two or more types of input bit data input to the segments of the optical modulator, The encoder outputs multiple bits of bit data, obtained by coding the input bit data for optical modulation by the optical modulator, to the segment. The delay adjustment unit adjusts the amount of delay between the segments. The control unit switches the bit data output by the encoder to different segments bit by bit and outputs it, and instructs the delay amount of the delay adjustment unit based on monitoring of the optical signal after optical modulation by the optical modulator. A timing adjustment method characterized by the following: [Explanation of Symbols]

[0166] 100,700,1400,2300 optical DAC 110 Electronic circuits 111 Frame 112 FEC 113 Mapping section 114 Optical DAC Encoder 115 switches 116 Drivers 116a Delay adjustment section 116b Binary driver array 117 Optical Monitor Section 118 Control Unit 120 Optical circuit 121 Optical modulator 122 segments (phase shifter) 123 Duplexer 124 Multiplexer 125 DC Phase Shifter 126 Optical waveguide 161 Monitor PD 162 Frequency Filter 163 Power Monitor 601 Processor 602 memory 605 Recording media 711 Serializer 1401 switch 1501 F / F 1502 Comparison Section 1503 Switching section

Claims

1. An optical modulator having three or more segments arranged in series along one or both of the two optical waveguides of a Mach-Zehnder interferometer, Two or more types of input bit data are input to the segment of the optical modulator, An encoder that outputs multi-bit bit data obtained by coding input bit data for optical modulation of the optical modulator to the segment, A switch capable of switching the bit data output by the encoder to different segments, A delay adjustment unit that adjusts the amount of delay between the segments, A control unit that switches the bit data output by the encoder to a different segment, and instructs the delay amount of the delay adjustment unit based on monitoring of the optical signal after optical modulation by the optical modulator, An optical transmitter characterized by having the following features.

2. The control unit controls the switch to switch the bit data, which outputs at least two or more identical data from the plurality of bits, to a segment where delay adjustment has not been performed on a bit-by-bit basis. The optical transmitter according to feature 1.

3. The serializer includes a converter that converts the output rate of the encoder into baud rate data. The optical transmitter according to claim 1, characterized in that the switch is placed before the serializer.

4. The serializer includes a converter that converts the output rate of the encoder into baud rate data. The optical transmitter according to claim 1, characterized in that the switch is located downstream of the serializer.

5. The control unit, In each of the different states before and after switching the bit data to different segments on a bit-by-bit basis using the switch, delay adjustment is performed between adjacent segments where delay adjustment has not been performed. The optical transmitter according to feature 1.

6. The control unit, During the process of switching the bit data to different segments on a bit-by-bit basis using the aforementioned switch, delay adjustment is performed between adjacent segments where delay adjustment has not yet been performed. The optical transmitter according to feature 1.

7. In claim 6, When the control unit detects that the bit data of different bits input to the segment has the same value for a predetermined number of consecutive times, it outputs an instruction to the switch to swap the data between the corresponding segments. An optical transmitter characterized by the following features.

8. A predetermined number of consecutive identical values ​​are inserted into a portion of the input data for transmission as a known signal. The control unit detects the predetermined number of consecutive identical values. The optical transmitter according to feature 7.

9. The optical transmitter according to claim 8, characterized in that the known signal is inserted into the training sequence of the data to be transmitted.

10. The optical transmitter according to claim 1, which has an optical DAC that includes the optical modulator, the encoder, the switch, the delay adjustment unit, and the control unit in the I-side circuit and the Q-side circuit, respectively, and outputs coherent light.

11. A timing adjustment method for an optical modulator having three or more segments arranged in series along one or both of the two optical waveguides of a Mach-Zehnder interferometer, and an optical transmitter that outputs an optical signal using two or more types of input bit data input to the segments of the optical modulator, The encoder outputs the input bit data to the segment by encoding it into a multi-bit dataset for optical modulation by the optical modulator. The delay adjustment unit adjusts the amount of delay between the segments. The control unit switches the bit data output by the encoder to different segments bit by bit and outputs it, and instructs the delay amount of the delay adjustment unit based on monitoring of the optical signal after optical modulation by the optical modulator. A timing adjustment method characterized by the following:

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