Gate driving method for GaN-HEMT elements, gate driving device for GaN-HEMT elements, and power conversion device

Abstract

The present invention provides a gate driving method for GaN-HEMT elements, a gate driving device for GaN-HEMT elements, and a power conversion device. [Solution] A method for driving the gates of two GaN-HEMT elements, wherein a gate signal, which is an on command or off command, obtained by PWM modulation is converted into a gate voltage via a gate driving circuit, and the gates of the GaN-HEMT elements are driven by applying the gate voltage, and at natural integer multiples of the carrier half-cycle of PWM modulation, the signal is used to determine which of the two GaN-HEMT elements is conducting in reverse, and a first period is provided during which an off command is given to both GaN-HEMT elements simultaneously, in which, based on the timing of the gate signal, the gate voltage applied to the GaN-HEMT element that is conducting in reverse is set higher than the negative gate voltage applied to the other GaN-HEMT element.

Description

[Technical Field]

[0001] This disclosure relates to a gate driving method for a GaN-HEMT element, a gate driving device for a GaN-HEMT element, and a power conversion device. [Background technology]

[0002] Patent Document 1 discloses a drive circuit for driving a pair of semiconductor elements constituting a half-bridge circuit, comprising: a gate drive circuit that applies an on-voltage to turn on the semiconductor elements and an off-voltage to turn off the semiconductor elements to the gates of the semiconductor elements; and an off-voltage generation circuit that generates an off-voltage, wherein when the first operating-side element, which is a semiconductor element that performs a first operation that flows current in the forward direction, turns on, the off-voltage applied to the gate of the second operating-side element, which is a semiconductor element that performs a second operation that flows current in the reverse direction, is changed to a more negative voltage than the normal voltage, and the off-voltage generation circuit is characterized in that it starts changing the off-voltage to a negative direction during the period when the current flowing through the first operating-side element in the forward direction is increasing.

[0003] However, the off-voltage generation circuit in Reference 1 operates by detecting changes in the drain current of the first operating element, and therefore its high-speed operation is limited by the detection delay. As a result, there is a challenge in that it must be implemented near the element and inside the gate drive circuit in order to minimize stray reactance and stray capacitance. [Prior art documents] [Patent Documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 2015-012624 [Overview of the project] [Problems that the invention aims to solve]

[0005] The present disclosure aims to provide a gate driving method for a GaN-HEMT element, a gate driving device for a GaN-HEMT element, and a power conversion device, which can be configured using a control sensor and a general-purpose gate driving circuit originally provided in the power conversion device. [Means for solving the problem]

[0006] A gate driving method for a GaN-HEMT element in the first aspect comprises a series circuit consisting of two GaN-HEMT elements having an ohmic junction or Schottky junction as a gate, and a current sensor or a phase sensor, and a power conversion device that drives the two GaN-HEMT elements by performing PWM modulation based on a signal from the current sensor or the phase sensor, wherein the gate signal, which is an on command or off command, obtained by the PWM modulation is converted into a gate voltage via the gate driving circuit. The gate voltage is applied to drive the gate of the GaN-HEMT element, and at natural integer multiples of the carrier half-cycle of the PWM modulation, the signal is used to determine which of the two GaN-HEMT elements is conducting in reverse, and during the period in which an off command is given to both GaN-HEMT elements simultaneously, a first period is provided in which, based on the timing of the gate signal, the gate voltage applied to the GaN-HEMT element that is conducting in reverse is set higher than the negative gate voltage applied to the other GaN-HEMT element. This makes it possible to provide a method for driving the gate of a GaN-HEMT element that can be configured using a control sensor and a general-purpose gate drive circuit that are originally equipped in the power conversion device. The gate driving method for a GaN-HEMT element according to the second aspect is the gate driving method for a GaN-HEMT element according to the first aspect, wherein, during the first period, the gate voltage applied to the reverse-conducting GaN-HEMT element is 0V or less. This makes it possible to suppress power loss due to reverse conduction while suppressing self-turn-on of the GaN-HEMT element. The third aspect of the GaN-HEMT element gate driving method is the gate driving method of the GaN-HEMT element according to the first or second aspect, wherein, during the first period, the negative gate voltage applied to the other GaN-HEMT element is greater than or equal to the minimum allowable voltage of the other GaN-HEMT element. This prevents damage to the GaN-HEMT element. The gate driving method for the GaN-HEMT element in the fourth aspect is a gate driving method for any one of the GaN-HEMT elements in the first to third aspects, wherein, during the period in which an off command is given simultaneously, if current flows into the series circuit, the GaN-HEMT element in the upper arm is determined to be the reverse-conducting GaN-HEMT element, and if current flows out of the series circuit, the GaN-HEMT element in the lower arm is determined to be the reverse-conducting GaN-HEMT element. This eliminates the need for a circuit to detect the reverse-conducting switch S. The fifth aspect of the GaN-HEMT element gate driving method is a gate driving method for any one of the first to fourth aspects, wherein, during the first period, the gate voltage applied to the reverse-conducting GaN-HEMT element is set to 0V or less on both the rising and falling sides of the drain-source voltage of the reverse-conducting GaN-HEMT element. This suppresses self-turn-on of the GaN-HEMT element while suppressing power loss due to reverse conduction. The gate driving method for GaN-HEMT elements in the sixth aspect is as described in the first aspect to Fourth perspective A gate driving method for any one of the GaN-HEMT elements, wherein, during the first period, on the rising side of the drain-source voltage of the reverse-conducting GaN-HEMT element, the gate voltage applied to the reverse-conducting GaN-HEMT element is set to 0V or less. This makes it possible to suppress the self-turn-on of the GaN-HEMT element in response to a positive surge voltage. The gate driving method for a GaN-HEMT element according to the seventh aspect is a gate driving method for a GaN-HEMT element according to any one of the first to sixth aspects, wherein, during the period in which off commands are given simultaneously, a second period is provided in which, on the falling edge of the drain-source voltage of one of the reverse-conducting GaN-HEMT elements, the gate voltage applied to the reverse-conducting GaN-HEMT element and the negative gate voltage applied to the other GaN-HEMT element are set to be equal. This makes it possible to suppress the effects of resonance. The gate driving method for a GaN-HEMT element according to the eighth aspect is a gate driving method for a GaN-HEMT element according to any one of the first to seventh aspects, wherein a third period is provided in which, during the period when the input / output current, output voltage, or power supply voltage of the series circuit cross over to zero and an off command is simultaneously given, the gate voltage applied to one of the reverse-conducting GaN-HEMT elements and the negative gate voltage applied to the other GaN-HEMT element are set to be equal. This enables stable gate driving. The gate driving method for a GaN-HEMT element according to the ninth aspect is a gate driving method for any one of the GaN-HEMT elements according to the first to eighth aspects, wherein the power conversion device is a converter having at least one of the series circuits, and the method for determining which GaN-HEMT element is conducting in reverse is a method using an input current sensor and power supply voltage phase information. This makes it possible to provide a converter that suppresses power loss due to reverse conduction. The gate driving method for a GaN-HEMT element according to the tenth aspect is a gate driving method for any one of the GaN-HEMT elements according to the first to eighth aspects, wherein the power conversion device is an inverter having at least one of the series circuits, and the method for determining which GaN-HEMT element is conducting in reverse is a method using an output current sensor or output voltage phase information. This makes it possible to provide an inverter that suppresses power loss due to reverse conduction. A gate drive device for a GaN-HEMT element in the eleventh aspect comprises a series circuit consisting of two GaN-HEMT elements having an ohmic junction or Schottky junction as a gate, and a current sensor or a phase sensor, and drives the two GaN-HEMT elements by performing PWM modulation based on the signal from the current sensor or the phase sensor, wherein the device drives the gates of the two GaN-HEMT elements, and the gate signal, which is an on command or off command, obtained by the PWM modulation is converted into a gate voltage via the gate drive circuit. The gate voltage is applied to drive the gate of the GaN-HEMT element, and at natural integer multiples of the carrier half-cycle of the PWM modulation, the signal is used to determine which of the two GaN-HEMT elements is conducting in reverse, and during the period in which an off command is given to both GaN-HEMT elements simultaneously, a first period is provided in which, based on the timing of the gate signal, the gate voltage applied to the GaN-HEMT element that is conducting in reverse is set higher than the negative gate voltage applied to the other GaN-HEMT element. This makes it possible to provide a gate drive device for a GaN-HEMT element that can be configured using a control sensor and a general-purpose gate drive circuit that are originally equipped in the power converter. The power converter according to the twelfth aspect incorporates the gate drive device described in the eleventh aspect. This makes it possible to provide a power converter that can suppress power loss due to reverse conduction while suppressing self-turn-on of the GaN-HEMT element. [Brief explanation of the drawing]

[0007] [Figure 1] This figure shows an example of a power conversion device to which this embodiment is applied. [Figure 2] This diagram illustrates the operating modes of the BTP circuit. (a) shows the upper half-wave charging mode of the AC power supply VAC, (b) shows the upper half-wave discharge mode of the AC power supply VAC, (c) shows the lower half-wave charging mode of the AC power supply VAC, and (d) shows the lower half-wave discharge mode of the AC power supply VAC. [Figure 3]This is a timing chart showing the gate drive operation. (a) shows the case where current flows into a series circuit consisting of two GaN-HEMT elements, and (b) shows the case where current flows out of a series circuit consisting of two GaN-HEMT elements. [Figure 4] This figure shows the BTP circuit of Example 1 and the current source load connected to it. [Figure 5] These are the block diagram and logic circuit diagram of the BTP control circuit in Example 1. [Figure 6] This diagram illustrates the gate drive of Example 1. (a) is a complementary gate drive circuit diagram, and (b) is a timing chart showing the gate drive operation. [Figure 7] This figure shows the BTP circuit of Example 2 and the current source load connected to it. [Figure 8] These are the block diagram and logic circuit diagram of the BTP control circuit in Example 2. [Figure 9] This figure shows the BTP circuit of Example 3 and the current source load connected to it. [Figure 10] These are the block diagram and logic circuit diagram of the inverter control circuit of Example 3. [Figure 11] This diagram illustrates the gate drive of the inverter in Example 3. (a) is a complementary gate drive circuit diagram, and (b) is a timing chart showing the gate drive operation. [Figure 12] This is a block diagram of the sensorless control unit and coordinate transformation unit of Embodiment 3. [Figure 13] This figure shows the results of a simulation regarding the gate drive method of the BTP circuit. (a) is the simulation result for Comparative Example 1, (b) is the simulation result for Example 1, and (c) is the circuit model used in the simulation. [Figure 14] This figure shows the results of the instantaneous loss analysis of the BTP circuit. (a) shows the analysis results for Comparative Example 1, and (b) shows the analysis results for Example 1. [Figure 15] This figure shows the total loss per element and the reduction rate of the total loss. [Figure 16]These are the block diagram and logic circuit diagram of the BTP control circuit in Example 4. [Figure 17] This is a timing chart showing the gate drive operation in Example 4. [Figure 18] This figure shows the simulation results regarding the gate drive method of the BTP circuit. (a) shows the simulation results for Comparative Example 2, and (b) shows the simulation results for Example 4. [Figure 19] This figure shows the results of the instantaneous loss analysis of the BTP circuit. (a) shows the analysis results for Comparative Example 2, and (b) shows the analysis results for Example 4. [Figure 20] This figure shows the total loss per element and the reduction rate of the total loss. [Figure 21] This diagram shows the characteristics of a GaN-HEMT element. (a) is a diagram illustrating the voltage drop that occurs during conduction, and (b) is a diagram illustrating the reverse conduction characteristics. [Modes for carrying out the invention]

[0008] The embodiments will be described in detail below with reference to the attached drawings. Figure 1 shows an example of a power conversion device to which this embodiment is applied. The power converter 1 to which this embodiment is applied includes a Bridgeless Totem Pole Power Factor Correction (BTP) circuit 10, a BTP control circuit 20, a polarity discrimination circuit 30, a complementary gate drive circuit 40, and a periodic gate drive circuit 50. The gate drive device includes the BTP control circuit 20, the polarity discrimination circuit 30, the complementary gate drive circuit 40, and the periodic gate drive circuit 50.

[0009] The BTP circuit 10 consists of two switches S1 and S2 made of GaN-HEMT elements, two switches S3 and S4 made of MOSFETs, two diodes D1 and D2, and an AC power supply V AC And reactor L1 and capacitor C L And, resistor R Land. When switches S1 and S2 are not distinguished, they are denoted as switch S.

[0010] The source of switch S1 and the drain of switch S2 are connected. This forms a series circuit composed of two GaN-HEMT elements each having an ohmic junction or a Schottky junction at the gate. The source of switch S3 and the drain of switch S4 are connected. The anode of diode D1 is connected to the source of switch S3. The cathode of diode D1 is connected to the drain of switch S3. The anode of diode D2 is connected to the source of switch S4. The cathode of diode D2 is connected to the drain of switch S4. Diodes D1 and D2 may be body diodes of a MOSFET.

[0011] The drain of switch S1, the drain of switch S3, and the capacitor C L has one end connected to, and the resistor R L has one end connected to. The source of switch S2, the source of switch S4, and the capacitor C L has the other end connected to, and the resistor R L has the other end connected to. One end of reactor L1 is connected to the AC power supply V AC on the live (L) side. The other end of reactor L1 is connected to a connection point between the source of switch S1 and the drain of switch S2. The AC power supply V AC on the neutral (N) side is connected to a connection point between the source of switch S3 and the drain of switch S4.

[0012] Switch S1 and switch S2 complementarily repeat an on state and an off state to perform Pulse Width Modulation (hereinafter referred to as PWM). For this reason, GaN-HEMT elements having high-speed switching characteristics are used for switch S1 and switch S2. Although switch S1 and switch S2 complementarily repeat the on state and the off state, a dead time period in which both switch S1 and switch S2 are in the off state is provided between the switching cycles. Switches S3 and S4 are AC power supply V AC The switch alternates between on and off states depending on the period. When the AC power supply is in the upper half-wave phase, switch S4 is on, and when it is in the lower half-wave phase, switch S3 is on. MOSFETs are used for switches S3 and S4 because they perform synchronous rectification (in the region where the Vf of the FRD connected in parallel with the Si-MOSFET is small, the Si-MOSFET recirculates the current). The operation of switches S1, S2, S3, and S4 causes resistor R L A DC voltage V is applied to both ends of it. dc This will occur.

[0013] The BTP control circuit 20 receives a signal I from the current sensor 21. s , AC power supply V AC Signal V from a phase sensor (not shown) s , resistance R L The value of the DC voltage V generated across the terminals of the wire. dc , resistance R L Command value V of the DC voltage generated across both ends dc * The BTP control circuit 20 receives the signal I from the current sensor 21. s , or the signal V from the phase sensor s PWM modulation is performed based on this. The BTP control circuit 20 receives the command value V of the DC voltage. dc * and the value of DC voltage V dc Based on the difference and the result of PWM modulation, gate signals S1 and S2 for switches S1 and S2 are generated. The BTP control circuit 20 uses gate signals S1 and S2 to generate a signal S indicating the dead time period. v0 The BTP control circuit 20 also generates the signal V from the phase sensor. s Based on this, gate signals S3 and S4 for switches S3 and S4 are generated. The current sensor 21 measures the current input to two switches S1 and S2, which are made of GaN-HEMT elements, and is an example of an input current sensor.

[0014] The polarity discrimination circuit 30 receives the signal I from the current sensor 21. sThe signal I from the current sensor 21 is input. The polarity discrimination circuit 30 receives the signal I from the current sensor 21. s Polarity is determined by this, and a signal S indicates whether current is flowing into the series circuit consisting of two GaN-HEMT elements or flowing out of the series circuit consisting of two GaN-HEMT elements. pn This generates a signal I from the current sensor 21 when the circuit is operated at a power factor of 1, such as in a BTP circuit. s Instead, the signal V from the phase sensor s It is also possible to use [this method]. Furthermore, if the power factor deviates from 1, it is possible to correct it using the phase lead angle and phase lagging angle.

[0015] The complementary gate drive circuit 40 receives the gate signals S1 and S2 generated by the BTP control circuit 20 and the signal S indicating the dead time period. v0 And the signal S generated by the polarity discrimination circuit 30 pn Based on this, the gate voltage V of switch S1 gs (S1) and the gate voltage V of switch S2 gs (S2) is generated. In other words, gate signals S1 and S2 are transmitted via the complementary gate drive circuit 40 to generate the gate voltage V gs (S1) and V gs This is converted to (S2). The algorithm for changing the gate voltage by the dead time period Td is shown in the upper right of Figure 1, but the details of the process will be described later.

[0016] The periodic gate drive circuit 50 uses the gate signals S3 and S4 generated by the BTP control circuit 20 to control the gate voltage V of switch S3. gs (S3) and the gate voltage V of switch S4 gs (S4) is generated.

[0017] Next, the gate driving method in this embodiment will be described. Figure 2 illustrates the operating modes of the BTP circuit 10. Figure 2(a) shows the AC power supply V AC This shows the upper half-wave charging mode. Switches S2 and S4 are in the ON position. The current is from the AC power supply VAC From the left side, through reactor L1, switch S2 and switch S4, AC power V AC The current flows to the N side and stores power in reactor L1. In the diagram, the path of the current is shown by a dashed line.

[0018] Figure 2(b) shows the AC power supply V AC This shows the upper half-wave discharge mode. Switches S1 and S4 are in the ON position. The current is from the AC power supply V AC From the left side, we have reactor L1, switch S1, and capacitor C. L And through switch S4, AC power supply V AC The current flows to the N side from reactor L1 to capacitor C. L It releases power. AC power supply V AC In the upper half-wave, switch S3 is in the off state and switch S4 is in the on state, and switches S1 and S2 alternate between the on and off states in a complementary manner.

[0019] Figure 2(c) shows the AC power supply V AC This shows the lower half-wave charging mode. Switches S1 and S3 are in the ON position. The current is from the AC power supply V AC From the N side, through switch S3, switch S1 and reactor L1, AC power V AC The current flows to the left side and stores power in reactor L1.

[0020] Figure 2(d) shows the AC power supply V AC This shows the discharge mode of the lower half-wave. Switches S2 and S3 are in the ON position. The current is from the AC power supply V AC From the N side, switch S3, capacitor C L , passing through switch S2 and reactor L1, AC power V AC Flow to the left side from reactor L1 to capacitor C L It releases power. AC power supply V AC In the lower half-wave, switch S3 is ON and switch S4 is OFF, and switches S1 and S2 alternate between ON and OFF in a complementary manner.

[0021] In the modes shown in Figures 2(a) and 2(b), the AC power supply V AC Current flows from switch S2 or switch S1. In this case, it is defined as current flowing into a series circuit consisting of two GaN-HEMT elements. Also, in the modes shown in Figures 2(c) and 2(d), AC power supply V flows from switch S1 or switch S2. AC Current flows out. In such cases, it is defined as current flowing out from a series circuit consisting of two GaN-HEMT elements.

[0022] Figure 3 is a timing chart showing the gate drive operation. In this embodiment, the gates of switch S1 and switch S2 are connected by a positive voltage V p and negative voltage V n It shall be driven by a dual power supply. However, V n This is above the minimum allowable voltage for the GaN-HEMT element. Figure 3(a) is a timing chart for when current flows into a series circuit consisting of two GaN-HEMT elements.

[0023] Between times t1 and t2, the mode is as shown in Figure 2(a) (indicated as (A) in Figure 3(a)). The gate signal S1 of switch S1 is 0, and the gate voltage V of switch S1 is gs (S1) is V n Therefore, switch S1 is in the off state. In contrast, the gate signal S2 of switch S2 is 1, and the gate voltage V of switch S2 is V gs (S2) is V p Therefore, switch S2 is in the ON state. Since switch S2 is ON, a low voltage is applied between the drain and source of switch S2 due to its small on-resistance. Switch S1 is OFF, so the DC voltage V dc The majority of this occurs between the drain and source of switch S1. As a result, the drain-source voltage V of switch S1 ds (S1) is V dc This will be almost the same value.

[0024] At time t2, the gate signal S2 of switch S2 changes from 1 to 0, and the gate voltage V of switch S2 changes. gs (S2) is also V p From V n This changes the signal. As a result, switch S2 turns off. The period between time t2 and t3 is a dead time period Td during which both switches S1 and S2 are in the off state. Signal S v0 This is obtained by the logical OR of gate signals S1 and S2. The dead time period Td during which both gate signals S1 and S2 are 0 is given by signal S v0 =0, but during periods other than the dead time, signal S v0 = 1. Signal S v0 This allows us to recognize the dead time period Td.

[0025] When switch S2 is turned off at time t2, current begins to flow back, causing switch S1 to conduct in reverse. The current path is as shown in Figure 2(b) (indicated as (B) in Figure 3(a)). The voltage drop across switch S1 at this time is the sum of the voltage drop across the on-resistance, the threshold voltage, and the gate reverse bias voltage. n Applying a large reverse bias voltage like this to the gate results in a large voltage drop and excessive power loss. In this embodiment, during the dead time period Td, the gate voltage V of the reverse-conducting switch S1 is gs (S1) V0 (0≧V0>V n This allows us to suppress power loss due to reverse conduction.

[0026] When switch S1 conducts in reverse at time t2, the drain-source voltage V of switch S1 ds (S1) drops sharply. Drain-source voltage V ds When (S1) decreases rapidly, the gate-drain feedback capacitance C dg This results in a surge voltage (V) being applied to the gate. g =R g C dg ·dV ds / dt) occurs. Here, R gis the resistance value between the gate and the drain. Since this surge voltage is a negative voltage, it does not cause the switch S1 to self-turn on. In addition, due to the delay caused by the GaN-HEMT element, the surge voltage occurs at a point in time when a short period of time has elapsed from time t2. The surge voltage is indicated by a downward arrow on the right side of time t2 in FIG. 3(a).

[0027] At time t3, the gate signal S1 of the switch S1 changes from 0 to 1, and the gate voltage V of the switch S1 gs (S1) changes from V0 to V p . As a result, the switch S1 is turned on. The period from time t3 to t4 corresponds to the mode shown in FIG. 2(b) (indicated as (B) in FIG. 3(a)).

[0028] At time t4, the gate signal S1 of the switch S1 changes from 1 to 0, and the gate voltage V of the switch S1 gs (S1) changes from V p to V0 (0≧V0>V n ). As a result, the switch S1 is turned off. The period from time t4 to t5 is the dead time period Td in which both the switch S1 and the switch S2 are in the off state. Even when the switch S1 is turned off, the current still flows through the original path. In other words, the switch S1 conducts reverse conduction. By setting the gate voltage V gs (S1) of the reversely conducting switch S1 to V0, power loss caused by reverse conduction can be suppressed.

[0029] At time t5, the gate signal S2 of the switch S2 changes from 0 to 1, and the gate voltage V of the switch S2 gs (S2) also changes from V n to V p . As a result, the switch S2 is turned on. The turning on of the switch S2 causes the mode to change from the mode of FIG. 2(b) to the mode of FIG. 2(a) (indicated as (A) in FIG. 3(a)). Since no current flows through the switch S1 any more, the drain-source voltage V ds (S1) of the switch S1 rises sharply. The drain-source voltage V of the switch S1 dsIf (S1) rises rapidly, a surge voltage will be generated at the gate of switch S1. Since this surge voltage is positive, switch S1 may self-turn on.

[0030] At time t5, the gate voltage V of switch S1 gs (S1) V0 to V n The voltage changes to V. The timing of the positive surge voltage is a short time after time t5 due to the delay caused by the GaN-HEMT element. The surge voltage is shown by an upward arrow to the right of time t5 in Figure 3(a). Thus, at the timing when the positive surge voltage is generated, the gate voltage V of switch S1 changes. gs (S1) is a negative V n Therefore, the possibility of switch S1 self-turning can be reduced.

[0031] Figure 3(b) is a timing chart for current flowing out of a series circuit consisting of two GaN-HEMT elements. From time t6 to t7, the mode is as shown in Figure 2(d) (indicated as (D) in Figure 3(b)). At time t7, the gate voltage of switch S2 is V gs (S2) is V p The voltage changes from V0 to V0. This causes switch S2 to turn off. The period from time t7 to t8 is the dead time period. Even though switch S2 is turned off, the current continues to flow through the same path. In other words, switch S2 conducts in reverse. The gate voltage of switch S2 is V gs Since (S2) is V0, power loss due to reverse conduction can be suppressed.

[0032] At time t8, the gate voltage V of switch S1 gs (S1) is V n From V p This changes the gate voltage of switch S2 V. gs (S2) V0 to V nThe mode changes to the mode shown in Figure 2(c) when switch S1 is turned ON (indicated as (C) in Figure 3(b)).

[0033] Since no current flows through switch S2, the drain-source voltage V across switch S2 decreases. ds (S2) rises sharply. The drain-source voltage V of switch S1 ds When (S2) rises rapidly, a surge voltage is generated at the gate of switch S2. Since this surge voltage is positive, switch S2 may self-turn on. The timing of the generation of the positive surge voltage is a short time after time t8. The surge voltage is shown by an upward arrow to the right of time t8 in Figure 3(b). At the timing of the generation of the positive surge voltage, the gate voltage V of switch S2 is gs (S2) is a negative V n Therefore, the possibility of switch S2 self-turning can be reduced.

[0034] At time t9, the gate voltage V of switch S1 gs (S1) is V p From V n This changes the gate voltage of switch S2 to V. gs (S2) is V n The current changes from V0. As switch S1 turns off, switch S2 conducts in reverse. The path of the current is as shown in Figure 2(d) (indicated as (D) in Figure 3(b)). From time t9 to t 10 This is the dead time period Td. The gate voltage V of the reverse-conducting switch S2 is... gs By setting (S2) to V0, power loss due to reverse conduction can be suppressed.

[0035] When switch S2 conducts in reverse at time t9, the drain-source voltage V of switch S2 ds (S2) drops sharply. Drain-source voltage V dsWhen (S2) drops sharply, a surge voltage is generated at the gate. Since this surge voltage is negative, the switch S2 does not self-turn on. The surge voltage is shown by a downward arrow to the right of time t9 in Figure 3(b).

[0036] When current flows into a series circuit consisting of two GaN-HEMT elements, the switch S that conducts in reverse during the dead time period Td is identified as switch S1 (the GaN-HEMT element on the upper arm). Similarly, when current flows out of the series circuit consisting of two GaN-HEMT elements, the switch S that conducts in reverse during the dead time period Td is identified as switch S2 (the GaN-HEMT element on the lower arm). This determination is performed at natural integer multiples of the carrier half-cycle during PWM modulation. This method eliminates the need for a circuit to detect the switch S that conducts in reverse. Eliminating this circuit prevents high-speed operation from being hindered by circuit delays.

[0037] The gate voltage of the reverse-conducting switch S is V0 (0≧V0>V n The period during which this occurs does not have to be the entire dead time period Td, but may be a part of the dead time period Td. In the above explanation, the gate voltage of the reverse-conducting switch S was assumed to be V0 for the entire dead time period Td, but this is not limited to this. The drain-source voltage of the reverse-conducting switch S is V ds If (S) rises sharply (starts up), a surge voltage is generated outside the dead time period Td due to the delay of the element. Therefore, the drain-source voltage V of the reverse-conducting switch S ds The gate voltage of the reverse-conducting switch S may be set to V0 only when (S) rises sharply (starts up).

[0038] Resonance occurs due to the gate capacitance and the gate's stray inductance, and when the gate voltage moves to the positive potential side, the gate voltage of the reverse-conducting switch S is V n This is also acceptable. The effect of resonance is the drain-source voltage V of the reverse-conducting switch S. dsIt is preferable to suppress the falling edge of (S). Therefore, the drain-source voltage V of the reverse-conducting switch S is preferable. ds When (S) falls, the gate voltage of the switch S that conducts in reverse is V. n This is also acceptable. This period is an example of the second period.

[0039] The zero-crossing period, including the zero-crossing point, is defined as the AC power supply V AC This is defined as a period during which it is difficult to accurately determine the positive and negative polarity. During the zero-crossing period and dead time period Td, the gate voltage of the reverse-conducting switch S is set to V instead of V0. n This is also acceptable. This period is an example of the third period.

[0040] In the upper right of Figure 1, an algorithm is shown that changes the gate voltage only for the dead time period Td. The signal I from the current sensor 21... s Only cases where the absolute value of is greater than the threshold are considered. The reason for setting a threshold is that current cannot be detected near the zero crossing point. pn =0 refers to the case where current flows into a series circuit consisting of two GaN-HEMT elements. The signal S is the logical OR of gate signals S1 and S2. v0 and the gate voltage V of switch S1 gs By multiplying (S1) by this, the gate voltage V of switch S1 during the dead time period Td is obtained. gs Set (S1) to 0. "else" is S pn The value is anything other than 0. In other words, it refers to the case where current flows out of a series circuit consisting of two GaN-HEMT elements. In that case, the signal S v0 and the gate voltage V of switch S2 gs By multiplying (S2) by this, the gate voltage V of switch S2 during the dead time period Td is obtained. gs Set (S2) to 0.

[0041] (Example 1) The present invention will be described in more detail below based on examples. However, the present invention is not limited to the following examples unless it exceeds the gist of the invention. Figure 4 shows the BTP circuit of Example 1 and the current source load connected to it. Figure 5 shows the block diagram and logic circuit diagram of the BTP control circuit of Example 1. Figure 6 illustrates the gate drive in Example 1. Figure 6(a) is a complementary gate drive circuit diagram, and Figure 6(b) is a timing chart showing the gate drive operation. This timing chart shows only the case where current flows into the series circuit.

[0042] The BTP circuit 10 in Example 1 is the same as the BTP circuit 10 shown in Figure 1. Switches S1, S2, S3, and S4 in Figure 1 correspond to the S in Figure 4, respectively. rp S rn S sp S sn This corresponds to a current source load 100 connected to the BTP circuit 10. The current source load 100 is a switch S consisting of IGBTs. up S un S vp S vn S wp S wn It comprises an inverter 110 composed of the above components and a motor M driven by the inverter 110.

[0043] The BTP control circuit 20 issues a DC voltage command V dc * Based on this, the PI controller output and the power supply voltage reference signal V s This generates a sinusoidal current command, and the current control system controls the input current I to achieve a power factor of 1. L Controls the gate signal S on the GaN-HEMT side. rp S rn The deviation of the obtained current control system is PWM modulated by the complementary PWM modulation unit 201 to generate a complementary signal with a dead time period Td. On the other hand, the gate signal on the Si-MOSFET side is the power supply voltage reference signal V s Depending on the polarity, the conductive electrode switching unit 202 switches between positive and negative power supply voltages. sn S sp These are each generated as conductive signals. This configures the GaN-HEMT side arm as a boost chopper.

[0044] The logic circuit 22 is on the GaN-HEMT side S rp S rn The dead time period Td is detected by the logical OR of the two, and furthermore, the Si-MOSFET side S sn S sp By logical OR with the gate voltage variable signal S, v0p S v0n To obtain. The complementary gate drive circuit 40 includes an isolated gate drive IC 41 and a negative voltage selection unit 42. Gate voltage variable signal S v0p S v0n This switches the bias in the negative voltage selection section 42 of the complementary gate drive circuit 40, increasing the negative voltage during reverse conduction. Also, the input current I L Near the zero-crossing point where the polarity is unstable, both variable signals are set to high by the ZeroX signal to perform bipolar drive. The gate drive operation is as shown in Figure 6(b). The periodic gate drive circuit 50 of the Si-MOSFET is configured as a normal dual power supply drive circuit without the negative voltage selection unit 42 shown in Figure 6(a).

[0045] (Example 2) Figure 7 shows the BTP circuit of Example 2 and the current source load connected to it. Figure 8 shows the block diagram and logic circuit diagram of the BTP control circuit of Example 2. In Example 2, the BTP circuit 11 uses natural commutation due to the power supply voltage to control the operation of the Si-MOSFET using a rectifier diode D. sp , D sn This is a substitution. Since it can be constructed using only the control circuit and gate drive circuit on the GaN-HEMT side, the circuit can be simplified. However, compared to Example 1, which employs synchronous rectification operation of the Si-MOSFET (recirculation occurs in the Si-MOSFET in regions where the Vf of the FRD connected in parallel with the Si-MOSFET is small), the conduction loss is larger, resulting in a decrease in efficiency at light loads. Therefore, Example 1 is preferable for applications where improving partial load efficiency is important. Gate voltage variable signal S v0p S v0n is, Sv0p =S rp +S rn + Sp S v0n =S rp +S rn + Sn Since this is the only difference from Example 1, the gate drive circuit diagram and timing chart are omitted.

[0046] (Example 3) Figure 9 shows the BTP circuit of Example 3 and the current source load connected to it. Figure 10 shows the block diagram and logic circuit diagram of the inverter control circuit of Example 3. The inverter control circuit 23 shown in Figure 10 is a circuit for one phase of the u-phase. Figure 11 illustrates the gate drive of the inverter in Example 3. Figure 11(a) is a gate drive circuit diagram, and Figure 11(b) is a timing chart showing the gate drive operation. This timing chart shows only the case where current flows into the series circuit. In Example 3, the inverter 111 of the current source load 101 is a switch S made of GaN-HEMT elements. up S un S vp S vn S wp S wn The difference from Example 2 is that it is composed of [this].

[0047] In Example 3, the gate driving method for GaN-HEMT elements of this embodiment is applied to the gate driving of GaN-HEMT elements constituting the inverter 111. The inverter control circuit 23 of Example 3 replaces the power factor 1 control unit (DC voltage control system, sinusoidal command generation, current control system) in the BTP control circuit 20 of Example 2 (see Figure 8) with a sensorless motor position control system (sensorless control unit 203 and coordinate transformation unit 204). The complementary PWM modulation unit 201, the pass / fail switching unit 202, the logic circuit 22, and the complementary gate drive circuit 40 are the same as in the BTP control circuit 20 of Example 2 (see Figure 8). The detailed configuration of the sensorless control unit 203 and the coordinate transformation unit 204 will be described later, but they constitute a general dq axis speed control system. The phase voltage command generation unit 205 receives the rotational position θ and phase difference phase obtained from the sensorless control unit 203 and the coordinate transformation unit 204. * , amplitude duty * Using the signal, the phase voltage command V of inverter 111 is used. u * (Only one phase is shown) is generated, and the complementary PWM modulation unit 201 modulates S up S un A complementary signal is obtained. The U-phase arm of inverter 111 generates a sinusoidal PWM voltage based on the complementary signal and supplies current to the motor.

[0048] Furthermore, the power supply voltage V applied in the BTP control circuit 20 (see Figure 5) is used as a reference signal for detecting the reverse conduction element through the conduction switching unit 202. s (Equivalent to a phase sensor) is replaced with the phase current signal i u This shows the case where (equivalent to a current sensor) is applied. Since the rotational position θ is known, it is also possible to apply the current phase β shown in the block diagram of Figure 12 (described later) and apply θ+β as the current phase to the reference signal. The current sensors 112 and 113 in Figure 9 measure the output current of the inverter 111 and are an example of an output current sensor. Complementary gate drive circuit for the u-phase of inverter 111 400 As shown in Figure 11(a), this has the same configuration as the complementary gate drive circuit 40 of the BTP circuit in Example 1 (see Figure 6). The gate drive operation of the u-phase of the inverter is as shown in Figure 11(b).

[0049] Figure 12 is a block diagram of the sensorless control unit 203 and coordinate transformation unit 204 (see Figure 10) of Embodiment 3. The sensorless control unit 203 and coordinate transformation unit 204 shown in Figure 12 use a three-phase AC voltage (V u , V v , W w ), three-phase alternating current (i u i v i w ) estimates the motor rotation position θ and speed ω, and constructs a speed control system. Specifically, the coordinate transformation unit 204 converts three-phase AC to two-phase AC (V a , V b i a i b ) Position estimation is performed, and the two-phase AC current is determined by the obtained rotational position θ to form the dq-axis current (i d i q Converts to ). A current control system is constructed as a DC flow rate using the stationary coordinate system (dq axis), and a dq axis voltage command (V) is issued based on the current command obtained by the speed control system. d * , V q * The coordinate transformation unit 204 uses the equation shown in the figure to obtain the phase difference phase that is given to the phase voltage command generation unit 205 (see Figure 10). * =φ, amplitude duty * =k s Perform the calculation.

[0050] (Simulation 1) Figure 13 shows the results of a simulation regarding the gate drive method of the BTP circuit. Figure 13(a) shows the simulation results for Comparative Example 1, Figure 13(b) shows the simulation results for Example 1, and Figure 13(c) shows the circuit model used in the simulation. In Figures 13(a) and 13(b), the horizontal axis represents time and the vertical axis represents voltage. SPICE was used for the simulation. The main circuit used the step-down chopper circuit shown in Figure 13(c) to simulate the mode in which current flows out from the series circuit, one of the two operating modes. The DC voltage generated by the BTP circuit was set to V dc =400V, switching frequency f swThe frequency was set to 200kHz, and the dead time period was set to Td = 500ns. d The L value was set so that the recirculation state occurs at 30A (L=V d c·(0.5 / f sw -Td) / I d (=26.7μH). Furthermore, the GaN-HEMT element used was the Level 1 model of GaN Systems' GS66516B, with the ON-state gate voltage set to V gs = +6V, gate voltage in the off state is V gs The voltage was set to -3V. The gate resistor in the ON state is R. g =100Ω, gate resistor in the off state is R g The gate resistance was set to 12Ω, and to improve waveform visibility, it was set to about an order of magnitude larger than usual.

[0051] Figure 21 shows the device characteristics of the GS66516B manufactured by GaN Systems. Figure 21(a) illustrates the voltage drop that occurs during conduction. A is in a forward conduction state with the gate turned on. In this case, the resistance R between the drain and source is... DS(ON) A voltage drop occurs due to this. B is in reverse conduction operation with the gate in the ON state. In this case, resistor R DS(ON) A voltage drop occurs due to this. C is in reverse conduction operation with the gate off. In this case, the threshold voltage V TH The gate voltage V GS(OFF) A voltage drop occurs when these are added together, and furthermore, the resistor R connected in series is also involved. DS(REV) A voltage drop occurs due to this. Figure 21(b) shows the reverse conduction characteristics at a junction temperature of 25°C. The horizontal axis represents the drain-source voltage V. SD The vertical axis represents the drain-source current I. SD The gate voltage is V. GS When V is 0V, the drain-source voltage V SD The threshold voltage V TH When the voltage exceeds approximately 1.7V, the drain-source current I SD The current flows. The slope of the graph is the resistance R between the drain and source. DS(REV) Determined by the gate voltage V GS When the voltage is -3V, the drain-source voltage VSD However, the threshold voltage V TH and gate voltage V GS When the combined voltage (approximately 4.7V) exceeds this value, the drain-source current I SD A current flows. In this case, the voltage drop becomes large, and power loss increases.

[0052] Comparative Example 1, shown in Figure 13(a), is a conventional dual power supply drive method, in which the gate voltage V applied to the switch S1, which is made of a GaN-HEMT element, during the dead time period Td is gs (S1) is set to a negative voltage of -3V. gs The surge voltage associated with dv / dt (dashed line) as seen in (S1) is suppressed by a negative voltage, but the drain-source voltage V during reverse conduction in the dead time period Td ds Because of this increase, the steady-state loss increases.

[0053] In the simulation of Example 1 shown in Figure 13(b), the gate voltage V applied to switch S1 during the dead time period Td is gs (S1) was set to 0V. S is the signal obtained by the logical OR of the gate signals S1 and S2. v0 Therefore, the gate voltage is set higher than the negative voltage (V gs By setting (S1)=0V, steady-state losses during reverse conduction are reduced. Note that a delay occurs due to control by the gate signal, but the falling edge of the surge voltage is within the dead time period Td. gs (S1) = 0V is also acceptable. The surge voltage rise is outside the dead time period Td, so V gs (S1) is a negative voltage, similar to Comparative Example 1. In addition, although the reverse conduction period increases or decreases during the dead time period Td in both cases, the delay time is small relative to the dead time period Td, so the impact on steady-state losses is extremely low.

[0054] Figure 14 shows the results of the instantaneous loss analysis of the BTP circuit. Figure 14(a) shows the analysis results for Comparative Example 1, and Figure 14(b) shows the analysis results for Example 1. The analysis conditions are that the frequency of the AC power supply is f s =50Hz, AC power supply voltage is V s =230V, Vdc =400V, switching frequency f sw The frequency was set to 65kHz, and the dead time period was set to Td = 100ns. The GaN-HEMT element was, Figure 13(c) The GS66516B shown is the ON gate voltage V gs = +6V, gate voltage in the off state is V gs The voltage was set to -3V. Also, the gate resistor in the ON state was set to R. g = 10Ω, the gate resistor in the off state is R g = 1Ω

[0055] As shown in the instantaneous loss waveform (Pout=3kW), L The period when is positive is S rn It conducts in the forward direction, S rp This results in reverse conduction. A dead time period occurs when the gate is off during reverse conduction, and a loss Pc_D occurs when the gate is off. In actual devices, current flows through the same device both during the dead time period Td and when the gate is on. However, the thermal model is based on MOSFETs, and it can be considered that current flows to the MOSFET side when the gate is on, and current flows to the FRD side during the dead time period Td. Also, S rp S rn Current I L The currents are separated, but the relative magnitudes of the instantaneous steady-state losses are determined by the time ratio of each. The reverse conduction loss Pc_D during the dead time period Td is smaller in Example 1 compared to Comparative Example 1, and the drain-source voltage V during reverse conduction is smaller. ds It can be confirmed that instantaneous losses can be reduced by implementing control measures to mitigate them.

[0056] Figure 15 shows the total loss per element and the reduction rate of the total loss. The horizontal axis represents the load Pout, the left vertical axis represents the total loss Pc, and the right vertical axis represents the reduction rate of the total loss. Compared to Comparative Example 1, Example 1 achieved a loss reduction effect of approximately 3.5% to 5% across the entire load range. In GaN-HEMT elements, the dead time period Td is generally set to about 100 ns, but the switching frequency f swIf the frequency is set to an even higher frequency, the ratio of the dead time period Td to the switching period increases, thus further increasing the effect of reducing steady-state losses.

[0057] (Example 4) In Example 1, the BTP control circuit 20 controls the switch S rp and S rn The two elements complementarily alternated between on and off states, performing PWM modulation. In Example 4, when current flowed into the series circuit, the lower arm switch S rn Only the upper arm switch S performs PWM modulation. rp The switch S on the upper arm should be in the OFF state. Also, if current flows out from the series circuit, the switch S on the upper arm should be turned OFF. rp Only the lower arm switch S performs PWM modulation. rn This should be turned off. This method is sometimes called 1-arm PWM modulation.

[0058] Figure 16 shows the block diagram and logic circuit diagram of the BTP control circuit of Example 4. Figure 17 is a timing chart showing the gate drive operation of Example 4. This timing chart shows only the case where current flows into the series circuit. The BTP circuit 10, the current source load 100 connected to it, and the complementary gate drive circuit 40 are the same as those in Figures 4 and 6(a) of Embodiment 1, so their description is omitted.

[0059] The BTP control circuit 24 has a 1-arm PWM modulation unit 206. The 1-arm PWM modulation unit 206 receives a gate signal S rp S rn Based on this, select the switch that performs PWM modulation and the switch that remains in the off state. As shown in Figure 17, the switch S on the upper arm rp It is always in the off state, but the lower arm switch S rn While it is in the OFF state, switch S on the upper arm rp The gate voltage is V gs (S rp Let ) = V0. This helps to suppress power loss due to reverse conduction. In Example 4, a gate driving method can be implemented without changing the configuration of the logic circuit or driving circuit, which involves "providing a first period during which an off command is simultaneously given to two GaN-HEMT elements, in which, based on the timing of the gate signal, the gate voltage applied to one of the GaN-HEMT elements that conducts in reverse is set higher than the negative gate voltage applied to the other GaN-HEMT element."

[0060] (Simulation 2) Figure 18 shows the results of a simulation regarding the gate drive method of the BTP circuit. Figure 18(a) shows the simulation results for Comparative Example 2, and Figure 18(b) shows the simulation results for Example 4. Comparative Example 2 uses a conventional dual power supply drive method with 1-arm PWM modulation. Simulation 2 was performed under the same conditions as Simulation 1.

[0061] Comparative Example 2, shown in Figure 18(a), is V gs The surge voltage associated with dv / dt (dashed line) as seen in (S1) is suppressed by a negative voltage, but the drain-source voltage V during reverse conduction in the dead time period Td ds Because of this increase, the steady-state loss increases. In the embodiment shown in Figure 18(b), the signal S is the logical OR of the gate signals S1 and S2. v0 Therefore, the gate voltage during the dead time period Td is set higher than the negative voltage (V gs By setting (S1)=0V, steady-state losses during reverse conduction are reduced. Note that a delay occurs due to control by the gate signal, but on the surge falling edge side, V is within the dead time period Td. gs (S1) = 0V is also acceptable. The surge rising side is outside the dead time period Td, so V gs (S1) is a negative voltage, similar to Comparative Example 2. In addition, delays occur at the start and end of the reverse conduction period at both ends of the dead time period Td, but since the delay time is small relative to the dead time period Td, the impact on steady-state losses is extremely low.

[0062] Figure 19 shows the results of the instantaneous loss analysis of the BTP circuit. Figure 19(a) shows the analysis results for Comparative Example 2, and Figure 19(b) shows the analysis results for Example 4. Switch S rp and S rn When two elements complementarily switch between on and off states to perform PWM modulation, there are two modes of reverse conduction: when the switch is on and when the switch is off. For example, in the timing chart of Figure 3(a), at times t2 to t3, switch S1 is in the off state and conducting in reverse. At times t3 to t4, switch S1 is in the on state and conducting in reverse. In contrast, in the case of 1-arm PWM modulation, there is only one mode where the switch is in the off state and conducting in reverse, so the single-element loss is relatively large. However, when comparing the loss Pc_D in the switch-off state in Figure 19(a) and Figure 19(b), a significant difference can be seen between Comparative Example 2 and Example 4.

[0063] Figure 20 shows the total loss per element and the reduction rate of the total loss. The horizontal axis represents the load Pout, the left vertical axis represents the total loss Pc, and the right vertical axis represents the reduction rate of the total loss. Compared to Comparative Example 2, Example 4 achieved a loss reduction effect of approximately 40% to 50% across the entire load range.

[0064] (Effects of the embodiment) The gate driving method for GaN-HEMT elements in this embodiment includes a series circuit consisting of two GaN-HEMT elements S1 and S2 having an ohmic junction or Schottky junction as a gate, and a current sensor 21 or a phase sensor, and a power conversion device 1 that drives the two GaN-HEMT elements S1 and S2 by performing PWM modulation based on a signal from the current sensor 21 or the phase sensor, and the method drives the gates of the two GaN-HEMT elements S1 and S2, wherein the gate signal, which is an on command or off command obtained by PWM modulation, is driven through the gate driving circuit to the gate The gates of GaN-HEMT elements S1 and S2 are driven by converting the signal to a voltage and applying a gate voltage. At natural integer multiples of the carrier half-cycle of PWM modulation, a signal is used to determine which of the two GaN-HEMT elements S1 and S2 is conducting in reverse. During the period in which an off command is simultaneously given to both GaN-HEMT elements S1 and S2, a first period is provided in which, based on the timing of the gate signal, the gate voltage applied to the GaN-HEMT element S that is conducting in reverse is set higher than the negative gate voltage applied to the other GaN-HEMT element S. This provides a method for driving the gates of GaN-HEMT elements that can be configured using the control sensor and general-purpose gate drive circuit originally provided in the power converter.

[0065] In this embodiment, the gate driving method for the GaN-HEMT element is such that, during the first period, the gate voltage applied to one of the GaN-HEMT elements S that conducts in reverse is 0V or less. This suppresses self-turn-on of the GaN-HEMT element while suppressing power loss due to reverse conduction.

[0066] In this embodiment, the gate driving method for the GaN-HEMT element ensures that, during the first period, the negative gate voltage applied to the other GaN-HEMT element S is equal to or greater than the minimum allowable voltage of the other GaN-HEMT element S. This prevents damage to the GaN-HEMT element.

[0067] In this embodiment, the gate driving method for the GaN-HEMT element determines which GaN-HEMT element S is conducting in reverse if current flows into the series circuit during the period when an off command is simultaneously given, and determines which GaN-HEMT element S is conducting in reverse if current flows out of the series circuit, and which GaN-HEMT element S is conducting in reverse if current flows out of the series circuit. This eliminates the need for a circuit to detect the switch S that is conducting in reverse.

[0068] In this embodiment, the gate driving method for the GaN-HEMT element involves setting the gate voltage applied to the reverse-conducting GaN-HEMT element S to 0V or less during both the rising and falling edges of the drain-source voltage of the reverse-conducting GaN-HEMT element S during the first period. This suppresses self-turn-on of the GaN-HEMT element while also suppressing power loss due to reverse conduction.

[0069] In this embodiment, the gate driving method for the GaN-HEMT element involves setting the gate voltage applied to the reverse-conducting GaN-HEMT element S to 0V or less during the rising edge of the drain-source voltage of the reverse-conducting GaN-HEMT element S during the first period. This suppresses the self-turn-on of the GaN-HEMT element in response to a positive surge voltage.

[0070] The gate driving method for the GaN-HEMT elements in this embodiment includes a second period during the period in which an off command is simultaneously issued, in which, on the falling edge of the drain-source voltage of one of the reverse-conducting GaN-HEMT elements S, the gate voltage applied to the reverse-conducting GaN-HEMT element S and the negative gate voltage applied to the other GaN-HEMT element are set to be equal. This makes it possible to suppress the effects of resonance.

[0071] The gate driving method for the GaN-HEMT element in this embodiment includes a third period during which, at the zero crossing point of the input / output current, output voltage, or power supply voltage of the series circuit, and simultaneously during the period when an off command is issued, the gate voltage applied to one GaN-HEMT element S that conducts in reverse and the negative gate voltage applied to the other GaN-HEMT element S are set to be equal. This enables stable gate driving.

[0072] In this embodiment, the gate driving method for the GaN-HEMT element is such that the power conversion device 1 is a converter having at least one series circuit, and the method for determining which GaN-HEMT element S is conducting in reverse is a method using an input current sensor and power supply voltage phase information. This makes it possible to provide a converter that suppresses power loss due to reverse conduction.

[0073] In this embodiment, the gate driving method for the GaN-HEMT element is such that the power conversion device 1 is an inverter having at least one series circuit, and the method for determining which GaN-HEMT element S is conducting in reverse is to use output current sensors 112, 113 or output voltage phase information. This makes it possible to provide an inverter that suppresses power loss due to reverse conduction.

[0074] The gate drive device for the GaN-HEMT element of this embodiment has a series circuit consisting of two GaN-HEMT elements S1 and S2 having an ohmic junction or Schottky junction as the gate, and a current sensor 21 or a phase sensor, and performs PWM modulation based on the signal from the current sensor 21 or the phase sensor to drive the two GaN-HEMT elements S1 and S2. The gate signal, which is an on command or off command obtained by PWM modulation, is transmitted via the gate drive circuit to the gate The power is converted to a gate voltage, and by applying the gate voltage, the gate of the GaN-HEMT element S is driven. At natural integer multiples of the carrier half-cycle of the PWM modulation, a signal is used to determine which of the two GaN-HEMT elements S1 and S2 is conducting in reverse. During the period in which an off command is given to both GaN-HEMT elements S1 and S2 simultaneously, a first period is provided in which, based on the timing of the gate signal, the gate voltage applied to the GaN-HEMT element S that is conducting in reverse is set higher than the negative gate voltage applied to the other GaN-HEMT element S. This makes it possible to provide a gate drive device for a GaN-HEMT element that can be configured using the control sensor and general-purpose gate drive circuit originally provided in the power converter.

[0075] The power converter 1 of this embodiment is equipped with the gate drive device of this embodiment. This makes it possible to provide a power converter that can suppress power loss due to reverse conduction while suppressing self-turn-on of the GaN-HEMT element.

[0076] Although embodiments have been described above, the technical scope of this disclosure is not limited to the embodiments described above. It is clear from the claims that combinations of two or more of the above embodiments, as well as various modifications or improvements to the above embodiments, are also included in the technical scope of this disclosure. [Explanation of symbols]

[0077] 1...Power converter, 10, 11...BTP circuit, 20, 24, ...BTP control circuit, 21...Current sensor, 22...Logic circuit, 23...Inverter control circuit, 30...Polarity discrimination circuit, 40...Complementary gate drive circuit, 41...Isolated gate drive IC, 42...Negative voltage selection unit, 50...Periodic gate drive circuit, 100, 101...Current source load, 110, 111...Inverter, 201...Complementary PWM modulation unit, 202...Passive electrode switching unit, 203...Sensorless control unit, 204...Coordinate transformation unit, 205...Phase voltage command generation unit, 206...1-arm PWM modulation unit

Claims

1. A power conversion device comprising a series circuit consisting of two GaN-HEMT elements having an ohmic junction or Schottky junction as its gate, and a current sensor or a phase sensor, which performs PWM modulation based on the signal from the current sensor or the phase sensor to drive the two GaN-HEMT elements, wherein the gates of the two GaN-HEMT elements are driven, The gate signal, which is an ON or OFF command, obtained by the PWM modulation described above, is converted into a gate voltage via a gate drive circuit, and the gate of the GaN-HEMT element is driven by applying this gate voltage. At each natural integer multiple of the carrier half-cycle during the PWM modulation, the signal is used to determine which of the two GaN-HEMT elements is conducting in the opposite direction. During the period in which an off command is simultaneously given to the two GaN-HEMT elements, a first period is provided in which, based on the timing of the gate signal, the gate voltage applied to one of the GaN-HEMT elements that conducts in reverse is set higher than the negative gate voltage applied to the other GaN-HEMT element. A method for driving the gate of a GaN-HEMT element.

2. The gate driving method for a GaN-HEMT element according to claim 1, wherein, during the first period, the gate voltage applied to one of the GaN-HEMT elements that conducts in the reverse direction is 0V or less.

3. The gate driving method for a GaN-HEMT element according to claim 1 or 2, wherein, during the first period, the negative gate voltage applied to the other GaN-HEMT element is greater than or equal to the minimum allowable voltage of the other GaN-HEMT element.

4. A method for driving the gate of a GaN-HEMT element according to claim 1 or 2, wherein, during the period in which an OFF command is given simultaneously, if current flows into the series circuit, the GaN-HEMT element of the upper arm is determined to be the GaN-HEMT element that conducts in the reverse direction, and if current flows out of the series circuit, the GaN-HEMT element of the lower arm is determined to be the GaN-HEMT element that conducts in the reverse direction.

5. A method for driving the gate of a GaN-HEMT element according to claim 1 or 2, wherein, during the first period, the gate voltage applied to the reverse-conducting GaN-HEMT element is 0V or less on both the rising and falling sides of the drain-source voltage of the reverse-conducting GaN-HEMT element.

6. A method for driving the gate of a GaN-HEMT element according to claim 1 or 2, wherein, during the first period, the gate voltage applied to the reverse-conducting GaN-HEMT element on the rising side of the drain-source voltage of the reverse-conducting GaN-HEMT element is set to 0V or less.

7. The gate driving method for a GaN-HEMT element according to claim 1 or 2, wherein, during the period in which an OFF command is given simultaneously, a second period is provided in which, on the falling edge of the drain-source voltage of the reverse-conducting GaN-HEMT element, the gate voltage applied to the reverse-conducting GaN-HEMT element and the negative gate voltage applied to the other GaN-HEMT element are set to be equal.

8. The gate driving method for a GaN-HEMT element according to claim 1 or 2, which includes a third period during which, at the zero crossing point of the input / output current, output voltage, or power supply voltage of the series circuit and during the period during which an off command is simultaneously given, the gate voltage applied to one of the reverse-conducting GaN-HEMT elements and the negative gate voltage applied to the other GaN-HEMT element are set to be equal.

9. The power conversion device is a converter having at least one of the series circuits, The method for determining which GaN-HEMT element is conducting in the reverse direction is a method using an input current sensor and power supply voltage phase information, as described in claim 1 or 2, for driving the gate of a GaN-HEMT element.

10. The power conversion device is an inverter having at least one of the series circuits, The method for determining which GaN-HEMT element is conducting in the reverse direction is a method using an output current sensor or output voltage phase information, as described in claim 1 or 2, for driving the gate of a GaN-HEMT element.

11. A power conversion device comprising a series circuit consisting of two GaN-HEMT elements having an ohmic junction or Schottky junction as its gate, and a current sensor or a phase sensor, which performs PWM modulation based on the signal from the current sensor or the phase sensor and drives the two GaN-HEMT elements, wherein the device drives the gates of the two GaN-HEMT elements, The gate signal, which is an ON or OFF command, obtained by the PWM modulation described above, is converted into a gate voltage via a gate drive circuit, and the gate of the GaN-HEMT element is driven by applying this gate voltage. At each natural integer multiple of the carrier half-cycle during the PWM modulation, the signal is used to determine which of the two GaN-HEMT elements is conducting in the opposite direction. During the period in which an off command is simultaneously given to the two GaN-HEMT elements, a first period is provided in which, based on the timing of the gate signal, the gate voltage applied to one of the GaN-HEMT elements that conducts in reverse is set higher than the negative gate voltage applied to the other GaN-HEMT element. A gate drive device for a GaN-HEMT element.

12. A power conversion device equipped with the gate drive device described in claim 11.

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