Semiconductor device and bonding method

Abstract

To provide a semiconductor device with low electrical resistance, which prevents a semiconductor device defect caused by thermal expansion differences by laminating an Fe-Ni alloy metal layer directly or indirectly on the front or back electrode of a semiconductor element.SOLUTION: An Fe-Ni alloy metal layer 5 is deposited directly or indirectly on the front surface electrode and / or the back surface electrode of a semiconductor chip 2, a semiconductor chip and a conductor 4 are connected via the Fe-Ni alloy metal layer 5, and if necessary, the Ni weight % of the Fe-Ni alloy metal layer 5 is in the range of 36% or more and 45% or less, and the thickness of the Fe-Ni alloy metal layer 5 is 2 μm or more and 20 μm or less.SELECTED DRAWING: Figure 2

Description

[[Technical Field]]

[0001] The present invention relates to a semiconductor device or the like that suppresses a difference in thermal expansion between objects to be bonded by means of an Fe-Ni alloy metal layer. [[Background Art]]

[0002] Mounting of a semiconductor element is basically based on fixing to a substrate, conductive connection of electrode terminals, and insulation protection thereof. A semiconductor generates heat due to a current flowing through a circuit and thermally expands. On the other hand, the coefficient of thermal expansion of metals and insulating resins connected to semiconductors is generally about one order of magnitude larger. For example, the coefficient of thermal expansion (CTE) of a Si material is about 2.6 ppm / K, whereas the coefficient of thermal expansion of copper, which is widely used as a wiring material and a conductive material for substrates, is about 16.5 ppm / K. When a Si semiconductor and copper, which is a conductive wiring material, are connected, the amount of strain due to the difference in thermal expansion increases in proportion to the temperature and the length of the connection. Stress on semiconductor elements and stress on connection materials caused by this strain amount cause damage to semiconductor devices that occurs due to thermal fatigue caused by temperature cycles. Although various countermeasures have been taken at present, the current situation is that a fundamental solution has not been achieved. Particularly in power devices through which large currents flow, this problem regarding thermal stress is significant.

[0003] Regarding such problems, ceramic substrates having a coefficient of thermal expansion close to that of Si semiconductors have been used as substrate materials, with copper wiring formed on the ceramic substrates. For example, in CPU elements which are logic devices, ceramic packages were frequently used in the early days, but high cost was a major problem. At present, countermeasures such as using organic material substrates and suppressing the strain amount due to the difference in thermal expansion with sealing resin or underfill have been taken, but the heat resistance temperature is limited. Therefore, for high-output power devices, alumina and silicon nitride substrates having a coefficient of thermal expansion close to that of Si and SiC semiconductors are still frequently used at present.

[0004] In recent years, compound semiconductors such as SiC semiconductor devices have seen remarkable progress in practical applications. These devices themselves can operate at higher temperatures compared to Si semiconductors, and they also enable high power densities. Therefore, there is a demand for packaging technologies that suppress thermal expansion differences and allow for operation at high temperatures.

[0005] Fe-Ni alloy metals (for example, 42 alloy with 42% Ni by weight) are known as materials with a low coefficient of thermal expansion and a coefficient of thermal expansion close to that of semiconductors, and are sometimes used for leads and lead frames in electronic components. Lead frames are generally made of copper, which has excellent conductivity, and are often connected to Si semiconductor chips or SiC semiconductor chips with solder or paste containing resin components. Therefore, in the case of solder connections, thermal stress caused by the difference in thermal expansion between the Si semiconductor or SiC semiconductor and the copper wiring due to temperature cycling can cause plastic deformation of the solder, and repeated deformation can lead to fatigue failure. In the case of paste connections, delamination of the paste material or at the interface can be a problem. As mentioned above, these problems have been addressed by forming the lead frame itself with 42 alloy, which has a coefficient of thermal expansion close to that of Si semiconductors or SiC semiconductors. However, the use of Fe-Ni alloy metals is limited due to their lower conductivity and thermal conductivity compared to copper, as well as material costs.

[0006] As a technology utilizing Fe-Ni alloy metal, for example, the technologies disclosed in Patent Documents 2 to 4 are shown. The technology shown in Patent Document 2 involves a copper second connecting lead with a thermal expansion coefficient of (1 to 6) × 10 -6 By connecting the first connecting lead of the / K iron-nickel alloy by welding or other means, and fixing the tip of the first connecting lead to the electrode pad with solder, the thermal stress applied to the electrode pad is reduced, and the thermal stress caused by the difference in thermal expansion between the electrode pad and the first connecting lead is reduced, thereby preventing cracks from forming in the solder and the silicon beneath the electrode pad. Furthermore, by making the length of the first connecting lead less than 40% of the combined length of the first and second connecting leads, electrical resistance can be kept low, and the cost of the connecting conductor can be reduced.

[0007] The technology described in Patent Document 3 is a semiconductor lead frame comprising a base material made of an iron-nickel alloy and a plating layer plated on the base material with a crystal grain size of 1 micron or less. This allows for minimizing the crystal grain size and suppressing whisker growth when plating the base material made of an iron-nickel alloy (alloy42) with tin.

[0008] The technology described in Patent Document 4 provides a low-expansion member having a plate member made of an iron-based material, with iron-nickel layers formed on the upper and lower surface portions of the plate member. Here, although the plate member has a large coefficient of thermal expansion, the iron-nickel layers formed on the upper and lower surface portions of the plate member have a small coefficient of thermal expansion, so the overall coefficient of thermal expansion of the low-expansion member can be kept small. Furthermore, the plate member has high thermal conductivity, and the iron-nickel layers are formed thinly relative to this plate member, so the low-expansion member has high thermal conductivity in the thickness direction. [Prior art documents] [Patent Documents]

[0009] [Patent Document 1] International Publication No. 2015 / 053356 [Patent Document 2] Japanese Patent Publication No. 2012-38983 [Patent Document 3] Japanese Patent Publication No. 2006-108666 [Patent Document 4] Japanese Patent Publication No. 2004-103700 [Overview of the project] [Problems that the invention aims to solve]

[0010] However, the technologies described in Patent Documents 1 and 2 are insufficient as countermeasures against defects caused by differences in thermal expansion between semiconductors and conductors. In particular, the technology described in Patent Document 2, which uses Fe-Ni alloy metal leads to relieve stress, has the problem that even if the length of the first connecting lead is made less than 40% of the combined length of the first and second connecting leads, it does not adequately address issues such as lower conductivity and thermal conductivity compared to copper, as well as cost.

[0011] Furthermore, even if the technologies described in Patent Documents 3 and 4 are used, the above-mentioned problems cannot be solved.

[0012] The present invention was made to solve the above problems, and aims to provide a semiconductor device that prevents defects in semiconductor devices caused by differences in thermal expansion by directly or indirectly laminating an Fe-Ni alloy metal layer on the surface electrode or back electrode of a semiconductor device, while also keeping electrical resistance low. [Means for solving the problem]

[0013] The semiconductor device according to the present invention has an Fe-Ni alloy metal layer directly or indirectly attached to the surface electrode or back electrode of a semiconductor element, and the semiconductor element and a conductor are connected via the Fe-Ni alloy metal layer.

[0014] Thus, in the semiconductor device according to the present invention, an Fe-Ni alloy metal layer is directly or indirectly attached to the surface electrode or back electrode of a semiconductor element, and the semiconductor element and the conductor are connected via the Fe-Ni alloy metal layer. As a result, the stress caused by the difference in thermal expansion between the semiconductor element and the conductor is relieved, and damage to the semiconductor element can be prevented. [Brief explanation of the drawing]

[0015] [Figure 1] This figure shows the composition dependence of the linear thermal expansion coefficient of Fe-Ni alloys. [Figure 2]FIG. 1 is a diagram showing a structure when a lead frame is used in a semiconductor device. [Figure 3] FIG. 2 is a diagram showing a bonded portion of a semiconductor chip in wire bonding. [Figure 4] FIG. 1 is a diagram showing a structure when flip-chip connection is performed in the semiconductor device according to the first embodiment. [Figure 5] FIG. 2 is a diagram showing a structure of flip-chip connection when the semiconductor device according to the first embodiment has Cu pillars. [Figure 6] FIG. 1 is a diagram showing a structure as a power device of the semiconductor device according to the first embodiment. [Figure 7] FIG. 1 is a diagram showing an example of a lead-frame-type power device structure in the semiconductor device according to the first embodiment. [Figure 8] FIG. 1 is a diagram showing an example of a power device structure when a Cu clip is used in the semiconductor device according to the first embodiment. [Figure 9] FIG. 1 is a diagram showing an example of an NMPB structure in the semiconductor device according to the first embodiment. [Figure 10] FIG. 1 is a diagram showing measurement results of coefficient of linear expansion corresponding to heating temperature after plating treatment of a Fe-Ni alloy metal layer in the semiconductor device according to the first embodiment. MODE FOR CARRYING OUT THE INVENTION

[0016] Hereinafter, embodiments of the present invention will be described. Also, the same reference numerals are assigned to the same elements throughout the present embodiment.

[0017] (First Embodiment of the Present Invention) The semiconductor device according to this embodiment will be described with reference to Figures 1 to 9. The semiconductor device according to this embodiment has a connection structure in which an Fe-Ni alloy metal layer is directly or indirectly laminated on the surface electrode or back electrode of a semiconductor chip, and the semiconductor chip and the conductor are connected via the Fe-Ni alloy metal layer. In each of the following embodiments, the Fe-Ni alloy metal layer is a metal layer containing at least an Fe-Ni alloy, and may contain metals other than Fe-Ni.

[0018] The thermal expansion coefficient of Fe-Ni alloy metals can be controlled to a few ppm, similar to that of Si and SiC semiconductors. Figure 1 shows the composition dependence of the linear thermal expansion coefficient of Fe-Ni alloys. The horizontal axis represents the Ni composition, and the vertical axis represents the thermal expansion coefficient. As shown in the graph, the thermal expansion coefficient is smallest at a Ni composition of 36%, while conventional lead frame materials have a Ni composition of 42%. In the semiconductor device according to this embodiment, the graph in Figure 1 suggests that an effective suppression of the thermal expansion coefficient of the conductor can be expected when the Ni weight% concentration is in the range of 30% to 45%.

[0019] The structure of the semiconductor device according to this embodiment will be described in detail below. Figure 2 is a diagram showing the structure when a lead frame is used in the semiconductor device. Figure 2(A) is a diagram showing a general semiconductor packaging structure when a lead frame is used, Figure 2(B) is the first diagram showing the junction structure between the semiconductor element and the conductor when a lead frame is used in this embodiment, Figure 2(C) is the second diagram showing the junction structure between the semiconductor element and the conductor when a lead frame is used in this embodiment, and Figure 2(D) is the third diagram showing the junction structure between the semiconductor element and the conductor when a lead frame is used in this embodiment.

[0020] In Figure 2, a Si semiconductor or SiC semiconductor (hereinafter referred to as semiconductor chip 2) is die-bonded to the die pad (island) 3a of the lead frame 3. The semiconductor chip 2 and the lead 3b of the lead frame 3 are connected by wire 8 and sealed with resin 6. Generally, the semiconductor chip 2 is often die-bonded to the die pad 3a with solder 7 or a paste containing resin components, and the lead frame 3 is often made of copper, which has excellent conductivity. In this case, as mentioned above, the solder 7 undergoes plastic deformation due to thermal stress caused by the difference in thermal expansion between the semiconductor chip 2 (Si or SiC) and the lead frame 3 (Cu) due to temperature cycling, and repeated deformation can lead to fatigue fracture or delamination at the paste material or its interface. Therefore, even if the lead frame 3 itself were made of Fe-42%Ni material, which has a thermal expansion coefficient close to that of the semiconductor, there are issues with conductivity and thermal conductivity as well as material costs, so its use is limited.

[0021] The problem in joining the semiconductor chip 2 and the conductor 4 (corresponding to the die pad 3a in Figure 2), which is copper, is a problem at the interface between the semiconductor chip 2 and the conductor 4. Therefore, in the semiconductor device 1 according to this embodiment, as shown in Figure 2(B), it is useful to adhere an Fe-Ni alloy metal layer 5 with a suppressed coefficient of thermal expansion to the surface of the die pad 3a, which is copper. That is, the Fe-Ni alloy metal layer 5 is adhered to the die pad 3a and stacked, and the Ti / Ni / Au film 2a of the semiconductor chip 2 is connected via solder 7. In this way, by forming a layer (Fe-Ni alloy metal layer 5) with an Fe-Ni alloy composition close to the coefficient of thermal expansion of the semiconductor chip 2 on the die pad 3a, it is possible to reduce the stress load on the solder 7 due to the thermal expansion of copper.

[0022] Figure 2(C) shows the structure when an Fe-Ni alloy metal layer 5, which has relatively high strength and a thermal expansion coefficient close to that of Si or SiC semiconductors, is deposited on the back (bottom) side of the semiconductor chip 2. In this case, the Fe-Ni alloy metal layer 5 is deposited on the surface of the Ti / Ni / Au film 2a of the semiconductor chip 2 and stacked, and then bonded to the conductor 4 via solder 7.

[0023] Figure 2(D) shows the structure when an Fe-Ni alloy metal layer 5 is attached to the back surface (bottom side) of the semiconductor chip 2, and the Fe-Ni alloy metal layer 5 is formed as a bonding material. In this case, the semiconductor chip 2 and the conductor 4 are bonded by the Fe-Ni alloy metal layer 5 with nano-sized Ni particles as a binder on the Ti / Ni / Au film 2a surface of the semiconductor chip 2.

[0024] In Figures 2(B) to 2(D), the Ni weight% concentration of the Fe-Ni alloy metal layer 5 can be expected to be effective in the range of approximately 30% to 45%, and the thickness is effective at 2 μm or more, with 5 μm or more being preferable.

[0025] Furthermore, in recent years, development has progressed on bonding technologies that can handle high-temperature operation as an alternative to bonding with solder 7 as shown in Figures 2(B) and (C). When using die bonding materials with high adhesiveness and strength, such as Ag sintered material, Ni sintered material, or nickel micro-plating bonding, fracture within the connecting material and delamination of the interface do not occur. However, this can increase stress on the semiconductor chip 2, and defects such as current leakage due to cracks within the semiconductor chip 2 may occur. To address this, in this embodiment, as shown in Figure 2(D), by mixing nano-sized Ni particles as a sintered material into the Fe-Ni alloy metal layer 5, a strong bond with reduced stress on the semiconductor chip 2 becomes possible. At this time, the Fe-Ni alloy metal layer 5 may also be formed to include micro-sized Al particles. The inclusion of Al particles makes it possible to reduce thermal stress due to the difference in thermal expansion caused by Al (see, for example, Japanese Patent Application Publication No. 2020-35983).

[0026] When forming the Fe-Ni alloy metal layer 5, if nano-sized Ni particles or micro-sized Al particles are included, the main component of the Fe-Ni alloy metal layer 5 is the Fe-Ni alloy particles. However, the coefficient of linear expansion of the mixture changes according to the composite law shown in Figure 1, depending on the mixing ratio. Specifically, the Ni particle mixture has a thermal expansion coefficient of 100% Ni, and the Al particle mixture has a thermal expansion coefficient of 100% Al. Therefore, the coefficient of linear expansion is determined by the Fe-Ni thermal expansion coefficient and their volume ratio. For this reason, it is desirable to adjust the composition ratio so that the coefficient of linear expansion of the Fe-Ni alloy metal layer 5 is close to the thermal expansion coefficient of Si or SiC semiconductors. It is desirable that the nano-sized Ni particles be between 10 nm and 200 nm in size. In addition, nano-sized Ag particles or Cu particles of similar size and volume ratio may be used instead of Ni. Furthermore, it is desirable that the effect of nano-sized Ni particles as a sintering material be 15% or more by volume ratio, but considering the effect of the thermal expansion coefficient, it is desirable that it be in the range of 60% or less.

[0027] Furthermore, methods such as cladding, physical vapor deposition, plating, thermal spraying, and sintering can be used to adhere the Fe-Ni alloy metal layer 5. As shown in Figure 2(B), any of the above methods may be used when adhering the Fe-Ni alloy metal layer 5 to the conductor 4. As shown in Figure 2(C), physical vapor deposition or plating is used when adhering to the back side of the semiconductor chip 2. In the case of Figure 2(D), adhesion and bonding are achieved by sintering nano-sized Ni.

[0028] In particular, when depositing an Fe-Ni alloy metal layer 5 by plating, it may be necessary to optimize the composition and rearrange atoms in order to achieve the Fe-Ni thermal expansion coefficient shown in Figure 1. Specifically, in order to form an Fe-Ni alloy metal layer 5 with a desired composition by plating, it is desirable to perform a heat treatment of about 200°C to 350°C after the plating process. By performing the above heat treatment after the plating process, a diffusion layer (for example, a layer in which the mutual metals are diffused at the interface of the Fe-Ni alloy metal layer 5 and the conductor 4 to a thickness of about 0.01 μm = 10 nm or more) is formed, making it possible to achieve a strong bond. Furthermore, by performing a heat treatment after the plating process, a part of the Fe-Ni alloy metal layer recrystallizes, making it possible to achieve a strong bond. That is, although the crystals after the plating process show anisotropy depending on the crystal growth direction, the heat treatment generates new crystal grains with different crystal orientations, resulting in an extremely strong bond between the Fe-Ni alloy metal layer 5 and the conductor 4.

[0029] Furthermore, as shown in Figure 2(C), when the Fe-Ni alloy metal layer 5 is deposited on the back side of the semiconductor chip 2, it is desirable to deposit it by plating before dicing the wafer. In other words, by performing the plating process on a wafer-by-wafer basis and then dicing, it becomes possible to produce a semiconductor chip 2 with the Fe-Ni alloy metal layer 5 formed on the back side very efficiently.

[0030] In Figure 2, the surface (top side) of the semiconductor chip 2 is wire-bonded to the electrode metal for the connection between the surface electrode and the lead 3b. However, no stress is applied between the wire 8 and the lead 3b because the wire 8 is flexible. On the other hand, although it is a small area, due to the difference in thermal expansion coefficients between the wire 8 material and the semiconductor chip 2, thermal stress damage may occur to the semiconductor chip 2 at the wire bonding site.

[0031] The material of wire 8 is generally aluminum, gold, or copper. In the case of ball bonding, thermal stress is rarely a problem because the wire 8 material is initially melted and the area is relatively small. However, in the case of power devices, wedge bonding is performed, so the diameter of wire 8 is thick, ranging from 50 μmφ to 500 μmφ, and it undergoes work hardening. As a result, plastic deformation of the wire 8 material does not progress during thermal cycling, and stress is applied to the semiconductor chip 2. Figure 3 shows the bonding portion of a semiconductor chip in wire bonding. Figure 3(A) shows the case where conventional wedge bonding is performed on an Al electrode 2b, and Figure 3(B) shows the case where wedge bonding is performed on an Al / Fe-Ni / Au electrode in this embodiment. As described above, in the case of the conventional Figure 3(A), plastic deformation of the wire 8 material does not progress during thermal cycling, and stress is applied to the semiconductor chip 2. In contrast, in this embodiment, as shown in Figure 3(B), the above-mentioned problems can be solved by depositing an Fe-Ni alloy metal layer 5, which has a lower coefficient of thermal expansion than the wire 8 material, onto the Al electrode 2b surface of the semiconductor chip 2.

[0032] In this case, the composition of the Fe-Ni alloy metal layer 5 is the same as described above, with a Ni weight% concentration in the range of approximately 30% to 45%, and a thickness of 2 μm or more, preferably 5 μm or more and 20 μm or less. The Fe-Ni alloy metal layer 5 can be deposited by physical vapor deposition or plating. Typically, the electrode material is aluminum of about 1 to 4 μm, but if the Fe-Ni alloy metal cannot be deposited directly, pretreatment such as Zn substitution treatment (zincate) or Ni plating may be performed. Furthermore, as shown in Figure 3(B), it is desirable to prevent oxidation of the Fe-Ni alloy metal layer 5 by depositing a plating layer 2c (e.g., Au, Ag, Al, etc.) on top of the Fe-Ni alloy metal layer 5.

[0033] Next, we will explain the case of a flip-chip structure. Figure 4 is a diagram showing the structure when a flip-chip connection is made in the semiconductor device according to this embodiment. Figure 4 shows a flip-chip structure in semiconductor packaging, in which the circuit surface of the semiconductor chip 2 is connected opposite to the substrate electrode 4a (e.g., Cu electrode) of the substrate 9. The substrate electrode 4a and the semiconductor chip 2 are connected via solder balls (solder 7), and are joined by melting the solder 7. Conventionally, ceramic substrates have been used for the substrate 9 to reduce the difference in thermal expansion with the semiconductor chip 2, but currently, organic substrates with a large coefficient of thermal expansion are the mainstream. It has been put into practical use by fixing the semiconductor chip 2 and the substrate 9 with an insulating resin underfill to suppress deformation due to the difference in thermal expansion, but when the size of the semiconductor chip 2 is large or the output is high, deformation due to the difference in thermal expansion cannot be ignored.

[0034] Therefore, by adopting a structure as shown in Figure 4, deformation due to differences in thermal expansion can be suppressed. In the case of Figure 4(A), the Fe-Ni alloy metal layer 5 is attached to the connection surface of the semiconductor chip 2 and connected to the conductor 4 (substrate electrode 4a of the substrate 9) via solder 7. On the other hand, in the case of Figure 4(B), the Fe-Ni alloy metal layer 5 is attached to the surface of the conductor 4 (substrate electrode 4a of the substrate 9) and connected to the connection surface of the semiconductor chip 2 via solder 7. In both cases, a heat sink 21 for heat dissipation is provided above the semiconductor chip 2. In Figure 4, since the Fe-Ni alloy metal layer 5 is formed between the semiconductor chip 2 and the substrate electrode 4a, it is possible to alleviate stress caused by differences in thermal expansion. In particular, the structure shown in Figure 4 is extremely effective when the electrode area is large, such as in power devices. In the case of the structure shown in Figure 4(A), the Fe-Ni alloy metal layer 5 is formed by physical vapor deposition or plating, and in the case of the structure shown in Figure 4(B), methods such as cladding, physical vapor deposition, plating, thermal spraying, and sintering can be used.

[0035] Figure 5 shows the structure of a flip-chip connection in the semiconductor device according to this embodiment, where a Cu pillar is present. In Figure 5, a Cu pillar 10, which is a conductor 4, is formed on the electrode side of the semiconductor chip 2, and is connected to the substrate electrode 4a with solder 7. An Fe-Ni alloy metal layer 5 is formed between the semiconductor chip 2 and the Cu pillar 10, thereby mitigating the difference in thermal expansion between the Cu pillar 10 and the semiconductor chip 2, and making it possible to mitigate stress caused by the difference in thermal expansion, as described above. The Fe-Ni alloy metal layer 5 in Figure 5 is formed by physical vapor deposition or plating.

[0036] Next, the structure of the power device mounting will be described. Figure 6 shows the structure of the semiconductor device as a power device according to this embodiment. In the mounting of power devices, in addition to high output, the heat dissipation structure is important. As shown in Figure 6, ceramics with a relatively small coefficient of thermal expansion are often used as the insulating substrate 61, but the difference in thermal expansion between the copper wiring (wiring 62 and heat dissipation substrate 63) that carries large currents and the semiconductor chip 2 can be a problem. For this reason, as shown in Figure 6, an Fe-Ni alloy metal layer 5 is attached to the back side of the semiconductor chip 2. By doing so, it is possible to alleviate the stress caused by the difference in thermal expansion, as before.

[0037] Furthermore, as shown in Figure 6, it is desirable to also apply the Fe-Ni alloy metal layer 5 to the bonding portion of the semiconductor chip 2 in the wire bonding described in Figure 3. In addition, the Fe-Ni alloy metal layer 5 in Figure 6 is formed by physical vapor deposition or plating.

[0038] Figure 7 shows an example of a lead-connected power device structure. The structure shown in Figure 7 uses leads 3b, and the leads 3b, which are expected to have heat dissipation properties, are directly bonded to the surface side of the semiconductor chip 2. Fe-Ni alloy metal layers 5 are formed between the copper wiring (leads 3b and heat dissipation substrate 63) on the front and back surfaces of the semiconductor chip 2, and each is joined via solder 7. Figure 8 shows an example of a double-sided heat dissipation power device structure. In these structures, the difference in thermal expansion coefficients becomes a problem because the electrodes on the surface of the semiconductor chip 2 and the copper wiring (wiring 62, etc.) are directly joined.

[0039] As shown in Figures 7 and 8, stress on the semiconductor chip 2 can be relieved by inserting an Fe-Ni alloy metal layer 5 between the semiconductor chip 2 and the copper wiring. In particular, in the case of a double-sided heat dissipation mounting structure as shown in Figure 8, it is desirable to form the Fe-Ni alloy metal layer 5 on the front and back electrodes of the semiconductor chip 2. The Fe-Ni alloy metal layer 5 in Figures 7 and 8 is formed by physical vapor deposition or plating.

[0040] Next, the structure of the Nickel Micro Plating Bonding (NMPB) developed by the inventors will be described. In the case of power devices, as shown in Figures 6 to 8, connections are often made with solder 7, or for high-heat-resistant devices, Ag sintered materials are often used. However, solder 7 has the problem of a low melting point, and Ag sintered materials have the problems of Ag migration and high cost. Therefore, the inventors have developed a nickel micro plating bonding technology that connects the semiconductor chip 2 and the leads 3b or substrate 9 (copper substrate) with Ni plating via the edges (see, for example, Patent Document 1, International Publication No. 2017 / 154893, etc.). In this technology, the semiconductor chip 2 and the leads 3a are in contact or close proximity at the edge portion of the tapered leads 3a in a point-like or linear manner, and the distance between the semiconductor chip 2 and the leads 3a gradually increases outward from the point of contact or proximity. The semiconductor chip 2 and the leads 3a are connected by filling the gap with Ni plating solution and performing a plating process. Although the bond created by the Ni plating is very strong and will not break due to thermal stress, thermal stress on semiconductor chip 2 may cause leakage on the semiconductor chip 2 side.

[0041] Figure 9 shows an example of an NMPB structure in a semiconductor device according to this embodiment. Figure 9(A) shows the structure when plating is performed with Ni, and Figure 9(B) shows the structure when plating is performed with Fe-Ni alloy metal. In Figure 9(A), an Fe-Ni alloy metal layer 5 is formed on the connection surface where the semiconductor chip 2 connects to the lead 3b, and the Fe-Ni alloy metal layer 5 and the edge of the lead 3b are in contact and joined with Ni plating 91. In this case, the Ni plating 91 may be formed with Fe-Ni alloy instead of Ni. The Fe-Ni alloy metal layer 5 here is formed by physical vapor deposition or plating. In Figure 9(B), the Fe-Ni alloy metal layer 5 is formed by plating with Fe-Ni alloy while the electrode of the semiconductor chip 2 and the edge of the lead 3b are in contact, and the semiconductor chip 2 and the lead 3b are joined via the edge. In either structure, the formation of the Fe-Ni alloy metal layer 5 between the semiconductor chip 2 and the copper electrode can alleviate stress on the semiconductor chip 2 caused by the difference in thermal expansion.

[0042] Furthermore, as shown in Figure 9, when performing Ni plating or Fe-Ni alloy plating, it is desirable to perform heat treatment at approximately 200°C to 350°C after the plating process in order to optimize the composition and rearrange the atoms. This allows for the formation of a diffusion layer at the interface between the plated metal and the conductor 4, enabling a strong bond. Additionally, heat treatment after the plating process allows for the recrystallization of a portion of the Fe-Ni alloy metal layer, further contributing to a strong bond.

[0043] While a strong bond can be achieved at the interface between the plated metal and the conductor 4 through diffusion and recrystallization, a similar phenomenon also occurs at the interface where opposing plated growth surfaces collide (interface 92 shown in Figure 9), making the bond by plating even stronger.

[0044] Figure 10 shows the results of the inventors' investigation into the effect of heat treatment after plating of the Fe-Ni alloy metal layer 5. Here, the current density during plating was set to 2 A / dm². 2 or 4 A / dm2 The Fe-Ni alloy metal layer 5 was plated to have a composition of Fe-(33~44)Ni(wt%), and then heat-treated at 0°C (untreated), 220°C, 250°C, 300°C, 350°C, 400°C, and 450°C. The integer linear expansion of the Fe-Ni alloy metal layer 5 heat-treated at each temperature was measured over a temperature change from 50°C to 250°C.

[0045] As shown in the measurement results in Figure 10, it can be seen that the coefficient of linear expansion changes depending on the heat treatment temperature. In other words, it is possible to adjust the integer value of linear expansion by heat treatment after plating, depending on the operating environment and application of the semiconductor device 1. Specifically, by heating the semiconductor device 1 to a temperature higher than the temperature at which it is used, it is possible to prevent the coefficient of linear expansion from changing significantly with temperature, and it can be used with a constant integer value of linear expansion.

[0046] As described above, in the semiconductor device according to this embodiment, the Fe-Ni alloy metal layer 5 is directly or indirectly attached to the surface electrode or back electrode of the semiconductor chip 2, and the semiconductor chip and the conductor are connected via the Fe-Ni alloy metal layer 5. Therefore, the stress caused by the difference in thermal expansion between the semiconductor chip 2 and the conductor is relieved, and damage to the semiconductor chip 2 can be prevented.

[0047] Furthermore, by setting the weight percentage of Ni in the Fe-Ni alloy metal layer to a range of 30% to 45%, and / or setting the thickness of the Fe-Ni alloy metal layer to 2 μm or more and 20 μm or less, it is possible to minimize stress while keeping the coefficient of thermal expansion as small as possible, thereby preventing damage to the semiconductor chip 2.

[0048] Furthermore, by forming the Fe-Ni alloy metal layer 5 by plating, it becomes possible to form it directly on the semiconductor chip 2, and because it can be made thicker compared to sputtering, it can be formed to a thickness sufficient to withstand thermal expansion. [Explanation of Symbols]

[0049] 1 Semiconductor device 2 Semiconductor chips 2a Ti / Ni / Au film 2b Al electrode 2c plating layer 3 Lead Frame 3a die pad 3b lead 4. Conductors 4a Substrate electrode 5 Fe-Ni alloy metal layer 6 resin 7 Handa 8 wires 9 circuit boards 10 Cu Pillar 21 Heatsink 61 Insulating substrate 62 Copper Wiring 63 Heat dissipation substrate 91 Ni plating 92 Interface

Claims

1. An Fe-Ni alloy metal layer is formed directly or indirectly on the surface electrode and / or back electrode of a semiconductor element by plating, and the semiconductor element and the conductor are connected via the Fe-Ni alloy metal layer. A semiconductor device characterized in that an electrode surface, which is the surface electrode or back electrode of the semiconductor element, and the conductor are in point-like or linear contact or proximity at a bonding surface, the distance between the electrode surface and the conductor at the bonding surface gradually increases outward from the point of contact or proximity, and the space between the electrode surface and the conductor is filled with an Fe-Ni alloy metal to form an Fe-Ni alloy metal layer.

2. The semiconductor element and the conductor are connected directly or indirectly to the surface electrode and / or back electrode of the semiconductor element via an Fe-Ni alloy metal layer formed by plating, A semiconductor device characterized in that the Fe-Ni alloy metal layer is formed by heat-treating an Fe-Ni plated metal, and a diffusion layer is formed at the interface between the conductor and the Fe-Ni plated metal, or at the interface between the surface electrode and / or back electrode of the semiconductor element and the Fe-Ni plated metal, or a portion of the Fe-Ni plated metal is recrystallized.

3. An Fe-Ni alloy metal layer is directly or indirectly attached to the surface electrode and / or back electrode of a semiconductor element, and the semiconductor element and a conductor are connected via the Fe-Ni alloy metal layer. A semiconductor device characterized in that the Fe-Ni alloy metal layer is formed by sintering a powder of nano-sized metal particles and Fe-Ni alloy particles.

4. In the semiconductor device described in claim 3, A semiconductor device characterized in that the powder contains micro-sized Al particles.

5. A joining method characterized in that an electrode surface which is the surface electrode or back electrode of a semiconductor element and a conductor are in point-like or linear contact or proximity at a joining surface, and Fe-Ni plated metal is filled into the gap where the distance between the electrode surface and the conductor at the joining surface gradually increases outward from the point of contact or proximity to perform plating joining, and then heat treatment of the said area.

6. A bonding material comprising nano-sized metal particles and Fe-Ni alloy particles, formed as an Fe-Ni alloy metal layer that is directly or indirectly adhered to the surface electrode and / or back electrode of a semiconductor device by sintering.

7. A method for forming an Fe-Ni alloy metal layer, wherein an Fe-Ni alloy metal is directly or indirectly plated onto the surface electrode and / or back electrode of a semiconductor element, or onto a conductor electrically connected to the surface electrode and / or back electrode of the semiconductor element, and then heat-treated at 220°C to 450°C to form the Fe-Ni alloy metal layer.

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