Chip device and method for randomized logical encryption

Abstract

To provide a chip device with a logic circuitry 105 protected by a randomized logic encryption based on a key K for preventing a designated usage of the logic circuitry 105 by an unauthorized user.SOLUTION: A chip device comprises a physically unclonable function PUF 110, a storage 120, and a chip enabler 130 with one or more registers 132. The physically unclonable function PUF 110 is configured to generate a device-individual response Re based on a challenge Ch. The storage 120 has stored the challenge Ch and a data element C, the data element C being an encryption of a key K with the response Re of the PUF 110 as encryption key. The enabler 130 is configured to enable the logic circuitry 105 for the designated usage only, when the key K is transferred to the register(s) 132, the key K being a decryption of the data element C with the response Re as the encryption key.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a chip device and method for protecting circuits by randomized logic encryption, and more particularly to logic encryption enhanced by additive manufacturing. [Background technology]

[0002] In chip manufacturing, it is widespread for the manufacturing process to be carried out in a foundry by a third party with only limited control over the process. As a result, there are several attack scenarios in which a potential attacker can gain access to hardware intellectual property (IP) that should be kept confidential for security reasons.

[0003] For example, the following attack scenarios are possible.

[0004] Attack Scenario-1 (AS): This scenario relies on reverse engineering and the insertion of a hardware Trojan. Here, the attacker can identify device technology in the foundry and extract its gate-level netlist, or otherwise infer its functionality. Using this knowledge, the attacker can create additional chips.

[0005] Attack Scenario 2 (AS-2): This scenario concerns the production or manufacture of so-called IP, i.e., the attacker producing additional chips.

[0006] Attack Scenario 3 (AS-3): This scenario concerns a hardware attack against countermeasures to the aforementioned attack scenarios. Here, a hardware attack is, for example, a so-called fault injection to overcome countermeasures against attack scenarios 1 and 2. For example, the attack in this scenario may target the read / write protection of a protected storage area (e.g., internal flash storage).

[0007] For all attack scenarios, it is possible to distinguish between case (a) where the System-on-Chip (SoC) is produced for the first time at the foundry, resulting in attack scenarios AS-1a, AS-2a, and AS-3a, and case (b) where the chip is produced multiple times thereafter at the foundry, resulting in attack scenarios AS-1b, AS-2b, and AS-3b.

[0008] Currently, only a limited number of countermeasures are available to reliably prevent all three attack scenarios. However, since not all attack scenarios are acceptable, it is necessary to ensure that attackers cannot at least activate the chips they produce or manufacture any extra chips they have produced. [Overview of the project] [Problems that the invention aims to solve]

[0009] Therefore, there is a demand for chip devices and their respective methods that reliably protect hardware intellectual property. [Means for solving the problem]

[0010] At least some of the above-mentioned problems are solved by the chip device described in claim 1 and the method for protecting a circuit by randomized logic encryption described in claim 11. Dependent claims refer to specific and advantageous realizations of the subject matter of the independent claims.

[0011] The present invention relates to a chip device having a logic circuit configuration protected by randomized logic encryption based on a key (e.g., a secret key) for preventing unauthorized designated use of the logic circuit configuration by an illegitimate user. The chip device comprises a Physically Unclonable Function (PUF), a storage, and a chip enabler having one or more registers. The physically unclonable function is configured to generate a device-specific response based on a challenge. The storage stores the challenge and a data element, wherein the data element is an encrypted form of a key (logic encryption key) that uses the PUF response as an encryption key. The chip enabler is configured to enable the logic circuit configuration for designated use only when the key is transferred to the register. The key is, for example, a secret key derived by decrypting the data element, and the PUF response serves as the decryption key.

[0012] Optionally, the chip enabler includes a cryptographic module and / or a processing device that decrypts the data element to generate the key. According to further embodiments, data processing such as encryption and decryption may be performed by an external device. Furthermore, the cryptographic module may or may not be a dedicated cryptographic hardware chip that is part of the device.

[0013] Optionally, the logic circuit configuration comprises regular (logic) gates and a plurality of logic key gates that define the logic encryption. Logic encryption may be defined such that the designated use is enabled only when the key bits stored in one or more registers are correctly received by the logic key gates. This correctness may be ensured by connecting the registers to corresponding logic key gates such that the enable key bits automatically enable the logic circuit configuration for the designated purpose.

[0014] Optionally, the device comprises an additively manufactured component, and the PUF is comprised in at least a part of this component. The additively manufactured component has a device-specific microstructure, which consequently produces device-specific characteristics. Accordingly, the response of the PUF depends on the device-specific characteristics. The device-specific microstructure arises as a result of additive manufacturing that generates random fine structures, for example, by mixing or fusing nanoparticles (e.g., nanoparticles of a conductive layered material or nanoparticles dispersed in a functional fluid). Due to this random structure, the PUF has individual characteristics that differ from device to device (i.e., device-specific characteristics).

[0015] Optionally, the additively manufactured component is at least one of a package, a circuit board, a solder layer, and a sealing material. For example, a logic circuit configuration may be formed as or within an integrated chip, and the integrated chip is enclosed, supported, or packaged in the additively manufactured component that accommodates the PUF.

[0016] Optionally, the component comprises an additively manufactured electrical circuit configuration including at least one of the following additively manufactured elements: a capacitor, a coil, a resistor, a strip line, a microstrip, or other elements. The electrical characteristics of each of these elements are device-specific due to the additive manufacturing process.

[0017] Optionally, the device-specific characteristics are - form factors of conductive elements (e.g., their size, shape, dimensional ratio, etc.), - operation, - resistance value (e.g., DC resistance), - latency or phase shift, - complex impedance values (e.g., resistance, capacitance, and inductance), - a resonant circuit or a resonant frequency thereof, - electromagnetic radiation or shielding thereof defined by one or more of the above.

[0018] When additively manufactured elements are compared to conventionally manufactured elements, it is clear that the random microstructure will result in randomly (slightly) different effective properties. Consequently, geometric properties such as form factor will also be substantially different. The same can be said for 3D-printed electric motors or engines, for example, which will have signal propagation along strip lines (resulting in random delays) or individual properties (such as speed and force as correlated elements of applied voltage).

[0019] According to the examples, a resonant circuit may be used to measure the complex impedance encoded within the additive manufacturing circuit configuration. The resonant frequency is a highly sensitive quantity that can be used to define the device-specific characteristics that can be used as a PUF.

[0020] Optionally, device-specific characteristics include the following optical identification, i.e., - Unique label engraving, - Intentional error pixels, - Engraved optical light source Defined by one or more of the following.

[0021] These embodiments may use, for example, a chip interposer positioned between the chip and the substrate, or a combination of two additively manufactured structures, at least one of which supports the chip. Error pixels can be implemented by embedded structures made of conductive fluid within the dielectric component. For example, silver particles of conductive fluid representing one or more pixels of the captured image may be intentionally additively manufactured within the polymer surface of the dielectric component. During visual inspection, this may appear as any other random impurities or minute contamination in the dielectric support structure that may be present in any practical additively manufactured component. Therefore, a camera that captures one or more images may be placed on one structure (e.g., one with the chip) after the interposer has been mounted on the substrate. According to the embodiments, the chip evaluates whether the defective pixels on the polymer surface (e.g., the exemplified silver particles) are in the correct predetermined locations where they were intentionally formed.

[0022] In a further embodiment, the label may be a QR code® formed on two layers of an interposer on a substrate. The two layers are arranged touching on each other's top surfaces so that a predetermined QR code® is visible as a superposition of both portions of the QR code® formed on separate layers. Since the printed circuit board exhibits some degree of transparency, the superposition is visible as a predetermined QR code®. A slight misalignment in one of the QR code® portions will result in an incorrect code. The accuracy of the code can also be checked with a camera that detects intentional error pixels. In this case as well, once accuracy is confirmed by image evaluation, the chip can be enabled. Naturally, there may be more than two QR code® portions, allowing for multiple valid QR codes® by selecting two of the usable QR code® portions. Similarly, three or more portions may be combined, which further complicates the coding.

[0023] Embodiments using engraved light sources rely on the same principle. The light source generates a unique electromagnetic spectrum that can be captured by a camera and evaluated by a processing device. In this case as well, the chip can be enabled when the correct light source is combined with the correct chip.

[0024] Since potential attackers are unaware of the coding (error pixels, QR code®, or light source) beforehand, this PUF also offers a high level of security.

[0025] Optionally, the device further comprises at least one finite state machine configured to utilize a PUF to generate a response from a challenge, and / or to decode data elements using the response as a decoding key.

[0026] Optionally, additive manufacturing includes an inkjet process or a laser sintering process configured to selectively form three-dimensional (3D) devices having dielectric and conductive structures. The inkjet process is based on different functional fluids for conductive elements and dielectric materials and includes, for example, a curing step after each layer has been printed. The conductive fluid includes, for example, nanoparticles that are mixed or fused in the curing process (e.g., using energy irradiation).

[0027] Further embodiments relate to a method for protecting a logic circuit configuration by key-based randomized logic encryption to prevent unauthorized use of the logic circuit configuration by an unauthorized user. The steps involve using a physically difficult-to-replicate function (PUF) to generate a challenge-based, device-specific response, A step of storing a challenge and data elements in storage, wherein the data elements are keys encrypted using the PUF response as the encryption key, The process includes the step of enabling a logic circuit configuration for a specified usage by transferring a key to a register using a chip enabler having one or more registers, wherein the key is obtained by decrypting a data element using the response as the encryption key.

[0028] The method is optional. Steps to generate a PUF response based on the challenge, and The process further includes one or more steps of encrypting the key using the PUF response as the encryption key and providing the result as a data element. The step of decrypting the data elements is to use the PUF response as the decryption key.

[0029] Data processing such as encryption and decryption may be performed by a dedicated cryptographic hardware chip or other (processing) device, which may or may not be located outside the device.

[0030] Similarly, according to further embodiments, all the functions described above, in conjunction with the chip device, may be carried out as optional method steps. The order of the method steps is limited only in that some method steps are required before others can be performed.

[0031] This method may be implemented in software or computer program products. Therefore, the embodiments also relate to computer program products having stored program code that perform the method described above when the program code is executed on a computer or processor.

[0032] Various embodiments of the present invention are described below for illustrative purposes only and with reference to the accompanying drawings. [Brief explanation of the drawing]

[0033] [Figure 1] This figure illustrates a chip device according to an embodiment of the present invention. [Figure 2] This figure illustrates logical encryption implemented by an embodiment on a chip device. [Figure 3] This figure illustrates the microstructure resulting from additive manufacturing that provides randomness, as used in PUF (Purpose-Based Fabrication) examples. [Figure 4] This diagram depicts a stripline as an example of a component within a chip device for implementing PUF. [Figure 5] This figure shows a schematic flowchart for a method of protecting logic circuit configurations using randomized logic encryption. [Modes for carrying out the invention]

[0034] Here, various embodiments will be explained more fully with reference to the attached drawings, which illustrate several examples.

[0035] The terms used herein are for illustrative purposes only and are not intended to be limiting. Where used herein, the singular forms “a,” “an,” and “the” are intended to similarly include the plural form unless the context clearly indicates that the plural form is not included. Where used herein, the terms “comprises,” “comprising,” “includes,” and / or “including” indicate the presence of the described feature, step, action, element, and / or component, but do not preclude the presence or addition of one or more other features, steps, actions, elements, components, and / or groups thereof.

[0036] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as generally understood by those skilled in the art in which the examples belong. It will also be understood that terms, for example, those defined in commonly used dictionaries, should be interpreted as having the meaning consistent with their meaning in the context of the art, and not as idealized or overly formal unless expressly defined herein.

[0037] Figure 1 depicts an exemplary SoC device having a logic circuit configuration 105, protected by randomized logic encryption based on key K to prevent unauthorized use of the logic circuit configuration 105 by an unauthorized user, according to an embodiment. In other words, the logic circuit configuration 105 is enabled only when the correct key K is received by the logic circuit configuration 105.

[0038] The SoC device comprises a physically hard-to-replicate function (PUF) 110, storage 120, and a chip enabler 130 having one or more registers 132. The physically hard-to-replicate function (PUF) 110 is configured to generate a device-specific response Re based on a challenge Ch. Storage 120 stores the challenge Ch and a data element C, where the data element C is a key K (e.g., a logical lock key) encrypted using the response Re from the PUF 110 as the encryption key. The enabler 130 is configured to enable a logic circuit configuration 105 for a specified usage only when the key K is transferred to register 132, where the key K is the data element C decrypted using the response Re as the encryption key. The embodiment is applicable to any type of chip device. In particular, the chip device may be a system-on-a-chip (SoC) device or part of an SoC device.

[0039] The underlying logical encryption scheme used in the embodiment can be summarized as illustrated in Figure 2. The purpose of logical encryption (LE) (logical locking / obfuscation) is to protect the integrity of the hardware design throughout the IC supply chain. LE is based on inserting additional gates into a gate-level netlist (NL) that hides the original functionality and structure of the design by locking it with a secret key K.

[0040] In detail, Figure 2 depicts an example in which additional key gates KG0, KG1 are inserted into a design that already includes regular (logic) gates G0, G1, G2, ... G5. It is understood that the number of regular and key gates can be arbitrary. The regular gates G0, G1, ... are adapted to achieve a specified purpose of the underlying chip, namely the generation of desired output signals O1, O2 based on a set of input signals (values) I1, I2, ...

[0041] For example, the 0th normal gate G0 receives two input values ​​I2 and I3, generates an output value which is received by the 2nd gate G2 and the 3rd gate G3. The 2nd gate G2 receives input signal I1 as a further input. The 3rd logic gate G3 receives the output of the 1st logic gate KG1, which receives the 2nd key value KI2 and the output value of the 1st logic gate G1 as its further inputs. The 1st logic gate G1 receives the 4th input signal I4 and the 5th input signal I5 as its inputs. The output of the 2nd logic gate G2 is input to the 0th key gate KG0, which receives the 1st key value KI1 as a further input. The output of the 0th key gate KG0, together with the output of the 3rd logic gate G3, is received by the 4th gate G4, which generates the 1st output value O1. The output of the 3rd logic gate G3 is received by the 5th gate G5, which receives the output of the 1st logic gate G1 as its 2nd input. The output of the fifth gate is the second output value O2.

[0042] Therefore, even if all the gates are known (for example, by reverse engineering), the correct (specified) way in which the circuit configuration functions is obfuscated by the key gates KG0 and KG1. Without the correct key values ​​KI1 and KI2, the circuit configuration may not function correctly. In other words, the chip can only be activated with the correct key values ​​KI1, KI2, ... stored in the specified location and correctly assigned to the chip. The multiple key values ​​KI1, KI2, ... define a logical encryption key (LEK), which is denoted here and below by K.

[0043] This key K must be stored in a secure location. At startup, key K may be read from storage (for example, via a finite state machine (FSM)) and transferred to dedicated registers connected to key gates KG0, KG1, ..., for example. Thus, by protecting key K, the functionality of the device can be kept secret.

[0044] This procedure can mitigate at least some of the aforementioned attack scenario AS. - Regarding AS-1a: As long as the key K is kept secret during chip production, the LE can prevent the insertion of hardware Trojans (HTs). - Regarding AS-1b: The attacker can obtain key K from the first round of produced chips and insert HT when the (n+1)th round is produced. - Regarding AS-2{a,b}: The attacker can retrieve K and activate / manufacture extra chips. - Regarding AS-3a: Fault E injected into slot 1 can propagate, and since the small variation between two different faults Ei and Ej is directly "transferred", K XOR E can be analyzed. - Regarding AS-3b: By learning from AS-3a, a fault attack can be reproduced against the (n+1)th SoC.

[0045] Therefore, in the embodiment, additional security measures are implemented using a physically hard-to-replicate function (PUF). A PUF is a physical object that provides a physically defined "digital fingerprint" output (response) that functions as a unique identifier for a given input and condition (denoted as a challenge). In the embodiment, the PUF maps the unique variation of at least one additive manufacturing component (e.g., an electronic structure) of the chip device to a digital output, where the unique physical variation that occurs during the additive manufacturing process is utilized. For this reason, according to the embodiment, the component with the PUF may be integrated in various locations, such as within the package, or within the chip encapsulant, or within the chip's circuit board support, or in a solder layer or interposer connecting the chips.

[0046] The additive manufacturing process used in the embodiment may rely on the technology of "additive manufactured electronics" (AME), which are 3D printed electronic devices for additive circuit boards (ACB). According to the embodiment, various additive manufacturing processes such as inkjet printing or laser sintering may be used, both of which enable the manufacture of conductive and dielectric structures for producing, for example, a desired electronic circuit.

[0047] Inkjet printing (the so-called inkjet process) may use conductive and non-conductive functional fluids (e.g., inks), which are additionally applied to a carrier to form a three-dimensional structure. For example, a photopolymer fluid may be used as an ink for non-conductive structures, and a fluid containing nanoparticles (e.g., silver nanoparticles) may be used as an ink for conductive structures. These fluids are layered in multiple layers. Each layer can be cured by irradiation with ultraviolet light or other suitable radiation. As a result, a three-dimensional object is produced by layering multiple layers.

[0048] The laser sintering process may utilize the so-called "Low-Temperature Cofired Ceramic" (LTCC) process. This process is based on a low-temperature sintered flexible ceramic foil, which is first mechanically structured and printed, then laminated, and subsequently sintered at approximately 850-900°C. The result is a highly integrated, three-dimensionally networked, multilayer ceramic substrate. Further processing may utilize known layering, bonding, or SMD (Surface Mounted Device) technologies. The carrier material here is ceramic. Its stability enables high-quality connection and packaging systems.

[0049] In both processes, the electronic structure is created from scratch to complete the 3D device. In particular, these additive manufacturing processes make it possible to integrate or embed, for example, a chip (such as an SoC) into an additively manufactured package. Alternatively, the chip may be mounted on an additively manufactured substrate or enclosed in an additively manufactured housing.

[0050] A unique nanoparticle structure is generated within the final chip device by sintering nanoparticles of conductive / insulating fluids or conductive functional fluids in the inkjet process, or by various post-processing modifications. Each chip has a nanoparticle fingerprint, which in the examples is used for incorporating the PUF.

[0051] Figure 3 illustrates a microstructure obtained from additive manufacturing of an exemplary electronic structure used in or containing a PUF. Additive manufacturing always produces a microstructure that is not uniform but is specific to the manufacturing process and therefore differs from one structure to another. For example, conductive nanoparticles 310 are mixed in during manufacturing, and random cavities 320 remain between the mixed nanoparticles 310.

[0052] Therefore, each additively manufactured conductive structure has its own unique microstructure. As a result, the electrical properties of the conductive material differ slightly from chip to chip (or additively manufactured component defining the PUF). Furthermore, additive manufacturing allows for complete 3D wiring and eliminates the need for vertical interconnect access (VIA), enabling the creation of 3D-printed centripetal elements (capacitors, coils). It is also possible to integrate or embed other electrical components (e.g., active elements). For example, when a coil, capacitor, or resistor is formed by this additive manufacturing process, the resulting properties become structure-specific and can be used as a physically difficult-to-replicate function.

[0053] Physically hard-to-replicate functions may be characterized by various circuits or structures. For example, a microstructure, such as the one depicted in Figure 3, generates a unique complex impedance value, which in turn generates a unique resistance value and / or capacitance value and / or inductance value. This then yields the structure-specific resonant characteristics of the resonant circuit. For example, the resonant frequency will differ for each structure. Since the structure is part of a chip device, the resonant frequency will similarly differ for each device.

[0054] Figure 4 depicts another embodiment of components within a chip device that may be used to integrate a physically hard-to-replicate function 110. In this embodiment, the additively manufactured component includes a strip line 410 embedded in a dielectric material 420. Instead of the strip line 410, a microstrip configuration can also be used within the PUF 110. The strip line 410 is completely embedded in the dielectric material 420. Since the conductive strip 410 and the dielectric material 420 are formed by additive manufacturing, the propagation speed of high-frequency signals along the strip line 410 will depend on the individual structure and, therefore, on the chip device. Due to the structure-specific propagation, an inherent latency (delay) and / or inherent signal attenuation through the line will result in the signal propagation.

[0055] Therefore, the fingerprint of nanoparticles affects electrical properties such as latency and phase shift of the propagated signal, which can be measured, for example, by comparing two signals propagating along different paths. Similarly, the fingerprint of nanoparticles slightly alters electromagnetic radiation properties (e.g., shielding).

[0056] Similarly, additive manufacturing can result in slight variations in form factor or performance (e.g., the characteristics of a 3D-printed electric motor).

[0057] According to a further embodiment, optical variations in optical properties may be further utilized in a physically unclonable function. For example, during additive manufacturing, a unique label may be imprinted in a chip device (e.g., in a package), and this unique label can be read and used as an encryption for the logical encryption utilized in the present invention. Further optical identification may be achieved by incorporating intentional error pixels or imprinted optical light sources.

[0058] The specific functioning of PUF 110 can be summarized as follows. Let the challenge of the j-th instance of the PUF (family) be Ch i . Each instance may be associated with a specific implementation on one chip device. The response is as follows. Re i =PUF j (Ch i ) (1)

[0059] One main characteristic of a PUF is the Hamming distance for a challenge Ch l . Dist H (PUF i (Ch l ),PUF j (Ch l )) (2) where i≠j is very large.

[0060] A PUF with a small output size and a small input size W is called a weak PUF. In this case, an untrusted foundry may perform complete characterization and may store all pairs {(Ch i ,Re i )} which are part of W for all chip devices, where W denotes the set of all possible input / output values of the weak PUF. On the other hand, a strong PUF has a very large input / output space S, making characterization impractical and thus achieving much higher security. That is, {(Ch i ,Re i )} i∈S , where |S|≫|W|.

[0061] According to the embodiment, the following information is stored in the storage 120 for the chip device "i". - ENC Rei (K), and - (Ch,He) Here Re i This is a PUF realized with the chip device "i". i This is the response and is used as the cryptographic key for LEK "K". The value He defines optional helper data for key generation (to ensure high entropy, repeatability, controllability, etc.). This information may be stored in different slots of storage 120 (e.g., slot 1 and slot 2).

[0062] Next, if the chip device is enabled to perform the desired purpose, the following steps may be taken. (1)C i ←ENC Rei (K) and (Ch,He) are read from storage, for example, via FSM. (2) Rei←PUF i (Ch,He) is generated, for example, via FSM. (3) K←DEC Rei (C i ) is decrypted, for example, via an FSM within a dedicated hardware module. (4) Transfer K to a dedicated register (connected to the insertion gate). Here, an arbitrarily chosen finite state machine (FSM) may be used.

[0063] According to the examples, these steps may be performed as part of the method, PUF i This defines the execution of a physically difficult replication function implemented using Challenge Ch. According to further embodiments, a processing unit and / or cryptographic hardware module, which may or may not be part of a chip device, may be configured to perform these steps.

[0064] In relation to the attack scenario described above, the embodiment offers the following advantages.

[0065] Regarding AS-1a: Key K (Each ENC Rei (K)) is kept secret even during the manufacturing of the chip device, and the resistance of LE to prevent the insertion of hardware Trojans can be relied upon.

[0066] Regarding AS-1b: Value ENC Rei (K) and the tuple (Ch,He) may be recoverable. However, the corresponding Re i The function that generates it relies on PUF110 protection and is unknown or irreproducible. Therefore, the cryptographic key Re needed to decrypt K is unknown. i It is impossible to obtain it.

[0067] Regarding AS-2{a,b}: The attacker is ENC Rei (K) and (Ch,He) can be reconstructed. However, it is impossible to reconstruct the PUF function 110, and other attacks would be necessary.

[0068] Regarding AS-3a: The situation is similar to that of Modification 1, i.e., the small Hamming distance distH(E) injected into slot 1. i ,E j ) Two different faults E i and E j Regarding the Hamming distance, that is, dist H (DEC Rei (ENC Rei (K) XOR E i ), DEC Rei (ENC Rei (K) XOR E j )) The odds are very large. Therefore, fault attacks are extremely difficult to "execute" (for example, by trying all possibilities).

[0069] Regarding AS-3b: The embodiment shows a significant improvement in security compared to a situation where key K and / or the encrypted key ENC(K) are the same on all devices. Even if an attacker infers information from an attack on device A, according to the embodiment, this information cannot be used to attack another device B (due to PUF reasons). Therefore, ENC Rei Since (K) is unique for each device chip, the learning from AS-3a is smaller (than that of Modification 1a).

[0070] As a result, the implementation provides reliable protection against all three attack scenarios.

[0071] Figure 5 shows a schematic flowchart of a method for protecting logic circuit configuration 105 by randomized logic encryption based on key K to prevent unauthorized use of logic circuit configuration 105 by unauthorized users. This method is - Step S110 generates a device-specific response based on the challenge Ch using a physically difficult-to-replicate function, - Step S120, which stores Challenge Ch and data element C in storage 120, wherein data element C is obtained by encrypting key K using the response Re of PUF 110 as the encryption key, - Step S130 enables a logic circuit configuration 105 for a specified usage by transferring a key K to a register using a chip enabler 130 having one or more registers 132, wherein the key K is obtained by decrypting a data element C using the response Re as the encryption key.

[0072] In further embodiments, it is understood that some or all of the functions performed by the aforementioned chip device may be optional method steps in the method shown in Figure 5. In particular, further optional steps may be A step to generate the response Re of PUF110 based on the challenge Ch, or The step may be to encrypt key K using the response Re of PUF110 as the encryption key, and provide the result as data element C, or The step of decrypting data element C is to use the response Re from PUF110 as the decryption key.

[0073] The order of method steps shall be restricted only by the condition that one method step can only be performed if another step has been performed beforehand.

[0074] This method may also be carried out by a computer. Those skilled in the art will readily recognize that the steps of the method described above may be performed by a programmed computer. The embodiments are also intended to cover program storage devices, such as digital data storage media, that are machine- or computer-readable and encode machine-executable or computer-executable programs of instructions, which, when executed on a computer or processor, perform some or all of the operations of the method described above.

[0075] This specification and drawings are merely illustrative of the principles of this disclosure. Therefore, it will be understood that a person skilled in the art could devise various configurations that embody the principles of this disclosure and that fall within the scope of this disclosure, even if not explicitly described or shown herein.

[0076] Furthermore, while each embodiment may stand independently as a separate example, it should be noted that other embodiments may combine the defined features in different ways; that is, a particular feature described in one embodiment may be realized in another. Such combinations are covered by the disclosure herein unless otherwise explicitly stated that a particular combination is not intended.

[0077] Therefore, it is clear that multiple possible modifications exist. It is also clear that the examples described are merely illustrative and should not be considered to limit the scope, applicability, or configuration of the present invention in any way. Indeed, the foregoing description and the description of the figures enable those skilled in the art to implement the exemplary embodiments in specific ways, and by knowing the disclosed inventive concept, they can try various modifications, for example, with respect to the way each element functions or is configured as described in the exemplary embodiments, without departing from the scope of the invention, and the scope of the invention is defined by the claims and their legal equivalents, such as further description herein. [Explanation of symbols]

[0078] 105 Logic Circuit Configuration 110 Physically Hard-to-Recreate Functions (PUFs) 120 storage 130 Tip Enabler 132 One or more registers 135 Cryptographic Modules 310 Nanoparticles mixed in 320 Cavities or voids created by additive manufacturing 410 strip tracks, microstrips 420 Additive Manufacturing Dielectric Materials K logical encryption key Re (device-specific) response Challenges that trigger a Ch response C Data Elements

Claims

1. A logic circuit configuration protected by key-based randomized logic encryption to prevent unauthorized use of the logic circuit configuration by an unauthorized user, A physically hard-to-replicate function (PUF) configured to generate a device-specific response based on a challenge, A storage device for storing the challenge and data elements, wherein the data elements are encrypted using the response of the PUF as the encryption key, A chip enabler having one or more registers, wherein the enabler is configured to enable the logic circuit configuration for the predetermined use only when the key is transferred to the register, and the key is obtained by decrypting the data element using the response as the encryption key, and A chip device equipped with, The logic circuit configuration comprises a regular gate and a plurality of logic key gates that define the randomized logic encryption, wherein the randomized logic encryption is defined as being enabled only when the bits of the key in the register are accurately received by the logic key gate connected to the register, A chip device comprising additively fabricated components, wherein the PUF is included in at least a portion of the components, the additively fabricated components have a device-specific microstructure that gives rise to device-specific characteristics, and the response of the PUF depends on the device-specific characteristics.

2. The device according to claim 1, wherein the chip enabler includes a cryptographic module and / or processing unit that performs the decryption of the data elements for generating the key.

3. The additively fabricated components are package, Circuit board, Solder layer, Sealing material The device according to claim 1, which is at least one of the following.

4. The device according to claim 1 or 3, wherein the component comprises an additively manufactured electrical circuit configuration having at least one of the following additively manufactured elements: a capacitor, a coil, a resistor, a strip line, and a microstrip, and the electrical characteristics of the additively manufactured elements are device-specific due to the additive manufacturing process.

5. The aforementioned device-specific characteristics are, form factor, operation, Resistance value, Latency or phase shift, Complex impedance value, Resonant circuit or its resonant frequency, Electromagnetic radiation or its shielding The device according to claim 1 or 2, as defined by one or more of the following.

6. The aforementioned device-specific characteristics are the following optical identification, namely, Unique label engraving, Intentional error pixels, Engraved optical light source A device according to any one of claims 1 to 5, defined by one or more of the following.

7. To use the PUF to generate the response from the challenge, and / or The response is used as the key for the decoding to decode the data element. The device according to any one of claims 1 to 6, further comprising at least one configured finite state machine.

8. A method for protecting a logic circuit configuration by key-based randomized logic encryption to prevent unauthorized use of the logic circuit configuration by an unauthorized user, The steps include generating a challenge-based device-specific response using a physically difficult-to-replicate function (PUF), and A step of storing the challenge and data elements in storage, wherein the data elements are encrypted using the response of the PUF as the encryption key, A step of enabling the logic circuit configuration for a predetermined use by transferring the key to the registers using a chip enabler having one or more registers, wherein the key is obtained by decrypting the data element using the response as the encryption key; Includes, The logic circuit configuration comprises a regular gate and a plurality of logic key gates that define the randomized logic encryption, wherein the randomized logic encryption is defined as being enabled only when the bits of the key in the register are accurately received by the logic key gate connected to the register, A method wherein the device comprises additively fabricated components, the PUF is included in at least a portion of the components, the additively fabricated components have a device-specific microstructure that gives rise to device-specific characteristics, and the response of the PUF depends on the device-specific characteristics.

9. A step of generating the response of the PUF based on the challenge, and The method further includes one or more steps of encrypting the response of the PUF using the key as the encryption key and providing the result as the data element, The method according to claim 8, wherein the data element is decoded using the response of the PUF as a decryption key.

10. A computer program comprising program code for performing the method described in claim 8 by being executed on a processing unit.

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