Semiconductor module and method for manufacturing a semiconductor module

Abstract

To provide a semiconductor module and a method for manufacturing the same that can reduce the effects of parasitic inductance at terminals, and do not require a reduction in the number of required terminals and an increase in the package size compared to common semiconductor modules for the reduction of parasitic inductance effects.SOLUTION: A semiconductor module 1 includes a semiconductor chip 10 having a source electrode 12, a drain electrode (not shown), and a gate electrode 16, a clip 20 having a joint 22 joined to the source electrode 12, a source terminal 24 protruding from the joint 22, and Kelvin source terminals 26, 27 protruding from the joint 22 separately from the source terminal 24, and a sealing resin 50 for sealing the semiconductor chip 10, and the Kelvin source terminals 26 and 27 are also hanging pins that protrude from joint 22 in a different direction from the source terminal 24.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] The present invention relates to a semiconductor module and a method for manufacturing a semiconductor module. Background Art

[0002] In the technical field of power semiconductor modules, there has always been a constant demand for higher current and higher speed. On the other hand, among power semiconductor modules, those using MOSFETs have three types of terminals: a source terminal, a drain terminal, and a gate terminal. With the progress of higher current and higher speed, the influence of parasitic inductance at the source terminal can no longer be ignored. For this reason, semiconductor modules having a Kelvin source terminal in addition to the source terminal have been conventionally known for the purpose of reducing the influence of parasitic inductance (see, for example, Patent Document 1).

[0003] FIG. 17 is a plan view of a conventional semiconductor module 900. As shown in FIG. 17, the conventional semiconductor module 900 includes: a semiconductor chip 910 (MOSFET) having a source electrode 912, a drain electrode (not shown), and a gate electrode 916; a clip 920 (source connector); a die pad frame 930 having a drain terminal 934; a gate clip (gate connector) 940; a source terminal 928; a Kelvin source terminal 929; and a gate terminal 942. The semiconductor module 900 is sealed with a sealing resin (not shown) except for the ends of the respective terminals. The clip 920 has: a chip bonding portion 922 bonded to the source electrode 912; a source terminal bonding portion 924 protruding from the chip bonding portion 922 and bonded to the source terminal 928; and a Kelvin source terminal bonding portion 926 protruding from the chip bonding portion 922 separately from the source terminal bonding portion 924 and bonded to the Kelvin source terminal 929.

[0004] According to the conventional semiconductor module 900, since the Kelvin source terminal 929 is provided, it is possible to reduce the influence of parasitic inductance at the source terminal 928 and suppress the occurrence of malfunction and noise. [Prior art documents] [Patent Documents]

[0005] [Patent Document 1] Japanese Patent Publication No. 2018-63993 [Overview of the project] [Problems that the invention aims to solve]

[0006] However, conventional semiconductor modules 900 have a problem in that, compared to semiconductor modules without a Kelvin source terminal (hereinafter referred to as "general semiconductor modules"), they require a reduction in essential terminals (terminals other than the Kelvin source terminal, especially source terminals) or an increase in package size. For example, it can be said that conventional semiconductor modules 900 use one of the three source terminals 928 in a general semiconductor module as a Kelvin source terminal 929. In other words, compared to a general semiconductor module, the number of source terminals 928 in conventional semiconductor modules 900 is reduced to 2 / 3, so in a simple calculation, the total current capacity of the source terminals 928 is reduced to 2 / 3, and the source wiring resistance increases by 1.5 times. To avoid this, it is conceivable to add a Kelvin source terminal while maintaining the number of source terminals, but in this case, it is often necessary to increase the package size of the semiconductor module by the amount of the increased terminal. This problem has a particularly large impact on small, high-current power semiconductor modules where package size cannot be easily increased.

[0007] Therefore, the present invention has been made to solve the above-mentioned problems, and aims to provide a semiconductor module that can reduce the influence of parasitic inductance at terminals, and that does not require a reduction in the number of terminals or an increase in package size compared to general semiconductor modules in order to reduce the influence of parasitic inductance. Another objective is to provide a method for manufacturing such a semiconductor module. [Means for solving the problem]

[0008] The semiconductor module of the present invention comprises a semiconductor chip having a first electrode, a second electrode, and a third electrode; a clip having a joint joined to the first electrode, a first terminal protruding from the joint, and a second terminal protruding from the joint separately from the first terminal; and a sealing resin for sealing the semiconductor chip, wherein the second terminal is also a suspension pin protruding from the joint in a direction different from that of the first terminal.

[0009] The present invention provides a method for manufacturing a semiconductor module, comprising: a clip placement step of placing a clip, which has a joint and a first terminal protruding from the joint and is fixed to a frame by a suspension pin protruding from the joint in a direction different from the first terminal, on the first electrode side of a semiconductor chip having a first electrode, a second electrode, and a third electrode; a bonding step of bonding the joint and the first electrode; a resin sealing step of sealing the semiconductor chip with a sealing resin; and a second terminal forming step of cutting the suspension pin so that a portion protruding from the sealing resin remains, thereby forming a second terminal protruding from the joint in a direction different from the first terminal. [Effects of the Invention]

[0010] Incidentally, when manufacturing semiconductor modules equipped with clips, a structure called a suspension pin is commonly used (see Embodiment 1 and Figure 7 described later). The suspension pin fixes the clip to a frame-shaped outer frame and is generally formed together with the outer frame and clip from a metal plate. By performing the processes of joining the semiconductor chip and the clip, and the process of resin-encapsulating the semiconductor chip, with the clip fixed to the outer frame by the suspension pin, misalignment, tilting, deformation, etc. of the clip can be suppressed. In general semiconductor module manufacturing methods, after resin encapsulation, the entire portion of the suspension pin that protrudes from the encapsulating resin is cut off. Therefore, the suspension pin remains inside the encapsulating resin of a semiconductor module manufactured using a suspension pin, but this suspension pin serves no electrical function. The inventors of the present invention have found the possibility of effectively utilizing the suspension pin and have completed the present invention.

[0011] According to the semiconductor module of the present invention, the second terminal is also a suspension pin that protrudes from the junction in a different direction from the first terminal, so that suspension pins that have existed but have not been utilized conventionally can be used as the second terminal. As a result, the semiconductor module of the present invention can reduce the effect of parasitic inductance at the terminals, and is a semiconductor module that does not require a reduction in the number of terminals or an increase in package size compared to general semiconductor modules in order to reduce the effect of parasitic inductance.

[0012] The present invention provides a semiconductor module manufacturing method that includes a second terminal formation step in which the suspension pin is cut so that a portion protrudes from the sealing resin, thereby forming a second terminal that protrudes from the joint in a direction different from that of the first terminal. This method makes it possible to reduce the influence of parasitic inductance at the terminals, and to manufacture a semiconductor module that does not require a reduction in the number of terminals or an increase in the package size compared to a typical semiconductor module in order to reduce the influence of parasitic inductance. [Brief explanation of the drawing]

[0013] [Figure 1]It is a perspective view of the semiconductor module 1 according to Embodiment 1. [Figure 2] It is a six-view drawing of the semiconductor module 1 according to Embodiment 1. [Figure 3] It is a plan view shown for explaining the internal structure of the semiconductor module 1 according to Embodiment 1. [Figure 4] It is a six-view drawing of the clip 20 in Embodiment 1. [Figure 5] It is a flowchart of the method for manufacturing the semiconductor module according to Embodiment 1. [Figure 6] It is a view shown for explaining the semiconductor chip placement step S10 in Embodiment 1. [Figure 7] It is a view shown for explaining the clip placement step S20 in Embodiment 1. [Figure 8] It is a view shown for explaining a state where the outer frame F1 is removed after the bonding step S30 in Embodiment 1. [Figure 9] It is a view shown for explaining the resin sealing step S40 in Embodiment 1. [Figure 10] It is a view shown for explaining the Kelvin source terminal formation step S50 (second terminal formation step) in Embodiment 1. [Figure 11] It is a perspective view of the semiconductor module 2 according to Embodiment 2. [Figure 12] It is a six-view drawing of the semiconductor module 2 according to Embodiment 2. [Figure 13] It is a plan view shown for explaining the internal structure of the semiconductor module 2 according to Embodiment 2. [Figure 14] It is a six-view drawing of the clips 20a and 20b in Embodiment 2. [Figure 15] It is a six-view drawing of the semiconductor module 3 according to Modification 1. [Figure 16] It is a six-view drawing of the semiconductor module 4 according to Modification 2. [Figure 17] It is a plan view of a conventional semiconductor module 900. DETAILED DESCRIPTION OF THE INVENTION

[0014] Hereinafter, the semiconductor module and the method for manufacturing a semiconductor module according to the present invention will be described based on each embodiment shown in the drawings. Note that the embodiments described below do not limit the invention according to the claims. In addition, not all of the elements described in each embodiment and combinations thereof are necessarily essential to the solution means of the present invention.

[0015] [Embodiment 1] 1. Semiconductor Module 1 First, the semiconductor module 1 according to Embodiment 1 will be described. Figure 1 is a perspective view of the semiconductor module 1 according to Embodiment 1. Figure 2 is a six-view drawing of the semiconductor module 1 according to Embodiment 1. Figure 2(a) is a front view of the semiconductor module 1, Figure 2(b) is a rear view of the semiconductor module 1, Figure 2(c) is a top plan view of the semiconductor module 1, Figure 2(d) is a bottom view of the semiconductor module 1, Figure 2(e) is a left side view of the semiconductor module 1, and Figure 2(f) is a right side view of the semiconductor module 1. Figure 3 is a top plan view shown for explaining the internal structure of the semiconductor module 1 according to Embodiment 1. In Figure 3, the outer shape of the sealing resin 50 is illustrated by a broken line. Figure 4 is a six-view drawing of the clip 20 in Embodiment 1. Figure 4(a) is a front view of the clip 20, Figure 4(b) is a rear view of the clip 20, Figure 4(c) is a top plan view of the clip 20, Figure 4(d) is a bottom view of the clip 20, Figure 4(e) is a left side view of the clip 20, and Figure 4(f) is a right side view of the clip 20.

[0016] As shown in Figures 1 to 3, the semiconductor module 1 according to Embodiment 1 includes a semiconductor chip 10, a clip 20, a die pad frame 30, a gate clip 40, and a sealing resin 50. Note that, since these are general matters, repeated descriptions and illustrations are omitted, but portions requiring electrical conduction among the respective constituent elements are bonded by a conductive bonding material such as solder.

[0017] The semiconductor chip 10 is a MOSFET. As shown in Figure 3, the semiconductor chip 10 has a source electrode 12 (first electrode), a drain electrode (second electrode) (not shown), and a gate electrode 16 (third electrode).

[0018] As shown in Figures 3 and 4, the clip 20 has a joint 22 joined to the source electrode 12 (first electrode), a source terminal 24 (first terminal) protruding from the joint 22, and Kelvin source terminals 26 and 27 (second terminals) protruding from the joint 22 separately from the source terminal 24 (first terminal). The Kelvin source terminals 26 and 27 (second terminals) are also suspension pins that protrude from the joint 22 in a different direction from the source terminal 24 (first terminal).

[0019] The junction 22 of the clip 20 is the rectangular portion corresponding to the source electrode 12. The source terminal 24 and the Kelvin source terminals 26 and 27 are bent toward the same side (bottom side). There are three source terminals 24 in the semiconductor module 1. When viewed from above, the three source terminals 24 ultimately extend in the same direction (at their ends).

[0020] The cross-sectional area of ​​the Kelvin source terminals 26 and 27 (second terminals) is smaller than the cross-sectional area of ​​source terminal 24 (first terminal). Also, when semiconductor module 1 is viewed from above, the width of the Kelvin source terminals 26 and 27 (second terminals) is narrower than the width of source terminal 24 (first terminal). Note that the comparison for the "cross-sectional area of ​​the Kelvin source terminal (second terminal)" is with the "cross-sectional area of ​​a single source terminal (first terminal)", not the "cross-sectional area of ​​the entire source terminal (first terminal)". The same applies to the width.

[0021] The semiconductor module 1 has Kelvin source terminals 26 and 27 (second terminals), a first Kelvin source terminal 26 (second terminal) that protrudes in a first direction, and a second Kelvin source terminal 27 (second terminal) that protrudes in a second direction opposite to the first direction. When the semiconductor module 1 is viewed from above, the first Kelvin source terminal 26 (second terminal) and the second Kelvin source terminal 27 (second terminal) extend in a direction perpendicular to the direction in which the source terminal 24 (first terminal) ultimately extends. Also, when the semiconductor module 1 is viewed from above, the first Kelvin source terminal 26 (second terminal) and the second Kelvin source terminal 27 (second terminal) are on the same straight line.

[0022] "The direction in which the first terminal ultimately extends" refers to the direction in which the end of the first terminal extends. In the case of semiconductor module 1, where there are multiple first terminals (source terminals 24), the above condition is satisfied if the first second terminal and the second second terminal (Kelvin source terminals 26, 27) extend in a direction perpendicular to the direction in which at least one first terminal ultimately extends.

[0023] As shown in Figure 3, when the semiconductor module 1 is viewed from above, the source terminal 24 (first terminal) and the Kelvin source terminals 26 and 27 (second terminals) protrude from the junction 22, starting from separate sides of the junction 22, separated by a virtual line V that passes through the centroid C of the junction 22 and is perpendicular to the protruding direction of the source terminal 24 (first terminal). In this case, the "centroid of the junction" is a virtual centroid derived from the shape of the junction when viewed from above.

[0024] The die pad frame 30 is a component for mounting the semiconductor chip 10. The die pad frame 30 has a die pad (not shown) and a drain terminal 34 that are joined to the drain electrode of the semiconductor chip 10.

[0025] The gate clip 40 has a gate electrode junction 42 that is joined to the gate electrode 16 and a gate terminal 44 that protrudes from the gate electrode junction 42.

[0026] The sealing resin 50 seals the semiconductor chip 10. As shown in Figures 1 and 2, the source terminal 24, Kelvin source terminals 26 and 27, drain terminal 34, gate terminal 44, and the bottom surface of the die pad frame 30 are exposed from the sealing resin 50. The bottom surface of the die pad frame 30 is exposed from the sealing resin 50 mainly for heat dissipation, and if there is no problem with heat dissipation, the bottom surface of the die pad frame 30 does not necessarily have to be exposed from the sealing resin 50.

[0027] 2. Method for manufacturing semiconductor modules Next, a method for manufacturing a semiconductor module according to Embodiment 1 will be described. Figure 5 is a flowchart of the method for manufacturing a semiconductor module according to Embodiment 1. Figure 6 is a diagram illustrating the semiconductor chip mounting process S10 in Embodiment 1. Figure 6(a) shows the die pad frame 30 fixed to the outer frame F1 via pins FP1, and Figure 6(b) shows the state after the semiconductor chip 10 has been mounted on the die pad frame 30. In order to avoid clutter with the notation of symbols, in Figure 6, the notation for the components related to the semiconductor module 1 is shown only in the upper left corner of the page. The same applies to Figures 7 to 10, which will be described later. Figure 7 is a diagram illustrating the clip placement process S20 in Embodiment 1. Figure 7(a) shows the clip 20 fixed to the outer frame F2 via the suspension pin FP2, and Figure 7(b) shows the state after the clip 20 has been placed on the semiconductor chip 10. Figure 8 is a diagram illustrating the state after the outer frame F1 has been removed following the joining process S30 in Embodiment 1. Figure 9 is a diagram illustrating the resin encapsulation process S40 in Embodiment 1. Figure 10 is a diagram illustrating the Kelvin source terminal formation process S50 (second terminal formation process) in Embodiment 1. Figure 10(a) shows the state immediately after cutting the suspension pin FP2, and Figure 10(b) shows the state in which the suspension pin FP2 has been made into Kelvin source terminals 26 and 27.

[0028] The method for manufacturing a semiconductor module according to Embodiment 1, as shown in Figure 5, includes a semiconductor chip mounting step S10, a clip mounting step S20, a bonding step S30, a resin encapsulation step S40, and a Kelvin source terminal formation step S50 (second terminal formation step). Each step will be described below.

[0029] The semiconductor chip mounting process S10 is a process of mounting a semiconductor chip 10 onto a die pad frame 30. In the semiconductor chip mounting process S10, first, a die pad frame 30 fixed to an outer frame F1 via pins FP1 is prepared (see Figure 6(a)). In Figure 6, nine die pad frames 30 are fixed to one outer frame F1, but this is merely an example. The number of die pad frames 30 fixed to the outer frame F1, that is, the number of semiconductor modules 1 manufactured simultaneously, may be eight or fewer, or ten or more. Also, in Figure 6, four pins FP1 are connected to one die pad frame 30, but this is also an example. The number of pins FP1 connected to a die pad frame 30 may be three or fewer, or five or more.

[0030] Next, a semiconductor chip 10 having a source electrode 12 (first electrode), a drain electrode (second electrode) (not shown), and a gate electrode 16 (third electrode) is placed on the die pad frame 30 via a conductive bonding material or its precursor (e.g., solder paste; not shown) (see Figure 6(b)). This placement is carried out so as to align the die pad of the die pad frame 30 with the drain electrode of the semiconductor chip 10.

[0031] The clip placement step S20 is a step of placing a clip 20, which has a joint portion 22 and a source terminal 24 (first terminal) protruding from the joint portion 22, and is fixed to the outer frame by a suspension pin FP2 that protrudes from the joint portion 22 in a direction different from the source terminal 24 (first terminal), on the source electrode 12 (first electrode) side of the semiconductor chip 10.

[0032] In the clip placement step S20, first, the clips 20 fixed to the outer frame F2 via suspension pins FP2 are prepared (see Figure 7(a)). The number and position of the clips 20 correspond to the number and position of the semiconductor chips 10. Note that the clips 20 prepared in the clip placement step S20 do not need to have the same shape as the final shape of the clips 20 in the semiconductor module 1, and in particular, the shape of the source terminals 24 does not need to be shaped. In this case, shaping of the clips 20 can be performed after the bonding step S30 or the resin encapsulation step S40. Next, the clips 20 are placed on the semiconductor chips 10 via a conductive bonding material or its precursor (e.g., solder paste; not shown) (see Figure 7(b)). This placement is performed so as to align the position of the source electrode 12 of the semiconductor chip 10 with the bonding portion 22 of the clip 20. At this time, by overlapping the outer frame F1 and the outer frame F2, misalignment and tilting of each component can be suppressed.

[0033] Furthermore, in the clip placement process S20, the gate clip 40 is also placed on the semiconductor chip 10. That is, the gate clip 40 is placed on the semiconductor chip 10 via a conductive bonding material or its precursor (for example, solder paste; not shown). This placement is carried out so as to align the gate electrode 16 of the semiconductor chip 10 with the gate electrode junction 42 of the gate clip 40. The gate clip 40 may also be connected to the outer frame F2 via a suspension pin. In this case, the placement of the clip 20 and the gate clip 40 can be carried out simultaneously, and misalignment and tilting of the gate clip 40 can also be suppressed.

[0034] The bonding process S30 is a process of bonding the bonding portion 22 and the source electrode 12 (first electrode). When using a conductive bonding material or its precursor (e.g., solder paste) that melts when heated, this process can be carried out by heating and cooling (reflow). In bonding process S30, the entire component that will become the semiconductor module 1 is heated and cooled, thereby simultaneously bonding the semiconductor chip 10 to the die pad frame 30 (bonding the drain electrode to the die pad) and bonding the semiconductor chip 10 to the gate clip 40 (bonding the gate electrode 16 to the gate electrode bonding portion 42). After that, the pin FP1 is cut from the base on the die pad frame 30 side and the outer frame F1 is removed (see Figure 8).

[0035] The resin encapsulation process S40 is a process of encapsulating the semiconductor chip 10 with encapsulation resin 50. In the resin encapsulation process S40, resin encapsulation is performed so that the source terminal 24, Kelvin source terminals 26, 27, drain terminal 34, gate terminal 44, and the bottom surface of the die pad frame 30 are exposed from the encapsulation resin 50 (see Figure 9). The resin encapsulation process S40 can be carried out, for example, by setting each component together with the suspension pins FP2 in a mold of a predetermined shape (not shown), pouring the encapsulation resin 50 into the mold, and curing it.

[0036] The Kelvin source terminal formation process S50 (second terminal formation process) is a process in which the suspension pin FP2 is cut so that a portion protruding from the sealing resin 50 remains, thereby forming Kelvin source terminals 26 and 27 (second terminals) that protrude from the joint portion 22 in a direction different from the source terminal 24 (first terminal). The outer frame F2 is removed after the suspension pin FP2 is cut (see Figure 10(a)). The cut suspension pin FP2 becomes the Kelvin source terminals 26 and 27 by performing appropriate bending or other processing (see Figure 10(b)). In Embodiment 1, the semiconductor module 1 is completed by performing the Kelvin source terminal formation process S50.

[0037] 3. Effects of the semiconductor module 1 and the method for manufacturing the semiconductor module according to Embodiment 1 According to the semiconductor module 1 of Embodiment 1, the Kelvin source terminals 26 and 27 (second terminals) are also suspension pins that protrude from the junction 22 in a different direction from the source terminal 24 (first terminal). Therefore, suspension pins that have existed but not been utilized conventionally can be used as Kelvin source terminals 26 and 27 (second terminals). As a result, the semiconductor module 1 of Embodiment 1 can reduce the influence of parasitic inductance at the terminals, and is a semiconductor module that does not require a reduction in the number of terminals or an increase in package size compared to general semiconductor modules in order to reduce the influence of parasitic inductance.

[0038] Furthermore, according to the semiconductor module 1 of Embodiment 1, the cross-sectional area of ​​the Kelvin source terminals 26 and 27 (second terminal) is smaller than the cross-sectional area of ​​the source terminal 24 (first terminal), making it possible to set an appropriate cross-sectional area for the Kelvin source terminals 26 and 27, which do not require the same current capacity as the source terminal 24.

[0039] Furthermore, according to the semiconductor module 1 of Embodiment 1, when viewed from above, the width of the Kelvin source terminals 26 and 27 (second terminals) is narrower than the width of the source terminal 24 (first terminal). Therefore, it is possible to set the width of the Kelvin source terminals 26 and 27, which do not require the same current capacity as the source terminal 24, to an appropriate level.

[0040] Furthermore, according to the semiconductor module 1 of Embodiment 1, since it has a first Kelvin source terminal 26 (second terminal) that protrudes in a first direction and a second Kelvin source terminal 27 (second terminal) that protrudes in a second direction opposite to the first direction, it is possible to use Kelvin source terminals 26 and 27 that directly utilize the protruding direction preferred for suspension pins.

[0041] Furthermore, according to the semiconductor module 1 of Embodiment 1, when viewed from above, the first Kelvin source terminal 26 (second terminal) and the second Kelvin source terminal 27 (second terminal) extend in a direction perpendicular to the direction in which the source terminal 24 (first terminal) ultimately extends. Therefore, it is possible to use Kelvin source terminals 26 and 27 that utilize the extension direction of the suspension pin which is preferable for balance.

[0042] Furthermore, according to the semiconductor module 1 of Embodiment 1, when viewed from above, the first Kelvin source terminal 26 (second terminal) and the second Kelvin source terminal 27 (second terminal) are on the same straight line, making it possible to use Kelvin source terminals 26 and 27 that utilize the protruding direction of the suspension pin, which is even more favorable in terms of balance.

[0043] Furthermore, according to the semiconductor module 1 of Embodiment 1, when viewed from above, the source terminal 24 (first terminal) and the Kelvin source terminals 26, 27 (second terminals) protrude from the joint 22 starting from separate sides of the joint 22, which are separated by an imaginary line V that passes through the centroid C of the joint 22 and is perpendicular to the protruding direction of the source terminal 24 (first terminal). Therefore, it is possible to have a sufficient distance between the starting point of the source terminal 24 and the starting points of the Kelvin source terminals 26, 27.

[0044] The semiconductor module manufacturing method according to Embodiment 1 includes a Kelvin source terminal forming step S50 (second terminal forming step) in which the suspension pin FP2 is cut so that a portion protruding from the sealing resin 50 remains, thereby forming Kelvin source terminals 26 and 27 (second terminals) that protrude from the joint in a direction different from the source terminal 24 (first terminal). Therefore, it is possible to reduce the influence of parasitic inductance at the terminals, and the semiconductor module manufacturing method makes it possible to manufacture a semiconductor module that does not require a reduction in the number of terminals or an increase in the package size compared to a general semiconductor module in order to reduce the influence of parasitic inductance.

[0045] [Embodiment 2] Figure 11 is a perspective view of the semiconductor module 2 according to Embodiment 2. Figure 12 is a six-view drawing of the semiconductor module 2 according to Embodiment 2. Figure 12(a) is a front view of the semiconductor module 2, Figure 12(b) is a rear view of the semiconductor module 2, Figure 12(c) is a top view of the semiconductor module 2, Figure 12(d) is a bottom view of the semiconductor module 2, Figure 12(e) is a left side view of the semiconductor module 2, and Figure 12(f) is a right side view of the semiconductor module 2. Figure 13 is a plan view illustrating the internal structure of the semiconductor module 2 according to Embodiment 2. In Figure 13, the external shape of the encapsulating resin 50 is shown with a dashed line. Figure 14 is a six-view drawing of clips 20a and 20b in Embodiment 2. Figure 14(a) is a front view of clips 20a and 20b, Figure 14(b) is a rear view of clips 20a and 20b, Figure 14(c) is a top view of clips 20a and 20b, Figure 14(d) is a bottom view of clips 20a and 20b, Figure 14(e) is a left side view of clip 20a, Figure 14(f) is a right side view of clip 20a, Figure 14(g) is a left side view of clip 20b, and Figure 14(h) is a right side view of clip 20b.

[0046] The semiconductor module 2 according to Embodiment 2 has basically the same configuration as the semiconductor module 2 according to Embodiment 1, but differs from the semiconductor module 1 according to Embodiment 1 in that it has two of each component other than the encapsulating resin. The differences between semiconductor module 2 and semiconductor module 1 will be explained below.

[0047] As shown in Figures 11 to 13, the semiconductor module 2 according to Embodiment 2 comprises semiconductor chips 10a and 10b, clips 20a and 20b, die pad frames 30a and 30b, gate clips 40a and 40b, and sealing resin 50. The sealing resin 50 is the same as the sealing resin 50 in Embodiment 1, so its description is omitted.

[0048] As shown in Figure 13, semiconductor chip 10a has a source electrode 12a (first electrode), a drain electrode (second electrode) (not shown), and a gate electrode 16a (third electrode). Semiconductor chip 10b has a source electrode 12b (first electrode), a drain electrode (second electrode) (not shown), and a gate electrode 16b (third electrode).

[0049] Clip 20a has a joint 22a, a source terminal 24a (first terminal), and a Kelvin source terminal 26a (second terminal), as shown in Figures 13 and 14. Clip 20b has a joint 22b, a source terminal 24b (first terminal), and a Kelvin source terminal 26b (second terminal). The Kelvin source terminals 26a and 26b (second terminals) are also suspension pins that protrude from the joints 22a and 22b in directions different from the source terminals 24a and 24b (first terminals).

[0050] The die pad frames 30a and 30b are components for mounting semiconductor chips 10a and 10b, respectively. Each die pad frame 30a and 30b has a die pad (not shown) and drain terminals 34a and 34b, respectively, which are joined to the drain electrodes of the semiconductor chips 10a and 10b.

[0051] Each gate clip 40a, 40b has gate joint portions 42a, 42b connected to gate electrodes 16a, 16b, and gate terminals 44a, 44b protruding from the gate joint portions 42a, 42b, respectively.

[0052] Although not shown in the illustrations and detailed explanation, the semiconductor module 2 according to Embodiment 2 can be manufactured by a method basically the same as that used for manufacturing the semiconductor module according to Embodiment 1 (i.e., a manufacturing method using clips fixed to the outer frame by suspension pins).

[0053] The semiconductor module 2 according to Embodiment 2 differs from the semiconductor module 1 according to Embodiment 1 in that it has two components other than the sealing resin. However, according to the semiconductor module 2 according to Embodiment 2, the Kelvin source terminals 26a and 26b (second terminals) are also suspension pins that protrude from the junctions 22a and 22b in a different direction from the source terminals 24a and 24b (first terminals). Therefore, suspension pins that have existed but not been utilized conventionally can be utilized as Kelvin source terminals 26a and 26b (second terminals). As a result, the semiconductor module 2 according to Embodiment 2, like the semiconductor module 1 according to Embodiment 1, can reduce the effect of parasitic inductance at the terminals, and is a semiconductor module that does not require a reduction in the number of terminals or an increase in package size compared to a general semiconductor module in order to reduce the effect of parasitic inductance.

[0054] Furthermore, the semiconductor module 2 according to Embodiment 2 also has the other effects of the semiconductor module 1 according to Embodiment 1.

[0055] Although the present invention has been described above based on the embodiments described above, the present invention is not limited to the embodiments described above. It can be implemented in various forms without departing from the spirit of the invention, and for example, the following modifications are also possible.

[0056] (1) The shapes, positions, sizes, etc. described in each of the above embodiments (including the modifications described later) are illustrative examples and can be changed within the scope that does not impair the effects of the present invention.

[0057] (2) In each of the above embodiments, the cross-sectional areas of the Kelvin source terminals 26, 27, 26a, 26b (second terminals) are smaller than the cross-sectional areas of the source terminals 24, 24a, 24b (first terminals), but the present invention is not limited thereto. The cross-sectional area of ​​the Kelvin source terminal (second terminal) may be the same as the cross-sectional area of ​​the source terminal (first terminal).

[0058] (3) In each of the above embodiments, the widths of the Kelvin source terminals 26, 27, 26a, 26b (second terminals) are narrower than the widths of the source terminals 24, 24a, 24b (first terminals), but the present invention is not limited thereto. The width of the Kelvin source terminal (second terminal) may be the same as the width of the source terminal (first terminal).

[0059] (4) In each of the above embodiments, the number of suspension pins (Kelvin source terminals 26, 27, 26a, 26b) was two per semiconductor module, but the present invention is not limited thereto. There is only one suspension pin (Kelvin source terminal) per clip, and any number can be used depending on the manufacturing method and other considerations. If there are two or more suspension pins on a single clip, it is not necessary to make all of them second terminals. Suspension pins that are not used as second terminals may be removed without being made into terminals.

[0060] (5) In each of the above embodiments, the Kelvin source terminals 26, 27, 26a, and 26b were bent to the same side as the source terminals 24, 24a, and 24b, but the present invention is not limited thereto. Figure 15 is a six-view drawing of a semiconductor module 3 according to Modification 1. Figure 15(a) is a front view, Figure 15(b) is a rear view, Figure 15(c) is a top view, Figure 15(d) is a bottom view, Figure 15(e) is a left side view, and Figure 15(f) is a right side view. The direction in which the second terminals (Kelvin source terminals) are bent can be any direction depending on the application of the chip, etc. For example, as shown in Figure 15, the second terminals (Kelvin source terminals 26c, 27c) may be bent to the opposite side from the first terminal (source terminal 24).

[0061] (6) In the semiconductor modules 1 and 2 according to the above embodiments, the source terminals 24, 24a, 24b, Kelvin source terminals 26, 27, 26a, 26b, drain terminals 34, 34a, 34b, gate terminals 44, 44a, 44b, and the bottom surfaces of the die pad frames 30, 30a, 30b are exposed from the sealing resin 50, but the present invention is not limited thereto. Figure 16 is a six-view drawing of a semiconductor module 4 according to Modification 2. Figure 16(a) is a front view, Figure 16(b) is a rear view, Figure 16(c) is a top view, Figure 16(d) is a bottom view, Figure 16(e) is a left side view, and Figure 16(f) is a right side view. In the semiconductor module 4 according to Modification 2, the upper surface (the side opposite to the semiconductor chip side) of the joint portion 22c of the clip 20c is also exposed from the sealing resin 50 for the purpose of further heat dissipation. Since the junction 22c in the semiconductor module 4 is thicker than the junction 22 in Embodiment 1, it becomes exposed from the sealing resin 50. The present invention is also applicable to such semiconductor modules.

[0062] (7) In each of the above embodiments, the semiconductor chips 10, 10a, and 10b were MOSFETs, but the present invention is not limited thereto. The present invention can also be applied to semiconductor modules that include three-terminal semiconductor chips other than MOSFETs (for example, IGBTs).

[0063] (8) The method for manufacturing a semiconductor module according to Embodiment 1 above includes the semiconductor chip mounting step S10 described above, but the present invention is not limited thereto. For example, the preparation of a die pad frame 30 fixed to an outer frame F1 via pins FP1 is illustrative, and a die pad frame not fixed to an outer frame may be prepared. Also, depending on the configuration of the semiconductor module to be manufactured, it may not be necessary to perform the semiconductor chip mounting step described above. [Explanation of symbols]

[0064] 1,2,3,4…Semiconductor module, 10,10a,10b…Semiconductor chip, 12,12a,12b…Source electrode, 16,16a,16b…Gate electrode, 20,20a,20b…Clip, 22,22a,22b…Junction, 24,24a,24b…Source terminal, 26,26a,26b,26c,27,27c…Kelvin source terminal, 30,30a,30b…Die pad frame, 34,34a,34b…Drain terminal, 40,40a,40b…Gate clip, 42,42a,42b…Gate electrode junction, 44,44a,44b…Gate terminal, 50,50a…Sealing resin, C…Center of gravity of junction, F1,F2…Outer frame, FP1…Pin, FP2…Suspension pin, V…Dummy line

Claims

1. A semiconductor chip having a first electrode, a second electrode, and a third electrode, A clip having a joint portion joined to the first electrode, a first terminal protruding from the joint portion, and a second terminal protruding from the joint portion separately from the first terminal, The semiconductor chip is enclosed in a sealing resin, The second terminal is also a suspension pin that protrudes from the joint in a direction different from that of the first terminal. The joint portion and the first terminal of the clip are integrated, A semiconductor module characterized in that the first electrode is a source electrode or an emitter electrode.

2. The semiconductor module according to claim 1, characterized in that the cross-sectional area of ​​the second terminal is the same as or smaller than the cross-sectional area of ​​the first terminal.

3. The semiconductor module according to claim 2, characterized in that, when viewed from above, the width of the second terminal is the same as or narrower than the width of the first terminal.

4. The semiconductor module according to any one of claims 1 to 3, characterized in that the second terminal includes a first second terminal protruding in a first direction and a second second terminal protruding in a second direction opposite to the first direction.

5. The semiconductor module according to claim 4, characterized in that, when viewed from above, the first second terminal and the second second terminal extend in a direction perpendicular to the direction in which the first terminal ultimately extends.

6. The semiconductor module according to claim 4, characterized in that, when viewed from above, the first second terminal and the second second terminal are on the same straight line.

7. The semiconductor module according to any one of claims 1 to 3, characterized in that, when viewed from above, the first terminal and the second terminal protrude from the joint starting from separate sides of the joint separated by an imaginary line that passes through the centroid of the joint and is perpendicular to the protrusion direction of the first terminal.

8. A clip placement step involves placing a clip, which has a joint and a first terminal protruding from the joint and is fixed to the outer frame by a suspension pin protruding from the joint in a direction different from that of the first terminal, on the first electrode side of a semiconductor chip having a first electrode, a second electrode, and a third electrode. A bonding step of bonding the joint portion and the first electrode, A resin encapsulation step in which the semiconductor chip is sealed with a sealing resin, The process includes a second terminal forming step, in which the suspension pin is cut so that a portion protruding from the sealing resin remains, thereby forming a second terminal that protrudes from the joint in a direction different from that of the first terminal, The joint portion and the first terminal of the clip are integrated, A method for manufacturing a semiconductor module, characterized in that the first electrode is a source electrode or an emitter electrode.

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