Semiconductor equipment

Abstract

To provide a semiconductor device capable of enhancing breakdown resistance compared with the conventional semiconductor device.SOLUTION: A semiconductor device 1 comprises a semiconductor base substance 10, a first electrode 20, and an insulating layer 30. The semiconductor base substance 10 has: a first semiconductor region 12 of a first conductivity type (an n-type); a second semiconductor region 16 of a second conductivity type (a p-type) formed at a position where the same is in contact with the first electrode 20 and the insulating layer 30; and a third semiconductor region 18 of the first conductivity type (the n-type) formed in contact with the second semiconductor region 16 so as to surround the second semiconductor region 16 when viewed in a planar manner. In the semiconductor device 1, when an impurity total sum of the second semiconductor region 16 is defined as S1 and an impurity total sum of the third semiconductor region 18 is defined as S2, a relation of S1<S2 is satisfied. A combination of the second semiconductor region 16 and the third semiconductor region 18 has a function of a Zener diode.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] This invention relates to a semiconductor device. [Background technology]

[0002] Conventionally, semiconductor devices with so-called guard rings formed on them for the purpose of increasing their voltage resistance are known (see, for example, Patent Document 1).

[0003] Figure 4 is a diagram illustrating a conventional semiconductor device 900. Figure 4(a) is a plan view of the semiconductor device 900, and Figure 4(b) is a cross-sectional view of AA in Figure 4(a). Figure 4(b) can also be described as a cross-sectional view of corner C in the semiconductor device 900. In Figure 4(a), the first electrode 920, insulating layer 930, and field plate 940, which are located on the first main surface of the semiconductor substrate 910, are not shown in order to display the shape of the first semiconductor region 912 and guard ring 916 as seen in plan.

[0004] A conventional semiconductor device 900, as shown in Figure 4, comprises a semiconductor substrate 910, a first electrode 920 located on the first main surface of the semiconductor substrate 910, an insulating layer 930 located on the first main surface so as to surround the first electrode 920 when viewed in plan, a field plate 940 connected to the first electrode 920 and located on the insulating layer 930, and a second electrode 950 located on the second main surface opposite to the first main surface. The semiconductor substrate 910 has an n-type first semiconductor region 912(n - Semiconductor region 913 and n ++ A type semiconductor region 914), a p-type guard ring 916, and an n-type semiconductor region located on the outer end side, separated from the guard ring 916. + It has a channel stopper 918 of a certain type. In conventional semiconductor devices 900, it is common practice to make the outer edge of the corner portion C of the guard ring 916 arc-shaped when viewed in plan (see Figure 4(a)). [Prior art documents] [Patent Documents]

[0005] [Patent Document 1] Japanese Unexamined Patent Publication No. Hei 5-75100 [Summary of the Invention] [Problem to be Solved by the Invention]

[0006] In a conventional semiconductor device 900, there has been a problem that a contact edge E (a location near the boundary between a first electrode 920 and an insulating layer 930 on a semiconductor substrate 910) tends to be easily broken during reverse bias, and it is difficult to increase the breakdown resistance.

[0007] Accordingly, the present invention has been made to solve the above problem, and an object of the present invention is to provide a semiconductor device capable of having higher breakdown resistance than conventional semiconductor devices. [Means for Solving the Problem]

[0008] The semiconductor device of the present invention comprises: a semiconductor substrate; a first electrode disposed on a first main surface of the semiconductor substrate; and an insulating layer disposed on the first main surface so as to surround the first electrode in plan view. The semiconductor substrate has a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type formed at a position in contact with the first electrode and the insulating layer, and a third semiconductor region of the first conductivity type formed in contact with the second semiconductor region so as to surround the second semiconductor region in plan view. When the total amount of impurities in the second semiconductor region is defined as S1, and the total amount of impurities in the third semiconductor region is defined as S2, the relationship S1 < S2 is satisfied, and the combination of the second semiconductor region and the third semiconductor region functions as a Zener diode. [Effect of the Invention]

[0009] According to the semiconductor device of the present invention, the semiconductor base includes a third semiconductor region of a first conductivity type formed in contact with the second semiconductor region so as to surround the second semiconductor region in plan view. When the total sum of impurities in the second semiconductor region is defined as S1 and the total sum of impurities in the third semiconductor region is defined as S2, the relationship S1 < S2 is satisfied, and the combination of the second semiconductor region and the third semiconductor region functions as a Zener diode. Therefore, during reverse bias, the electric field intensity between the second semiconductor region and the third semiconductor region is made higher than that near the contact edge, and avalanche breakdown can be caused to occur between the second semiconductor region and the third semiconductor region before the vicinity of the contact edge is destroyed. As a result, the semiconductor device of the present invention can achieve higher breakdown resistance than conventional semiconductor devices. [BRIEF DESCRIPTION OF THE DRAWINGS]

[0010] [Figure 1] It is a diagram shown for explaining the semiconductor device 1 according to the first embodiment. [Figure 2] It is a diagram shown for explaining the semiconductor device 2 according to the second embodiment. [Figure 3] It is a diagram shown for explaining how a depletion layer extends at a corner portion of a semiconductor device. [Figure 4] It is a diagram shown for explaining a conventional semiconductor device 900. [MODE FOR CARRYING OUT THE INVENTION]

[0011] Hereinafter, the semiconductor device of the present invention will be described based on each embodiment shown in the drawings. It should be noted that the embodiments described below do not limit the invention according to the claims. In addition, not all of the elements and combinations thereof described in the embodiments are necessarily essential to the solution of the present invention.

[0012] [First Embodiment] FIG. 1 is a diagram provided to explain the semiconductor device 1 according to the first embodiment. FIG. 1(a) is a plan view of the semiconductor device 1, and FIG. 1(b) is a cross-sectional view taken along line A1-A1 of FIG. 1(a). It can also be said that FIG. 1(b) is a cross-sectional view of a corner portion C1 in the semiconductor device 1. In FIG. 1(a), in order to show the planar shapes of the first semiconductor region 12, the second semiconductor region 16, and the third semiconductor region 18, the first electrode 20, the insulating layer 30, and the field plate 40 disposed on the first main surface of the semiconductor substrate 10 are not illustrated.

[0013] As shown in FIG. 1, the semiconductor device 1 according to the first embodiment includes a semiconductor substrate 10, a first electrode 20 disposed on a first main surface of the semiconductor substrate 10, an insulating layer 30 disposed on the first main surface so as to surround the first electrode 20 in plan view, a field plate 40 connected to the first electrode 20 and disposed on the insulating layer 30, and a second electrode 50 disposed on a second main surface of the semiconductor substrate 10 opposite to the first main surface. Note that the semiconductor device 1 shown in FIG. 1 may further include components other than those described above. The semiconductor device 1 is a Schottky barrier diode.

[0014] The semiconductor substrate 10 includes a first semiconductor region 12 of a first conductivity type (n-type in the first embodiment), a second semiconductor region 16 of a second conductivity type (p-type in the first embodiment), and a third semiconductor region 18 of the first conductivity type (n-type in the first embodiment). Note that the impurity concentration of the third semiconductor region 18 is higher than that of an n - -type semiconductor region 13, which will be described later, and lower than that of an n ++ -type semiconductor region 14, so in FIG. 1, the third semiconductor region 18 is denoted as "n + -" in the figure. In the semiconductor device 1, it can also be said that the second semiconductor region 16 is a guard ring and the third semiconductor region 18 is a channel stopper.

[0015] The first semiconductor region 12 includes an n - -type semiconductor region 13 disposed on the first main surface side and an n ++ -type semiconductor region 14 disposed on the second main surface side. n -The wafer resistivity of the semiconductor region 13 can be, for example, 0.6 to 25 Ω·cm. - The thickness of the semiconductor region 13 can be, for example, 4 to 65 μm. ++ The surface impurity concentration of the semiconductor region 14 is, for example, 1 × 10⁻⁶. 20 m -3 The above can be applied. Also, n ++ The thickness of the semiconductor region 14 can be, for example, 100 to 400 μm.

[0016] The second semiconductor region 16 is formed in a position in contact with the first electrode 20 and the insulating layer 30. In the semiconductor device 1, when viewed in plan, the outer edge of the corner portion C1 of the second semiconductor region 16 (in Figure 1(a), only the one in the upper right of the page is indicated by a symbol) has an arc shape. The total impurity of the second semiconductor region 16 is, for example, 3 × 10⁻⁶. 12 ~8×10 12 cm -2 This can be done. Furthermore, the depth of the second semiconductor region 16 can be, for example, 0.4 to 4.0 μm.

[0017] In this specification, "total impurities" refers to the value obtained by integrating the concentration distribution from the surface in the depth direction. While the total impurities are related to the dose (the amount of impurities injected), a proper correlation between pressure resistance and dose may not always be obtained. This is because the amount of impurities can change due to heat treatment, etc.

[0018] The third semiconductor region 18 is formed in contact with the second semiconductor region 16, surrounding it when viewed in plan view. The third semiconductor region 18 extends to the edge of the semiconductor device 1 when viewed in plan view. Furthermore, the third semiconductor region 18 extends deeper than the deepest part of the second semiconductor region 16 from the first main surface. The total impurity content of the third semiconductor region 18 is, for example, 3 × 10⁻¹⁰ 12 ~1 × 10 15 cm -2 This can be done. Furthermore, the depth of the third semiconductor region 18 can be, for example, 0.5 to 5.0 μm.

[0019] In the semiconductor device 1, when S1 represents the total impurity amount of the second semiconductor region 16 and S2 represents the total impurity amount of the third semiconductor region 18, the relationship S1 < S2 is satisfied. In the semiconductor device 1, it is preferable that the relationship 0.15 < (S1 / S2) < 1 is satisfied. In the semiconductor device 1, the combination of the second semiconductor region 16 and the third semiconductor region 18 functions as a Zener diode.

[0020] The term "Zener diode" used in the present specification does not only include devices in which only Zener breakdown occurs at the pn junction surface, but also includes devices in which avalanche breakdown occurs depending on conditions.

[0021] Hereinafter, effects of the semiconductor device 1 according to the first embodiment will be described.

[0022] According to the semiconductor device 1 of the first embodiment, the semiconductor substrate 10 includes: a first semiconductor region 12 of a first conductivity type; a second semiconductor region 16 of a second conductivity type formed at a position in contact with the first electrode 20 and the insulating layer 30; and a third semiconductor region 18 of the first conductivity type formed in contact with the second semiconductor region 16 so as to surround the second semiconductor region 16 in a plan view. When S1 is the total impurity amount of the second semiconductor region 16 and S2 is the total impurity amount of the third semiconductor region 18, the relationship S1 < S2 is satisfied, and the combination of the second semiconductor region 16 and the third semiconductor region 18 functions as a Zener diode. Therefore, during reverse bias, the electric field strength between the second semiconductor region 16 and the third semiconductor region 18 is made higher than that in the vicinity of the contact edge E1, and avalanche breakdown can be caused between the second semiconductor region 16 and the third semiconductor region 18 before the contact edge E1 is broken. As a result, the semiconductor device 1 according to the first embodiment can have higher breakdown resistance than conventional semiconductor devices.

[0023] Further, according to the semiconductor device 1 of the first embodiment, the third semiconductor region 18 is formed from the first main surface to a position deeper than the deepest portion of the second semiconductor region 16, so that sufficient contact between the second semiconductor region 16 and the third semiconductor region 18 can be ensured.

[0024] Furthermore, according to the semiconductor device 1 of Embodiment 1, since the relationship 0.15 < (S1 / S2) < 1 is satisfied, by making the ratio of the total impurity sum S1 in the second semiconductor region 16 to the total impurity sum S2 in the third semiconductor region 18 somewhat large, it is possible to suppress the breakdown voltage drop caused by too few impurities in the second semiconductor region 16.

[0025] Furthermore, the semiconductor device 1 according to Embodiment 1 is a Schottky barrier diode capable of having a higher breakdown resistance than conventional diodes.

[0026] [Embodiment 2] Figure 2 is a diagram illustrating the semiconductor device 2 according to Embodiment 2. Figure 2(a) is a plan view of the semiconductor device 2, and Figure 2(b) is a cross-sectional view taken along line A2-A2 in Figure 2(a). Figure 2(b) can also be described as a cross-sectional view of corner C2 in the semiconductor device 2. In Figure 2(a) as well, the first electrode 20a, insulating layer 30a, and field plate 40a, which are located on the first main surface of the semiconductor substrate 10a, are not shown in order to display the shapes of the first semiconductor region 12a, the second semiconductor region 16a, and the third semiconductor region 18a as seen in plan.

[0027] The semiconductor device 2 according to Embodiment 2 has basically the same configuration as the semiconductor device 1 according to Embodiment 1, but the shape of the outer edge of the second semiconductor region when viewed in plan view is different from that of the semiconductor device 1 according to Embodiment 1. In the semiconductor device 2 according to Embodiment 2, when viewed in plan view, the outer edge of the second semiconductor region 16a is rectangular (square). In other words, when viewed in plan view, the outer edge of the corner portion C2 of the second semiconductor region 16a is angular.

[0028] Here, the phenomenon that occurs when the outer edge of the second semiconductor region 16a is made rectangular will be explained using Figure 3. Figure 3 is a diagram shown to explain how the depletion layer extends at the corner of a semiconductor device. Figure 3(a) is a plan view showing the corner C of a conventional semiconductor device 900, and Figure 3(b) is a lower plan view showing the corner C2 of the semiconductor device 2 according to Embodiment 2. As with Figures 2(a) and 4(a), the first electrode, insulating layer, and field plate arranged on the first main surface of the semiconductor substrate are not shown in Figure 3.

[0029] First, in the conventional semiconductor device 900, as shown in Figure 3(a), when viewed in plan, the outer edge of the corner portion C of the guard ring 916 has an arc shape. Also, the outer edge of the guard ring 916 has a lower impurity concentration than the guard ring 916. - It is in contact with the type semiconductor region 913. Therefore, under reverse bias, the depletion layer extends from the outer boundary of the guard ring 916 to n - The depletion layer tends to extend towards the semiconductor region 913 (outside) (see dashed line D1 in Figure 3(a)). At this time, due to the charge balance, the depletion layer tends to narrow at the point corresponding to 45° of the arc (see point P1 in Figure 3(a)) (see double arrow in Figure 3(a)). For this reason, in conventional semiconductor devices 900, the electric field strength tended to concentrate near this point.

[0030] On the other hand, in the semiconductor device 2 according to Embodiment 2, as shown in Figure 3(b), when viewed in plan, the outer edge of the second semiconductor region 16a (guard ring) has a rectangular shape. Furthermore, the outer edge of the second semiconductor region 16a is in contact with the third semiconductor region 18a, which has a larger total impurity amount (and usually a higher impurity concentration) than the second semiconductor region 16a. For this reason, under reverse bias, the depletion layer tends to extend from the outer boundary of the second semiconductor region 16a toward the second semiconductor region 16a side (inward) (see dashed line D2 in Figure 3(b)). In the case of this shallow junction, due to the charge balance at the interface, the depletion layer tends to spread wider at the vertex of the second semiconductor region 16a (the part corresponding to 45°; see point P2 in Figure 3(b)) (see double arrow in Figure 3(b)). For this reason, in the semiconductor device 2 according to Embodiment 2, it is possible to mitigate the electric field strength near this point.

[0031] In the semiconductor device 1 according to Embodiment 1, the outer edge of the corner portion C1 of the second semiconductor region 16 has an arc shape. However, unlike the conventional semiconductor device 900, the outer edge of the second semiconductor region 16 is in contact with the third semiconductor region 18, which has a larger total impurity sum than the second semiconductor region 16a. In this case, the depletion layer tends to extend from the outer boundary of the second semiconductor region 16 toward the second semiconductor region 16 (inward), and unlike the conventional semiconductor device 900, the expansion of the depletion layer is not inhibited even at the point corresponding to 45° of the arc.

[0032] Furthermore, in semiconductor device 2, the first semiconductor region 12a(n - Outer edge (n - The boundary between the first semiconductor region 13a and the second semiconductor region 16a also has a rectangular shape. Furthermore, since the outer edge of the second semiconductor region 16a is the boundary between the second semiconductor region 16a and the third semiconductor region 18a, the inner edge of the third semiconductor region 18a also has a shape corresponding to the second semiconductor region 16a. Although the plan view is omitted from the illustration, the first electrode 20a, insulating layer 30a, and field plate 40a, which are arranged on the first main surface, also have a shape corresponding to the second semiconductor region 16a (a shape in which the outer edge has a rectangular shape when viewed from above).

[0033] The semiconductor device 2 according to the second embodiment differs from the semiconductor device 1 according to the first embodiment in the shape of the outer edge of the second semiconductor region when viewed in plan view. However, according to the semiconductor device 2, the semiconductor substrate 10a includes a first conductive-type first semiconductor region 12a, a second conductive-type second semiconductor region 16a formed at a position in contact with the first electrode 20a and the insulating layer 30a, and a first conductive-type third semiconductor region 18a formed in contact with the second semiconductor region 16a so as to surround the second semiconductor region 16a when viewed in plan view. When the total sum of impurities in the second semiconductor region 16a is S1 and the total sum of impurities in the third semiconductor region 18a is S2, the relationship S1<S2 is satisfied, and the combination of the second semiconductor region 16a and the third semiconductor region 18a functions as a Zener diode. Therefore, during reverse bias, the electric field strength between the second semiconductor region 16a and the third semiconductor region 18a is made higher than that near the contact edge E2, and avalanche breakdown can be caused to occur between the second semiconductor region 16a and the third semiconductor region 18a before the contact edge E2 is broken. As a result, similar to the semiconductor device 1 according to the first embodiment, the semiconductor device 2 according to the second embodiment is a semiconductor device capable of having higher breakdown tolerance than conventional semiconductor devices.

[0034] Furthermore, according to the semiconductor device 2 according to the second embodiment, when viewed in plan view, the outer edge of the second semiconductor region 16a has a rectangular (square) shape. Therefore, during reverse bias, a depletion layer is more likely to extend from the corner portion of the second semiconductor region 16a, and the electric field strength at the apex of the second semiconductor region 16a (the portion corresponding to 45°) can be relaxed. As a result, in the semiconductor device 2 according to the second embodiment, avalanche breakdown can be more easily caused to occur at the side portions than at the corner portion C2 of the outer edge of the second semiconductor region 16a, and the breakdown tolerance can be further increased.

[0035] Note that the semiconductor device 2 according to the second embodiment also has the effects of the semiconductor device 1 according to the first embodiment other than those described above.

[0036] Although the present invention has been described above based on the embodiments described above, the present invention is not limited to the embodiments described above. It can be implemented in various forms without departing from the spirit of the invention, and for example, the following modifications are also possible.

[0037] (1) The positions, sizes, etc. described in each of the above embodiments (including the following modified examples; the same applies hereinafter) are illustrative and can be changed within the scope that does not impair the effects of the present invention.

[0038] (2) Although the semiconductor devices 1 and 2 in each of the above embodiments were Schottky barrier diodes, the present invention is not limited thereto. The present invention can also be applied to diodes other than Schottky barrier diodes, as well as transistors and thyristors. Furthermore, in each of the above embodiments, the first conductivity type was n-type and the second conductivity type was p-type, but depending on the type of semiconductor device, the first conductivity type may be p-type and the second conductivity type may be n-type.

[0039] (3) In the semiconductor device 2 according to Embodiment 2 described above, the outer edge of the second semiconductor region 16a is square when viewed in plan, but the present invention is not limited thereto. The outer edge of the second semiconductor region may be rectangular. [Explanation of symbols]

[0040] 1,2…Semiconductor device, 10,10a…Semiconductor substrate, 12,12a…First semiconductor region, 13,13a…n - Semiconductor region, 14...n + Type 1 semiconductor region, 16, 16a... Second semiconductor region, 18, 18a... Third semiconductor region, 20, 20a... First electrode, 30, 30a... Insulating layer, 40, 40a... Field plate, 50... Second electrode, C1, C2... Corner section, E1, E2... Contact edge

Claims

1. Semiconductor substrate and, A first electrode is disposed on the first main surface of the semiconductor substrate, The device comprises an insulating layer arranged on the first main surface so as to surround the first electrode when viewed in plan, The semiconductor substrate has a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type formed at a position in contact with the first electrode and the insulating layer, and a third semiconductor region of a first conductivity type formed in contact with the second semiconductor region so as to surround it when viewed in plan, When the sum of impurities in the second semiconductor region is S1 and the sum of impurities in the third semiconductor region is S2, the relationship S1 < S2 is satisfied. The combination of the second semiconductor region and the third semiconductor region has the function of a Zener diode. The semiconductor device is characterized in that the third semiconductor region is formed to a depth greater than the deepest part of the second semiconductor region from the first main surface.

2. The semiconductor device according to claim 1, characterized in that it satisfies the relationship 0.15 < (S1 / S2) < 1.

3. The semiconductor device according to claim 1, characterized in that, when viewed in plan, the outer edge of the second semiconductor region has a rectangular shape.

4. The semiconductor device according to claim 1, characterized in that it is a Schottky barrier diode.

5. A semiconductor substrate and A first electrode is disposed on the first main surface of the semiconductor substrate, The device comprises an insulating layer arranged on the first main surface so as to surround the first electrode when viewed in plan, The semiconductor substrate has a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type formed at a position in contact with the first electrode and the insulating layer, and a third semiconductor region of a first conductivity type formed in contact with the second semiconductor region so as to surround it when viewed in plan, When the sum of impurities in the second semiconductor region is S1 and the sum of impurities in the third semiconductor region is S2, the relationship S1 < S2 is satisfied. The combination of the second semiconductor region and the third semiconductor region has the function of a Zener diode. A semiconductor device characterized in that, when viewed in plan, the outer edge of the second semiconductor region is rectangular in shape, and the outer edge of the corner portion of the second semiconductor region is angular in shape.

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