Semiconductor device and method for manufacturing the same

Abstract

To provide a semiconductor device capable of obtaining stable characteristics and a manufacturing method therefor.SOLUTION: A semiconductor device includes: a first electrode; a second electrode; a third electrode; a semiconductor member; and a first insulating member. A second insulating region of the first insulating member includes a first surface facing a third partial region of a first semiconductor region. A third insulating region of the first insulating member includes a second surface facing the third partial region. The first surface includes a first end on a first electrode side. The second surface includes a second end on a second electrode side. A second position of the second end is different from the first position of the first end.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] Embodiments of the present invention relate to a semiconductor device and a method for manufacturing the same. [Background Art]

[0002] For example, stable characteristics are desired in semiconductor devices. [Prior Art Literature] [Patent Literature]

[0003] [Patent Document 1] Japanese Unexamined Patent Publication No. 2016-72482 [Summary of the Invention] [Problem to be Solved by the Invention]

[0004] Embodiments of the present invention provide a semiconductor device capable of obtaining stable characteristics and a method for manufacturing the same. [Means for Solving the Problem]

[0005] According to embodiments of the present invention, the semiconductor device includes a first electrode, a second electrode, a third electrode, a semiconductor member, a first conductive member, and a first insulating member. The direction from the first electrode to the second electrode is along a first direction. The second electrode includes a first electrode portion and a second electrode portion connected to the first electrode portion. The third electrode is provided between the first electrode and the second electrode portion. The semiconductor member includes a first semiconductor region of a first conductivity type and a second semiconductor region of the first conductivity type. The first semiconductor region includes a first subregion, a second subregion, a third subregion, and a fourth subregion. The first subregion is provided between the first electrode and the third electrode in the first direction. The second direction from the first subregion to the second subregion intersects the first direction. The position of the third subregion in the second direction is between the position of the first subregion in the second direction and the position of the second subregion in the second direction. The fourth subregion is located between the second subregion and the first electrode portion. The impurity concentration of the first conductivity type in the second semiconductor region is higher than the impurity concentration of the first conductivity type in the first semiconductor region. The second semiconductor region is provided between the third electrode and the first electrode portion in the second direction. The second semiconductor region is provided between the third subregion and the second electrode portion in the first direction. The first conductive member is provided between the first subregion and the third electrode in the first direction. The direction from the first conductive member to the fourth subregion is along the second direction. The first conductive member is electrically connected to the second electrode, or can be electrically connected to the second electrode. The first insulating member includes a first insulating region, a second insulating region, and a third insulating region. The first insulating region is provided between the third electrode and the second semiconductor region. The second insulating region is provided between the semiconductor member and the first conductive member. At least a portion of the third insulating region is provided between the first conductive member and the third electrode. The second insulating region includes a first surface facing the third partial region. The third insulating region includes a second surface facing the third partial region. The first surface is in the first direction. 2The first end on the electrode side is included. The second surface is in the first direction. 1 It includes a second end on the electrode side. The second position of the second end in the second direction is different from the first position of the first end in the second direction. [Brief explanation of the drawing]

[0006] [Figure 1] Figure 1 is a schematic cross-sectional view illustrating a semiconductor device according to the first embodiment. [Figure 2] Figure 2 is a schematic cross-sectional view illustrating a part of a semiconductor device according to the first embodiment. [Figure 3] Figures 3(a) to 3(d) are schematic cross-sectional views illustrating a method for manufacturing a semiconductor device according to the second embodiment. [Figure 4] Figures 4(a) to 4(d) are schematic cross-sectional views illustrating a method for manufacturing a semiconductor device according to the second embodiment. [Figure 5] Figures 5(a) to 5(d) are schematic cross-sectional views illustrating a method for manufacturing a semiconductor device according to the second embodiment. [Figure 6] Figures 6(a) to 6(d) are schematic cross-sectional views illustrating a method for manufacturing a semiconductor device according to the second embodiment. [Figure 7] Figures 7(a) to 7(d) are schematic cross-sectional views illustrating a method for manufacturing a semiconductor device according to the second embodiment. [Figure 8] Figures 8(a) and 8(b) are schematic cross-sectional views illustrating a method for manufacturing a semiconductor device according to the second embodiment. [Modes for carrying out the invention]

[0007] Embodiments of the present invention will be described below with reference to the drawings. Drawings are schematic or conceptual, and the relationships between the thickness and width of each part, as well as the ratios of the sizes of different parts, are not necessarily identical to those of reality. Even when representing the same part, the dimensions and ratios may be depicted differently in different drawings. In this specification and in each figure, elements similar to those described above are denoted by the same reference numerals, and detailed explanations are omitted as appropriate.

[0008] (First Embodiment) Figure 1 is a schematic cross-sectional view illustrating a semiconductor device according to the first embodiment. Figure 2 is a schematic cross-sectional view illustrating a part of a semiconductor device according to the first embodiment. As shown in Figure 1, the semiconductor device 110 according to this embodiment includes a first electrode 51, a second electrode 52, a third electrode 53, a semiconductor member 10, a first conductive member 61, and a first insulating member 41.

[0009] The direction from the first electrode 51 to the second electrode 52 is along the first direction D1. The first direction D1 is defined as the Z-axis direction. One direction perpendicular to the Z-axis direction is defined as the X-axis direction. The direction perpendicular to both the Z-axis direction and the X-axis direction is defined as the Y-axis direction.

[0010] For example, the first electrode 51 includes a first electrode surface 51f. The first electrode surface 51f faces the semiconductor member 10. The first electrode surface 51f is substantially parallel to the XY plane. The first direction D1 intersects the first electrode surface 51f.

[0011] The second electrode 52 includes a first electrode portion 52a and a second electrode portion 52b. The second electrode portion 52b is connected to the first electrode portion 52a. The third electrode 53 is provided between the first electrode 51 and the second electrode portion 52b.

[0012] The semiconductor member 10 includes a first semiconductor region 11 and a second semiconductor region 12. The first semiconductor region 11 is a first conductivity type. The first conductivity type is either n-type or p-type. In this example, the first conductivity type is n-type. The semiconductor member 10 includes, for example, silicon.

[0013] The first semiconductor region (11) includes a first partial region (11a), a second partial region (11b), a third partial region (11c), and a fourth partial region (11d). The first partial region (11a) is provided between the first electrode (51) and the third electrode (53) in the first direction D1. The second direction D2 from the first partial region (11a) to the second partial region (11b) intersects the first direction D1. The second direction D2 is, for example, the X-axis direction.

[0014] The position of the third partial region (11c) in the second direction D2 is between the position of the first partial region (11a) in the second direction D2 and the position of the second partial region (11b) in the second direction D2. The fourth partial region (11d) is located between the second partial region (11b) and the first electrode portion (52a). The boundaries between the first partial region (11a), the second partial region (11b), the third partial region (11c), and the fourth partial region (11d) may be indistinct.

[0015] The second semiconductor region (12) is of the first conductivity type. The impurity concentration of the first conductivity type in the second semiconductor region (12) is higher than the impurity concentration of the first conductivity type in the first semiconductor region (11). The first semiconductor region (11) is, for example, n - layer. The second semiconductor region (12) is an n-layer or n + layer.

[0016] The second semiconductor region (12) is provided between the third electrode (53) and the first electrode portion (52a) in the second direction D2. The second semiconductor region (12) is provided between the third partial region (11c) and the second electrode portion (52b) in the first direction D1.

[0017] The first conductive member (61) is provided between the first partial region (11a) and the third electrode (53) in the first direction D1. The direction from the first conductive member (61) to the fourth partial region (11d) is along the second direction D2.

[0018] The first conductive member 61 is electrically connected to the second electrode 52. Alternatively, the first conductive member 61 can be electrically connected to the second electrode 52. For example, a first conductive member terminal 61T and a second electrode terminal 52T may be provided. The first conductive member terminal 61T and the second electrode terminal 52T may be electrically connected by wiring 52L. The wiring 52L may be included in the semiconductor device 110. The wiring 52L may be provided separately from the semiconductor device 110. The first conductive member 61 and the third electrode 53 extend along a third direction D3. The third direction D3 intersects a plane containing the first direction D1 and the second direction D2. The third direction D3 is, for example, the Y-axis direction.

[0019] The first insulating member 41 includes a first insulating region 41a, a second insulating region 41b, and a third insulating region 41c. The first insulating region 41a is provided between the third electrode 53 and the second semiconductor region 12. The second insulating region 41b is provided between the semiconductor member 10 and the first conductive member 61. At least a portion of the third insulating region 41c is provided between the first conductive member 61 and the third electrode 53.

[0020] In the semiconductor device 110, the current between the first electrode 51 and the second electrode 52 may be controlled by the potential of the third electrode 53. The potential of the third electrode 53 may be, for example, a potential referenced to the potential of the second electrode 52. The first electrode 51 functions, for example, as a drain electrode. The second electrode 52 functions, for example, as a source electrode. The third electrode 53 functions, for example, as a gate electrode. The semiconductor device 110 is, for example, a transistor.

[0021] The first conductive member 61 functions, for example, as a field plate. For example, it mitigates the concentration of the electric field. It suppresses the breakdown of the first insulating member 41 and other components caused by the concentration of the electric field. Stable characteristics are easily obtained. High reliability is easily obtained.

[0022] As shown in Figures 1 and 2, in this embodiment, the second insulating region 41b includes the first surface F1. The first surface F1 faces the third partial region 11c. The third insulating region 41c includes the second surface F2. The second surface F2 faces the third partial region 11c. The first surface F1 includes the first end Fe1. The first end Fe1 is the end of the first surface F1 on the second electrode 52 side in the first direction D1. The second surface F2 includes the second end Fe2. The second end Fe2 is the end of the second surface F2 on the first electrode 51 side in the first direction D1.

[0023] For example, if the direction from the first electrode 51 to the second electrode 52 is "upward", then the first end Fe1 is the upper end of the first surface F1, and the second end Fe2 is the lower end of the second surface F2.

[0024] As shown in Figures 1 and 2, the second position of the second end Fe2 in the second direction D2 is different from the first position of the first end Fe1 in the second direction D2. A step 41s is provided between the first end Fe1 and the second end Fe2.

[0025] For example, as shown in Figure 2, the third insulating region 41c further includes a third surface F3. The third surface F3 is located between the first surface F1 and the second surface F2. The third surface F3 connects to the first surface F1 and the second surface F2. The third surface F3 is nonparallel to the first surface F1. The third surface F3 is nonparallel to the second surface F2.

[0026] By providing such a step 41s, the charge balance can be adjusted. For example, it is possible to provide a semiconductor device with stable characteristics.

[0027] As shown in Figure 2, the distance between the first conductive member 61 and the first position along the second direction D2 is defined as the first distance d1. The distance between the first conductive member 61 and the second position along the second direction D2 is defined as the second distance d2. The first distance d1 is shorter than the second distance d2. The first surface F1 is recessed relative to the second surface F2. The second surface F2 is projected relative to the first surface F1.

[0028] As shown in Figure 2, the distance Δd is defined as the distance along the second direction D2 between the first position and the second position. The distance Δd corresponds to the size of the step 41s. For example, the distance Δd may be between 0.3 and 2 times the thickness dx of the first insulating region 41a along the second direction D2.

[0029] As shown in Figure 1, the second semiconductor region 12 is in contact with the first semiconductor region 11. In the semiconductor device 110, a semiconductor region of the second conductivity type does not necessarily have to be provided. For example, the first electrode portion 52a makes Schottky contact with the semiconductor member 10. For example, the first electrode portion 52a is in contact with the second semiconductor region 12 and the fourth portion region 11d. The first electrode portion 52a includes, for example, at least one selected from the group consisting of Pt, Co, and Ni. The first electrode portion 52a includes, for example, a material with a relatively large work function. This provides Schottky contact. The semiconductor device 110 is, for example, a Schottky contact type transistor. The height of the Schottky barrier can be controlled by the potential of the third electrode 53. The current flowing between the first electrode 51 and the second electrode 52 can be controlled by the potential of the third electrode 53.

[0030] As shown in Figure 2, the first electrode portion 52a includes the first electrode portion end 52ae. The first electrode portion end 52ae is the end on the first electrode 51 side in the first direction D1. The first electrode portion end 52ae is the lower end of the first electrode portion 52a. The third electrode 53 includes the third electrode end 53e. The third electrode end 53e is the end on the first electrode 51 side in the first direction D1. The third electrode end 53e is the lower end of the third electrode 53. Preferably, the third electrode end 53e is lower than the first electrode portion end 52ae.

[0031] For example, the position of the third electrode end 53e in the first direction D1 is between the position of the first electrode 51 in the first direction D1 and the position of the first electrode portion end 52ae in the first direction D1. This makes it easier to suppress the deterioration of the gate-drain capacitance Qgd.

[0032] As shown in Figure 2, the width of the third electrode 53 along the second direction D2 is wider than the width of the first conductive member 61 along the second direction D2.

[0033] As shown in Figure 2, the first semiconductor region 11 includes a first semiconductor surface SF1, a second semiconductor surface SF2, a third semiconductor surface SF3, and a fourth semiconductor surface SF4. The third electrode 53 is located between the first semiconductor surface SF1 and the second semiconductor surface SF2 in the second direction D2. A portion of the first insulating member 41 is located between the first semiconductor surface SF1 and the third electrode 53. Another portion of the first insulating member 41 is located between the third electrode 53 and the second semiconductor surface SF2.

[0034] The first electrode portion 52a is located between the third semiconductor surface SF3 and the fourth semiconductor surface SF4 in the second direction D2. The distance along the second direction D2 between the first semiconductor surface SF1 and the second semiconductor surface SF2 is defined as the first width w1. The distance along the second direction D2 between the third semiconductor surface SF3 and the fourth semiconductor surface SF4 is defined as the second width w2. The first width w1 is greater than the second width w2.

[0035] As shown in Figure 2, the first semiconductor region 11 may include a first semiconductor surface SF1, a second semiconductor surface SF2, a fifth semiconductor surface SF5, and a sixth semiconductor surface SF6. The first conductive member 61 is located between the fifth semiconductor surface SF5 and the sixth semiconductor surface SF6 in the second direction D2. A portion of the first insulating member 41 is located between the fifth semiconductor surface SF5 and the first conductive member 61. Another portion of the first insulating member 41 is located between the first conductive member 61 and the sixth semiconductor surface SF6. The distance along the second direction D2 between the fifth semiconductor surface SF5 and the sixth semiconductor surface SF6 is defined as the third width w3. The first width w1 (the distance along the second direction D2 between the first semiconductor surface SF1 and the second semiconductor surface SF2) is greater than the third width w3.

[0036] As shown in Figure 1, the width of the first conductive member 61 along the second direction D2 is continuously changing or constant in the first direction D1. Compared to the case where the first conductive member 61 changes in a step-like manner, the concentration of the electric field can be suppressed more effectively.

[0037] As shown in Figure 2, the width of the second semiconductor region 12 along the second direction D2 is defined as the second semiconductor region width 12w. In this embodiment, the second semiconductor region width 12w is, for example, 25 nm or more and 50 nm or less.

[0038] As shown in Figure 1, the semiconductor device 110 may further include a second insulating member 42. At least a portion of the second insulating member 42 is provided between the third electrode 53 and the second electrode portion 52b.

[0039] (Second Embodiment) The second embodiment relates to a method for manufacturing a semiconductor device. Figures 3(a) to 3(d), 4(a) to 4(d), 5(a) to 5(d), 6(a) to 6(d), 7(a) to 7(d), 8(a) and 8(b) are schematic cross-sectional views illustrating a method for manufacturing a semiconductor device according to the second embodiment.

[0040] As shown in Figure 3(a), a first semiconductor region 11 of the first conductivity type is prepared. The first semiconductor region 11 is, for example, a silicon layer. A mask film 79 is formed on the first semiconductor region 11. The mask film 79 is, for example, SiN x A membrane is sufficient. The upper surface of the mask membrane 79 aligns with the XY plane. The direction perpendicular to the upper surface of the mask membrane 79 is defined as the first direction D1.

[0041] A resist film 77 having the desired pattern shape is formed on the mask film 79. A carbon film 78 may be provided between the mask film 79 and the resist film 77. The carbon film 78 may be provided or omitted as needed. The carbon film 78 is processed using the resist film 77 as a mask. The mask film 79 is processed using the carbon film 78 as a mask. This gives the mask film 79 the desired pattern shape.

[0042] As shown in Figure 3(b), a mask film 79 is used as a mask to form a first trench 91 and a second trench 92 in the first semiconductor region 11 at once. For example, these trenches are formed by RIE (Reactive Ion Etching). The width of the first trench 91 is wider than the width of the second trench 92. These widths are based on the pattern shape of the mask film 79. In the wider first trench 91, the first semiconductor region 11 is removed more efficiently than in the narrower second trench 92. As a result, the depth of the first trench 91 is greater than the depth of the second trench 92. The direction from the first trench 91 to the second trench 92 corresponds to the second direction D2. These trenches are aligned with the third direction D3. The width is, for example, the length aligned with the second direction D2. The depth is the length aligned with the first direction D1.

[0043] As shown in Figure 3(c), the first insulating film 81 is formed in the first trench 91 and the second trench 92. The first insulating film 81 is made of, for example, SiN x That's fine. The first insulating film 81 includes a first insulating portion 81a, a second insulating portion 81b, and a third insulating portion 81c. The first insulating portion 81a is provided at the bottom of the first trench 91. The second insulating portion 81b is provided on the side wall of the first trench 91. A space is left inside the first trench 91. The third insulating portion 81c is provided in the second trench 92. The second trench 92 is substantially closed by the third insulating portion 81c.

[0044] As shown in Figure 3(d), the first insulating portion 81a is removed to expose a part of the first semiconductor region 11. The removal is performed, for example, by RIE. At this time, at least a part of the second insulating portion 81b remains. The third insulating portion 81c also remains.

[0045] As shown in Figure 4(a), the above portion of the exposed first semiconductor region 11 is removed to form the third trench 93. The removal is performed, for example, by RIE.

[0046] As shown in Figure 4(b), after the formation of the third trench 93, the remaining second insulating portion 81b is removed. As shown in Figure 4(b), a step is formed between the side wall of the first trench 91 and the side wall of the third trench 93. The size of the step is based on the thickness of the remaining second insulating portion 81b. In this way, the removal of the second insulating portion 81b creates a step between the side surface of the first trench 91 and the side surface of the third trench 93.

[0047] As shown in Figure 4(c), a second insulating film 82 is formed inside the first trench 91 and the third trench 93. The second insulating film 82 may be, for example, SiO2.

[0048] As shown in Figure 4(d), the first conductive material 65a is introduced into the third trench 93. The first conductive material 65a may be, for example, polysilicon. The first conductive material 65a may also be formed in parts other than the inside of the trench.

[0049] As shown in Figure 5(a), the portion of the first conductive material 65a excluding the portion inside the third trench 93 is removed. This forms the first conductive member 61. In this way, the first conductive material 65a is introduced into the third trench 93 to form the first conductive member 61. A space remains inside the first trench 91.

[0050] As described later, after the formation of the first conductive member 61, a third electrode 53 is formed on the first conductive member 61. Furthermore, after removing the third insulating portion 81c, a second conductive material 65b is introduced into the second trench 92 to form the first electrode portion 52a. This allows the semiconductor device 110 to be formed.

[0051] In this embodiment, the third electrode 53 may be formed as follows. As shown in Figure 5(a), after the formation of the first conductive member 61, the first conductive material 65a present in the remaining space of the first trench 91 is removed.

[0052] As shown in Figure 5(b), the third insulating film 83 is embedded on the first conductive member 61 and in the remaining space of the first trench 91. The third insulating film 83 may be, for example, an SiO2 film formed by CVD (Chemical Vapor Deposition). The third insulating film 83 may be, for example, a BPSG (Boro-Phospho Silicate Glass) film. For example, the etching rate of the third insulating film 83 for wet etching may be substantially the same as the etching rate of SiO2 for wet etching.

[0053] As shown in Figure 5(c), the third insulating film 83 is planarized. If the third insulating film 83 is a BPSG film, the planarization step may be omitted.

[0054] As shown in Figure 5(d), the third insulating film 83 is wet-etched to remove the remaining portion of the third insulating film 83 while leaving the portion located at the bottom of the first trench 91. In this etching process, the upper portion of the second insulating film 82 (the portion close to the opening of the first trench 91) is removed. In this way, a portion of the third insulating film 83 inside the first trench 91 is removed, while another portion of the third insulating film 83 remains inside the first trench 91.

[0055] As shown in Figure 6(a), a fourth insulating film 84 is formed on the side wall of the first trench 91. The fourth insulating film 84 is formed, for example, by thermal oxidation of silicon. The fourth insulating film 84 becomes, for example, the first insulating region 41a.

[0056] As shown in Figure 6(b), a third conductive material 65c is introduced into the remaining space of the first trench 91 after the formation of the fourth insulating film 84. The third conductive material 65c may be, for example, polysilicon.

[0057] As shown in Figure 6(c), the unnecessary portion of the third conductive material 65c is removed. The remaining third conductive material 65c forms the third electrode 53. In the state shown in Figure 6(c), a mask film 79 exists on the first semiconductor region 11.

[0058] As shown in Figure 6(d), the mask film 79 is removed.

[0059] As shown in Figure 7(a), for example, the fifth insulating film 85 is formed from the upper portion of the third electrode 53 and the upper portion of the first semiconductor region. For example, the fifth insulating film 85 is formed by thermal oxidation.

[0060] As shown in Figure 7(b), a first conductivity type impurity is introduced to the surface portion of the first semiconductor region 11 via the fifth insulating film 85 to form the second semiconductor region 12.

[0061] Subsequently, the first electrode portion 52a is formed in the second trench 92. The first electrode portion 52a may be formed, for example, as follows.

[0062] As shown in Figure 7(c), a sixth insulating film 86 is formed on the fifth insulating film 85. The sixth insulating film 86 may be, for example, an SiO2 film. The sixth insulating film 86 becomes at least a part of the second insulating member 42.

[0063] As shown in Figure 7(d), an opening 86o is formed in the sixth insulating film 86. The third insulating portion 81c, which is located inside the second trench 92, is exposed at the opening 86o.

[0064] As shown in Figure 8(a), the third insulating portion 81c is removed. Removal of the third insulating portion 81c exposes the bottom and side walls of the second trench 92.

[0065] As shown in Figure 8(b), the second conductive material 65b is introduced into the space within the second trench 92. The introduced second conductive material 65b forms the first electrode portion 52a. The remaining portion of the second conductive material 65b forms the second electrode portion 52b. This forms the second electrode 52.

[0066] Subsequently, the first electrode 51 is formed on the lower surface of the first semiconductor region 11. In this way, the semiconductor device 110 is obtained.

[0067] In the semiconductor device manufacturing method according to this embodiment, the first trench 91 and the second trench 92 are formed in one step using one mask. If these trenches are formed in separate steps, a misalignment of their positions will occur. In this embodiment, this misalignment can be suppressed.

[0068] In this embodiment, fine trenches can be formed with high precision. For example, misalignment between the third electrode 53 and the first electrode portion 52a can be suppressed. This suppresses, for example, a decrease in carrier discharge efficiency caused by misalignment. For example, electrical short circuits are suppressed. For example, more stable characteristics can be obtained. Reliability can be further improved.

[0069] The embodiment may include the following configuration (e.g., proposed technical details). (Composition 1) First electrode and, A second electrode, wherein the direction from the first electrode to the second electrode is along the first direction, and the second electrode includes a first electrode portion and a second electrode portion connected to the first electrode portion, A third electrode is provided between the first electrode and the second electrode portion, A semiconductor component, wherein the semiconductor component is A first semiconductor region of a first conductivity type, wherein the first semiconductor region includes a first subregion, a second subregion, a third subregion and a fourth subregion, the first subregion is provided between the first electrode and the third electrode in the first direction, the second direction from the first subregion to the second subregion intersects the first direction, the position of the third subregion in the second direction is between the position of the first subregion in the second direction and the position of the second subregion in the second direction, and the fourth subregion is between the second subregion and the first electrode portion, and The second semiconductor region of the first conductivity type, wherein the impurity concentration of the first conductivity type in the second semiconductor region is higher than the impurity concentration of the first conductivity type in the first semiconductor region, the second semiconductor region is provided between the third electrode and the first electrode portion in the second direction, and the second semiconductor region is provided between the third portion region and the second electrode portion in the first direction, The semiconductor member including, A first conductive member, wherein the first conductive member is provided between the first partial region and the third electrode in the first direction, the direction from the first conductive member to the fourth partial region is along the second direction, and the first conductive member is electrically connected to the second electrode, or can be electrically connected to the second electrode, A first insulating member comprising a first insulating region, a second insulating region, and a third insulating region, wherein the first insulating region is provided between the third electrode and the second semiconductor region, the second insulating region is provided between the semiconductor member and the first conductive member, at least a portion of the third insulating region is provided between the first conductive member and the third electrode, the second insulating region includes a first surface facing the third partial region, the third insulating region includes a second surface facing the third partial region, and the first surface is in the first direction. 2 The first end on the electrode side is included, and the second surface is in the first direction 1 The first insulating member includes a second end on the electrode side, wherein the second position of the second end in the second direction is different from the first position of the first end in the second direction. A semiconductor device equipped with [the necessary components].

[0070] (Configuration 2) The semiconductor device according to configuration 1, wherein the first distance along the second direction between the first conductive member and the first position is shorter than the second distance along the second direction between the first conductive member and the second position.

[0071] (Composition 3) The semiconductor device according to configuration 1 or 2, wherein the distance along the second direction between the first position and the second position is 0.3 times or more and 2 times or less the thickness of the first insulating region along the second direction.

[0072] (Composition 4) A semiconductor device according to any one of configurations 1 to 3, wherein a step is provided between the first surface and the second surface.

[0073] (Composition 5) The third insulating region further includes a third surface, The semiconductor device according to any one of configurations 1 to 4, wherein the third surface is located between the first surface and the second surface, is connected to the first surface and the second surface, and the third surface is nonparallel to the first surface and nonparallel to the second surface.

[0074] (Composition 6) The second semiconductor region is in contact with the first semiconductor region, and is a semiconductor device according to any one of configurations 1 to 5.

[0075] (Composition 7) The semiconductor device according to any one of configurations 1 to 6, wherein the first electrode portion makes Schottky contact with the semiconductor material.

[0076] (Composition 8) The first electrode portion is in contact with the second semiconductor region and the fourth partial region. The semiconductor device according to any one of configurations 1 to 7, wherein the first electrode portion includes at least one selected from the group consisting of Pt, Co, and Ni.

[0077] (Composition 9) The first electrode portion includes the first electrode portion end on the first electrode side in the first direction, The third electrode includes the third electrode end on the first electrode side in the first direction. The semiconductor device according to any one of configurations 1 to 8, wherein the position of the third electrode end in the first direction is between the position of the first electrode in the first direction and the position of the first electrode portion end in the first direction.

[0078] (Composition 10) The semiconductor device according to any one of configurations 1 to 9, wherein the width of the third electrode along the second direction is wider than the width of the first conductive member along the second direction.

[0079] (Composition 11) The first semiconductor region includes a first semiconductor surface, a second semiconductor surface, a third semiconductor surface, and a fourth semiconductor surface. The third electrode is located between the first semiconductor surface and the second semiconductor surface in the second direction. A portion of the first insulating member is located between the first semiconductor surface and the third electrode. Another part of the first insulating member is located between the third electrode and the second semiconductor surface. The first electrode portion is located between the third semiconductor surface and the fourth semiconductor surface in the second direction. A semiconductor device according to any one of configurations 1 to 10, wherein the first width along the second direction between the first semiconductor surface and the second semiconductor surface is greater than the second width along the second direction between the third semiconductor surface and the fourth semiconductor surface.

[0080] (Composition 12) The first semiconductor region includes a first semiconductor surface, a second semiconductor surface, a fifth semiconductor surface, and a sixth semiconductor surface. The third electrode is located between the first semiconductor surface and the second semiconductor surface in the second direction. A portion of the first insulating member is located between the first semiconductor surface and the third electrode. Another part of the first insulating member is located between the third electrode and the second semiconductor surface. The first conductive member is located between the fifth semiconductor surface and the sixth semiconductor surface in the second direction. A portion of the first insulating member is located between the fifth semiconductor surface and the first conductive member. Another part of the first insulating member is located between the first conductive member and the sixth semiconductor surface. A semiconductor device according to any one of configurations 1 to 10, wherein the first width along the second direction between the first semiconductor surface and the second semiconductor surface is greater than the third width along the second direction between the fifth semiconductor surface and the sixth semiconductor surface.

[0081] (Composition 13) The semiconductor device according to any one of configurations 1 to 12, wherein the width of the first conductive member along the second direction is continuously varying or constant in the first direction.

[0082] (Composition 14) The semiconductor device according to any one of configurations 1 to 13, wherein the width of the second semiconductor region along the second direction is 25 nm or more and 50 nm or less.

[0083] (Composition 15) Further comprising a second insulating member, At least a portion of the second insulating member is provided between the third electrode and the second electrode portion, as described in any one of configurations 1 to 14, for the semiconductor device.

[0084] (Composition 16) A first trench and a second trench are formed simultaneously in a first semiconductor region of a first conductivity type, wherein the width of the first trench is wider than the width of the second trench, and the depth of the first trench is deeper than the depth of the second trench. A first insulating film is formed in the first trench and the second trench, the first insulating film comprising a first insulating portion, a second insulating portion and a third insulating portion, the first insulating portion being located at the bottom of the first trench, the second insulating portion being located on the side wall of the first trench, a space remaining in the first trench, and the second trench being substantially closed by the third insulating portion. The first insulating portion is removed to expose a part of the first semiconductor region. A portion of the exposed first semiconductor region is removed to form a third trench. After the formation of the third trench, the second insulating portion is removed. A second insulating film is formed inside the first trench and the third trench. A first conductive material is introduced into the third trench to form a first conductive member. After the formation of the first conductive member, a third electrode is formed on the first conductive member. A method for manufacturing a semiconductor device, comprising: removing the third insulating portion and then introducing a second conductive material into the second trench to form a first electrode portion.

[0085] (Composition 17) The formation of the third electrode is After the formation of the first conductive member, the first conductive material present in the remaining space of the first trench is removed. A third insulating film is embedded on the first conductive member and in the remaining space of the first trench. Remove a portion of the third insulating film inside the first trench, leaving another portion of the third insulating film inside the first trench. A fourth insulating film is formed on the side wall of the first trench. A method for manufacturing a semiconductor device according to configuration 16, comprising introducing a third conductive material into the remaining space of the first trench after the formation of the fourth insulating film to form the third electrode.

[0086] (Composition 18) A fifth insulating film is formed from the upper portion of the third electrode and the upper portion of the first semiconductor region. A method for manufacturing a semiconductor device according to configuration 17, comprising introducing an impurity of a first conductivity type into the surface portion of the first semiconductor region via the fifth insulating film to form a second semiconductor region.

[0087] (Composition 19) The formation of the first electrode portion is After the formation of the second semiconductor region, the third insulating portion is removed. A method for manufacturing a semiconductor device according to configuration 18, comprising introducing a second conductive material into the second trench formed by the removal of the third insulating portion.

[0088] (Composition 20) A method for manufacturing a semiconductor device according to any one of configurations 16 to 19, wherein a step is formed between the side surface of the first trench and the side surface of the third trench by removing the second insulating portion.

[0089] According to the embodiment, a semiconductor device and a method for manufacturing the same that can be obtained with stable characteristics can be provided.

[0090] Embodiments of the present invention have been described above with reference to examples. However, the present invention is not limited to these examples. For example, the specific configuration of each element included in a semiconductor device, such as electrodes, semiconductor regions, conductive members, and insulating members, is included within the scope of the present invention as long as it can be implemented in the same way and similar effects can be obtained by appropriately selecting from the range known to those skilled in the art.

[0091] Combinations of two or more elements from each example, to the extent technically feasible, are also included within the scope of the present invention, insofar as they encompass the gist of the invention.

[0092] All semiconductor devices and their manufacturing methods that a person skilled in the art can implement by appropriately modifying the design based on the semiconductor device and its manufacturing method described above as embodiments of the present invention also fall within the scope of the present invention, insofar as they encompass the gist of the present invention.

[0093] Within the scope of the concept of this invention, a person skilled in the art would be able to conceive of various modifications and alterations, and it is understood that such modifications and alterations also fall within the scope of this invention.

[0094] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of symbols]

[0095] 10: Semiconductor material, 11, 12: First and second semiconductor regions, 11a~11d: First to fourth partial regions, 12w: Second semiconductor region width, 41, 42: First and second insulating materials, 41a~41c: First to third insulating regions, 41s: Step, 51~53: First to third electrodes, 51f: First electrode surface, 52L: Wiring, 52T: Second electrode terminal, 52a: First electrode portion, 52ae: First electrode portion end, 52b: Second electrode portion, 53e: Third electrode end, 61: First conductive material, 61T: First conductive material terminal, 65a~65c: First to third conductive materials, 77: Resist film, 78: Carbon film, 79: Mask film, 81~86: First to sixth insulating films, 81a~81c: 1st to 3rd insulating portions, 86o: opening, 91~93: 1st to 3rd trenches, 110: semiconductor device, D1~D3: 1st to 3rd directions, F1~F3: 1st to 3rd surfaces, Fe1, Fe2: 1st and 2nd ends, SF1~SF6: 1st to 6th semiconductor surfaces, d1, d2: 1st and 2nd distances, dx: thickness, w1~w3: 1st to 3rd widths, Δd: distance

Claims

1. First electrode and A second electrode, wherein the direction from the first electrode to the second electrode is along the first direction, and the second electrode includes a first electrode portion and a second electrode portion connected to the first electrode portion. A third electrode is provided between the first electrode and the second electrode portion, A semiconductor component, wherein the semiconductor component is A first semiconductor region of a first conductivity type, the first semiconductor region includes a first subregion, a second subregion, a third subregion and a fourth subregion, the first subregion is provided between the first electrode and the third electrode in the first direction, the second direction from the first subregion to the second subregion intersects the first direction, the position of the third subregion in the second direction is between the position of the first subregion in the second direction and the position of the second subregion in the second direction, and the fourth subregion is between the second subregion and the first electrode portion, the first semiconductor region and The second semiconductor region of the first conductivity type, wherein the impurity concentration of the first conductivity type in the second semiconductor region is higher than the impurity concentration of the first conductivity type in the first semiconductor region, the second semiconductor region is provided between the third electrode and the first electrode portion in the second direction, and the second semiconductor region is provided between the third portion region and the second electrode portion in the first direction, The semiconductor member including, A first conductive member, wherein the first conductive member is provided between the first partial region and the third electrode in the first direction, the direction from the first conductive member to the fourth partial region is along the second direction, and the first conductive member is electrically connected to the second electrode, or can be electrically connected to the second electrode, A first insulating member comprising a first insulating region, a second insulating region, and a third insulating region, wherein the first insulating region is provided between the third electrode and the second semiconductor region, the second insulating region is provided between the semiconductor member and the first conductive member, at least a portion of the third insulating region is provided between the first conductive member and the third electrode, the second insulating region includes a first surface facing the third partial region, the third insulating region includes a second surface facing the third partial region, the first surface includes a first end on the second electrode side in the first direction, the second surface includes a second end on the first electrode side in the first direction, and the second position of the second end in the second direction is different from the first position of the first end in the second direction, and the first insulating member comprises these two parts. Equipped with, A semiconductor device wherein the width of the second semiconductor region along the second direction is 25 nm or more and 50 nm or less.

2. The semiconductor device according to claim 1, wherein the first distance along the second direction between the first conductive member and the first position is shorter than the second distance along the second direction between the first conductive member and the second position.

3. The semiconductor device according to claim 1, wherein the distance along the second direction between the first position and the second position is 0.3 times or more and 2 times or less the thickness of the first insulating region along the second direction.

4. The semiconductor device according to claim 1, wherein a step is provided between the first surface and the second surface.

5. The third insulating region further includes a third surface, The semiconductor device according to claim 1, wherein the third surface is located between the first surface and the second surface, is connected to the first surface and the second surface, and the third surface is nonparallel to the first surface and nonparallel to the second surface.

6. The semiconductor device according to claim 1, wherein the second semiconductor region is in contact with the first semiconductor region.

7. The semiconductor device according to claim 1, wherein the first electrode portion is in Schottky contact with the semiconductor member.

8. The first electrode portion is in contact with the second semiconductor region and the fourth partial region. The semiconductor device according to claim 1, wherein the first electrode portion includes at least one selected from the group consisting of Pt, Co, and Ni.

9. The first electrode portion includes the first electrode portion end on the first electrode side in the first direction, The third electrode includes the third electrode end on the first electrode side in the first direction. The semiconductor device according to any one of claims 1 to 8, wherein the position of the third electrode end in the first direction is between the position of the first electrode in the first direction and the position of the portion end of the first electrode in the first direction.

10. The semiconductor device according to claim 1, wherein the width of the third electrode along the second direction is wider than the width of the first conductive member along the second direction.

11. The first semiconductor region includes a first semiconductor surface, a second semiconductor surface, a third semiconductor surface, and a fourth semiconductor surface. The third electrode is located between the first semiconductor surface and the second semiconductor surface in the second direction. A portion of the first insulating member is located between the first semiconductor surface and the third electrode. Another part of the first insulating member is located between the third electrode and the second semiconductor surface. The first electrode portion is located between the third semiconductor surface and the fourth semiconductor surface in the second direction. The semiconductor device according to claim 1, wherein the first width along the second direction between the first semiconductor surface and the second semiconductor surface is greater than the second width along the second direction between the third semiconductor surface and the fourth semiconductor surface.

12. The first semiconductor region includes a first semiconductor surface, a second semiconductor surface, a fifth semiconductor surface, and a sixth semiconductor surface. The third electrode is located between the first semiconductor surface and the second semiconductor surface in the second direction. A portion of the first insulating member is located between the first semiconductor surface and the third electrode. Another part of the first insulating member is located between the third electrode and the second semiconductor surface. The first conductive member is located between the fifth semiconductor surface and the sixth semiconductor surface in the second direction. A portion of the first insulating member is located between the fifth semiconductor surface and the first conductive member. Another part of the first insulating member is located between the first conductive member and the sixth semiconductor surface. The semiconductor device according to claim 1, wherein the first width along the second direction between the first semiconductor surface and the second semiconductor surface is greater than the third width along the second direction between the fifth semiconductor surface and the sixth semiconductor surface.

13. The semiconductor device according to claim 1, wherein the width of the first conductive member along the second direction is continuously changing or constant in the first direction.

14. Further comprising a second insulating member, The semiconductor device according to claim 1, wherein at least a portion of the second insulating member is provided between the third electrode and the second electrode portion.

15. A first trench and a second trench are formed simultaneously in a first semiconductor region of a first conductivity type, wherein the width of the first trench is wider than the width of the second trench, and the depth of the first trench is deeper than the depth of the second trench. A first insulating film is formed in the first trench and the second trench, the first insulating film comprising a first insulating portion, a second insulating portion and a third insulating portion, the first insulating portion being provided at the bottom of the first trench, the second insulating portion being provided on the side wall of the first trench, a space remaining in the first trench, and the second trench being substantially closed by the third insulating portion. The first insulating portion is removed to expose a part of the first semiconductor region. A portion of the exposed first semiconductor region is removed to form a third trench. After the formation of the third trench, the second insulating portion is removed. A second insulating film is formed inside the first trench and the third trench. A first conductive material is introduced into the third trench to form a first conductive member. After the formation of the first conductive member, a third electrode is formed on the first conductive member. After removing the third insulating portion, the second conductive material is introduced into the second trench to form the first electrode portion. The formation of the third electrode is After the formation of the first conductive member, the first conductive material present in the remaining space of the first trench is removed. A third insulating film is embedded on the first conductive member and in the remaining space of the first trench. Remove a portion of the third insulating film inside the first trench, leaving another portion of the third insulating film inside the first trench. A fourth insulating film is formed on the side wall of the first trench. The process includes introducing a third conductive material into the remaining space of the first trench after the formation of the fourth insulating film to form the third electrode, A fifth insulating film is formed from the upper portion of the third electrode and the upper portion of the first semiconductor region. A second semiconductor region is formed by introducing an impurity of the first conductivity type into the surface portion of the first semiconductor region via the fifth insulating film. The formation of the first electrode portion is After the formation of the second semiconductor region, the third insulating portion is removed. This includes introducing the second conductive material into the second trench formed by the removal of the third insulating portion, A method for manufacturing a semiconductor device, wherein a step is formed between the side surface of the first trench and the side surface of the third trench by removing the second insulating portion, The aforementioned semiconductor device is First electrode and A second electrode, wherein the direction from the first electrode to the second electrode is along the first direction, and the second electrode includes the first electrode portion and the second electrode portion connected to the first electrode portion. The third electrode is provided between the first electrode and the second electrode portion, A semiconductor component, wherein the semiconductor component is The first semiconductor region of the first conductivity type, the first semiconductor region includes a first subregion, a second subregion, a third subregion and a fourth subregion, the first subregion is provided between the first electrode and the third electrode in the first direction, the second direction from the first subregion to the second subregion intersects the first direction, the position of the third subregion in the second direction is between the position of the first subregion in the second direction and the position of the second subregion in the second direction, and the fourth subregion is between the second subregion and the first electrode portion, the first semiconductor region and The second semiconductor region of the first conductivity type, wherein the impurity concentration of the first conductivity type in the second semiconductor region is higher than the impurity concentration of the first conductivity type in the first semiconductor region, the second semiconductor region is provided between the third electrode and the first electrode portion in the second direction, and the second semiconductor region is provided between the third portion region and the second electrode portion in the first direction, The semiconductor member including, The first conductive member is provided between the first partial region and the third electrode in the first direction, the direction from the first conductive member to the fourth partial region is along the second direction, and the first conductive member is electrically connected to the second electrode, or can be electrically connected to the second electrode. A first insulating member comprising a first insulating region, a second insulating region, and a third insulating region, wherein the first insulating region is provided between the third electrode and the second semiconductor region, the second insulating region is provided between the semiconductor member and the first conductive member, at least a portion of the third insulating region is provided between the first conductive member and the third electrode, the second insulating region includes a first surface facing the third partial region, the third insulating region includes a second surface facing the third partial region, the first surface includes a first end on the second electrode side in the first direction, the second surface includes a second end on the first electrode side in the first direction, and the second position of the second end in the second direction is different from the first position of the first end in the second direction, and the first insulating member comprises these two parts. Equipped with, A method for manufacturing a semiconductor device, wherein the width of the second semiconductor region along the second direction is 25 nm or more and 50 nm or less.

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