Output circuits, photoelectric converters, photoelectric conversion systems, and electronic equipment

Abstract

To provide a technique advantageous to suppress voltage fluctuation on a power line.SOLUTION: An output circuit outputs an amplitude modulation signal having a voltage value chosen from voltage values of three or more. The output circuit includes a differential circuit arranged between a first power line and a second power line, a switch and a resistor connected in series so as to configure a path connecting the first power line and the second power line, the differential circuit includes a first differential output circuit having a first positive side output terminal and a first negative side output terminal, a second differential output circuit having a second positive side output terminal and a second negative side output terminal, a first output line for connecting the first positive side output terminal and the second positive side output terminal, and a second output line for connecting the first negative side output terminal and the second negative side output terminal, the amplitude modulation signal is outputted with the first output line and the second output line, the switch and the resistor suppress change of current value flowing between the first power line and the second power line due to operation state change of the differential circuit.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to an output circuit, a photoelectric conversion device, a photoelectric conversion system, and an electronic apparatus. Background Art

[0002] As one transmission scheme for transmitting multi-level voltage signals, there is a standard called PAM4. In PAM4, information is transmitted using four voltage values corresponding to 00, 01, 10, and 11. Patent Document 1 describes an output circuit (transmitter) that can be applied to PAM4. Prior Art Documents Patent Documents

[0003] Patent Document 1 US Patent Publication No. 2016-0352315 Summary of the Invention Problems to be Solved by the Invention

[0004] However, with the configuration of the transmitter described in Patent Document 1, the current supplied from the power supply line fluctuates in accordance with the voltage value output by the transmitter, which may cause the potential of the power supply line to fluctuate. This can lead to deterioration of the eye pattern of the output signal of the transmitter. To suppress this, a bypass capacitor (capacitor) having a large capacitance can be connected to the power supply line, but this results in an increase in circuit area and an increase in cost.

[0005] An object of the present invention is to provide an advantageous technique for suppressing fluctuations in the potential of a power supply line. Means for Solving the Problems

[0006] One aspect of the present invention relates to an output circuit that outputs an amplitude-modulated signal having a voltage value selected from three or more voltage values, the output circuit comprising: a differential circuit disposed between a first power line and a second power line; and a switch and a resistor connected in series to form a path connecting the first power line and the second power line, the differential circuit comprising: a first differential output circuit having a first positive output terminal and a first negative output terminal; a second differential output circuit having a second positive output terminal and a second negative output terminal; a first output line connecting the first positive output terminal and the second positive output terminal; and the amplitude-modulated signal is output by the first output line and the second output line, the switch and the resistor suppress changes in the value of the current flowing between the first power line and the second power line due to changes in the operating state of the differential circuit, and the output circuit, the second differential output circuit, A 21st resistor element positioned between the first power line and the second positive output terminal, a 21st switch element positioned between the 21st resistor element and the second positive output terminal, a 22nd switch element positioned between the 21st resistor element and the second negative output terminal, a 22nd resistor element positioned between the second power line and the second negative output terminal, a 23rd switch element positioned between the 22nd resistor element and the second positive output terminal, a 24th switch element positioned between the 22nd resistor element and the second negative output terminal, a node connecting the 21st switch element and the 22nd switch element and the 21st resistor element A first switch is positioned between and A node connecting the 23rd switch element and the 24th switch element and the 22nd resistor element It further includes a second switch positioned between and . [Effects of the Invention]

[0007] According to the present invention, an advantageous technique is provided for suppressing fluctuations in the potential of power lines. [Brief explanation of the drawing]

[0008] [Figure 1] A diagram showing the configuration of the output circuit of the first embodiment. [Figure 2] A diagram illustrating the operation of the output circuit of the first embodiment. [Figure 3] A diagram illustrating the operation of the output circuit of the first embodiment. [Figure 4] A diagram illustrating the operation of the output circuit of the first embodiment. [Figure 5] A diagram illustrating the operation of the output circuit of the first embodiment. [Figure 6] A diagram showing the configuration of the output circuit of the first embodiment. [Figure 7] A diagram showing a modified example of the output circuit of the first embodiment. [Figure 8]A diagram showing the configuration of the output circuit of the second embodiment. [Figure 9] This figure shows a modified example of the output circuit of the second embodiment. [Figure 10] A diagram illustrating the operation of the output circuit of the second embodiment. [Figure 11] A diagram illustrating the operation of the output circuit of the second embodiment. [Figure 12] A diagram showing the configuration of the output circuit of the third embodiment. [Figure 13] A diagram illustrating photoelectric converters, photoelectric conversion systems, and electronic equipment. [Modes for carrying out the invention]

[0009] The embodiments will be described in detail below with reference to the attached drawings. Note that the following embodiments do not limit the invention as defined in the claims. While the embodiments describe multiple features, not all of these features are essential to the invention, and the features may be combined in any way. Furthermore, in the attached drawings, identical or similar configurations are given the same reference numerals, and redundant descriptions are omitted.

[0010] Figure 1 shows the configuration of the output circuit 100 of the first embodiment. The output circuit 100 can be understood as a transmitter or a differential signal output circuit. The output circuit 100 can be configured to output an amplitude-modulated signal having a voltage value selected from three or more arbitrary numbers of voltage values ​​(e.g., 4, 6, 8, etc.). In the example shown in Figure 1, the output circuit 100 outputs an amplitude-modulated signal having a voltage value selected from four voltage values. An amplitude-modulated signal having a voltage value selected from four voltage values ​​can transmit two bits of information (i.e., 00, 01, 10, 11). The four voltage values ​​can be assigned, for example, a negative large amplitude value, a negative small amplitude value, a positive small amplitude value, and a positive small amplitude value. Here, the large amplitude value and small amplitude value are relative expressions, and the absolute value of the large amplitude value is greater than the absolute value of the small amplitude value.

[0011] The output circuit 100 may include a differential circuit DC positioned between a first power line VS1 and a second power line VS2, and a switch S3 and a resistor R3 connected in series to form at least a portion of a path 30 connecting the first power line VS1 and the second power line VS2. Here, the resistor R3 may be positioned between the switch S3 and the second power line VS2, or between the switch S3 and the first power line VS1. A predetermined voltage is supplied between the first power line VS1 and the second power line VS2. Here, the potential of the first power line VS1 is assumed to be higher than the potential of the second power line VS2. The second power line VS2 may be grounded, in which case the second power line VS2 is a ground wire.

[0012] The differential circuit DC may include a first differential output circuit 10 having a first positive output terminal P1 and a first negative output terminal N1, and a second differential output circuit 20 having a second positive output terminal P2 and a second negative output terminal N2. The differential circuit DC may also include a first output line OUT1 connecting the first positive output terminal P1 and the second positive output terminal P2, and a second output line OUT2 connecting the first negative output terminal N1 and the second negative output terminal N2. The amplitude-modulated signal is output as the output of the output circuit 100 through the first output line OUT1 and the second output line OUT2.

[0013] The switch S3 and resistor R3 arranged on the path 30 suppress the change in the value of current flowing between the first power supply line VS1 and the second power supply line VS2 caused by a change in the operating state of the differential circuit DC (a change in the voltage value output from the differential circuit DC). Preferably, the switch S3 and the resistor R3 maintain the value of the current flowing between the first power supply line VS1 and the second power supply line VS2 at a constant value or within a predetermined allowable range regardless of the change in the operating state of the differential circuit DC (the change in the output voltage value). The operating states of the differential circuit DC may include a first state in which the first differential output circuit 10 and the second differential output circuit 20 drive the load R0 connected between the first output line OUT1 and the second output line OUT2, and a second state in which only the first differential output circuit 10 drives the load R0. The switch S3 may be controlled to be conductive in the second state. It is preferable that the value of the current flowing between the first power supply line VS1 and the second power supply line VS2 through the differential circuit DC in the first state is equal to the value of the current flowing between the first power supply line VS1 and the second power supply line VS2 through the differential circuit DC and the path 30 in the second state.

[0014] The first differential output circuit 10 can operate when the output circuit 100 or the differential circuit DC outputs a negative or positive large-amplitude voltage between the first output line OUT1 and the second output line OUT2. The first differential output circuit 10 can also operate when the output circuit 100 or the differential circuit DC outputs a negative or positive small-amplitude voltage between the first output line OUT1 and the second output line OUT2. The operation of the first differential output circuit 10 means that the first differential output circuit 10 supplies current between the first output line OUT1 and the second output line OUT2. Alternatively, the operation of the first differential output circuit 10 means that a substantial current flows from the first power supply line VS1 to the second power supply line VS2 through the first differential output circuit 10. A substantial current is a current whose value has a significant difference from the value of an unintended current such as a through current.

[0015] The second differential output circuit 20 can operate when the output circuit 100 or the differential circuit DC outputs a voltage with a large negative or positive amplitude between the first output line OUT1 and the second output line OUT2. However, the second differential output circuit 20 can stop operating when the output circuit 100 or the differential circuit DC outputs a voltage with a small negative or positive amplitude between the first output line OUT1 and the second output line OUT2. The operation of the second differential output circuit 20 means that the second differential output circuit 20 supplies a current between the first output line OUT1 and the second output line OUT2. Alternatively, the operation of the second differential output circuit 20 means that a substantial current flows from the first power supply line VS1 to the second power supply line VS2 through the second differential output circuit 20.

[0016] The first differential output circuit 10 can include an eleventh resistance element R11 disposed between the first power supply line VS1 and the first positive output terminal P1. The first differential output circuit 10 can also include an eleventh switch element S11 disposed between the eleventh resistance element R11 and the first positive output terminal P1, and a twelfth switch element S12 disposed between the eleventh resistance element R11 and the first negative output terminal N1. The first differential output circuit 10 can also include a twelfth resistance element R12 disposed between the second power supply line VS2 and the first negative output terminal N1. Further, the first differential output circuit 10 can include a thirteenth switch element S13 disposed between the twelfth resistance element R12 and the first positive output terminal P1, and a fourteenth switch element S14 disposed between the twelfth resistance element R12 and the first negative output terminal N1.

[0017] The second differential output circuit 20 may include a 21st resistor R21 positioned between the first power line VS1 and the second positive output terminal P2. The second differential output circuit 20 may also include a 21st switch element S21 positioned between the 21st resistor R21 and the second positive output terminal P2, and a 22nd switch element S22 positioned between the 21st resistor R21 and the second negative output terminal N2. The second differential output circuit 20 may also include a 22nd resistor R22 positioned between the second power line VS2 and the second positive output terminal P2. The second differential output circuit 20 may also include a 23rd switch element S23 positioned between the 22nd resistor R22 and the second positive output terminal P2, and a 24th switch element S24 positioned between the 22nd resistor R22 and the second negative output terminal N2.

[0018] The numerical value of xx in the xxth resistor element is used to distinguish between multiple resistor elements, and the value itself has no other meaning. Similarly, the numerical value of xx in the xxth switch element is used to distinguish between multiple switch elements, and the value itself has no other meaning. The above switch elements may be composed of transistors such as MOS transistors. The transistors may be P-type, N-type, or a mixture of both as long as it does not cause inconsistencies in operation.

[0019] The first output line OUT1 and the second output line OUT2 can be connected to the first input terminal and the second input terminal of the receiver (receiving circuit), respectively. In Figure 1, R0 is the load between the first input terminal and the second input terminal of the receiver (receiving circuit).

[0020] The output circuit 100 may further include a capacitor C1 positioned between the first power line VS1 and the second power line VS2. Capacitor C1 functions to smooth the voltage between the first power line VS1 and the second power line VS2, i.e., the power supply voltage. Capacitor C1 may be called a decoupling capacitor. Providing a switch S3 and a resistor R3 connected in series with path 30 is advantageous in order to reduce the capacitance value required of capacitor C1.

[0021] The output circuit 100 may further include a control circuit CNT that controls the differential circuit DC and switch S3. The control circuit CNT controls each switch element of the differential circuit DC and switch S3 of path 30 according to the voltage values ​​that the output circuit 100 should output (in this example, large positive amplitude value, large negative amplitude value, small positive amplitude value, and small negative amplitude value).

[0022] The following will illustrate the control of each switch element in the differential circuit DC by the control circuit CNT and the switch S3 in the path 30 when the output circuit 100 outputs a large positive amplitude value, a large negative amplitude value, a small positive amplitude value, and a small negative amplitude value, with reference to Figures 2, 3, 4, and 5. Here, as an example, the potential of the first power line VS1 (the potential difference between the first power line VS1 and the second power line VS2) is assumed to be 0.5V. Also, the resistance values ​​of R11 and R12 are assumed to be 200Ω, the resistance values ​​of R21 and R22 are assumed to be 40Ω, the resistance value of R3 is assumed to be 250Ω, and the resistance value of R0 is assumed to be 100Ω. In Figures 2, 3, 4, and 5, the thick gray lines indicate the current path. The large positive amplitude value is assumed to be +300mV, the large negative amplitude value is assumed to be -300mV, the small positive amplitude value is assumed to be +100mV, and the small negative amplitude value is assumed to be -100mV.

[0023] Figure 2 schematically shows the operation of the output circuit 100 when it outputs a large positive amplitude value (+300mV). The control circuit CNT turns on (conducts) switch elements S11, S14, S21, and S24, and turns off (disconducts) switch elements S12, S13, S22, S23 and switch S3. The combined resistance between the first power line VS1 and the first output line OUT1 is 33Ω, and the combined resistance between the second power line VS2 and the second output line OUT2 is 33Ω. Therefore, the combined resistance between the first power line VS1 and the second power line VS2 is 166Ω. A current of 3mA flows through the load R0 from the first output line OUT1 to the second output line OUT2, and a voltage of +300mV appears across the load R0. Also, since switch S3 is off, no current flows through path 30. Therefore, a current of 3mA flows from the first power line VS1 to the second power line VS1.

[0024] Figure 3 schematically shows the operation of the output circuit 100 when it outputs a large negative amplitude value (-300mV). The control circuit CNT turns on (conducts) switch elements S12, S13, S22, and S23, and turns off (disconducts) switch elements S11, S14, S21, S24 and switch S3. The combined resistance between the first power line VS1 and the first output line OUT1 is 33Ω, and the combined resistance between the second power line VS2 and the second output line OUT2 is also 33Ω. Therefore, the combined resistance between the first power line VS1 and the second power line VS2 is 166Ω. A current of 3mA flows through the load R0 from the second output line OUT2 towards the first output line OUT1, and a voltage of -300mV appears across the load R0. Also, since switch S3 is off, no current flows through path 30. Therefore, a current of 3mA flows from the first power line VS1 to the second power line VS1.

[0025] Figure 4 schematically shows the operation of the output circuit 100, which outputs a small positive amplitude value (+100mV). The control circuit CNT turns on (conducts) switch elements S11, S14 and switch S3, and turns off (disconducts) switch elements S12, S13, S21, S22, S23, and S24. The resistance between the first power line VS1 and the first output line OUT1 is 200Ω, and the resistance between the second power line VS2 and the second output line OUT2 is 200Ω. Therefore, the combined resistance between the first power line VS1 and the second power line VS2 is 500Ω. A current of 1mA flows through the load R0 from the first output line OUT1 to the second output line OUT2, and a voltage of +100mV appears across the load R0. In addition, a current of 2mA flows through path 30 from the first power line VS1 to the second power line VS1 through switch S3 and resistor R3. Therefore, a total current of 3mA flows from the first power line VS1 to the second power line VS1.

[0026] Figure 5 schematically shows the operation of the output circuit 100 when it outputs a small negative amplitude value (-100mV). The control circuit CNT turns on (conducts) switch elements S12, S13 and switch S3, and turns off (disconducts) switch elements S11, S14, S21, S22, S23, and S24. The resistance between the first power line VS1 and the first output line OUT1 is 200Ω, and the resistance between the second power line VS2 and the second output line OUT2 is 200Ω. Therefore, the combined resistance between the first power line VS1 and the second power line VS2 is 500Ω. A current of 1mA flows through the load R0 from the second output line OUT2 towards the first output line OUT1, and a voltage of -100mV appears across the load R0. In addition, a current of 2mA flows through path 30 from the first power line VS1 towards the second power line VS1 through switch S3 and resistor R3. Therefore, a total current of 3mA flows from the first power line VS1 to the second power line VS1.

[0027] As described above, according to the first embodiment, regardless of the voltage value that the output circuit 100 should output (in this example, the large positive amplitude value, the large negative amplitude value, the small positive amplitude value, and the small negative amplitude value), a current of 3mA always flows from the first power line VS1 to the second power line VS1. This makes it possible to maintain a constant potential across the first power line VS1 (the potential difference between the first power line VS1 and the second power line VS2). This is advantageous for reducing the capacitance value required for capacitor C1. Reducing the capacitance value required for capacitor C1 is advantageous for reducing circuit area and cost.

[0028] As illustrated in Figure 6, the output circuit 100 may further include an ESD protection circuit 60 to protect the differential DC circuit. The ESD protection circuit 60 may include diodes D1, D2, D3, and D4. The anode of diode D1 may be connected to the first output line OUT1, and the cathode of diode D1 may be connected to the first power line VS1. The anode of diode D2 may be connected to the second output line OUT2, and the cathode of diode D2 may be connected to the first power line VS1. The anode of diode D3 may be connected to the second power line VS2, and the cathode of diode D3 may be connected to the first output line OUT1. The anode of diode D4 may be connected to the second power line VS2, and the cathode of diode D4 may be connected to the second output line OUT2. By providing the ESD protection circuit 60, the switching elements connected to the first output line OUT1 and the second output line OUT2 can be protected from ESD.

[0029] Figure 7 shows an output circuit 100 according to a modified example of the first embodiment. The differential circuit DC of the output circuit 100 may include one or more differential output circuits 20' in addition to the first differential output circuit 10 and the second differential output circuit 20. The differential output circuit 20' may have the same configuration as the first differential output circuit 10 or the second differential output circuit 20. The addition of the differential output circuit 20' makes it possible to generate a multi-level amplitude modulated signal.

[0030] Figure 8 shows the configuration of the output circuit 100 of the second embodiment. Matters not mentioned regarding the configuration and operation of the output circuit 100 of the second embodiment may follow those of the first embodiment. As illustrated in Figure 8, the path 30 may be arranged to connect the 21st resistive element R21 and the 22nd resistive element R22. In other words, the switch S3 and resistor R3 may be arranged to connect the 21st resistive element R21 and the 22nd resistive element R22. Here, the resistor R3 may be placed between the switch S3 and the 21st resistive element R21, or between the switch S3 and the 22nd resistive element R22.

[0031] As illustrated in Figure 8, the output circuit 100 may further include a disconnection section 50 that disconnects the second differential output circuit 20 from the first differential output circuit 10 (or the first output line OUT1 and the second output line OUT2). The disconnection section 50 may be controlled by a control circuit CNT. The control unit CNT may control the disconnection section 50 so that the second differential output circuit 20 is disconnected from the first differential output circuit 10 (or the first output line OUT1 and the second output line OUT2) during periods when the second differential output circuit 20 is not in operation. The control unit CNT may control the disconnection section 50 so that the second differential output circuit 20 is connected to the first differential output circuit 10 (or the first output line OUT1 and the second output line OUT2) during periods when the second differential output circuit 20 is in operation. The disconnection section 50 may include a first switch S51 located on the first output line OUT1 that can disconnect the second differential output circuit 20 from the first differential output circuit 10, and a second switch S52 located on the second output line OUT2 that can disconnect the second differential output circuit 20 from the first differential output circuit 10.

[0032] The output circuit 100 may further include a current path 40 provided in parallel with the load R0 connected between the first output line OUT1 and the second output line OUT2. A third switch S4 and a third resistor R4 may be arranged in series in the current path 40. The third switch S4 may be controlled by a control circuit CNT. The current path 40 may function, for example, to adjust the width of small amplitudes by the ratio of the resistance value of the load R0 to the resistance value of the third resistor R4.

[0033] Figure 9 shows a modified configuration of the output circuit 100 of the second embodiment shown in Figure 8. In the modified configuration shown in Figure 9, the first switch S51 is located between the node connecting the 21st switch element S21 and the 22nd switch element S22 and the 21st resistor element R21. The second switch S52 is located between the node connecting the 23rd switch element S23 and the 24th switch element S24 and the 22nd resistor element R22. The first switch S51 and the second switch S52 disconnect the second differential output circuit 20 from the first differential output circuit 10 (or the first output line OUT1 and the second output line OUT2) by stopping the operation of the second differential output circuit 20. Alternatively, the first switch S51 and the second switch S52 may be understood simply as circuits that stop the operation of the second differential output circuit 20. The path 30 may be arranged to connect the 21st resistor element R21 and the 22nd resistor element R22.

[0034] The following will exemplify the control of each switch element in the differential circuit DC by the control circuit CNT and the switch S3 in the path 30 when the output circuit 100 outputs a large positive amplitude value, a large negative amplitude value, a small positive amplitude value, and a small negative amplitude value, with reference to Figures 10 and 11. Here, as an example, let's assume that the potential of the first power line VS1 (the potential difference between the first power line VS1 and the second power line VS2) is 0.5V. Let's assume that the resistance values ​​of R11 and R12 are 100Ω, the resistance values ​​of R21 and R22 are 50Ω, the resistance value of R0 is 100Ω, the resistance value of R3 is 400Ω, and the resistance value of R4 is 100Ω. The large positive amplitude value is +300mV, the large negative amplitude value is -300mV, the small positive amplitude value is +100mV, and the small negative amplitude value is -100mV.

[0035] Figure 10 schematically shows the operation of the output circuit 100 to output a large positive or negative amplitude value (+300mV or -300mV). When the output circuit 100 outputs a large positive amplitude value (+300mV), the control circuit CNT turns on switch elements S11, S14, S21, S24, and switches S51 and S52, and turns off switch elements S12, S13, S22, S23, and switches S3 and S4. This operation is the same as the operation shown in Figure 2. When the output circuit 100 outputs a large negative amplitude value (-300mV), the control circuit CNT turns on switch elements S12, S13, S22, S23, and switches S51 and S52, and turns off switch elements S11, S14, S21, S24, and switches S3 and S4. This operation is the same as the operation shown in Figure 3.

[0036] Figure 11 schematically shows the operation of the output circuit 100 to output a small amplitude value on the positive or negative side (+100mV or -100mV). When the output circuit 100 outputs a small amplitude value on the positive side (+100mV), the control circuit CNT turns on switch elements S11, S14, S21, S24, S3, and S4, and turns off switch elements S12, S13, S22, S23, S51, and S52. The voltage across the load R0 and the current flowing from the first power line VS1 to the second power line VS2 are the same as in the operation shown in Figure 4. On the other hand, when the output circuit 100 outputs a negative small amplitude value (-100mV), the control circuit CNT turns on switch elements S12, S13, S22, S23, S3, and S4, and turns off switch elements S11, S14, S21, S24, S51, and S52. The voltage across the load R0 and the current flowing from the first power line VS1 to the second power line VS2 are the same as in the operation shown in Figure 5.

[0037] Figure 12 shows the configuration of the output circuit 100 of the third embodiment. Matters not mentioned regarding the configuration and operation of the output circuit 100 of the third embodiment may follow those of the first embodiment. The output circuit 100 of the third embodiment may, like the first embodiment, include a differential circuit DC located between the first power line VS1 and the second power line VS2, and a switch S3 and a resistor R3 connected in series to the path 30 connecting the first power line VS1 and the second power line VS2. Here, the resistor R3 may be located between the switch S3 and the second power line VS2, or between the switch S3 and the first power line VS1.

[0038] The differential circuit DC may include a first differential output circuit 10 having a first positive output terminal P1 and a first negative output terminal N1, and a second differential output circuit 20 having a second positive output terminal P2 and a second negative output terminal N2. The differential circuit DC may also include a first output line OUT1 connecting the first positive output terminal P1 and the second positive output terminal P2, and a second output line OUT2 connecting the first negative output terminal N1 and the second negative output terminal N2. The amplitude-modulated signal is output as the output of the output circuit 100 through the first output line OUT1 and the second output line OUT2.

[0039] The configuration of the first differential output circuit 10 and the first differential output circuit 10 in the third embodiment differs from the configuration of the first differential output circuit 10 and the first differential output circuit 10 in the first embodiment. However, the output circuit 100 in the third embodiment can operate similarly to the output circuit 100 in the first embodiment. The 11th resistor R11 in the first embodiment is replaced by the 101st resistor R101 and the 111th resistor R111, and the 12th resistor R12 in the first embodiment is replaced by the 102nd resistor R102 and the 112th resistor R112. Also, the 21st resistor R21 in the first embodiment is replaced by the 201st resistor R201 and the 211th resistor R211, and the 22nd resistor R22 in the first embodiment is replaced by the 202nd resistor R202 and the 212th resistor R212.

[0040] The 101st resistor R101 and the 111th resistor R111 may have a resistance value equal to that of the 11th resistor R11. The 102nd resistor R102 and the 112th resistor R112 may have a resistance value equal to that of the 12th resistor R12. The 201st resistor R201 and the 211th resistor R211 may have a resistance value equal to that of the 21st resistor R21. The 202nd resistor R202 and the 212th resistor R212 may have a resistance value equal to that of the 22nd resistor R22.

[0041] The first differential output circuit 10 may include an eleventh switch element S11 positioned between the first power line VS1 and the first positive output terminal P1, and a twelfth switch element S12 positioned between the first power line VS1 and the first negative output terminal N1. The first differential output circuit 10 may also include a tenth resistor element R101 positioned between the eleventh switch element S11 and the first positive output terminal P1, and a twelfth resistor element R111 positioned between the twelfth switch element S12 and the first negative output terminal N1. The first differential output circuit 10 may also include a thirteenth switch element S13 positioned between the second power line VS2 and the first positive output terminal P1, and a fourteenth switch element S14 positioned between the second power line VS2 and the first negative output terminal N1. Furthermore, the first differential output circuit 10 may include a 102nd resistor R102 positioned between the 13th switch element S13 and the first positive output terminal P1, and a 112th resistor R112 positioned between the 14th switch element S14 and the first negative output terminal N1.

[0042] The second differential output circuit 20 may include a 21st switch element S21 positioned between the first power line VS1 and the second positive output terminal P2, and a 22nd switch element S22 positioned between the first power line VS1 and the second negative output terminal N2. The second differential output circuit 20 may also include a 201st resistor element R201 positioned between the 21st switch element S21 and the second positive output terminal P2, and a 211th resistor element R211 positioned between the 22nd switch element S22 and the second negative output terminal N2. The second differential output circuit 20 may also include a 23rd switch element S23 positioned between the second power line VS2 and the second positive output terminal P2, and a 24th switch element S24 positioned between the second power line VS2 and the second negative output terminal N2. Furthermore, the second differential output circuit 20 may include a 202nd resistor R202 positioned between the 23rd switch element S23 and the second positive output terminal P2, and a 212th resistor R212 positioned between the 24th switch element S24 and the second negative output terminal N2.

[0043] In the third embodiment, a resistive element is placed between the output lines OUT1 and OUT2 and the switch element, which is advantageous for improving ESD resistance. Of course, as in the first embodiment, an ESD protection circuit 60 may also be provided.

[0044] Figure 13 shows a photoelectric conversion system SYS relating to an application example of the output circuit 100, as represented by the first to third embodiments. The photoelectric conversion system SYS may be understood as an example of an electronic device to which the output circuit 100 is applied. The photoelectric conversion system SYS may include a photoelectric conversion device 200. The photoelectric conversion device 200 may include a pixel array 210 having a plurality of pixels and a signal processing unit 220 including an AD conversion unit that converts analog signals output from the pixel array 210 into digital signals. The photoelectric conversion device 200 may also include an output unit 230 configured to output an amplitude-modulated signal having a voltage value selected from three or more voltage values ​​based on the signal output from the signal processing unit 220. The output unit 230 may have a configuration similar to the output circuit 100, as represented by the first to third embodiments. The photoelectric conversion system SYS may also include a processor 300 (second device) that processes the signals output by the photoelectric conversion device 200. The photoelectric conversion device 200 may be replaced by another device (first device) having an output unit 230.

[0045] This disclosure includes the following disclosures: (Item 1) An output circuit that outputs an amplitude-modulated signal having a voltage value selected from 3 or more voltage values, A differential circuit is placed between the first power line and the second power line, The system comprises a switch and a resistor connected in series to form a path connecting the first power line and the second power line, The differential circuit is A first differential output circuit having a first positive output terminal and a first negative output terminal, A second differential output circuit having a second positive output terminal and a second negative output terminal, A first output line connecting the first positive output terminal and the second positive output terminal, The device includes a second output line connecting the first negative output terminal and the second negative output terminal, and the amplitude modulation signal is output by the first output line and the second output line. The switch and the resistor suppress changes in the value of the current flowing between the first power line and the second power line due to changes in the operating state of the differential circuit. An output circuit characterized by the following features. (Item 2) The operating state of the differential circuit is, A first state in which the first differential output circuit and the second differential output circuit drive a load connected between the first output line and the second output line, A second state in which only the first differential output circuit drives the load, The output circuit described in item 1, characterized by the features described herein. (Item 3) The switch is conductive in the second state. The output circuit described in item 2, characterized by the features described herein. (Item 4) In the first state, the value of the current flowing between the first power line and the second power line through the differential circuit is equal to the value of the current flowing between the first power line and the second power line through the differential circuit and the path in the second state. The output circuit described in item 3, characterized by the features described herein. (Item 5) The device further includes a cutting section for disconnecting the second differential output circuit from the first differential output circuit. The output circuit described in item 1, characterized by the features described herein. (Item 6) The aforementioned cut portion is A first switch is provided on the first output line to enable disconnection of the second differential output circuit from the first differential output circuit, Includes a second switch positioned on the second output line that can disconnect the second differential output circuit from the first differential output circuit, The output circuit described in item 5, characterized by the features described herein. (Item 7) The system further includes a current path provided in parallel with a load connected between the first output line and the second output line, A third switch and a third resistor are arranged in series in the current path. The output circuit according to item 5 or 6, characterized by the features described herein. (Item 8) The system further comprises a capacitor placed between the first power line and the second power line. An output circuit according to any one of items 1 to 7, characterized by the above. (Item 9) The differential circuit is further provided with an ESD protection circuit. An output circuit according to any one of items 1 to 8, characterized by the above. (Item 10) The first differential output circuit includes an 11th resistor element disposed between the first power line and the first positive output terminal, an 11th switch element disposed between the 11th resistor element and the first positive output terminal, a 12th switch element disposed between the 11th resistor element and the first negative output terminal, a 12th resistor element disposed between the second power line and the first positive output terminal, a 13th switch element disposed between the 12th resistor element and the first positive output terminal, and a 14th switch element disposed between the 12th resistor element and the first negative output terminal. The second differential output circuit includes a 21st resistor element positioned between the first power line and the second positive output terminal, a 21st switch element positioned between the 21st resistor element and the second positive output terminal, a 22nd switch element positioned between the 21st resistor element and the second negative output terminal, a 22nd resistor element positioned between the second power line and the second negative output terminal, a 23rd switch element positioned between the 22nd resistor element and the second positive output terminal, and a 24th switch element positioned between the 22nd resistor element and the second negative output terminal. An output circuit according to any one of items 1 to 9, characterized by the above. (Item 11) The aforementioned path is arranged to connect the 21st resistive element and the 22nd resistive element. The output circuit described in item 10, characterized by the features described herein. (Item 12) A first switch is positioned between the node connecting the 21st switch element and the 22nd switch element and the 21st resistor element, A second switch is positioned between the node connecting the 23rd switch element and the 24th switch element and the 22nd resistor element, The output circuit according to item 10, further comprising the following: (Item 13) The aforementioned path is arranged to connect the 21st resistive element and the 22nd resistive element. The output circuit described in item 12, characterized by the features described herein. (Item 14) The first differential output circuit includes an 11th switch element disposed between the first power line and the first positive output terminal, a 12th switch element disposed between the first power line and the first negative output terminal, a 101st resistor element disposed between the 11th switch element and the first positive output terminal, a 111th resistor element disposed between the 12th switch element and the first negative output terminal, a 13th switch element disposed between the second power line and the first positive output terminal, a 14th switch element disposed between the second power line and the first negative output terminal, a 102nd resistor element disposed between the 13th switch element and the first positive output terminal, and a 112th resistor element disposed between the 14th switch element and the first negative output terminal. The second differential output circuit includes a 21st switch element positioned between the first power line and the second positive output terminal, a 22nd switch element positioned between the first power line and the second negative output terminal, a 201st resistor element positioned between the 21st switch element and the second positive output terminal, a 211th resistor element positioned between the 22nd switch element and the second negative output terminal, a 23rd switch element positioned between the second power line and the second positive output terminal, a 24th switch element positioned between the second power line and the second negative output terminal, a 202nd resistor element positioned between the 23rd switch element and the second positive output terminal, and a 212th resistor element positioned between the 24th switch element and the second negative output terminal. An output circuit according to any one of items 1 to 9, characterized by the above. (Item 15) The differential circuit and the control circuit for controlling the switch are further comprising An output circuit according to any one of items 1 to 14, characterized by the features described herein. (Item 16) A pixel array having multiple pixels, A signal processing unit including an AD conversion unit that converts analog signals output from the pixel array into digital signals, An output circuit according to any one of items 1 to 15, configured to output an amplitude-modulated signal having a voltage value selected from three or more voltage values ​​based on the signal output from the signal processing unit, A photoelectric conversion device characterized by comprising the following features. (Item 17) A photoelectric converter described in any one of items 1 to 16, A processor that processes the signal output by the aforementioned photoelectric converter, A photoelectric conversion system characterized by comprising the following features. (Item 18) An electronic device characterized by comprising an output circuit as described in any one of items 1 to 15.

[0046] The invention is not limited to the embodiments described above, and various modifications and variations are possible without departing from the spirit and scope of the invention. Accordingly, claims are attached to disclose the scope of the invention. [Explanation of Symbols]

[0047] DC: Differential circuit, R3: Resistor, S3: Switch, VS1: First power line, VS2: Second power line, OUT1: First output line, OUT2: Second output line, P1: First positive output terminal, P2: Second positive output terminal, N1: First negative output terminal, N2: First negative output terminal, 100: Output circuit, 10: First differential output circuit, 20: Second differential output circuit

Claims

1. An output circuit that outputs an amplitude-modulated signal having a voltage value selected from three or more voltage values, A differential circuit is placed between the first power line and the second power line, The system comprises a switch and a resistor connected in series to form a path connecting the first power line and the second power line, The differential circuit is A first differential output circuit having a first positive output terminal and a first negative output terminal, A second differential output circuit having a second positive output terminal and a second negative output terminal, A first output line connecting the first positive output terminal and the second positive output terminal, The first output terminal and the second output terminal are connected by a second output line, and the amplitude modulation signal is output by the first output line and the second output line. The switch and the resistor suppress changes in the value of the current flowing between the first power line and the second power line due to changes in the operating state of the differential circuit. The second differential output circuit further comprises: a 21st resistor element disposed between the first power line and the second positive output terminal; a 21st switch element disposed between the 21st resistor element and the second positive output terminal; a 22nd switch element disposed between the 21st resistor element and the second negative output terminal; a 22nd resistor element disposed between the second power line and the second negative output terminal; a 23rd switch element disposed between the 22nd resistor element and the second positive output terminal; a 24th switch element disposed between the 22nd resistor element and the second negative output terminal; a first switch disposed between the node connecting the 21st switch element and the 22nd switch element and the 21st resistor element; and a second switch disposed between the node connecting the 23rd switch element and the 24th switch element and the 22nd resistor element. An output circuit characterized by the following features.

2. An output circuit that outputs an amplitude-modulated signal having a voltage value selected from three or more voltage values, A differential circuit is placed between the first power line and the second power line, The system comprises a switch and a resistor connected in series to form a path connecting the first power line and the second power line, The differential circuit is A first differential output circuit having a first positive output terminal and a first negative output terminal, A second differential output circuit having a second positive output terminal and a second negative output terminal, A first output line connecting the first positive output terminal and the second positive output terminal, The first output terminal and the second output terminal are connected by a second output line, and the amplitude modulation signal is output by the first output line and the second output line. The switch and the resistor suppress changes in the value of the current flowing between the first power line and the second power line due to changes in the operating state of the differential circuit. The output circuit further comprises a first switch arranged on the first output line to disconnect the second differential output circuit from the first differential output circuit, and a second switch arranged on the second output line to disconnect the second differential output circuit from the first differential output circuit. An output circuit characterized by the following features.

3. The system further includes a current path provided in parallel with a load connected between the first output line and the second output line, A third switch and a third resistor are arranged in series in the current path. The output circuit according to feature 1.

4. The operating state of the differential circuit is, A first state in which the first differential output circuit and the second differential output circuit drive a load connected between the first output line and the second output line, This includes a second state in which only the first differential output circuit drives the load, The output circuit according to feature 1.

5. The switch is conductive in the second state. The output circuit according to feature 4.

6. In the first state, the value of the current flowing between the first power line and the second power line through the differential circuit is equal to the value of the current flowing between the first power line and the second power line through the differential circuit and the path in the second state. The output circuit according to feature 5.

7. The system further comprises a capacitor placed between the first power line and the second power line. The output circuit according to feature 1.

8. The differential circuit is further provided with an ESD protection circuit. The output circuit according to feature 1.

9. The first differential output circuit includes an eleventh resistor element disposed between the first power line and the first positive output terminal, an eleventh switch element disposed between the eleventh resistor element and the first positive output terminal, a twelfth switch element disposed between the eleventh resistor element and the first negative output terminal, a twelfth resistor element disposed between the second power line and the first positive output terminal, a thirteenth switch element disposed between the twelfth resistor element and the first positive output terminal, and a fourteenth switch element disposed between the twelfth resistor element and the first negative output terminal. The output circuit according to feature 1.

10. The aforementioned path is arranged to connect the 21st resistive element and the 22nd resistive element. The output circuit according to feature 1.

11. The differential circuit and the control circuit for controlling the switch are further comprising The output circuit according to any one of claims 1 to 10.

12. A pixel array having multiple pixels, A signal processing unit including an AD conversion unit that converts analog signals output from the pixel array into digital signals, An output circuit according to any one of claims 1 to 10, configured to output an amplitude-modulated signal having a voltage value selected from three or more voltage values ​​based on a signal output from the signal processing unit, A photoelectric conversion device characterized by comprising the following features.

13. The photoelectric conversion device according to claim 12, A processor that processes the signal output by the aforementioned photoelectric converter, A photoelectric conversion system characterized by comprising the following features.

14. An electronic device characterized by comprising an output circuit according to any one of claims 1 to 10.

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