Method for manufacturing a semiconductor device, and method for separating a substrate.

Abstract

To provide a method for manufacturing a semiconductor device and a method for peeling a substrate, which enable substrates to be suitably separated from each other after lamination.SOLUTION: A method for manufacturing a semiconductor device includes forming a first insulating film or a first conductor layer on a first substrate, forming a porous layer on the first insulating film or the first conductor layer, forming a first film including a first device on the porous layer, and forming a second film including a second device on a second substrate. The method further includes laminating the first substrate and the second substrate so as to sandwich the first insulating film or the first conductor layer, the porous layer, the first film, and the second film. The method further includes separating the first substrate from the second substrate such that the first insulating film or the first conductor layer and the first portion of the porous layer remain above the first substrate and the second portion of the porous layer remains above the second substrate.SELECTED DRAWING: Figure 6

Description

Technical Field

[0001] Embodiments of the present invention relate to a method for manufacturing a semiconductor device and a method for separating substrates. Background Art

[0002] When a semiconductor device is manufactured by bonding one substrate to another substrate, these bonded substrates may be separated after the bonding step. In this case, it is desirable to adopt a method that can properly separate these substrates. Prior Art Literature Patent Literature

[0003] Patent Literature 1 Japanese Unexamined Patent Publication No. 2013-112880 Patent Literature 2 Japanese Unexamined Patent Publication No. 2022-034881 Summary of Invention Problem to be Solved by the Invention

[0004] To provide a method for manufacturing a semiconductor device and a method for separating substrates, which can properly separate bonded substrates from each other. Means for Solving the Problem

[0005] According to one embodiment, a method for manufacturing a semiconductor device includes forming a first insulating film or a first conductive layer on a first substrate, forming a porous layer on the first insulating film or the first conductive layer, forming a first film including a first device on the porous layer, and forming a second film including a second device on a second substrate. The method further includes bonding the first substrate and the second substrate together such that the first insulating film or the first conductive layer, the porous layer, the first film, and the second film are sandwiched between them. The method further includes separating the first substrate and the second substrate such that the first insulating film or the first conductive layer and a first portion of the porous layer remain above the first substrate, and a second portion of the porous layer remains above the second substrate. [Brief explanation of the drawing]

[0006] [Figure 1] This is a cross-sectional view (1 / 3) showing the structure of the semiconductor manufacturing apparatus according to the first embodiment. [Figure 2] This is a cross-sectional view (2 / 3) showing the structure of the semiconductor manufacturing apparatus according to the first embodiment. [Figure 3] This is a cross-sectional view (3 / 3) showing the structure of the semiconductor manufacturing apparatus according to the first embodiment. [Figure 4] This is a cross-sectional view (1 / 4) showing a method for manufacturing a semiconductor device according to the first embodiment. [Figure 5] This is a cross-sectional view (2 / 4) showing a method for manufacturing a semiconductor device according to the first embodiment. [Figure 6] This is a cross-sectional view (3 / 4) showing a method for manufacturing a semiconductor device according to the first embodiment. [Figure 7] This is a cross-sectional view (4 / 4) showing a method for manufacturing a semiconductor device according to the first embodiment. [Figure 8] This is a cross-sectional view (1 / 2) showing a method for manufacturing a semiconductor device of a comparative example of the first embodiment. [Figure 9] This is a cross-sectional view (2 / 2) showing a method for manufacturing a semiconductor device of a comparative example of the first embodiment. [Figure 10] This is a cross-sectional view showing the structure of the semiconductor device of the first embodiment. [Figure 11]It is a cross-sectional view illustrating the structure of the columnar portion according to the first embodiment. [Figure 12] It is a cross-sectional view illustrating the method of manufacturing the semiconductor device according to the first embodiment. [Figure 13] It is a cross-sectional view (1 / 4) illustrating the method of manufacturing the semiconductor device according to the second embodiment. [Figure 14] It is a cross-sectional view (2 / 4) illustrating the method of manufacturing the semiconductor device according to the second embodiment. [Figure 15] It is a cross-sectional view (3 / 4) illustrating the method of manufacturing the semiconductor device according to the second embodiment. [Figure 16] It is a cross-sectional view (4 / 4) illustrating the method of manufacturing the semiconductor device according to the second embodiment. [Figure 17] It is a cross-sectional view illustrating details of the method of manufacturing the semiconductor device according to the second embodiment. [Figure 18] It is a cross-sectional view illustrating details of the method of manufacturing the semiconductor device according to the second embodiment. MODES FOR CARRYING OUT THE INVENTION

[0007] Hereinafter, embodiments of the present invention will be described with reference to the drawings. In FIGS. 1 to 18, the same components are denoted by the same reference numerals, and overlapping descriptions are omitted.

[0008] (First Embodiment) FIGS. 1 to 3 are cross-sectional views illustrating the structure of the semiconductor manufacturing apparatus 101 according to the first embodiment.

[0009] The semiconductor manufacturing apparatus 101 is, for example, an anodization apparatus that forms a porous layer on the surface of a substrate by an anodization method. FIGS. 1 and 2 show different longitudinal cross-sections of the semiconductor manufacturing apparatus 101. FIG. 3 shows a part of the semiconductor manufacturing apparatus 101 in detail.

[0010] Figures 1 to 3 show mutually perpendicular X direction, Y direction, and Z direction. In this specification, the +Z direction is treated as an upward direction, and the -Z direction is treated as a downward direction. Furthermore, a direction parallel to the Z direction is treated as a vertical direction, and a direction perpendicular to the Z direction is treated as a horizontal direction. The -Z direction may or may not coincide with the direction of gravity.

[0011] A semiconductor manufacturing apparatus 101 includes an outer container 111, an inner container 112, a partition wall 113, a lower holder 121, a transfer robot 122, a plurality of pressure arms 123, an electrode 131, an electrode 132, an electric circuit 133, and a switching circuit 134. The transfer robot 122 includes an upper holder 122a, a suspension unit 122b, and a moving mechanism 122c, and the upper holder 122a includes an upper holder 141, a left holder 142, a right holder 143, a plurality of suspension arms 144, and a locking bar 145. The lower holder 121, the upper holder 141, the left holder 142, and the right holder 143 each include elastic members 121a, 141a, 142a, and 143a, respectively.

[0012] As shown in Figures 1 and 2, the inner container 112 is disposed inside the outer container 111, and the partition wall 113 is disposed inside the inner container 112. As a result, the inner container 112 forms a storage tank T including an inner tank T1 inside the partition wall 113 and an outer tank T2 between the partition wall 113 and the inner container 112. The storage tank T stores an electrolyte solution. The electrolyte solution is supplied to the inner tank T1 from a weighing tank (not shown), and the electrolyte solution overflowing from the inner tank T1 passing over the top of the partition wall 113 is recovered in the outer tank T2. The inner tank T1 can accommodate a plurality of substrates W. The planar shape of these substrates W is, for example, circular or quadrangular. The planar shape of the substrate W illustrated in Figure 1 is quadrangular.

[0013] The lower holder 121 is located inside the inner tank T1. The lower holder 121, together with the upper holder 122a of the transport robot 122, holds multiple substrates W inside the inner tank T1. As shown in Figure 3, the upper holder 122a comprises an upper holder 141, a left holder 142, and a right holder 143. Each substrate W is held by being sandwiched between the lower holder 121, the upper holder 141, the left holder 142, and the right holder 143. Each substrate W is held by the lower holder 121, the upper holder 141, the left holder 142, and the right holder 143 so as to be in contact with elastic members 121a, 141a, 142a, and 143a.

[0014] The transport robot 122 comprises an upper holder 122a, a suspension unit 122b for suspending the upper holder 122a, and a moving mechanism 122c for moving the suspension unit 122b. The transport robot 122 can move the upper holder 122a vertically and horizontally using the suspension unit 122b and the moving mechanism 122c. The suspension unit 122b can move the upper holder 141, the left holder 142, and the right holder 143 using a suspension arm 144 and a locking bar 145.

[0015] The pressurizing arm 123 presses the upper holder 141 downward. As a result, the lower holder 121 is pressed by the upper holder 141 via the left holder 142 and the right holder 143.

[0016] Electrodes 131 and 132 are positioned within the inner chamber T1 and are used to electrically process each substrate W held by the lower holder 121 and the upper holder 122a. Electrodes 131 and 132 can process multiple substrates W held by the lower holder 121 and the upper holder 122a simultaneously (batch processing). For example, if electrode 131 is the anode and electrode 132 is the cathode, a porous layer can be formed on the electrode 132 side of each substrate W.

[0017] The electrical circuit 133 applies a voltage to electrodes 131 and 132. The electrical circuit 133 includes, for example, a DC power supply that applies a DC voltage to electrodes 131 and 132.

[0018] The switching circuit 134 is positioned between the electrical circuit 133 and electrodes 131 and 132. The switching circuit 134 can, for example, switch the polarity of the DC voltage applied from the electrical circuit 133 at a predetermined period.

[0019] Figures 4 to 7 are cross-sectional views showing a method for manufacturing a semiconductor device according to the first embodiment. In this embodiment, a semiconductor device is manufactured by bonding wafer 1 and wafer 2, which will be described later.

[0020] First, a substrate 11 for wafer 1 is prepared (Figure 4(a)). Substrate 11 is, for example, a semiconductor substrate such as a silicon substrate. The resistivity of substrate 11 is, for example, 20 to 30 Ω·cm. Substrate 11 is an example of a first substrate.

[0021] Next, an insulating film 12 is formed on the substrate 11 (Figure 4(b)). The insulating film 12 is, for example, an SiO2 film (silicon oxide film), a SiN film (silicon nitride film), or a SiCN film (silicon carbonitride film). The thickness of the insulating film 12 is, for example, 20 nm or less, preferably 5 to 10 nm. The insulating film 12 is an example of a first insulating film.

[0022] Next, a porous layer 13 is formed on the insulating film 12 (Figure 4(c)). The porous layer 13 is, for example, a porous semiconductor layer such as a porous polysilicon layer. The porous layer 13 is formed, for example, by forming a material layer for forming the porous layer 13 on the insulating film 12 and creating voids in the material layer. In other words, the porous layer 13 is formed by making the material layer porous. If the material layer is a polysilicon layer (semiconductor layer), the porous layer 13 becomes a porous polysilicon layer (porous semiconductor layer). Porousizing the material layer is performed, for example, by setting the substrate 11 on which the insulating film 12 and the material layer are formed in the semiconductor manufacturing apparatus 101 described above, and applying an anodic deposition method to the material layer. As a result, the material layer is transformed into a porous layer 13 by the anodic deposition method.

[0023] If the porous layer 13 is a porous semiconductor layer, the porous layer 13 may contain p-type or n-type impurity atoms. Examples of impurity atoms in the porous layer 13 include boron (B) atoms, phosphorus (P) atoms, arsenic (As) atoms, indium (In) atoms, and gallium (Ga) atoms. In this case, the concentration of p-type or n-type impurity atoms in the porous layer 13 is, for example, 2.5 × 10⁻⁶. 20 atoms / cm 3 That concludes the explanation. The porous layer 13 may contain impurity atoms, for example, if the material layer described above contains impurity atoms. Generally, the lower the resistivity of the material layer, the easier it is to porousize the material layer by the anodic deposition method. According to this embodiment, by setting a high concentration of impurity atoms in the material layer, it is possible to lower the resistivity of the material layer, making it easier to porousize the material layer by the anodic deposition method.

[0024] The resistivity of the porous layer 13 is, for example, less than 1 / 2000th of the resistivity of the substrate 11. Specifically, the resistivity of the porous layer 13 is, for example, about 0.01 Ω·cm. Such low resistivity can be achieved, for example, by adjusting the concentration of impurity atoms in the porous layer 13. The thickness of the porous layer 13 is, for example, 100 to 20000 nm. The porosity of the porous layer 13 is, for example, 40% or more, preferably 50% or more. The porosity of the porous layer 13 represents, for example, the ratio of vacancies per unit area in the porous layer 13. The porosity of the porous layer 13 can be measured, for example, by spectroscopic ellipsometry or gas adsorption. The gas used in the gas adsorption method is, for example, Kr (krypton) gas or N2 (nitrogen) gas.

[0025] During the anodic deposition process, electric charge moves within the substrate 11, the insulating film 12, and the aforementioned material layer. Therefore, it is desirable to reduce the thickness of the insulating film 12 so that it does not hinder the movement of electric charge. For this reason, the thickness of the insulating film 12 is set to, for example, 20 nm or less, and preferably to 5 to 10 nm.

[0026] Furthermore, the anodic deposition method of this embodiment is carried out under conditions such as the following: The current density is, for example, 132 mA / cm². 2 The electrolyte solution used is, for example, a liquid containing HF (hydrogen fluoride) and H2O (water) in a ratio of 1:3.8. Alternatively, the electrolyte solution may also be a liquid containing HF, H2O, and C2H5OH (ethanol). The processing time is, for example, 20 seconds. According to this embodiment, by porousizing the material layer described above instead of the substrate 11, it becomes possible to easily perform porosification by anodic deposition even when using a substrate 11 having high resistivity.

[0027] Next, a diffusion-blocking layer 14 is formed on the porous layer 13 (Figure 5(a)). The diffusion-blocking layer 14 is formed to prevent the diffusion of impurity atoms from the porous layer 13 to the layer later formed on the diffusion-blocking layer 14. The diffusion-blocking layer 14 is, for example, an SiO2 film, a SiN film, or an AlOx film (aluminum oxide film). The thickness of the diffusion-blocking layer 14 is, for example, 10 to 100 nm.

[0028] Next, a device layer 15 is formed on the diffusion prevention layer 14 (Figure 5(b)). The device layer 15 is a layer containing a device, which is a component of the semiconductor device of this embodiment. The device layer 15 includes, for example, a memory cell array of a three-dimensional memory as such a device. The device layer 15 is an example of a first film, and the above device is an example of a first device.

[0029] Next, a substrate 16 for wafer 2 is prepared, and a device layer 17 is formed on the substrate 16 (Figure 5(c)). The substrate 16 is, for example, a semiconductor substrate such as a silicon substrate. Substrate 16 is an example of a second substrate. The device layer 17 is a layer that includes a device which is a component of the semiconductor device of this embodiment. The device layer 17 includes, for example, a circuit that controls the operation of the memory cell array. The device layer 17 is an example of a second film, and the device is an example of a second device.

[0030] Next, wafer 1 and wafer 2 are bonded together (Figure 6(a)). Specifically, substrate 11 and substrate 16 are bonded together with the insulating film 12, porous layer 13, diffusion prevention layer 14, device layer 15, and device layer 17 in between. This bonds substrate 11 and substrate 16 so that device layer 15 and device layer 17 are in contact with each other. Note that device layer 15 and device layer 17 may face each other via another layer instead of facing each other in contact. In Figure 6(a), wafer 1 is shown with its orientation reversed and bonded to wafer 2.

[0031] Figure 6(a) shows a stacked structure including wafer 1 and wafer 2. This stacked structure is divided into multiple chips in a subsequent dicing process. Each chip is, for example, a 3D memory. This stacked structure and each chip after dicing are examples of semiconductor devices.

[0032] Next, the bonded wafers 1 and 2 are separated (Figure 6(b)). However, in this embodiment, wafers 1 and 2 are separated not at the interface between the device layer 15 and the device layer 17, but at a surface within the porous layer 13. Figure 6(b) shows porous layer 13a, which is part of the porous layer 13, and porous layer 13b, which is the remaining part of the porous layer 13. In this embodiment, wafers 1 and 2 are separated such that the porous layer 13 is divided into porous layer 13a and porous layer 13b. Porous layer 13a is an example of the first part, and porous layer 13b is an example of the second part.

[0033] In this embodiment, the substrates 11 and 16, which were bonded together in the process shown in Figure 6(a), are separated in the process shown in Figure 6(b). At this time, the porous layer 13 is divided into porous layer 13a and porous layer 13b as described above. As a result, the insulating film 12 and porous layer 13a remain on substrate 11, while the device layer 17, device layer 15, diffusion prevention layer 14, and porous layer 13b remain on substrate 16.

[0034] In other words, in the process shown in Figure 6(b), the substrate 11 is peeled off from the substrate 16 together with the insulating film 12 and the porous layer 13a. The peeled surface at this time is the surface within the porous layer 13, that is, the surface between the porous layer 13a and the porous layer 13b.

[0035] The porous layer 13 has lower physical hardness compared to the material layer before porosification. Therefore, according to this embodiment, in the process shown in Figure 6(b), wafer 1 and wafer 2 can be easily separated along a surface within the porous layer 13. This surface may be located anywhere within the porous layer 13.

[0036] Next, the porous layer 13b is removed from the wafer 2 (Figure 6(c)). The wafer 2 is then divided into multiple chips by a dicing process. Each chip in this embodiment is, for example, a three-dimensional memory including the memory cell array in the device layer 15 and the circuit in the device layer 17.

[0037] Figure 7(a) shows wafer 1 separated from wafer 2. In the method of this embodiment, the porous layer 13a is then removed from wafer 1 (Figure 7(b)). The porous layer 13a is removed, for example, by wet etching. The chemical used in this wet etching is, for example, a mixed aqueous solution containing HF (hydrofluoric acid), HNO3 (nitric acid), and CH3COOH (acetic acid). The porous layer 13a may also be removed by CMP (Chemical Mechanical Polishing) instead of wet etching.

[0038] When removing the porous layer 13a by wet etching, the insulating film 12 is used as an etching stopper for wet etching. This makes it possible to remove the porous layer 13a without thinning the substrate 11 by wet etching. Generally, when the porous layer 13a is a semiconductor layer, the etching selectivity ratio between the porous layer 13a and the insulating film 12 is large. Also, generally, when the substrate 11 is a semiconductor substrate and the porous layer 13a is a semiconductor layer, the etching selectivity ratio between the substrate 11 and the porous layer 13a is small. That is, the etching selectivity ratio between the substrate 11 and the insulating film 12 is larger than the etching selectivity ratio between the substrate 11 and the porous layer 13a. Therefore, according to this embodiment, by using the insulating film 12 as an etching stopper, it is possible to perform suitable wet etching. Similarly, when removing the porous layer 13a by CMP, the insulating film 12 is used as a polishing stopper for CMP.

[0039] Next, a porous layer 13' similar to the porous layer 13 is formed on the insulating film 12 remaining on the substrate 11 (Figure 7(c)). Then, the process shown in Figures 4(c) to 7(b) is repeated using the wafer 1 containing the porous layer 13'. This makes it possible to reuse the substrate 11 for wafer 1 in the manufacture of semiconductor devices. For example, by repeatedly performing the method of this embodiment using one substrate 11 and N substrates 16, it is possible to manufacture multiple chips (3D memories) from each of the N substrates 16 (where N is an integer of 2 or more).

[0040] Figures 8 and 9 are cross-sectional views showing a method for manufacturing a semiconductor device of a comparative example of the first embodiment.

[0041] Figure 8(a) is a cross-sectional view corresponding to Figure 6(a). In Figure 8(a), wafer 1 and wafer 2 are bonded together. Note that wafer 1 in this comparative example does not contain the insulating film 12.

[0042] Next, wafer 1 and wafer 2 are separated (Figure 8(b)). In this comparative example, wafer 1 and wafer 2 are also separated along the plane within the porous layer 13. As a result, the porous layer 13 is divided into porous layer 13a and porous layer 13b. Consequently, porous layer 13a remains on substrate 11, and device layer 17, device layer 15, diffusion prevention layer 14, and porous layer 13b remain on substrate 16.

[0043] Next, the porous layer 13b is removed from wafer 2 (Figure 8(c)). Afterward, wafer 2 is divided into multiple chips through a dicing process.

[0044] Figure 9(a) shows wafer 1 separated from wafer 2. In the method of this comparative example, the porous layer 13a is then removed from wafer 1 (Figure 9(b)). The porous layer 13a is removed, for example, by wet etching (or CMP).

[0045] In this comparative example, for example, if the substrate 11 is a semiconductor substrate and the porous layer 13 is a semiconductor layer, the etching selectivity ratio between the substrate 11 and the porous layer 13a is small. As a result, the substrate 11 may be thinned by wet etching. Furthermore, since the surface of the substrate 11 is exposed by wet etching, the surface of the substrate 11 may be damaged or otherwise adversely affected by the wet etching. Figure 9(b) shows how the thickness of the substrate 11 has decreased by a thickness D due to thinning. This phenomenon can also occur when the porous layer 13a is removed by CMP.

[0046] Next, a porous layer 13' similar to the porous layer 13 is formed on the substrate 11 (Figure 9(c)). Then, the process shown in Figures 8(a) to 9(b) is repeated using the wafer 1 containing the porous layer 13'. In this case, if the surface of the substrate 11 is damaged or thinned by wet etching or CMP, it may hinder the reuse of the substrate 11. On the other hand, in this embodiment, a porous layer 13a is provided on the substrate 11 via an insulating film 12. This makes it possible to suppress damage to the surface of the substrate 11 or thinning of the substrate 11 due to wet etching or CMP. Therefore, it is possible to remove the porous layer 13a from the substrate 11 to facilitate the reuse of the substrate 11.

[0047] An example of a semiconductor device according to the first embodiment will be described below with reference to Figures 10 to 12.

[0048] Figure 10 is a cross-sectional view showing the structure of a semiconductor device according to the first embodiment. The semiconductor device in Figure 10 is a three-dimensional memory in which an array region 1' derived from wafer 1 and a circuit region 2' derived from wafer 2 are bonded together.

[0049] The array region 1' comprises a device layer 15. The device layer 15 in Figure 10 comprises a memory cell array 15a containing multiple memory cells, an insulating film 15b on the memory cell array 15a, and an interlayer insulating film 15c below the memory cell array 15a. The insulating film 15b is, for example, an SiO2 film or a SiN film. The interlayer insulating film 15c is, for example, a laminated film containing an SiO2 film and other insulating films.

[0050] The circuit region 2' is located beneath the array region 1'. The symbol S indicates the bonding surface between the array region 1' and the circuit region 2'. The circuit region 2' comprises a device layer 17 and a substrate 16 beneath the device layer 17. The device layer 17 in Figure 10 includes an interlayer insulating film 17a between the interlayer insulating film 15c and the substrate 16. The interlayer insulating film 17a is, for example, a laminated film containing an SiO2 film and other insulating films.

[0051] Array region 1' comprises multiple word lines WL and source lines SL as multiple electrode layers within the memory cell array 15a. Figure 10 shows the stepped structure 21 of the memory cell array 15a. Each word line WL is electrically connected to the word wiring layer 23 via a contact plug 22. Each columnar section CL that penetrates the multiple word lines WL is electrically connected to the bit line BL via a via plug 24 and is also electrically connected to the source line SL. The source line SL includes a first layer SL1 which is a semiconductor layer and a second layer SL2 which is a metal layer.

[0052] Circuit region 2' comprises a plurality of transistors 31. Each transistor 31 comprises a gate electrode 32 provided on the substrate 16 via a gate insulating film, and a source diffusion layer and a drain diffusion layer (not shown) provided within the substrate 16. Circuit region 2' also comprises a plurality of contact plugs 33, a wiring layer 34, and a wiring layer 35. The plurality of contact plugs 33 are provided on the respective gate electrode 32, source diffusion layer, or drain diffusion layer of the plurality of transistors 31. The wiring layer 34 is provided on the plurality of contact plugs 33 and contains a plurality of wires. The wiring layer 35 is provided on the wiring layer 34 and contains a plurality of wires.

[0053] The circuit region 2' further comprises a wiring layer 36 provided on the wiring layer 35 and containing multiple wirings, multiple via plugs 37 provided on the wiring layer 36, and multiple metal pads 38 provided on these via plugs 37. The metal pads 38 include, for example, a Cu (copper) layer or an Al (aluminum) layer. The circuit region 2' functions as a control circuit (logic circuit) that controls the operation of the array region 1'. This control circuit is composed of transistors 31 and the like and is electrically connected to the metal pads 38.

[0054] The array region 1' comprises a plurality of metal pads 41 provided on a metal pad 38 and a plurality of via plugs 42 provided on the metal pads 41. The array region 1' also comprises a wiring layer 43 provided on these via plugs 42 and containing a plurality of wirings, and a wiring layer 44 provided on the wiring layer 43 and containing a plurality of wirings. The metal pads 41 include, for example, a Cu layer or an Al layer. The aforementioned bit line BL is included in the wiring layer 44. The control circuit described above is electrically connected to the memory cell array 15a via the metal pads 41, 38, etc., and controls the operation of the memory cell array 15a via the metal pads 41, 38, etc.

[0055] The array region 1' further comprises a plurality of via plugs 45 provided on the wiring layer 44, metal pads 46 provided on these via plugs 45 and on the insulating film 15b, and a passivation film 47 provided on the metal pads 46 and on the insulating film 15b. The metal pads 46 include, for example, a Cu layer or an Al layer and function as external connection pads (bonding pads) of the semiconductor device in Figure 10. The passivation film 47 is, for example, a multilayer film including an SiO2 film and other insulating films and has an opening P that exposes the upper surface of the metal pads 46. The metal pads 46 can be connected to a mounting substrate or other devices via this opening P using bonding wires, solder balls, metal bumps, etc.

[0056] Figure 11 is a cross-sectional view showing the structure of the columnar portion CL of the first embodiment.

[0057] As shown in Figure 11, the memory cell array 15a comprises multiple word lines WL and multiple insulating films 51 alternately stacked on top of the interlayer insulating film 15c (Figure 10). The word lines WL are, for example, W (tungsten) layers. The insulating films 51 are, for example, SiO2 films.

[0058] The columnar portion CL includes, in order, a block insulating film 52, a charge storage layer 53, a tunnel insulating film 54, a channel semiconductor layer 55, and a core insulating film 56. The charge storage layer 53 is, for example, a SiN film and is formed on the side surfaces of the word line WL and the insulating film 51 via the block insulating film 52. The charge storage layer 53 may also be a semiconductor layer such as a polysilicon layer. The channel semiconductor layer 55 is, for example, a polysilicon layer and is formed on the side surfaces of the charge storage layer 53 via the tunnel insulating film 54. The block insulating film 52, the tunnel insulating film 54, and the core insulating film 56 are, for example, SiO2 films.

[0059] Figure 12 is a cross-sectional view showing a method for manufacturing a semiconductor device according to the first embodiment.

[0060] Figure 12 shows wafer 1 containing multiple array regions 1' and wafer 2 containing multiple circuit regions 2'. The orientation of wafer 1 in Figure 12 is the opposite of the orientation of array regions 1' in Figure 10. In this embodiment, a semiconductor device is manufactured by bonding wafer 1 and wafer 2 together. Figure 12 shows wafer 1 before its orientation is reversed for bonding, and Figure 10 shows array regions 1' after their orientation has been reversed for bonding, and after bonding and dicing.

[0061] In Figure 12, the symbol S1 indicates the top surface of wafer 1, and the symbol S2 indicates the top surface of wafer 2. Wafer 1 comprises a substrate 11 provided via a diffusion prevention layer 14, a porous layer 13, and an insulating film 12 beneath an insulating film 15b.

[0062] In this embodiment, first, as shown in Figure 12, an insulating film 12, a porous layer 13, a diffusion prevention layer 14, an insulating film 15b, a memory cell array 15a, an interlayer insulating film 15c, a metal pad 41, etc. are formed on the substrate 11 of wafer 1. For example, a via plug 45, a wiring layer 44, a wiring layer 43, a via plug 42, and a metal pad 41 are formed in order above the substrate 11. In addition, an interlayer insulating film 17a, a transistor 31, a metal pad 38, etc. are formed on the substrate 16 of wafer 2. For example, a contact plug 33, a wiring layer 34, a wiring layer 35, a wiring layer 36, a via plug 37, and a metal pad 38 are formed in order above the substrate 16.

[0063] Next, as shown in Figure 10, wafer 1 and wafer 2 are bonded together by mechanical pressure. This bonds the interlayer insulating film 15c and the interlayer insulating film 17a. Next, wafer 1 and wafer 2 are annealed at 400°C. This bonds the metal pad 41 and the metal pad 38.

[0064] Subsequently, substrate 11 and substrate 16 are separated along the plane within the porous layer 13, and substrate 16 and the various layers on substrate 16 are cut into multiple chips. In this way, the semiconductor device shown in Figure 10 is manufactured. The metal pad 46 and passivation film 47 are formed on the insulating film 15b, for example, after separating substrate 11 and substrate 16 and removing the porous layer 13b and diffusion prevention layer 14 on substrate 16.

[0065] As described above, in this embodiment, a porous layer 13 is formed on the substrate 11 via an insulating film 12, and the substrate 11 and the substrate 16 are bonded together. Furthermore, after bonding the substrate 11 and the substrate 16, the substrate 11 and the substrate 16 are separated. Therefore, according to this embodiment, it is possible to suitably separate these substrates 11 and 16 after bonding. For example, it is possible to easily separate the substrate 11 and the substrate 16 along the surface within the porous layer 13, or to remove the porous layer 13a from the substrate 11 in a manner suitable for the reuse of the substrate 11. In addition, by using the insulating film 12 as a stopper when removing the porous layer 13a from the substrate 11, it is possible to increase the selectivity ratio between the porous layer 13a and the stopper.

[0066] (Second Embodiment) Figures 13 to 16 are cross-sectional views showing a method for manufacturing a semiconductor device according to a second embodiment.

[0067] The method of this embodiment is carried out using a conductive layer 18 instead of an insulating film 12. The conductive layer 18 is an example of a first conductive layer. In the description of the second embodiment, explanations of matters common to the first and second embodiments will be omitted as appropriate.

[0068] First, a substrate 11 for wafer 1 is prepared (Figure 13(a)). Substrate 11 is, for example, a semiconductor substrate such as a silicon substrate.

[0069] Next, a conductive layer 18 is formed on the substrate 11 (Figure 13(b)). While the semiconductor layer is a layer made of semiconductor material, the conductive layer 18 is a layer made of conductor material. The conductive layer 18 is, for example, a metal layer or a graphite layer. The thickness of the conductive layer 18 is, for example, 10 to 100 nm. The resistivity of the conductive layer 18 is, for example, 0.05 Ω·cm or less.

[0070] Next, a porous layer 13 is formed on the conductive layer 18 (Figure 13(c)). The porous layer 13 is a porous semiconductor layer, such as a porous polysilicon layer. The porous layer 13 is formed, for example, by forming a material layer for forming the porous layer 13 on the conductive layer 18 and creating voids in the material layer. In other words, the porous layer 13 is formed by making the material layer porous. Porous formation of the material layer is performed, for example, by setting the substrate 11 in the semiconductor manufacturing apparatus 101 described above and applying an anodic deposition method to the material layer.

[0071] Next, a diffusion prevention layer 14 is formed on the porous layer 13 (Figure 14(a)). Next, a device layer 15 is formed on the diffusion prevention layer 14 (Figure 14(b)). Next, a substrate 16 for wafer 2 is prepared, and a device layer 17 is formed on the substrate 16 (Figure 14(c)).

[0072] Next, wafer 1 and wafer 2 are bonded together (Figure 15(a)). Specifically, substrate 11 and substrate 16 are bonded together with the conductive layer 18, porous layer 13, diffusion prevention layer 14, device layer 15, and device layer 17 sandwiched between them.

[0073] Next, the bonded wafer 1 and wafer 2 are separated (Figure 15(b)). In this embodiment, wafer 1 and wafer 2 are separated such that the porous layer 13 is divided into porous layer 13a and porous layer 13b.

[0074] In this embodiment, the substrates 11 and 16, which were bonded together in the process shown in Figure 15(a), are separated in the process shown in Figure 15(b). At this time, the porous layer 13 is divided into porous layer 13a and porous layer 13b as described above. As a result, the conductive layer 18 and porous layer 13a remain on substrate 11, and the device layer 17, device layer 15, diffusion prevention layer 14, and porous layer 13b remain on substrate 16.

[0075] Next, the porous layer 13b is removed from wafer 2 (Figure 15(c)). Afterward, wafer 2 is divided into multiple chips through a dicing process.

[0076] Figure 16(a) shows wafer 1 separated from wafer 2. In this method, the porous layer 13a is then removed from wafer 1 (Figure 16(b)). The porous layer 13a is removed, for example, by wet etching. The chemical used in this wet etching is, for example, a mixed aqueous solution containing HF, HNO3, and CH3COOH. The porous layer 13a may also be removed by CMP instead of wet etching.

[0077] When removing the porous layer 13a by wet etching, the conductive layer 18 is used as an etching stopper for wet etching. This makes it possible to remove the porous layer 13a without thinning the substrate 11 by wet etching. Generally, when the porous layer 13a is a semiconductor layer, the etching selectivity ratio between the porous layer 13a and the conductive layer 18 is large. Also, generally, when the substrate 11 is a semiconductor substrate and the porous layer 13a is a semiconductor layer, the etching selectivity ratio between the substrate 11 and the porous layer 13a is small. That is, the etching selectivity ratio between the substrate 11 and the conductive layer 18 is larger than the etching selectivity ratio between the substrate 11 and the porous layer 13a. Therefore, according to this embodiment, by using the conductive layer 18 as an etching stopper, it is possible to perform suitable wet etching. Similarly, when removing the porous layer 13a by CMP, the conductive layer 18 is used as a polishing stopper for CMP.

[0078] Next, a porous layer 13' similar to the porous layer 13 is formed on the conductive layer 18 remaining on the substrate 11 (Figure 16(c)). Then, the process shown in Figures 13(c) to 16(b) is repeated using the wafer 1 containing the porous layer 13'. This makes it possible to reuse the substrate 11 for wafer 1 in the manufacture of semiconductor devices.

[0079] Figure 17 is a cross-sectional view showing details of the manufacturing method of a semiconductor device according to the second embodiment.

[0080] Figure 17 shows the substrate 11, conductive layer 18, and porous layer 13 during the anodic deposition process. Figure 17 further shows the charges used in the anodic deposition process. During anodic deposition, charges move within the substrate 11, conductive layer 18, and the aforementioned material layers. In the first embodiment, the insulating film 12 may hinder the movement of charges. Therefore, in the first embodiment, it is desirable to reduce the thickness of the insulating film 12 so that it does not hinder the movement of charges. On the other hand, according to this embodiment, by using the conductive layer 18 instead of the insulating film 12, it is possible to suppress such hindering of charge movement. For this reason, the resistivity of the conductive layer 18 is preferably low, for example, preferably 0.05 Ω·cm or less. Examples of preferred conductive layers 18 are metal layers and graphite layers.

[0081] Figure 18 is a cross-sectional view showing details of the manufacturing method of a semiconductor device according to the second embodiment.

[0082] Figures 18(a) and 18(b) show wafer 1 as shown in Figures 16(a) and 16(b), respectively, i.e., wafer 1 before and after the removal of the porous layer 13a. However, Figure 18(a) shows the maximum thickness Tmax, minimum thickness Tmin, and average thickness T of the porous layer 13a. Note that in Figure 18(a), the porous layer 13a has a shape with an inclined upper surface, but it may have other shapes. For example, the porous layer 13a may have a shape with an uneven upper surface. In this case, for example, the thickness of the porous layer 13a at the highest point of the convex portion of the upper surface of the porous layer 13a becomes the maximum thickness Tmax, and the thickness of the porous layer 13a at the lowest point of the concave portion of the upper surface of the porous layer 13a becomes the minimum thickness Tmin.

[0083] When removing the porous layer 13a by wet etching, it is desirable to etch the porous layer 13a to a thickness greater than the average thickness T, for example, to about 1.3 times the average thickness T. This makes it possible to completely remove the porous layer 13a in most cases. For example, it is possible to suppress the remaining porous layer 13a in the portion having the maximum thickness Tmax after etching. This is also true when removing the porous layer 13a by CMP. Since the surface of the porous layer 13a is often rough, it is preferable to perform wet etching or CMP in this manner. In this embodiment, a rough surface of the porous layer 13a means that the thickness of the porous layer 13a differs depending on the position in the X or Y direction. Furthermore, according to the method of this embodiment, it is possible to suppress the excessive removal of the conductive layer 18 when removing the porous layer 13a by wet etching. Therefore, it is possible to leave the conductive layer 18 on the substrate 11 so that the substrate 11 can be easily reused.

[0084] While it is stated that the etching thickness should be set to approximately 1.3 times the average thickness T, this is not limited to this. For example, the etching thickness may be set according to the difference between the maximum thickness Tmax and the minimum thickness Tmin of the porous layer 13a shown in Figure 18(a). In other words, the etching thickness may be set according to the variation in the film thickness of the porous layer 13a after the bonded wafers 1 and 2 have been separated.

[0085] As described above, in this embodiment, a porous layer 13 is formed on the substrate 11 via a conductive layer 18, and the substrate 11 and the substrate 16 are bonded together. Furthermore, after bonding the substrate 11 and the substrate 16, the substrate 11 and the substrate 16 are separated. Therefore, according to this embodiment, it is possible to suitably separate the substrates 11 and 16 after bonding. For example, it is possible to easily separate the substrate 11 and the substrate 16 along the surface within the porous layer 13, or to remove the porous layer 13a from the substrate 11 in a manner suitable for the reuse of the substrate 11. In addition, by using the conductive layer 18 as a stopper when removing the porous layer 13a from the substrate 11, it is possible to increase the selectivity ratio between the porous layer 13a and the stopper.

[0086] Although several embodiments have been described above, these embodiments are presented only as examples and are not intended to limit the scope of the invention. The novel methods described herein can be carried out in a variety of other forms. Furthermore, various omissions, substitutions, and modifications can be made to the forms of the methods described herein, without departing from the spirit of the invention. The appended claims and equivalents are intended to include such forms and modifications that fall within the scope and spirit of the invention. [Explanation of symbols]

[0087] 1: Wafer, 1': Array area, 2: Wafer, 2': Circuit area, 11: Substrate, 12: Insulating film, 13: Porous layer, 13a: Porous layer, 13b: Porous layer, 13': Porous layer, 14: Diffusion prevention layer, 15: Device layer, 15a: Memory cell array, 15b: Insulating film, 15c: Interlayer insulating film, 16: Substrate, 17: Device layer, 17a: Interlayer insulating film, 18: Conductor layer, 21: Staircase structure, 22: Contact plug, 23: Word wiring layer, 24: Via plug, 31: Transistor, 32: Gate electrode, 33: Contact plug, 34: Wiring layer, 35: Wiring layer, 36: Wiring layer, 37: Via plug, 38: Metal pad, 41: Metal pad, 42: Via plug, 43: Wiring layer, 44: Wiring layer, 45: Via plug, 46: Metal pad, 47: Passivation membrane, 51: insulating film, 52: block insulating film, 53: charge storage layer, 54: Tunnel insulating film, 55: Channel semiconductor layer, 56: Core insulating film, 101: Semiconductor manufacturing equipment, 111: Outer container, 112: Inner container, 113: Partition, 121: Lower holder, 121a: Elastic member, 122: Transport robot, 122a: Upper holder, 122b: Suspension unit, 122c: Moving mechanism, 123: Pressurizing arm, 131: Electrode, 132: Electrode, 133: Electrical circuit, 134: Switching circuit, 141: Upper holder, 141a: Elastic member, 142: Left holder, 142a: Elastic member, 143: Right-side holder, 143a: Elastic member, 144: Suspension arm, 145: Locking bar

Claims

1. A first insulating film or a first conductive layer is formed on the first substrate. A porous layer is formed on the first insulating film or the first conductive layer. A first film including the first device is formed on the porous layer. A second film containing a second device is formed on the second substrate. The first substrate and the second substrate are bonded together such that the first insulating film or the first conductive layer, the porous layer, the first film, and the second film are sandwiched between them. The first substrate and the second substrate are separated such that the first insulating film or the first conductive layer and the first portion of the porous layer remain above the first substrate, and the second portion of the porous layer remains above the second substrate. A method for manufacturing a semiconductor device, including the following.

2. A method for manufacturing a semiconductor device according to claim 1, further comprising removing the first portion from the first substrate after separating the first substrate and the second substrate.

3. The method for manufacturing a semiconductor device according to claim 2, wherein the first portion is removed from the first substrate by CMP (Chemical Mechanical Polishing) or wet etching.

4. The method for manufacturing a semiconductor device according to claim 1, wherein the etching selectivity ratio between the first insulating film or the first conductive layer and the first substrate is greater than the etching selectivity ratio between the porous layer and the first substrate.

5. The method for manufacturing a semiconductor device according to claim 1, wherein the porous layer is a semiconductor layer.

6. The method for manufacturing a semiconductor device according to claim 5, wherein the semiconductor layer contains p-type impurity atoms or n-type impurity atoms.

7. The concentration of the p-type impurity atoms or the n-type impurity atoms in the semiconductor layer is 2.5 × 10⁻⁶ ２０ atoms / cm ３ The method for manufacturing a semiconductor device according to claim 6.

8. The porous layer is formed by an anodic deposition method, as described in claim 1, for the method of manufacturing a semiconductor device.

9. The method for manufacturing a semiconductor device according to claim 1, wherein the porosity of the porous layer is 40% or more.

10. The method for manufacturing a semiconductor device according to claim 1, wherein the thickness of the porous layer is 100 to 20,000 nm.

11. The method for manufacturing a semiconductor device according to claim 1, wherein the resistivity of the porous layer is 1 / 2000 or less of the resistivity of the first substrate.

12. The method for manufacturing a semiconductor device according to claim 1, wherein the resistivity of the first substrate is 20 to 30 Ω·cm.

13. The method for manufacturing a semiconductor device according to claim 1, wherein the first insulating film comprises silicon.

14. The method for manufacturing a semiconductor device according to claim 1, wherein the thickness of the first insulating film is 20 nm or less.

15. The method for manufacturing a semiconductor device according to claim 1, wherein the first conductive layer is a metal layer or a graphite layer.

16. The method for manufacturing a semiconductor device according to claim 1, wherein the thickness of the first conductive layer is 10 to 100 nm.

17. The method for manufacturing a semiconductor device according to claim 1, wherein the resistivity of the first conductor layer is 0.05 Ω·cm or less.

18. The first device includes a memory cell array, The second device includes a circuit for controlling the memory cell array, A method for manufacturing a semiconductor device according to claim 1.

19. A first insulating film or a first conductive layer is formed on the first substrate. A porous layer is formed on the first insulating film or the first conductive layer. The first substrate and the second substrate are bonded together such that the first insulating film or the first conductive layer and the porous layer are sandwiched between them. The first substrate and the second substrate are separated such that the first insulating film or the first conductive layer and the first portion of the porous layer remain above the first substrate, and the second portion of the porous layer remains above the second substrate. A method for separating substrates, including the following.

20. The method for separating substrates according to claim 19, further comprising removing the first portion from the first substrate after separating the first substrate and the second substrate, and then reusing the first substrate.

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