Semiconductor equipment

Abstract

To provide a semiconductor device whose reverse recovery characteristic at diode operation is improved.SOLUTION: An embodiment includes a first electrode, a second electrode, a semiconductor part, a gate electrode, and a structure. The semiconductor part is provided between the first electrode and the second electrode. The gate electrode is provided between the semiconductor part and the second electrode. The structure extends into the semiconductor part under the gate electrode. The semiconductor part includes first to fifth layers. The first to fifth layers are stacked in this order. The first to third layers and the fifth layer are of a first conductivity type. The fourth layer is of a second conductivity type. The gate electrode faces the fourth layer. The structure includes an insulating film, a conductor, an insulating layer, and a silicide layer. The silicide layer is provided at a lower end of the structure. The lower end of the structure is in contact with the second layer. The second layer contains a heavy metal. The concentration of the heavy metal in the third layer is lower than that in the second layer.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The embodiments relate to semiconductor devices. [Background technology]

[0002] A metal oxide semiconductor field effect transistor (MOSFET) incorporates a diode connected in antiparallel. When the diode is operating, it is preferable to improve the reverse recovery characteristics.

[0003] One known method to improve the reverse recovery characteristics during diode operation is to introduce heavy metals or other substances into the drift layer to control the lifetime of minority carriers in the drift layer. [Prior art documents] [Patent Documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 2022-141955 [Overview of the project] [Problems that the invention aims to solve]

[0005] The embodiment aims to provide a semiconductor device with improved reverse recovery characteristics during diode operation. [Means for solving the problem]

[0006] The semiconductor device according to this embodiment includes a first electrode, a second electrode, a semiconductor portion provided between the first electrode and the second electrode, a gate electrode provided within the semiconductor portion and extending from the second electrode toward the first electrode, and a structure provided between the gate electrode and the first electrode and extending within the semiconductor portion from the gate electrode side toward the first electrode side. The semiconductor portion includes a first layer of a first conductivity type provided on the first electrode and electrically connected to the first electrode, a second layer of a first conductivity type provided on the first layer and containing a heavy metal, a third layer of a first conductivity type provided on the second layer and containing the heavy metal at a lower concentration than that of the second layer, a fourth layer of a second conductivity type provided on the third layer, facing the gate electrode via a gate insulating film and electrically connected to the second electrode, and a fifth layer of a first conductivity type provided on the fourth layer and electrically connected to the second electrode. The structure includes a silicide layer in contact with the second layer, an insulating layer provided on the silicide layer, a conductor provided on the insulating layer, extending from below the gate electrode toward the insulating layer and electrically isolated from the gate electrode, and an insulating film provided between the conductor and the second layer, and between the conductor and the third layer. The bottom surface and at least a portion of the side surface of the silicide layer are in contact with the second layer. [Brief explanation of the drawing]

[0007] [Figure 1] This is a schematic plan view illustrating a semiconductor device according to the first embodiment. [Figure 2] This is a schematic cross-sectional view taken along line AA in Figure 1. [Figure 3] This is a schematic enlarged view of section B in Figure 2. [Figure 4] This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device according to the first embodiment. [Figure 5] This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device according to the first embodiment. [Figure 6] This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device according to the first embodiment. [Figure 7]It is a schematic cross-sectional view illustrating the method for manufacturing a semiconductor device according to the first embodiment. [Figure 8] It is a schematic cross-sectional view illustrating the method for manufacturing a semiconductor device according to the first embodiment. [Figure 9] It is a schematic cross-sectional view illustrating the method for manufacturing a semiconductor device according to the first embodiment. [Figure 10] It is a schematic cross-sectional view illustrating the method for manufacturing a semiconductor device according to the first embodiment. [Figure 11] It is a schematic cross-sectional view illustrating the method for manufacturing a semiconductor device according to the first embodiment. [Figure 12] It is a schematic cross-sectional view illustrating the method for manufacturing a semiconductor device according to the first embodiment. [Figure 13] It is a schematic cross-sectional view illustrating the method for manufacturing a semiconductor device according to the first embodiment. [Figure 14] It is a schematic cross-sectional view illustrating the method for manufacturing a semiconductor device according to the first embodiment. [Figure 15] It is a schematic cross-sectional view illustrating the method for manufacturing a semiconductor device according to the first embodiment. [Figure 16] It is a schematic cross-sectional view illustrating the method for manufacturing a semiconductor device according to the first embodiment. [Figure 17] It is a schematic cross-sectional view illustrating the method for manufacturing a semiconductor device according to the first embodiment. [Figure 18] It is a schematic cross-sectional view illustrating the method for manufacturing a semiconductor device according to the first embodiment. [Figure 19] It is a schematic cross-sectional view illustrating the method for manufacturing a semiconductor device according to the first embodiment. [Figure 20] It is a schematic cross-sectional view illustrating the method for manufacturing a semiconductor device according to the first embodiment. [Figure 21] It is a schematic cross-sectional view illustrating the method for manufacturing a semiconductor device according to the first embodiment. [Figure 22] It is a schematic cross-sectional view illustrating the method for manufacturing a semiconductor device according to the first embodiment. [Figure 23]This is a schematic cross-sectional view illustrating a semiconductor device according to the second embodiment. [Figure 24] This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device according to a second embodiment. [Figure 25] This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device according to a second embodiment. [Figure 26] This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device according to a second embodiment. [Figure 27] This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device according to a second embodiment. [Modes for carrying out the invention]

[0008] Each embodiment of the present invention will be described below with reference to the drawings. Drawings are schematic or conceptual, and the relationships between the thickness and width of each part, as well as the ratios of the sizes of different parts, are not necessarily identical to those of reality. Even when representing the same part, the dimensions and ratios may be depicted differently in different drawings. In this specification and in each figure, elements similar to those already described are denoted by the same reference numerals, and detailed explanations are omitted as appropriate. In the following description and drawings, n + , n - and p + The notation "p" indicates the relative level of each impurity concentration. That is, a notation with "+" indicates a relatively higher impurity concentration than a notation without either "+" or "-", and a notation with "-" indicates a relatively lower impurity concentration than a notation without either. When both p-type and n-type impurities are present in each region, these notations represent the relative level of the net impurity concentration after the impurities have compensated for each other. Each embodiment described below may be implemented by reversing the p-type and n-type of each semiconductor region.

[0009] (First Embodiment) Figure 1 is a schematic plan view illustrating a semiconductor device according to the first embodiment. Figure 2 is a schematic cross-sectional view taken along line AA in Figure 1. Figure 3 is a schematic enlarged view of section B in Figure 2. As shown in Figures 1 and 2, the semiconductor device 100 according to this embodiment comprises a first electrode 1, a second electrode 2, a semiconductor portion 10, a gate electrode 21, and a structure 40. The semiconductor portion 10 is provided between the first electrode 1 and the second electrode 2. The first electrode 1 is provided on the back surface of the semiconductor portion 10 and functions as a drain electrode. The second electrode 2 is provided on the front surface side of the semiconductor portion and functions as a source electrode E2. The gate electrode 21 faces the semiconductor portion 10 via a gate insulating film 31. The gate electrode 21 is electrically connected to a gate electrode pad G1. The source electrode E2 and the gate electrode pad G1 are arranged separately in a plan view and are electrically isolated. In this example, an insulating layer K1 may be provided between the source electrode E2 and the gate electrode pad G1, but an insulating layer K1 may not be provided between the source electrode E2 and the gate electrode pad G1.

[0010] The semiconductor device 100 is a MOSFET having a gate electrode 21, with a first electrode 1 as the drain electrode and a second electrode 2 as the source electrode E2. In the diode operation of the semiconductor device 100, if the semiconductor device 100 is an n-channel MOSFET, the first electrode 1 functions as the cathode electrode and the second electrode 2 functions as the anode electrode. If the semiconductor device 100 is a p-channel MOSFET, the first electrode 1 functions as the anode electrode and the second electrode 2 functions as the cathode electrode.

[0011] As shown in Figure 2, the semiconductor portion 10 includes a first layer 11, a second layer 12, a third layer 13, a fourth layer 14, and a fifth layer 15. The first layer 11, the second layer 12, the third layer 13, and the fifth layer 15 are semiconductor layers of the first conductivity type. The fourth layer is a semiconductor layer of the second conductivity type. The semiconductor portion 10 further includes a sixth layer 16. The sixth layer 16 is a semiconductor layer of the second conductivity type. The semiconductor portion 10 includes, for example, Si.

[0012] The first layer 11 is provided on the first electrode 1. The first layer 11 is a semiconductor substrate.

[0013] The second layer 12 is provided on the first layer 11. The impurity concentration of the first conductivity type in the second layer 12 is lower than that of the first conductivity type in the first layer 11. In addition to the impurities of the first conductivity type, the second layer 12 contains heavy metal 12a. The heavy metal 12a is, for example, Pt or Au. In the second layer 12, the concentration of Pt or Au is 1 × 10⁻⁶. 13 cm -3 ~1 × 10 20 cm -3 The second layer 12 is an n-type drift layer into which heavy metals have been introduced.

[0014] In the specific example shown in Figure 2, the second layer 12 is provided on the first layer 11 and is in contact with the first layer 11. However, a semiconductor layer having an impurity concentration of a first conductivity type approximately equal to the impurity concentration of the first conductivity type in the second layer may be provided between the second layer 12 and the first layer 11, in which the concentration of heavy metal 12a is lower than the concentration of heavy metal 12a in the second layer 12.

[0015] The third layer 13 is provided on the second layer 12. The impurity concentration of the first conductivity type in the third layer 13 is approximately the same as that of the second layer 12, and lower than that of the first conductivity type in the first layer 11. The third layer 13 is, for example, an n-type drift layer.

[0016] The third layer 13 may contain heavy metal 12a. The concentration of heavy metal 12a in the third layer 13 is lower than the concentration of heavy metal 12a in the second layer 12. Preferably, the concentration of heavy metal 12a in the third layer 13 is approximately zero. For example, the concentration of heavy metal 12a in the third layer 13 decreases as it moves away from the second layer 12. By making the concentration of heavy metal 12a in the third layer 13 sufficiently low, the leakage current when a reverse bias is applied between the first electrode 1 and the second electrode 2 while the semiconductor device 100 is in the off state can be reduced.

[0017] The fourth layer 14 is provided on the third layer 13. The fourth layer 14 is, for example, a p-type base layer.

[0018] The fifth layer 15 is provided on the fourth layer 14. The impurity concentration of the first conductivity type in the fifth layer 15 is higher than that of the second layer 12 and higher than that of the third layer 13. The fifth layer 15 is, for example, an n-type contact layer.

[0019] The sixth layer 16 is selectively provided on the third layer 13. The fourth layer 14 is provided on the sixth layer 16. The fourth layer 14 is provided on the side surface of the sixth layer 16. The impurity concentration of the second conductivity type in the sixth layer 16 is higher than the impurity concentration of the second conductivity type in the fourth layer 14. The sixth layer 16 is, for example, a p-type contact layer.

[0020] An interlayer insulating film 60 is provided on the fifth layer 15. A second electrode 2 is provided on the interlayer insulating film 60.

[0021] The second electrode 2 includes a connecting portion 2a that penetrates the interlayer insulating film 60. The connecting portion 2a penetrates the fifth layer 15 and the fourth layer 14 and reaches the sixth layer 16. The connecting portion 2a is electrically connected to the fifth layer 15, the fourth layer 14, and the sixth layer 16. The fifth layer 15, the fourth layer 14, and the sixth layer 16 are electrically connected to the second electrode 2 via the connecting portion 2a.

[0022] The following explanation may use the XYZ coordinate system. The first layer 11 has a first surface 11a. The first surface 11a is a plane. The second layer 12 is provided on the first surface 11a. The XY plane is assumed to be parallel to the first surface 11a. The direction from the first electrode 1 to the second electrode 2 is considered to be the Z-axis direction and is sometimes referred to as the Z-direction. A view of the semiconductor device 100 from the Z-direction is a plan view.

[0023] The gate electrode 21 is provided between the second electrode 2 and the first electrode 1. The gate electrode 21 extends in the Z direction within the semiconductor portion 10. Multiple gate electrodes 21 are provided. In the example in Figure 2, the multiple gate electrodes 21 are arranged at equal intervals in the X direction. The multiple gate electrodes 21 are also arranged at equal intervals in the Y direction, for example. In a plan view, the gate electrodes 21 are arranged, for example, in a matrix.

[0024] The gate electrode 21 faces the fourth layer 14 via the gate insulating film 31. In the specific example shown in Figure 2, the gate electrode 21 faces the fifth layer 15 via the gate insulating film 31. Alternatively, the gate electrode 21 may also face a portion of the third layer 13 via the gate insulating film 31.

[0025] The gate electrode 21, for example, contains polycrystalline Si containing impurities of the first conductivity type.

[0026] The structure 40 is provided between the gate electrode 21 and the first electrode 1. The structure 40 extends in the Z direction within the semiconductor portion 10. The structure 40 is in contact with the third layer 13 on its side surface. The structure 40 is in contact with the second layer 12 on its bottom surface. The structure 40 is in contact with the second layer 12 on a portion of its side surface that is continuous with the bottom surface.

[0027] The structure 40 includes an insulating film 41, a conductor 42, an insulating layer 43, and a silicide layer 45. The conductor 42 extends in the Z direction below the gate electrode 21. The insulating film 41 is provided between the gate electrode 21 and the conductor 42. The conductor 42 is provided on the insulating layer 43. The insulating layer 43 is provided on the silicide layer 45. The silicide layer 45 is provided on the second layer 12.

[0028] The insulating film 41 extends in the Z direction below the gate electrode 21. In the specific example shown in Figure 2, the insulating film 41 is provided continuously from the gate insulating film 31.

[0029] The insulating film 41 surrounds the conductor 42, the insulating layer 43, and the silicide layer 45. The silicide layer 45 is in contact with the second layer 12 on the second layer 12, and the second layer 12 is in contact with the bottom surface of the silicide layer 45 and a portion of the side surface continuous with the bottom surface.

[0030] As shown in Figure 3, the lower end of the insulating film 41 is located at a distance Z1 in the Z direction from the first surface 11a. The lower end of the silicide layer 45 is located at a distance Z2 in the Z direction from the first surface 11a. The relationship between distances Z1 and Z2 is Z1 > Z2, and Z1 - Z2 = ΔZ > 0. In other words, the silicide layer 45 protrudes from the insulating film 41 of the structure 40 toward the second layer 12.

[0031] In the structure 40, the conductor 42 extends in the Z direction and faces the third layer 13 via the insulating film 41. The conductor 42 functions as a field plate, mitigating the electric field in the third layer 13 caused by the reverse bias voltage applied between the first electrode 1 and the second electrode 2. Preferably, the conductor 42 faces the third layer 13 via the insulating film 41 from its upper end 42T to its lower end 42B.

[0032] The insulating film 41 and the insulating layer 43 include, for example, silicon oxide. The crystalline structure of the insulating film 41 and the crystalline structure of the insulating layer 43 may differ. The conductor 42 includes, for example, polycrystalline Si containing impurities of a first conductivity type. The silicide layer 45 includes, for example, Pt and Pt silicide.

[0033] The operation and effects of the semiconductor device 100 according to this embodiment will be described. The operation of the semiconductor device 100 will be described below, assuming that the first conductivity type is n-type and the second conductivity type is p-type. First, the operation of the semiconductor device 100 when it is off will be explained. In the semiconductor device 100, by applying a voltage to the second electrode 2 that is sufficiently lower than the gate threshold voltage to the gate electrode 21, an inversion layer is not formed on the surface of the third layer 13 facing the gate electrode 21. Therefore, no channel is formed in the third layer 13, and the semiconductor device 100 is in the off state. When a high voltage is applied to the second electrode 2 to the first electrode 1, a reverse bias state is created between the third layer 13 and the fourth layer 14.

[0034] The conductor 42 functions as a field plate. Therefore, the electric field caused by the voltage applied between the first electrode 1 and the second electrode 2 is formed from the third layer 13 toward the conductor 42.

[0035] The electric field formed between the conductor 42 and the third layer 13 causes a depletion layer to form in the third layer 13. The depletion layer extends within the third layer 13 along the direction of the electric field. Since the structures 40 are aligned in the X and Y directions, the depletion layers formed by adjacent structures 40 are coupled together and continuous. In other words, in a reverse bias state, the depletion layer is formed throughout the entire third layer 13, and the entire third layer 13 is depleted.

[0036] If crystal defects or the like exist in the depleted third layer 13, leakage current will occur. In particular, if heavy metals 12a are introduced into the third layer 13, the heavy metals will aggregate in the crystal defects, increasing the leakage current. In the semiconductor device 100 according to this embodiment, the concentration of heavy metals 12a in the third layer 13 is sufficiently lower than the concentration of heavy metals 12a in the second layer 12, so leakage current is suppressed.

[0037] When the semiconductor device 100 is in the off state and a higher voltage is applied to the second electrode 2 than to the first electrode 1, minority carriers, or holes, are injected from the fourth layer 14 to the third layer 13. These holes are supplied to the second layer 12 via the third layer 13. Meanwhile, electrons are supplied from the first layer 11 to the second layer 12. As a result, a current flows from the second electrode 2 to the first electrode 1. This current is equivalent to the operation of a diode with the second electrode 2 as the anode and the first electrode 1 as the cathode. This type of operation is sometimes called diode operation.

[0038] When holes are injected by the diode operation, carriers accumulate in the second layer 12. In this state, if a voltage higher than that of the second electrode 2 is applied to the first electrode 1, a reverse recovery current flows due to the accumulated carriers. Because the mobility of holes is low, the current continues to flow even after the electrons have been discharged.

[0039] In the semiconductor device 100 according to this embodiment, the second layer 12 contains a heavy metal 12a at a higher concentration than that of the third layer 13. Since the heavy metal 12a functions as a recombination center, excess holes are recombined and eliminated by the heavy metal 12a. By appropriately setting the concentration of the heavy metal 12a in the second layer 12, most of the excess holes can be eliminated, and the reverse recovery time after current is passed due to diode operation can be shortened.

[0040] The field plate of the conductor 42 provides an electric field relaxation effect, which allows for a higher impurity concentration in the third layer 13, thereby lowering the on-resistance of the semiconductor device 100. Because of the high impurity concentration in the third layer 13, the number of accumulated carriers increases, while the heavy metal 12a further shortens the reverse recovery time. Thus, in this embodiment, it is possible to achieve low on-resistance and a shortened reverse recovery time in a MOSFET using a field plate.

[0041] Next, the operation of the semiconductor device 100 when it is ON will be described. In the semiconductor device 100, by applying a voltage to the second electrode 2 that is sufficiently higher than the gate threshold voltage to the gate electrode 21, an inversion layer is formed on the surface of the third layer 13 facing the gate electrode 21. The inversion layer of the third layer 13 functions as a channel.

[0042] By applying a high voltage to the first electrode 1 relative to the second electrode 2, electrons supplied from the fifth layer 15 travel through the inversion layer, through the third layer 13, the second layer 12, and the first layer 11, and reach the first electrode 1. In other words, the on-resistance of the semiconductor device 100 is the sum of the resistances of each layer from the first layer 11 to the fifth layer 15, and the lower these resistance values ​​are, the lower the on-resistance can be.

[0043] As described above, the semiconductor device 100 according to this embodiment includes a structure 40 that extends in the Z direction within the third layer 13. The structure 40 converts the electric field when a reverse bias is applied to a direction perpendicular to the Z direction. By ensuring that the length of the conductor 42 facing the third layer 13 is sufficient, the electric field between the conductor 42 and the third layer 13 can be reduced, and sufficient breakdown voltage can be achieved without reducing the impurity concentration of the second layer 12 and the third layer 13. As a result, the on-resistance of the semiconductor device 100 is reduced.

[0044] In this way, the semiconductor device 100 according to this embodiment is configured such that most of the depletion layer formed in the off state is formed on the third layer 13 and not formed on the second layer 12, thereby achieving low leakage current and improved reverse recovery characteristics.

[0045] Furthermore, in order to form a depletion layer in the third layer 13, the structure 40 has a conductor 42 that extends in the Z direction. As a result, the resistance of the third layer 13 can be reduced, and the on-resistance of the semiconductor device 100 is reduced.

[0046] A method for manufacturing the semiconductor device 100 according to this embodiment will be described. Figures 4 to 22 are schematic cross-sectional views illustrating a method for manufacturing a semiconductor device according to the first embodiment. As shown in Figure 4, a mask 1001 is formed on the intermediate layer 13a formed on the first layer 11, and trenches T1 are formed at positions corresponding to the mask 1001. For the formation of the trenches T1, for example, reactive ion etching (RIE) can be used. The intermediate layer 13a is a semiconductor layer of the first conductivity type. The mask 1001 is, for example, a photoresist.

[0047] As shown in Figure 5, an insulating film 1002 is formed to cover the side walls 13aS, bottom surface 13aB, and mask 1001 of the formed trench T1. The insulating film 1002 contains, for example, Si oxide. The insulating film 1002 can be formed, for example, by chemical vapor deposition (CVD).

[0048] As shown in Figure 6, the insulating film 1002 is anisotropically processed in the Z direction. In Z-direction anisotropic processing, the insulating film 1002a is processed in the Z direction and hardly processed in the direction perpendicular to the Z direction. In processing the insulating film 1002, the insulating film 1002 is removed until the bottom surface 13aB1 of the intermediate layer 13a is exposed. The depth of the bottom surface 13aB1 may be the same as the depth of the bottom surface 13aB of the insulating film 1002a, or it may be deeper than the bottom surface 13aB, as in the specific example in Figure 6. The side wall 1002aS of the insulating film 1002a is almost the same as before processing. For anisotropic processing, for example, RIE can be used.

[0049] As shown in Figure 7, a heavy metal layer 1003 is formed. The heavy metal layer 1003 is formed on at least the bottom surface 13aB1 of the intermediate layer 13a. As in the specific example in Figure 7, the heavy metal layer 1003 may be formed on the side wall 1002aS of the insulating film 1002a, on the insulating film 1002a, and on the mask 1001. The heavy metal layer 1003 contains Pt or Au as the heavy metal. The heavy metal layer 1003 can be formed, for example, by sputtering.

[0050] In the step of forming the heavy metal layer 1003, on the bottom surface 13aB1, the heavy metal reacts with Si of the intermediate layer 13a. Therefore, a portion of the heavy metal layer 1003 in contact with the bottom surface 13aB1 contains the heavy metal of the heavy metal layer 1003 and a silicide containing the heavy metal.

[0051] As shown in FIG. 8, the heavy metal layer 1003 is removed, leaving the silicide layer 1004 containing heavy metal and silicide. For removing the heavy metal layer 1003, for example, wet etching can be used.

[0052] As shown in FIG. 9, the heavy metal 12a in the silicide layer 1004 is diffused into the intermediate layer 13a by heat treatment. The second layer 12 is formed in a region where the heavy metal 12a is diffused. The heavy metal 12a in the silicide layer 1004 diffuses into the second layer 12, the concentration of the heavy metal decreases, and the silicide layer 45 is formed.

[0053] Since the silicide layer 45 is provided at the lower end of the insulating film 1002a, the second layer 12 is formed below the insulating film 1002a. Further, since the heavy metal 12a randomly diffuses in the intermediate layer 13a by the heat treatment, as shown in the specific example of FIG. 9, the second layer 12 is also formed above the lower end of the insulating film 1002a.

[0054] For the heat treatment of the silicide layer 1004, for example, Rapid Thermal Anneal (RTA) can be used. In RTA, by appropriately setting and controlling the temperature and time, the second layer 12 can be formed by diffusing the heavy metal 12a over a sufficient range while suppressing upward diffusion of the heavy metal 12a. For example, when the RTA temperature is set to about 600° C. to 900° C., upward spreading of the second layer 12 is suppressed.

[0055] Before performing the heat treatment on the silicide layer 1004, H is applied from the first layer 11 side + may be irradiated. By irradiating H + only to a location where a heavy metal layer is to be formed, H +This method allows for the aggregation of heavy metals to the required concentration in the irradiated area, and suppresses excessive diffusion of heavy metals during subsequent heat treatment.

[0056] As shown in Figure 10, an insulating layer 1005 is formed. The insulating layer 1005 is formed on the mask 1001, the insulating film 1002a, and the silicide layer 45. Through the process of forming the insulating layer 1005, an insulating layer 43 is formed on the silicide layer 45.

[0057] For example, the insulating layer 1005 can be formed using high-density plasma CVD (HDP-CVD). In the HDP-CVD method, a self-planarization function can be provided by applying a bias voltage to the first layer 11. Due to the self-planarization function, as shown in the specific example in Figure 10, the film can be formed while removing deposits from the sidewall 1002aS of the insulating film 1002a. Note that if the insulating film 1002 shown in Figure 5 is formed by the CVD method and the insulating layer 43 is formed by the HDP-CVD method, they will have different crystal structures.

[0058] As shown in Figure 11, a conductive layer 1006 is formed on the insulating layer 43 and the insulating layer 1005. The conductive layer 1006 is also formed on the sidewall 1002aS of the insulating film 1002a. In plan view, the diameter of the sidewall 1002aS is sufficiently small, and the conductive layer 1006 fills the space between the sidewalls 1002aS. The conductive layer 1006 can be formed, for example, by CVD.

[0059] As shown in Figure 12, the conductive layer 1006 is removed until the upper sidewall 1002aS of the insulating film 1002a is exposed, and the conductor 42 is formed. The conductive layer 1006 can be removed by, for example, chemical dry etching (CDE).

[0060] When the conductive layer 1006 shown in Figure 11 is formed, a conductor 42 of an appropriate length in the Z direction can be obtained by flattening the upper surface of the conductive layer 1006 and then removing the conductive layer 1006. For example, chemical mechanical polishing (CMP) can be used to flatten the upper surface of the conductive layer 1006.

[0061] As shown in Figure 13, insulating film 1007 is formed on the insulating layer 43, the insulating layer 1005, and the side wall 1002aS that are exposed by the removal of the conductive layer 1006. For example, CVD can be used to form the insulating film 1007.

[0062] As shown in Figure 14, the insulating layer 1005 and the insulating film 1007 are removed to expose the upper side wall 13aS of the third layer 13. The insulating films 1002a and 1007a form the insulating film 41. The removal of the insulating layer 1005 and the insulating film 1007 can be done, for example, by wet etching.

[0063] As shown in Figure 15, a gate insulating film 1008 is formed on the side wall 13aS. For example, thermal oxidation treatment can be used to form the gate insulating film 1008. In the thermal oxidation deposition method, the gate insulating film 1008 is also formed on the third layer 13 and the insulating film 41.

[0064] As shown in Figure 16, a gate electrode layer 1009 is formed on the gate insulating film 1008. For example, the gate electrode layer 1009 can be formed using low-pressure CVD (LPCVD).

[0065] As shown in Figure 17, the upper part of the gate electrode layer 1009 is removed to form the gate electrode 21. For example, a CDP can be used to remove the gate electrode layer 1009.

[0066] As shown in Figure 18, a fourth layer 14 is formed on top of the third layer 13. Subsequently, a fifth layer 15 is formed on top of the fourth layer 14. The formation of the fourth layer 14 and the fifth layer 15 can be done, for example, by ion implantation.

[0067] As shown in Figure 19, an interlayer insulating film 60 is formed on the gate electrode 21 and the fifth layer 15. The interlayer insulating film 60 can be formed, for example, by CVD.

[0068] As shown in Figure 20, a contact C1 is formed in the interlayer insulating film 60. The contact C1 is formed so as to penetrate the interlayer insulating film 60 and expose the fifth layer 15.

[0069] As shown in Figure 21, for example, by ion implantation, ions that form p-type impurities are irradiated through contact C2 to form the sixth layer 16 in the fourth layer 14.

[0070] As shown in Figure 22, a conductive layer is formed on the interlayer insulating film 60, and a conductive layer is also formed on the contact C2 to form the second electrode 2. Subsequently, the first electrode can be formed on the back surface of the first layer 11 to form the semiconductor device 100.

[0071] In the semiconductor device 100 according to this embodiment, a second layer 12 containing heavy metal 12a can be formed between the first layer 11 and the third layer 13 by the manufacturing method described above. The heavy metal 12a diffuses from the silicide layer 1004 formed at the lower end of the insulating film 41 forming the structure 40 through heat treatment. By appropriately setting the temperature and time during the heat treatment, the diffusion of heavy metal 12a to the upper part of the structure 40 can be suppressed. As a result, the second layer 12 containing heavy metal 12a is formed at the lower part of the structure 40, and most of the side surface of the structure 40 is in contact with the third layer 13. This makes it possible to manufacture a semiconductor device 100 that shortens the reverse recovery time during diode operation without increasing the leakage current when a reverse bias is applied.

[0072] Instead of introducing the heavy metal 12a from the lower end of the structure 40, the layer containing the heavy metal 12a can be introduced, for example, via the contact C1 described in relation to Figure 21. In this case, the third layer 13 is provided on the first layer 11, and the layer containing the heavy metal 12a is provided between the third layer 13 and the fourth layer 14. In this case, a layer containing a high concentration of heavy metal 12a is formed in the region that becomes depleted when a reverse bias is applied. As a result, the reverse recovery time is shortened, while the leakage current increases.

[0073] A specific method for introducing the heavy metal 12a through the contact C1 is to form a layer of the heavy metal 12a on the wall surface of the contact C1, and then perform a heat treatment to diffuse the heavy metal 12a. In this case, since a layer of heavy metal silicide remains on the wall surface of the contact C1, if a second electrode 2 is formed afterward, the contact resistance between the contact C1 and the second electrode 2 will increase, and the on-resistance may increase.

[0074] In contrast, in the manufacturing method of the semiconductor device 100 described above, a silicide layer 1004 is formed on the lower end of the structure 40 and then heat-treated. Therefore, no layer that increases on-resistance is formed at either the contact position of the first electrode 1 or the second electrode 2. As a result, a semiconductor device 100 with low on-resistance can be manufactured stably.

[0075] (Second embodiment) Figure 23 is a schematic cross-sectional view illustrating a semiconductor device according to the second embodiment. Figure 23 is a cross-sectional view taken along the arrow at the position corresponding to line AA in Figure 1. As shown in Figure 23, the configuration of the structure 240 in the semiconductor device 200 according to this embodiment differs from that of the semiconductor device 100 in Figure 2. In other respects, the components of the semiconductor device 200 are the same as those of the semiconductor device 100 in Figure 2, and the same reference numerals are used for the same components, and detailed descriptions are omitted as appropriate.

[0076] Similar to the semiconductor device 100 according to the first embodiment, multiple structures 240 are provided, each provided beneath a plurality of gate electrodes 21 and extending in the Z direction. Also, similar to the semiconductor device 100, the structure 240 is in contact with a portion of the second layer 12 at its lower part, and is in contact with the second layer 12 at least at its bottom surface.

[0077] The structure 240 includes an insulating film 41, a conductor 42, and an insulating layer 243. The conductor 42 extends in the Z-axis direction below the gate electrode 21. The insulating film 41 is provided between the gate electrode 21 and the conductor 42. The conductor 42 is provided on the insulating layer 243. The insulating layer 243 is provided on the second layer 12.

[0078] The insulating film 41 extends in the Z direction below the gate electrode 21. Similar to the example in Figure 2, the insulating film 41 is provided continuously from the gate insulating film 31.

[0079] The insulating film 41 surrounds the conductor 42 and the insulating layer 243. The insulating layer 243 is in contact with the second layer 12 on the second layer 12. The second layer 12 is in contact with the bottom surface of the insulating layer 243 and a portion of the side surface continuous with the bottom surface. Similar to the silicide layer 45 of the semiconductor device 100 shown in Figure 2, the insulating layer 243 protrudes from the lower end of the insulating film 41 onto the second layer 12.

[0080] As will be described later in relation to Figure 27, the insulating layer 243 contains silicon oxide formed by, for example, the HDP-CVD method, and has a different crystal structure from the insulating film 41 which contains silicon oxide formed by the CVD method.

[0081] The semiconductor device 200 according to this embodiment has the same effects as the semiconductor device 100 according to the first embodiment. That is, in the off state of the semiconductor device 200, the depletion layer of the third layer 13 extends throughout the third layer 13 between the structures 240, and since the concentration of heavy metal 12a in the third layer 13 is low, the leakage current between the first electrode 1 and the second electrode 2 is small. The lower part of the structure 240 has a second layer 12 containing heavy metal 12a at a higher concentration than the third layer 13, and since the heavy metal 12a functions as a recombination center for minority carriers, the reverse recovery time during diode operation of the semiconductor device 200 is shortened.

[0082] Furthermore, in the semiconductor device 200, since the conductor 42 of the structure 240 functions as a field plate, the depletion layer of the third layer 13 extends across the entire third layer 13 between the structures 240. As a result, the impurity concentration of the first conductivity type in the third layer 13 can be increased, and the on-resistance of the semiconductor device 200 can be reduced.

[0083] A method for manufacturing the semiconductor device 200 according to this embodiment will be described. Figures 24 to 27 are schematic cross-sectional views illustrating a method for manufacturing a semiconductor device according to a second embodiment. The manufacturing method for the semiconductor device 200 differs from the manufacturing method for the semiconductor device 100 according to the first embodiment in the process of forming the second layer 12, but is the same in other processes. In the following description, it will be assumed that the processes shown in Figures 4 to 6 are performed first, followed by the processes shown in Figures 24 to 27, and thereafter the processes shown in Figures 11 to 21 are applied.

[0084] Following the anisotropic processing of the insulating film 1002 in the Z direction, as described in relation to Figure 6, a heavy metal region 1201 is formed as shown in Figure 24. The heavy metal region 1201 is formed through the bottom surface 13aB1 of the intermediate layer 13a, for example, by ion implantation. In ion implantation, by appropriately setting the dose amount and acceleration energy of the heavy metal 12a, the heavy metal region 1201 is formed in the intermediate layer 13a from the bottom surface 13aB1. The upper end 1201T of the heavy metal region 1201 is in contact with the bottom surface 13aB1. The upper end 1201T is exposed from the bottom of the region surrounded by the side wall 1002aS of the insulating film 1002a.

[0085] Figure 25 shows a cross-section of a modified method for manufacturing the semiconductor device 200, illustrating the case where the heavy metal region 1201a is formed at a deeper position in the intermediate layer 13a than the heavy metal region 1201. As shown in Figure 25, the heavy metal region 1201a is formed below the heavy metal region 1201 and is continuous with the heavy metal region 1201. For example, the heavy metal region 1201a is formed at an appropriate position by increasing the acceleration energy during ion implantation of the heavy metal 12a compared to the formation of the heavy metal region 1201.

[0086] As shown in Figure 26, the heavy metal 12a in the heavy metal region 1201 is diffused into the intermediate layer 13a by heat treatment. A second layer 12 is formed in the region where the heavy metal 12a has diffused. The end portion 12T of the second layer 12 is exposed from the bottom of the region surrounded by the side walls 1002aS of the insulating film 1002a. For example, the RTA method can be used for the heat treatment.

[0087] As shown in Figure 27, an insulating layer 1005 is formed. The insulating layer 1005 is formed on the mask 1001, the insulating film 1002a, and the second layer 12. Similar to the process described in relation to Figure 10, the insulating layer 1005 is formed by the HDP-CVD method. As a result, an insulating layer 243 is formed at the bottom of the region surrounded by the side wall 1002aS. The insulating layer 243 has a different crystalline structure from the insulating film 1002.

[0088] Subsequently, a semiconductor device is formed by applying the processes described in relation to Figures 11 to 21.

[0089] In the manufacturing method of the semiconductor device 200 according to this embodiment, a heavy metal region 1201 containing heavy metal 12a is formed in the lower part of the structure 240 by using an ion implantation method to form the second layer 12. With the ion implantation method, it is possible to form the heavy metal region 1201 at an appropriate position in the intermediate layer 13a by setting the dose amount of heavy metal 12a and the acceleration energy. As a result, it is possible to make the second layer 12 having a low concentration of heavy metal 12a cover almost the entire side surface of the insulating film 41 of the structure 240, thereby achieving both a reduction in leakage current and a shortening of the reverse recovery time during diode operation.

[0090] In this way, a semiconductor device with improved reverse recovery characteristics during diode operation can be realized.

[0091] The relative levels of impurity concentrations between semiconductor regions in each embodiment described above can be confirmed, for example, using an SCM (Scanning Capacitive Microscope). The carrier concentration in each semiconductor region can be considered equal to the concentration of activated impurities in that region. Therefore, the relative levels of carrier concentrations between semiconductor regions can also be confirmed using an SCM. Furthermore, the impurity concentration in each semiconductor region can be measured, for example, by SIMS (Secondary Ion Mass Spectrometry).

[0092] Although several embodiments of the present invention have been illustrated above, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. Furthermore, the embodiments described above can be implemented in combination with each other.

[0093] The embodiments include the following aspects:

[0094] (Note 1) First electrode and, The second electrode and A semiconductor portion provided between the first electrode and the second electrode, A gate electrode is provided within the semiconductor portion and extends from the second electrode toward the first electrode, A structure provided between the gate electrode and the first electrode, extending within the semiconductor portion from the gate electrode side toward the first electrode side, Equipped with, The aforementioned semiconductor section is A first layer of a first conductivity type is provided on the first electrode and electrically connected to the first electrode, A second layer of the first conductive type, comprising a heavy metal, is provided on the first layer, A third layer of the first conductivity type is provided on the second layer and contains the heavy metal at a lower concentration than the concentration of the second layer, A fourth layer of second conductivity is provided on the third layer, facing the gate electrode via a gate insulating film, and electrically connected to the second electrode, A fifth layer of first conductivity type is provided on the fourth layer and electrically connected to the second electrode, Includes, The aforementioned structure is A silicide layer in contact with the second layer, An insulating layer provided on the silicide layer, A conductor provided on the insulating layer, extending from below the gate electrode toward the insulating layer, and electrically isolated from the gate electrode, An insulating film is provided between the conductor and the second layer, and between the conductor and the third layer, Includes, The bottom surface and at least a portion of the side surface of the silicide layer are semiconductor devices in contact with the second layer.

[0095] (Note 2) The semiconductor device described in Appendix 1, wherein the conductor faces the third layer via the insulating film from the upper end to the lower end of the conductor.

[0096] (Note 3) The insulating film is in contact with the second layer below the insulating film, as described in Appendix 1 or 2, for the semiconductor device.

[0097] (Note 4) The semiconductor device according to any one of the appendices 1 to 3, wherein the insulating layer has a crystal structure different from that of the insulating film.

[0098] (Note 5) First electrode and, The second electrode and A semiconductor portion provided between the first electrode and the second electrode, A gate electrode is provided within the semiconductor portion and extends from the second electrode toward the first electrode, A structure provided between the gate electrode and the first electrode, extending within the semiconductor portion from the gate electrode side toward the first electrode side, Equipped with, The aforementioned semiconductor section is A first layer of a first conductivity type is provided on the first electrode and electrically connected to the first electrode, A second layer of the first conductive type, comprising a heavy metal, is provided on the first layer, A third layer of the first conductivity type is provided on the second layer and contains the heavy metal at a lower concentration than the concentration of the second layer, A fourth layer of second conductivity is provided on the third layer, facing the gate electrode via a gate insulating film, and electrically connected to the second electrode, A fifth layer of first conductivity type is provided on the fourth layer and electrically connected to the second electrode, Includes, The aforementioned structure is An insulating layer in contact with the second layer on the second layer, A conductor provided on the insulating layer, extending from below the gate electrode toward the insulating layer, and electrically isolated from the gate electrode, An insulating film is provided between the conductor and the second layer, and between the conductor and the third layer, Includes, The insulating layer is a semiconductor device having a different crystal structure from the insulating film.

[0099] (Note 6) The heavy metal is a semiconductor device according to any one of the appendices 1 to 5, comprising either Pt or Au.

[0100] (Note 7) The concentration of heavy metals in the second layer is 1 × 10⁻⁶ 13 cm -3 ~1 × 10 20 cm -3 The semiconductor device described in Appendix 6. [Explanation of symbols]

[0101] 1...First electrode, 2...Second electrode, 10...Semiconductor part, 11...First layer, 12...Second layer, 12a...Heavy metal, 13...Third layer, 14...Fourth layer, 15...Fifth layer, 16...Sixth layer, 21...Gate electrode, 31...Gate insulating film, 40, 240...Structure, 41...Insulating film, 42...Conductor, 43, 243...Insulating layer, 45...Silicide layer, 60...Interlayer insulating film, 100, 200...Semiconductor device

Claims

1. First electrode and, The second electrode and A semiconductor portion provided between the first electrode and the second electrode, A gate electrode is provided within the semiconductor portion and extends from the second electrode toward the first electrode, A structure provided between the gate electrode and the first electrode, extending within the semiconductor portion from the gate electrode side toward the first electrode side, Equipped with, The aforementioned semiconductor section is A first layer of a first conductivity type is provided on the first electrode and electrically connected to the first electrode, A second layer of the first conductivity type, comprising a heavy metal, is provided on the first layer, A third layer of the first conductivity type is provided on the second layer and contains the heavy metal at a lower concentration than that of the second layer, A fourth layer of second conductivity is provided on the third layer, facing the gate electrode via a gate insulating film, and electrically connected to the second electrode, A fifth layer of the first conductivity type is provided on the fourth layer and electrically connected to the second electrode, Includes, The aforementioned structure is A silicide layer in contact with the second layer, An insulating layer provided on the silicide layer, A conductor provided on the insulating layer, extending from below the gate electrode toward the insulating layer, and electrically isolated from the gate electrode, An insulating film is provided between the conductor and the second layer, and between the conductor and the third layer, Includes, The bottom surface and at least a portion of the side surface of the silicide layer are semiconductor devices in contact with the second layer.

2. The semiconductor device according to claim 1, wherein the conductor faces the third layer via the insulating film from the upper end to the lower end of the conductor.

3. The semiconductor device according to claim 1, wherein the insulating film is in contact with the second layer at the lower part of the insulating film.

4. The semiconductor device according to claim 1, wherein the insulating layer has a crystal structure different from that of the insulating film.

5. The semiconductor device according to any one of claims 1 to 4, wherein the heavy metal comprises either Pt or Au.

6. The concentration of heavy metals in the second layer is 1 × 10⁻⁶ １３ cm －３ ~1 x 10 ２０ cm －３ The semiconductor device according to claim 5.

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