Method for manufacturing a semiconductor device, and semiconductor device.

Abstract

To provide a method for manufacturing a semiconductor device that is capable of shortening the time required to form a lifetime control region.SOLUTION: A method for manufacturing a semiconductor device includes forming a semiconductor portion having a transistor region and a diode region, forming a first lifetime control region at a lower portion of a semiconductor portion in the diode region by ions irradiated from above the semiconductor portion, and forming a second lifetime control region, simultaneously with the first life time region, at an upper portion of the semiconductor portion by ions irradiated from above through a mask such that the second lifetime control region does not overlap the first lifetime control region.SELECTED DRAWING: Figure 6

Description

Technical Field

[0001] Embodiments of the present invention relate to a method for manufacturing a semiconductor device and a semiconductor device. Background Art

[0002] As one type of semiconductor device, Reverse Conductive (RC)-Insulated Gate Bipolar Transistor (IGBT) is known. In an RC-IGBT, a transistor region provided with an IGBT and a diode region provided with a Free Wheeling Diode (FWD) connected in anti-parallel with the IGBT are formed on the same substrate. That is, the IGBT and the FWD are formed on a single semiconductor chip.

[0003] The above-described semiconductor device has a technical problem in that recovery loss deteriorates due to tail current caused by accumulated carriers in the diode region during the recovery operation of the FWD, and parasitic diode operation that induces hole injection from the transistor region to the diode region during the on-operation of the FWD.

[0004] Therefore, in order to solve the above technical problem, a technique is known in which a lifetime control region is provided by generating lattice defects with ions irradiated into the transistor region and the diode region. Prior Art Literature Patent Literature

[0005] Patent Literature 1 International Publication No. WO 2021 / 251011 Summary of the Invention Problem to be Solved by the Invention

[0006] To reduce tail current, it is effective to form a lifetime control region below the diode region. On the other hand, to suppress parasitic diode operation, it is effective to form a lifetime control region above the boundary between the transistor region and the diode region. When multiple lifetime control regions are formed locally in different locations in this way, multiple ion irradiations are required. Therefore, the formation of lifetime control regions takes a considerable amount of time.

[0007] The problem that this invention aims to solve is to provide a method for manufacturing a semiconductor device and a semiconductor device that can shorten the time required to form a lifetime control region. [Means for solving the problem]

[0008] A method for manufacturing a semiconductor device according to one embodiment involves forming a semiconductor portion having a transistor region and a diode region, forming a first lifetime control region in the lower part of the semiconductor portion within the diode region by irradiating the semiconductor portion from above with ions, and simultaneously forming a second lifetime control region in the upper part of the semiconductor portion, without overlapping with the first lifetime control region, by irradiating the semiconductor portion from above through a mask with ions. [Brief explanation of the drawing]

[0009] [Figure 1] This is a cross-sectional view of a semiconductor device according to the first embodiment, taken in a vertical direction. [Figure 2] This figure shows the process flow before and after the lifetime control region formation process of the semiconductor device according to the first embodiment. [Figure 3] This is a cross-sectional view illustrating the surface element structure formation process. [Figure 4] This is a cross-sectional view illustrating the resist pattern formation process. [Figure 5] This is a cross-sectional view illustrating the metal mask mounting process. [Figure 6] This is a cross-sectional view illustrating the ion irradiation process. [Figure 7] This is a cross-sectional view illustrating the backside grinding process. [Figure 8] This is a cross-sectional view illustrating the process of forming a diffusion layer on the back surface. [Figure 9] This is a cross-sectional view illustrating the first electrode process. [Figure 10] This is a cross-sectional view of a semiconductor device relating to a comparative example, obtained by cutting it vertically. [Figure 11] This is a cross-sectional view illustrating the first metal mask mounting process and the first ion irradiation process. [Figure 12] This is a cross-sectional view illustrating the second metal mask mounting process and the second ion irradiation process. [Figure 13] This is a cross-sectional view of the semiconductor device according to the second embodiment, cut in the vertical direction. [Modes for carrying out the invention]

[0010] Embodiments of the present invention will be described below with reference to the drawings. These embodiments are not intended to limit the present invention.

[0011] (First Embodiment) Figure 1 is a cross-sectional view of the semiconductor device according to the first embodiment, cut vertically. In the following description, the arrangement and configuration of each part of the semiconductor device may be described using the X, Y, and Z axes shown in each figure. The X, Y, and Z axes are mutually orthogonal and represent the X, Y, and Z directions, respectively. In addition, the Z direction may be described as upward and the opposite direction as downward. In this embodiment, the X and Y directions correspond to the second and third directions, respectively, and represent in-plane directions parallel to the surface (or back surface) of the semiconductor device 1. The Z direction corresponds to the first direction and represents out-of-plane directions perpendicular to the surface (or back surface) of the semiconductor device 1.

[0012] Also, p, p + The notation indicates that the p-type impurity concentration increases in this order. Furthermore, n - , n, n +This notation indicates that the concentration of n-type impurities increases in this order.

[0013] Impurity concentrations can be measured, for example, by SIMS (Secondary Ion Mass Spectrometry). Furthermore, the relative levels of impurity concentrations can be determined, for example, from the carrier concentrations obtained by SCM (Scanning Capacitance Microscopy). Additionally, distances such as the depth of semiconductor regions can be determined, for example, by SIMS.

[0014] The semiconductor device 1 shown in Figure 1 is an RC-IGBT. This semiconductor device 1 comprises a first electrode 10, a second electrode 20, and a semiconductor portion 30. The semiconductor portion 30 has a transistor region 30a on which transistor elements such as IGBTs are provided, and a diode region 30b on which diode elements such as FWDs are provided. The transistor region 30a and the diode region 30b are arranged alternately along the x-direction. A separation region without transistor or diode elements may be provided between the transistor region 30a and the diode region 30b.

[0015] The first electrode 10 is provided on the back surface of the semiconductor portion 30. The first electrode 10 can be formed using a metal such as aluminum. The first electrode 10 functions as a collector electrode in the transistor region 30a and as a cathode electrode in the diode region 30b.

[0016] The second electrode 20 faces the first electrode in the Z direction, with the semiconductor portion 30 in between. The second electrode can be formed using a metal such as aluminum. The second electrode 20 functions as an emitter electrode in the transistor region 30a and as an anode electrode in the diode region 30b.

[0017] The semiconductor part 30 is p + Collector area 31, n + Cathode area 32, n buffer area 33, n -a base region 34, a p base region 35, a p anode region 36, an n + emitter region 37, a gate electrode 38, and a gate insulating film 39. The p + collector region 31 corresponds to a p-type third semiconductor region. The n + cathode region 32 corresponds to an n-type fourth semiconductor region. An n buffer region 33 corresponds to an n-type second semiconductor region. The n - base region 34 corresponds to an n-type first semiconductor region.

[0018] p + collector region 31 is provided on the first electrode 10 in the transistor region 30a. The n + cathode region 32 is provided on the first electrode 10 in the diode region 30b. In the present embodiment, the n + cathode region 32 has a thickness that is + substantially the same as the thickness of the p + collector region 31. That is, the n + cathode region 32 and the p + collector region 31 are formed in layers having the same depth from the surface of the semiconductor portion 30. However, the thickness of the n + cathode region 32 does not need to be the same as the thickness of the p collector region 31, and may be different therefrom.

[0019] The n buffer region 33 is provided on the p + collector region 31 and on the n + cathode region 32. The n base region 34 is provided on the n buffer region 33. - The n base region 34 is provided on the n buffer region 33.

[0020] n - The base region 34 is provided with a first lifetime control region 41 and a second lifetime control region 42. In each of the first lifetime control region 41 and the second lifetime control region 42, lattice defects that function as lifetime killers are formed.

[0021] The first lifetime control region 41 is provided in the n -It is located at the bottom of the base region 34, in other words, at the boundary with the n buffer region 33. On the other hand, the second lifetime control region 42 is n - It is located in the upper part of the base region 34, at the boundary between the transistor region 30a and the diode region 30b.

[0022] The first lifetime control region 41 and the second lifetime control region 42 are formed by irradiation with hydrogen ions, helium ions, etc. In order to form the first lifetime control region 41 and the second lifetime control region 42 simultaneously, these two lifetime control regions are formed so as not to overlap in the Z direction. In other words, the first lifetime control region 41 and the second lifetime control region 42 are formed offset from each other in the X direction.

[0023] n located in transistor region 30a - A p-base region 35 is provided on the base region 34. Also, n located in the diode region 30b - A p-anode region 36 is provided on the base region 34. In this embodiment, the concentration of p-type impurities contained in the p-base region 35 is the same as the concentration of p-type impurities contained in the p-anode region 36. However, the p-type impurities in the p-base region 35 and the p-anode region 36 do not need to be the same; they may be different. The p-base region 35 and the p-anode region 36 with different p-type impurity concentrations can be formed, for example, by ion implantation separately.

[0024] In this embodiment, the thickness of the p-base region 35 is greater than the thickness of the p-anode region 36. In other words, the p-base region 35 is formed to a depth greater than that of the p-anode region 36 from the surface of the semiconductor portion 30. However, the thickness of the p-base region 35 does not need to be greater than that of the p-anode region 36; it may be the same or even smaller.

[0025] In the p-base region 35, n + The emitter region 37 is in contact with n.+ The emitter region 37 is in contact with the second electrode 20. When the voltage between the gate electrode 38 and the second electrode 20 (emitter electrode) exceeds the threshold voltage, an n channel is formed in the p-base region 35. As a result, in the transistor region 30a, p + From collector region 31, via n channels + A current path is generated leading to the emitter region 37.

[0026] The gate electrode 38 is connected to the p-base region 35 and n-base region via the gate insulating film 39. + The gate electrode 38 faces the emitter region 37. The gate electrode 38 can be formed using, for example, polysilicon. The gate insulating film 39 is, for example, a silicon oxide film (SiO2).

[0027] In this embodiment, the gate electrode 38 and gate insulating film 39 are provided not only in the transistor region 30a but also in the diode region 30b. However, in the diode region 30b, n + The emitter region 37 is not provided. Therefore, the gate electrode 38 provided in the diode region 30b is a dummy gate electrode.

[0028] In semiconductor device 1, if the tail current due to the stored carriers in the diode region 30b is large during the FWD recovery operation, the FWD recovery loss will be large. Therefore, in this embodiment, the n - A first lifetime control region 41 is formed below the base region 34. Since a lattice defect, which acts as a lifetime killer, is formed in the first lifetime control region 41, the tail current can be reduced. This makes it possible to reduce recovery losses.

[0029] Furthermore, in semiconductor device 1, when FWD is turned ON, the p-base region 35 of transistor region 30a and the n-base region 30b are... +When the cathode region 32 operates as a parasitic diode, holes are injected from the transistor region 30a into the diode region 30b. As a result, the recovery loss of the FWD may worsen. Therefore, in this embodiment, n at the boundary between the transistor region 30a and the diode region 30b - A second lifetime control region 42 is formed on the upper part of the base region 34. Since lattice defects, which are lifetime killers, are also formed in the second lifetime control region 42, the operation of parasitic diodes can be suppressed. This makes it possible to reduce recovery losses. However, if the second lifetime control region 42 is formed on the surface of the transistor region 30a, the on-characteristics of the IGBT may deteriorate. Furthermore, the gate threshold voltage (Vth) may fluctuate due to damage to the gate insulating film 39 when the second lifetime control region 42 is formed. Therefore, in this embodiment, the formation area of ​​the second lifetime control region 42 is limited to the surface of the boundary between the transistor region 30a and the diode region 30b. This makes it possible to suppress parasitic diode operation while suppressing disadvantages such as deterioration of the IGBT's on-characteristics and fluctuations in the gate threshold voltage (Vth).

[0030] Here, with reference to Figures 2 to 9, the manufacturing method of the semiconductor device 1 according to this embodiment will be described. Here, the lifetime control region formation step of forming the first lifetime control region 41 and the second lifetime control region 42, and the manufacturing steps before and after the lifetime control region formation step will be mainly described.

[0031] Figure 2 is a diagram showing the process flow before and after the lifetime control region formation process of the semiconductor device 1 according to this embodiment. As shown in Figure 2, the surface element structure formation process (step S1) precedes the lifetime control region formation process (step S2). Furthermore, the back surface element structure formation process (step S3) follows the lifetime control region formation process. In addition, the dicing process (step S4) follows the back surface element structure formation process (step S3).

[0032] Figure 3 is a cross-sectional view illustrating the surface element structure formation process. In the surface element structure formation process, first, n is applied to the semiconductor wafer 11. - It forms a base region 34.

[0033] Next, in the transistor region 30a, n - On the base region 34, p base region 35, n + The emitter region 37, gate electrode 38, and gate insulating film 39 are formed sequentially. Meanwhile, in the diode region 30b, n - A p-anode region 36, a gate electrode 38, and a gate insulating film 39 are sequentially formed on the base region 34. However, the gate electrode 38 formed on the diode region 30b is a dummy gate electrode.

[0034] Finally, the second electrode 20 is formed. The p-base region 35 to the gate insulating film 39 and the second electrode 20 can be formed by commonly used manufacturing methods, so a detailed explanation is omitted.

[0035] Next, the lifetime control region formation process will be described. The lifetime control region formation process consists of a resist pattern formation process, a metal mask mounting process, and an ion irradiation process.

[0036] Figure 4 is a cross-sectional view illustrating the resist pattern formation process. In the resist pattern formation process, first, the resist 40 is applied to the entire upper surface of the second electrode 20. Subsequently, the resist 40 applied to the region of the upper surface of the second electrode 20 facing the boundary between the transistor region 30a and the diode region 30b, and the resist 40 applied to the region facing the diode region 30b, are removed by exposure and defrosting. As a result, as shown in Figure 4, a pattern of resist 40 is formed that exposes the region facing the boundary between the transistor region 30a and the diode region 30b and the region facing the diode region 30b.

[0037] Figure 5 is a cross-sectional view illustrating the metal mask mounting process. In the metal mask mounting process, the metal mask 50 is placed above the resist 40. The metal mask 50 contains, for example, aluminum or nickel.

[0038] The metal mask 50 is patterned to shield the area where the second lifetime control region 42 is formed, while exposing the area where the first lifetime control region 41 is formed. The thickness of the metal mask 50 is designed to allow ions irradiated in the subsequent ion irradiation process to remain in the area where the second lifetime control region 42 is formed.

[0039] Figure 6 is a cross-sectional view illustrating the ion irradiation process. In the ion irradiation process, ions containing hydrogen or helium are emitted from above the metal mask 50. - It is irradiated toward the base region 34. At this time, n - In the exposed portion of the base region 34 that is not shielded by the metal mask 50, the irradiated ions are n - It reaches a predetermined depth in the base region 34. As a result, the first lifetime control region 41 is formed.

[0040] Also, n - In the portion of the base region 34 that is shielded only by the metal mask 50, i.e., the boundary between the transistor region 30a and the diode region 30b, the irradiated ions are n - The upper part of the base region 34 is reached. As a result, the second lifetime control region 42 is formed simultaneously with the first lifetime control region 41.

[0041] Note that n - In the base region 34, the irradiated ions do not reach the areas that are shielded by both the resist 40 and the metal mask 50. After the ion irradiation process, the resist 40 is removed. This completes the lifetime control region formation process.

[0042] Next, the back surface element structure formation process will be described. The back surface element structure formation process consists of a back surface grinding process, a back surface diffusion layer formation process, and a first electrode process.

[0043] Figure 7 is a cross-sectional view illustrating the back grinding process. In the back grinding process, n - The base region 34 is ground from its back side. As a result, the first lifetime control region 41 is n - It is located at the bottom of the base region 34.

[0044] Figure 8 is a cross-sectional view illustrating the back surface diffusion layer formation process. In the back surface diffusion layer formation process, n - An n-buffer region 33 is formed below the base region 34. Subsequently, in the transistor region 30a, a p + A collector region 31 is formed. On the other hand, in the diode region 30b, n buffer region 33 is formed below n + Forms a cathode region 32. + Collector area 31, n + The cathode region 32 and the n-buffer region 33 can be formed by commonly used manufacturing methods, so a detailed explanation is omitted.

[0045] Figure 9 is a cross-sectional view illustrating the first electrode process. In the first electrode process, the first electrode 10 is p + Below and n + It is formed beneath the cathode region 32. This completes the back surface element structure formation process.

[0046] In the final dicing step, a blade is used to cut the semiconductor wafer 11, as shown in Figure 9, into a grid pattern. As a result, the semiconductor wafer 11 is divided into multiple semiconductor chips.

[0047] Here, we will describe comparative examples that are different from this embodiment.

[0048] Figure 10 is a cross-sectional view of a semiconductor device according to a comparative example, cut vertically. In Figure 10, the same reference numerals are used for components similar to those of semiconductor device 1 described above, and redundant explanations are omitted.

[0049] In the semiconductor device 100 of this comparative example, as shown in Figure 10, the first lifetime control region 41 and the second lifetime control region 42 overlap in the Z direction. Therefore, it is not possible to form the first lifetime control region 41 and the second lifetime control region 42 of the comparative example simultaneously. The lifetime control region formation process of the comparative example will be described below.

[0050] The lifetime control region formation process in the comparative example consists of a first metal mask mounting step, a first ion irradiation step, a second metal mask mounting step, and a second ion irradiation step.

[0051] Figure 11 is a cross-sectional view illustrating the first metal mask mounting process and the first ion irradiation process.

[0052] In the first metal mask mounting process, the first metal mask 51 is positioned above the second electrode 20. The first metal mask 51 shields the transistor region 30a while exposing the diode region 30b. The thickness of the first metal mask 51 is designed to prevent the ions irradiated in the subsequent first ion irradiation process from passing through.

[0053] In the first ion irradiation step, ions containing hydrogen or helium are emitted from above the first metal mask 51. - It is irradiated toward the base region 34. At this time, n - In the exposed portion of the base region 34 that is not shielded by the metal mask 50, i.e., the diode region 30b, the irradiated ions are n - It reaches a predetermined depth in the base region 34. As a result, the first lifetime control region 41 according to the comparative example is formed.

[0054] Figure 12 is a cross-sectional view illustrating the second metal mask mounting process and the second ion irradiation process.

[0055] In the second metal mask mounting process, the second metal mask 52 is positioned above the second electrode 20. The second metal mask 52 shields the portion of the device except for the boundary between the transistor region 30a and the diode region 30b. The thickness of the second metal mask 52 is designed to prevent the ions irradiated in the subsequent second ion irradiation process from passing through.

[0056] In the second ion irradiation step, ions containing hydrogen or helium are emitted from above the second metal mask 52. - It is irradiated towards the base region 34. At this time, the ions are n - The light is directed to reach the exposed portion of the base region 34 that is not shielded by the second metal mask 52, i.e., the upper part of the boundary between the transistor region 30a and the diode region 30b. As a result, the second lifetime control region 42 according to the comparative example is formed.

[0057] The lifetime control region formation process in this comparative example requires two metal masks, consisting of a first metal mask 51 and a second metal mask 52, and two ion irradiation processes, consisting of a first ion irradiation process and a second ion irradiation process. Therefore, the formation of the first lifetime control region 41 and the second lifetime control region 42 takes a lot of time. As a result, the process cost is high.

[0058] In contrast, this embodiment uses a metal mask 50 that has been thinned to allow ions to pass through, thereby deliberately reducing its shielding ability, in combination with a resist 40. As a result, the first lifetime control region 41 and the second lifetime control region 42 can be formed simultaneously with a single metal mask 50 and a single ion irradiation. This makes it possible to shorten the lifetime control region formation process time, and as a result, process costs can be reduced.

[0059] (Second Embodiment) Figure 13 is a cross-sectional view of the semiconductor device according to the second embodiment, cut in the vertical direction. In Figure 13, the same reference numerals are used for components similar to those in the semiconductor device 1 according to the first embodiment described above, and redundant explanations are omitted.

[0060] In the semiconductor device 2 shown in Figure 13, the semiconductor portion 30 has an isolation region 30c provided between the transistor region 30a and the diode region 30b. In the isolation region 30c, n buffer region 33, n - The base region 34 and the p-anode region 36 are stacked between the first electrode 10 and the second electrode 20 in this order.

[0061] Also, n of the separation region 30c - A gate electrode 38 and a gate insulating film 39 are provided in the base region 34 and the p-anode region 36. However, this gate electrode 38 is a dummy gate electrode, similar to the gate electrode 38 provided in the diode region 30b.

[0062] Furthermore, in the semiconductor device 2 according to this embodiment, the first lifetime control region 41 is n in the diode region 30b - It is located at the bottom of the base region 34. This first lifetime control region 41 can reduce the tail current caused by the accumulated carriers in the diode region 30b during the recovery operation of the FWD.

[0063] On the other hand, the second lifetime control region 42 is n in the separation region 30c - n - It is provided across the upper part of the base region 34. This second lifetime control region 42 can suppress the operation of parasitic diodes when the FWD is turned on.

[0064] In this embodiment, as in the first embodiment, the first lifetime control region 41 and the second lifetime control region 42 are offset from each other in the X direction and do not overlap in the Z direction. Therefore, as in the first embodiment, by using the metal mask 50 and the resist 40 in combination, the first lifetime control region 41 and the second lifetime control region 42 can be formed simultaneously with one metal mask 50 and one ion irradiation.

[0065] Therefore, according to this embodiment, it is possible to shorten the lifetime control region formation process time, and as a result, process costs can be reduced.

[0066] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims and their equivalents. [Explanation of Symbols]

[0067] 1: Semiconductor equipment 10: 1st electrode 20: 2nd electrode 30: Semiconductor Department 30a: Transistor region 30b: Diode region 30c: Separation area 31:p + Collector region (third semiconductor region) 32:n + Cathode region (fourth semiconductor region) 33: n-buffer region (second semiconductor region) 34:n - Base region (first semiconductor region) 40: Resist 41: First Lifetime Control Domain 42: Second lifetime control region 50: Metal Mask

Claims

1. A semiconductor portion having a transistor region and a diode region is formed. Ions irradiated from above the semiconductor portion form a first lifetime control region in the lower part of the semiconductor portion within the diode region. A method for manufacturing a semiconductor device, comprising: forming a second lifetime control region on the upper part of the semiconductor portion simultaneously with the first lifetime control region, such that the second lifetime control region does not overlap with the first lifetime control region, by ions irradiated from above the semiconductor portion through a mask.

2. A method for manufacturing a semiconductor device according to claim 1, wherein the second lifetime control region is formed on the upper part of the boundary between the transistor region and the diode region.

3. A separation region is formed between the transistor region and the diode region. A method for manufacturing a semiconductor device according to claim 1, wherein the second lifetime control region is formed on the upper part of the boundary between the transistor region and the isolation region.

4. A method for manufacturing a semiconductor device according to claim 1, wherein the first lifetime control region and the second lifetime control region are formed with a resist that does not allow the ions to pass through placed between the transistor region and the mask.

5. The method for manufacturing a semiconductor device according to claim 1 or 2, wherein the mask is a metal mask containing aluminum or nickel.

6. The method for manufacturing a semiconductor device according to claim 1 or 2, wherein the ion is a hydrogen ion or a helium ion.

7. A method for manufacturing a semiconductor device according to claim 1 or 2, wherein the first lifetime control region and the second lifetime control region are formed in the n-type first semiconductor region of the semiconductor portion.

8. After forming the first lifetime control region and the second lifetime control region, an n-type second semiconductor region is formed below the first semiconductor region. A third p-type semiconductor region is formed below the second semiconductor region in the transistor region. An n-type fourth semiconductor region is formed below the second semiconductor region in the diode region. A method for manufacturing a semiconductor device according to claim 7, wherein the first electrode is formed below the third semiconductor region and below the fourth semiconductor region.

9. A method for manufacturing a semiconductor device according to claim 8, wherein the first lifetime control region and the second lifetime control region are formed with the second electrode formed on the semiconductor portion.

10. A method for manufacturing a semiconductor device according to claim 1 or 2, wherein an IGBT (Insulated Gate Bipolar Transistor) is formed in the transistor region and a FWD (Free Wheeling Diode) is formed in the diode region.

11. First electrode and A second electrode facing the first electrode in a first direction, A semiconductor portion is provided between the first electrode and the second electrode, having a transistor region and a diode region, A first lifetime control region is provided below the diode region, A semiconductor device comprising: a second lifetime control region provided on the upper part of the semiconductor portion such that it does not overlap with the first lifetime control region in the first direction; and

Images