Manufacturing method for multilayer substrates and wiring boards

Abstract

Provided is a multilayer substrate manufacturing method such that it is possible to inhibit between-bump short-circuiting and substrate warping. This multilayer substrate manufacturing method includes: a step for preparing a first substrate which is a rigid substrate comprising a plurality of first bumps on the surface thereof at specified dispositions, and a second substrate or a semiconductor device comprising a plurality of second bumps on the surface thereof at corresponding dispositions, said step being such that the first bumps and the second bumps are composed of a metal or an alloy having a melting point of 600°C or greater, and the first bumps and the second bumps have a height of 0.3 μm or greater; and a step for carrying out cleaning processing of bonding surfaces of the first bumps and bonding surfaces of the second bumps in an atmosphere having a pressure of 1×10-3 Pa or less, stacking the first substrate and the second substrate or the semiconductor device such that the bonding surfaces of the first bumps and the bonding surfaces of the second bumps are continuously abutting, pressure welding the first bumps and the second bumps at a temperature of 90°C or less, and forming a multilayer substrate.

Description

[Technical Field]

[0001] This invention relates to a method for manufacturing a multilayer substrate and a wiring substrate. [Background technology]

[0002] In recent years, multilayering of printed circuit boards (PCBs) has become widespread in order to increase the mounting density and miniaturize PCBs. These multilayer PCBs are used in many portable electronic devices for the purpose of reducing weight and size. Furthermore, there is a demand for further reduction in the thickness of the interlayer insulating layer and even greater weight reduction as a PCB.

[0003] To meet these requirements, a method for manufacturing multilayer printed circuit boards using the coreless build-up method has been adopted. The coreless build-up method is a method of creating a multilayer by alternately stacking (building up) insulating layers and wiring layers without using a so-called core substrate. In the coreless build-up method, it has been proposed to use a carrier-attached metal foil to facilitate the peeling of the support from the multilayer printed circuit board. For example, Patent Document 1 (Japanese Patent Application Publication No. 2005-101137) discloses a method for manufacturing a semiconductor device mounting package substrate, which includes attaching an insulating resin layer to the carrier surface of a carrier-attached copper foil to form a support, forming a first wiring conductor on the ultrathin copper layer side of the carrier-attached copper foil by processes such as photoresist processing, pattern electrolytic copper plating, and resist removal, forming a build-up wiring layer, peeling off the carrier-attached support substrate, and removing the ultrathin copper layer.

[0004] Furthermore, in order to miniaturize embedded circuits as shown in Patent Document 1, a carrier-mounted metal foil with a metal layer thickness of 1 μm or less is desired. Therefore, in order to reduce the thickness of the metal layer, it has been proposed to form the metal layer by a vapor phase method such as sputtering. For example, Patent Document 2 (International Publication No. 2017 / 150283) discloses a carrier-mounted copper foil in which a release layer, an anti-reflective layer, and an ultrathin copper layer (e.g., a film thickness of 300 nm) are formed by sputtering on a carrier such as a glass sheet. Patent Document 3 (International Publication No. 2017 / 150284) also discloses a carrier-mounted copper foil in which an intermediate layer (e.g., an adhesive metal layer and a release assist layer), a release layer, and an ultrathin copper layer (e.g., a film thickness of 300 nm) are formed by sputtering on a carrier such as a glass sheet. Patent documents 2 and 3 teach that interposing an intermediate layer made of a predetermined metal provides excellent stability in the mechanical peel strength of the carrier, and that the anti-reflective layer exhibits a desirable dark color, thereby improving visibility in image inspection (e.g., automated image inspection (AOI)).

[0005] In particular, with the increasing miniaturization and power saving of electronic devices, there is a growing need for higher integration and thinner semiconductor chips and printed circuit boards. To meet these needs, the adoption of FO-WLP (Fan-Out Wafer Level Packaging) and PLP (Panel Level Packaging) has been considered in recent years as next-generation packaging technologies. Furthermore, the adoption of coreless build-up methods is also being considered for FO-WLP and PLP. One such method is called the RDL-First (Redistribution Layer-First) method, in which a wiring layer and, if necessary, a build-up wiring layer are formed on the surface of a coreless support, the chip is mounted and sealed, and then the support is peeled off. For example, Patent Document 4 (Japanese Patent Application Publication No. 2015-35551) discloses a method for manufacturing a semiconductor device, which includes forming a metal delamination layer on the main surface of a support made of glass or a silicon wafer, forming an insulating resin layer thereon, forming a redistribution layer including a build-up layer thereon, mounting and sealing a semiconductor integrated circuit thereon, exposing the delamination layer by removing the support, exposing secondary mounting pads by removing the delamination layer, forming solder bumps on the surface of the secondary mounting pads, and secondary mounting.

[0006] Incidentally, flip-chip technology is widely used as a method for mounting semiconductor chips and the like onto wiring boards. In flip-chip technology, chip mounting is performed by connecting, for example, the mounting pads (bumps) on the semiconductor chip side to protruding electrodes (bumps) formed on the redistribution layer of the wiring board. In this case, solder (for example, SnAg solder) is generally applied to the bumps on the wiring board side in advance to ensure electrical connection between the bumps, and then the semiconductor chip is mounted. In this method, the solder melts and the bumps are joined together when the wiring board is heated after the semiconductor chips are stacked.

[0007] However, as the number of terminals increases due to the miniaturization of wiring, the spacing between adjacent bumps becomes narrower (for example, a wiring distance of 10 μm), and if bumps are connected using the above method, there is a high possibility of a short circuit occurring. In other words, when bumps are joined by heating the wiring board and melting the solder, the solder that spills out from the bump during melting may reach the adjacent bump, potentially causing a short circuit.

[0008] For this reason, methods have been proposed for solderless chip mounting on wiring boards. For example, Patent Document 5 (Japanese Patent No. 5159273) discloses a method for manufacturing an electronic device in which a wiring body and two laminates consisting of a first semiconductor chip and a second semiconductor chip are fixed by pressing them together at a predetermined temperature using a press heater. Also, Patent Document 6 (Japanese Patent No. 5699891) discloses a method for manufacturing an electronic device that includes a step of thermocompressing a first electrode provided on the main surface of a first electronic component with a second electrode provided on the main surface of a second electronic component. [Prior art documents] [Patent Documents]

[0009] [Patent Document 1] Japanese Patent Publication No. 2005-101137 [Patent Document 2] International Publication No. 2017 / 150283 [Patent Document 3] International Publication No. 2017 / 150284 [Patent Document 4] Japanese Patent Publication No. 2015-35551 [Patent Document 5] Patent No. 5159273 [Patent Document 6] Patent No. 5699891 [Overview of the project]

[0010] However, in chip mounting methods such as those disclosed in Patent Documents 5 and 6, there is a risk that the wiring substrate may warp due to heat treatment. That is, if thermocompression bonding is performed at a temperature at which the metal constituting the bumps sufficiently diffuses, there is a risk that the substrate may warp or deform due to the shrinkage of the wiring and the resin between the wirings. Thus, it is difficult to suppress short circuits between bumps in the planar direction and warping of the substrate while joining the upper and lower bumps.

[0011] The present inventors have now discovered that when bonding a rigid substrate to another substrate or semiconductor device, by cleaning the bonding surfaces of predetermined bumps provided on them, and then pressing the bumps together at a predetermined temperature or below, it is possible to manufacture a multilayer substrate in which short circuits between bumps and warping of the substrate are suppressed.

[0012] Therefore, an object of the present invention is to provide a method for manufacturing a multilayer substrate that can suppress short circuits between bumps and warping of the substrate.

[0013] According to one aspect of the present invention, a method for manufacturing a multilayer substrate, A step of preparing a first substrate, which is a rigid substrate having a plurality of first bumps on its surface in a predetermined arrangement, and a second substrate or semiconductor device having a plurality of second bumps on its surface in an arrangement corresponding to the predetermined arrangement, wherein each of the first bumps and the second bumps is made of a metal or alloy having a melting point of 600°C or higher and has a height of 0.3 μm or higher, Pressure 1 × 10 -3 In an atmosphere of Pa or less, the joint surfaces of the first bump and the second bump are subjected to a cleaning treatment. Continue with pressure 1 × 10 -3 A process of forming a multilayer substrate by stacking the first substrate and the second substrate or semiconductor device in an atmosphere of Pa or less such that the bonding surface of the first bump and the bonding surface of the second bump are in contact, and pressing the first bump and the second bump together at a temperature of 90°C or less. A method for manufacturing a multilayer substrate is provided, which includes the following.

[0014] According to another aspect of the present invention, a first substrate that is a rigid substrate, a second substrate, a plurality of bumps interposed between said first substrate and said second substrate to couple said first substrate and said second substrate, there is provided a wiring board comprising: said bumps are made of a metal or an alloy having a melting point of 600°C or higher, and have a height of 0.6 µm or more. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] [Figure 1A] it is a process flow diagram schematically showing, in cross-section, an example of a method for producing a multilayer board according to the present invention, and shows initial steps (steps (i) and (ii)). [Figure 1B] it is a process flow diagram schematically showing, in cross-section, an example of a method for producing a multilayer board according to the present invention, and shows steps following FIG. 1A (steps (iii) and (iv)). [Figure 1C] it is a process flow diagram schematically showing, in cross-section, an example of a method for producing a multilayer board according to the present invention, and shows steps following FIG. 1B (steps (v) and (vi)). [Figure 2] it is a schematic diagram showing the height H, diameter D, and pitch P (center-to-center distance) of a bump. [Figure 3] it is a schematic cross-sectional view showing one aspect of the wiring board according to the present invention. [Figure 4] it is an optical microscope observation image (magnification: 100x) of first bumps provided on a first substrate in Example A1. [Figure 5] it is a scanning electron microscope (SEM) observation image (magnification: 2000x) of first bumps provided on a first substrate in Example A1. [Figure 6A] it is a schematic cross-sectional view of a first substrate including pillars produced in Example A2. [Figure 6B] it is a schematic top view of the first substrate shown in FIG. 6A as viewed from the redistribution layer side. [Figure 7] it is a schematic cross-sectional view of a multilayer board including pillars produced in Example A2. [Figure 8]These are SEM images (magnification: 10,000x) of the bumps after etching in examples B1, B3, or B5-B8. [Figure 9] This is an SEM image (magnification: 10,000x) of the bump after etching in Example B2. [Modes for carrying out the invention]

[0016] Manufacturing method for multilayer substrates The present invention relates to a method for manufacturing a multilayer substrate. The method of the present invention includes the steps of (1) preparing a first substrate and a second substrate or semiconductor device, (2) cleaning the bump bonding surface, (3) pressure bonding, (4) optionally performing underfill filling, (5) optionally performing resin sealing, and (6) optionally performing carrier peeling and removal.

[0017] The following explains each of the steps (1) to (6) with reference to the diagrams.

[0018] (1) Preparation of the first substrate and the second substrate or semiconductor device An example of a method for manufacturing a multilayer substrate according to the present invention is shown in Figures 1A to 1C. First, as shown in Figure 1A(i), a first substrate 22 is prepared, having a plurality of first bumps 24 on its surface in a predetermined arrangement. A second substrate or semiconductor device 26 is also prepared, having a plurality of second bumps 28 on its surface. The second bumps 28 are provided on the surface of the second substrate or semiconductor device 26 in an arrangement corresponding to the first bumps 24 provided on the surface of the first substrate 22.

[0019] The first substrate 22 is a rigid substrate, preferably having an elastic modulus of 30 GPa or more and 600 GPa or less, more preferably 40 GPa or more and 400 GPa or less, even more preferably 50 GPa or more and 250 GPa or less, and particularly preferably 60 GPa or more and 150 GPa or less. The rigidity of the first substrate 22 makes it possible to suitably perform the bump pressing described later.

[0020] The first substrate 22 is preferably a rigid substrate comprising a rigid carrier 12, a redistribution layer 20 on the rigid carrier 12, and a plurality of first bumps 24 on the redistribution layer 20. In this case, it is preferable that the rigid carrier 12 has the elastic modulus described above. The redistribution layer 20 may also be formed on a carrier-attached metal foil 18. The formation of the redistribution layer 20 can be carried out by known methods and is not particularly limited. For example, the redistribution layer 20 can be preferably formed by alternately stacking insulating layers and wiring layers to form a multilayer structure using the coreless build-up method described above. In this specification, the rigid carrier 12, intermediate layer 14 (if present), release layer 15, and metal layer 16 may be collectively referred to as "carrier-attached metal foil 18". Preferred embodiments of the carrier-attached metal foil 18 will be described later.

[0021] The rigid carrier 12 constituting the first substrate 22, if desired, is not limited in material as long as it has the desired rigidity, and may be composed of glass, ceramics, a silicon-containing substrate, resin, or metal, but is preferably a silicon-containing substrate or a glass substrate. Among these, the silicon-containing substrate can be any substrate that contains Si as an element, such as an SiO2 substrate, a SiN substrate, a Si single crystal substrate, or a Si polycrystalline substrate. More preferably, it is a glass carrier, a single crystal silicon substrate, or a polycrystalline silicon substrate. According to a preferred embodiment of the present invention, the rigid carrier 12 is rectangular in shape with a short side of 100 mm or more, more preferably with a short side of 150 mm or more and 600 mm or less, and a long side of 200 mm or more and 650 mm or less. According to another preferred embodiment of the present invention, the rigid carrier 12 is disc-shaped with a diameter of 100 mm or more, more preferably with a disc-shaped with a diameter of 200 mm or more and 450 mm or less.

[0022] The configuration of the second substrate may be similar to that of the first substrate 22, except that it does not necessarily have to be a rigid substrate. Therefore, preferred embodiments for the first substrate 22 also apply directly to the second substrate. However, the second substrate may be a rigid substrate. In this case, it is preferable that at least one of the first substrate 22 and the second substrate has the elastic modulus described above. Furthermore, the second substrate may be a rigid substrate comprising a rigid carrier, a redistribution layer on the rigid carrier, and a plurality of second bumps 28 on the redistribution layer. Therefore, it is preferable that at least one of the first substrate 22 and the second substrate contains glass, silicon, or alumina, and more preferably glass.

[0023] The semiconductor device 26 can be any device that has the desired device function, and its type is not particularly limited. Preferred examples of the semiconductor device 26 include GaN, SiC, Si, alumina substrate, zirconia substrate, and ceramic substrate. Two or more semiconductor devices 26 may be provided for one first substrate 22, and the number is not particularly limited.

[0024] Each of the first bumps 24 provided on the surface of the first substrate 22 and the second bumps 28 provided on the surface of the second substrate or semiconductor device 26 is made of a metal or alloy having a melting point of 600°C or higher so as to effectively suppress short circuits between the bumps. Preferably, the first bumps 24 and the second bumps 28 are made only of the above metal or alloy, but may contain unavoidable impurities. Furthermore, preferably, the first bumps 24 and the second bumps 28 are made of transition metals, more preferably at least one selected from the group consisting of Au, Ag, and Cu, and even more preferably Cu. In particular, it is preferable that both the first bumps 24 and the second bumps 28 are made of Cu metal. In this invention, bumps are bonding members for mounting a semiconductor device or another substrate on a substrate, and include those commonly referred to as pads, pillars, or posts.

[0025] Figure 2 shows one embodiment of the first bump 24 and the second bump 28. As shown in Figure 2, the first bump 24 and the second bump 28 each have a height H of 0.3 μm or more, preferably 0.5 μm to 200 μm, more preferably 0.7 μm to 150 μm, particularly preferably 0.9 μm to 100 μm, and most preferably 1 μm to 50 μm. This allows for diffusion bonding between the bumps during the pressure bonding of the first bump 24 and the second bump 28, as described later, enabling a strong bond between the first substrate 22 and the second substrate or semiconductor device 26. Furthermore, the rigidity of the entire multilayer substrate 34 can be further improved by performing resin encapsulation or other methods as described later, if necessary.

[0026] Furthermore, as shown in Figure 2, the first bump 24 and the second bump 28 are preferably circular or cylindrical in shape. In this case, the first bump 24 and the second bump 28 each preferably have a diameter D of 1 μm to 50 μm, more preferably 2 μm to 35 μm, even more preferably 3 μm to 30 μm, particularly preferably 4 μm to 25 μm, and most preferably 5 μm to 20 μm. Moreover, the pitch of the first bump 24 and the second bump 28 is preferably regularly arranged with a pitch P (center-to-center distance) of 1 μm to 40 μm, within the range where the bumps do not touch each other within each substrate surface, more preferably 2 μm to 35 μm, even more preferably 5 μm to 30 μm, particularly preferably 7 μm to 25 μm, and most preferably 8 μm to 20 μm. This allows for more favorable diffusion bonding between the bumps.

[0027] The joint surface of the first bump 24 (i.e., the surface that comes into contact with the second bump 28 during the pressure welding process described later) and the joint surface of the second bump 28 (i.e., the surface that comes into contact with the first bump 24 during the pressure welding process described later) preferably have an arithmetic mean height Sa of 0.1 nm to 70 nm, more preferably 0.2 nm to 60 nm, even more preferably 0.3 nm to 50 nm, and particularly preferably 0.5 nm to 40 nm. This allows for more favorable diffusion bonding between the bumps. The arithmetic mean height Sa can be measured using a commercially available 3D surface roughness shape measuring machine in accordance with standards such as ISO 25178, and under the conditions described in the examples of this specification.

[0028] (2) Cleaning treatment of bump joint surfaces As shown in Figure 1A(ii), the pressure is 1 × 10⁻⁶. -3 The bonding surfaces of the first bump 24 and the second bump 28 are subjected to a cleaning treatment in an atmosphere of Pa or less. This activates the bonding surfaces of the first bump 24 and the second bump 28. Normally, the surface of a bump made of metal or alloy has an oxide layer or an adsorbed layer (impurity layer). By performing the cleaning treatment in the above atmosphere, the oxide layer or adsorbed layer on the bump surface is removed, and the bonding hands of the metal atoms constituting the bonding surface of the bump are exposed (i.e., the surface is activated). Then, by bringing the activated bonding surfaces of the bumps into contact with each other, a bonding force is exerted, and the bumps are firmly bonded together. Thus, according to the present invention, even when using bumps with a high melting point of 600°C or higher, the first bump 24 and the second bump 28 can be bonded at a temperature of 90°C or lower, as described later. As a result, warping of the substrate due to heat treatment can be suppressed.

[0029] The cleaning process (and the pressure welding process described later) is performed at a pressure of 1 × 10 -3 The process is carried out in an atmosphere of Pa or less, preferably 1 × 10⁻⁶. -4 Pa or less, more preferably 1 × 10 -5 The procedure is carried out in an atmosphere of Pa or less. The lower limit of the pressure is not particularly limited and may be 0 Pa, but 1 × 10 -8A pressure of Pa or higher is practical. The above atmosphere may be either a vacuum atmosphere or an inert gas (e.g., nitrogen gas) atmosphere, but a vacuum atmosphere is preferred. For example, as shown in Figure 1A(ii), after transporting the first substrate 22 and the second substrate or semiconductor device 26 into the vacuum chamber 30, the inside of the vacuum chamber 30 can be made into a vacuum atmosphere by using a vacuum evacuation device (e.g., a vacuum pump) to discharge the gas from inside the vacuum chamber 30.

[0030] The cleaning treatment is preferably at least one selected from the group consisting of ion beam irradiation, neutral atom beam irradiation, and inert gas plasma treatment, and more preferably neutral atom beam irradiation. For example, as shown in Figure 1A(ii), the bonding surfaces of the first bump 24 and the second bump 28 can be preferably activated by irradiating the surface of the first substrate 22 on the first bump 24 side and the surface of the second substrate or semiconductor device 26 on the second bump 28 side with an ion beam (e.g., argon ion beam) or a neutral atom beam (e.g., argon atom beam) from a beam source 32. This cleaning treatment can preferably be performed using a commercially available room-temperature wafer bonding apparatus (e.g., "BOND MEISTER" manufactured by Mitsubishi Heavy Industries Machine Tools Ltd.).

[0031] (3) Pressure welding treatment As shown in Figure 1B(iii), the pressure continues to be 1 × 10⁻⁶. -3 In an atmosphere of Pa or less, the first substrate 22 and the second substrate or semiconductor device 26 are stacked so that the bonding surface of the (activated) first bump 24 and the bonding surface of the (activated) second bump 28 are in contact, and the first bump 24 and the second bump 28 are pressed together at a temperature of 90°C or less. This forms a multilayer substrate 34 in which the first substrate 22 and the second substrate or semiconductor device 26 are bonded. In this way, a multilayer substrate 34 can be manufactured in which short circuits between adjacent bumps in the planar direction of the substrate and warping of the substrate are suppressed.

[0032] As mentioned above, it is generally difficult to suppress both short circuits between bumps and warping of the substrate. In other words, conventional methods such as those disclosed in Patent Documents 5 and 6 involve thermocompression bonding at a temperature (e.g., 260°C or higher) at which the metal or alloy constituting the bumps sufficiently diffuses, thereby performing chip mounting. In such cases, although short circuits between wirings or between bumps can be prevented, the heat treatment can cause the wiring and the resin between wirings (e.g., photosensitive polyimide) to shrink, potentially causing deformation of the substrate. That is, differences in the thermal expansion coefficients of the materials constituting the substrate result in differences in the shrinkage rate during cooling, which can lead to problems such as warping of the molded product or deviation of the chip position from the design. In particular, substrates used in the next-generation packaging technologies FO-WLP and PLP, as mentioned above, have a lower profile package compared to conventional designs, making them more susceptible to warping during redistribution layer formation, and the above-mentioned problems become more pronounced.

[0033] In contrast, according to the present invention, the pressure bonding of the bonding surfaces of activated bumps can be performed in an environment without intentional heating and / or cooling. That is, direct bonding can be performed at a low temperature of 90°C or less, making it possible to effectively suppress warping of the substrate. Furthermore, according to the present invention, since no solder is interposed between the bumps, there is no risk of solder spreading, and even when the first substrate 22 or the second substrate has fine-pitch wiring (e.g., on the order of several μm), short circuits between wiring or between bumps can be effectively suppressed by arranging the bumps on the first substrate 22 and the second substrate (or semiconductor device 26) in opposing positions.

[0034] The pressure welding of the first bump 24 and the second bump 28 is preferably carried out by applying a surface pressure of 10 MPa to 350 MPa to the bonding surfaces of the first bump 24 and the second bump 28, more preferably 30 MPa to 300 MPa, and even more preferably 50 MPa to 200 MPa to the bonding surfaces of the first bump 24 and the second bump 28. The pressure welding of the first bump 24 and the second bump 28 is preferably carried out continuously in a vacuum chamber 30 that has undergone a cleaning treatment. Such continuous processing can preferably be carried out using a commercially available room-temperature wafer bonding apparatus (for example, "BOND MEISTER" manufactured by Mitsubishi Heavy Industries Machine Tools Ltd.).

[0035] From the viewpoint of more effectively suppressing warping of the multilayer substrate 34, it is preferable that the pressing of the first bump 24 and the second bump 28 be carried out in an environment without intentional heating and / or cooling. However, from the viewpoint of making the bond between the first bump 24 and the second bump 28 stronger, pressing with heating below a predetermined temperature is permissible. In this case, the temperature during pressing is preferably 90°C or lower, more preferably -30°C to 80°C, and even more preferably -20°C to 45°C.

[0036] (4) Underfill filling (optional step) As shown in Figure 1B(iv), after the first bump 24 and the second bump 28 are pressed together, a resin (e.g., a liquid-curable resin) may be filled into the gap between the first substrate 22 and the second substrate or semiconductor device 26 to form a resin layer 36 that covers the first bump 24 and the second bump 28. This will more firmly bond the first substrate 22 and the second substrate or semiconductor device 26, improving the vibration resistance and heat resistance of the multilayer substrate 34.

[0037] Preferred examples of the resin to be used for filling include epoxy resins, phenolic resins, and combinations thereof, with epoxy resin being more preferred.

[0038] (5) Resin sealing (optional process) When bonding the semiconductor device 26 to the first substrate 22, it is preferable to resin-encapsulate the semiconductor device 26 with a encapsulating material 38, as shown in Figure 1C(v). This further improves the overall rigidity of the multilayer substrate 34. The encapsulating material 38 can be made of any known material used for resin encapsulation of semiconductor devices (e.g., Si chips) (e.g., epoxy resin, etc.), and is not particularly limited.

[0039] (6) Detachment and removal of carrier (optional step) If the first substrate 22 includes a carrier-attached metal foil 18, the rigid carrier 12 and the intermediate layer 14 (if present) may optionally be peeled off from the multilayer substrate 34 at the location of the release layer 15, as shown in Figure 1C(vi). This peeling off is preferably performed by physical peeling. The physical peeling method is a technique in which the rigid carrier 12 is separated from the multilayer substrate 34 by being pulled off by hand, with tools, or by machine. Alternatively, the metal layer 16 exposed after the peeling off of the rigid carrier 12 may be removed by etching or chemical mechanical polishing (CMP).

[0040] Furthermore, if the rigid carrier 12 is a single-crystal silicon carrier, it is preferable to pay attention to the direction of delamination. Single-crystal silicon carriers typically have a notch or orientation flat on their outer circumference to indicate a reference point for crystal orientation. Generally, an orientation flat is formed when the diameter of single-crystal silicon is 200 mm or less, and a notch is formed when it is 200 mm or more. Hereinafter, these notches and orientation flats may be collectively referred to as "notches, etc."

[0041] If delamination occurs in a direction where the direction of external stress propagation coincides with the cleavage direction, the silicon carrier may be fractured, such as by the generation of cracks along the cleavage direction, starting from the point where the external stress was applied due to the initial delamination. To suppress such fracture due to cleavage of the silicon carrier, when the rigid carrier 12 is a single-crystal silicon carrier, it is preferable to apply external stress to delaminate the rigid carrier 12 in a manner that does not coincide with any direction of cleavage in the silicon carrier.

[0042] Therefore, according to a preferred embodiment of the present invention, the rigid carrier 12 is a single-crystal silicon carrier having a notch or the like on its outer circumference, and in the carrier peeling process, when the angle θ is defined clockwise starting from a half-line from the center of the single-crystal silicon carrier to the notch or the like, the peeling is performed such that the direction of external stress propagation is within the range of 1° < θ < 89°.

[0043] Wiring board A wiring board is provided according to a preferred embodiment of the present invention. Figure 3 conceptually shows a wiring board according to the present invention. As shown in Figure 3, the wiring board 56 of the present invention comprises a first substrate 22, a second substrate 52, and a plurality of bumps 54. The first substrate 22 is a rigid substrate. The plurality of bumps 54 are interposed between the first substrate 22 and the second substrate 52 to bond the first substrate 22 and the second substrate 52. The bumps 54 are made of a metal or alloy having a melting point of 600°C or higher and have a height of 0.6 μm or higher.

[0044] The wiring board 56 may be manufactured by any method. Typically, the wiring board 56 corresponds to the multilayer substrate 34 obtained after joining the first substrate 22 with the first bump 24 and the second substrate with the second bump 28 in the multilayer substrate manufacturing method described above. Therefore, the first substrate 22, the second substrate 52 and the bump 54 included in the wiring board 56 are as described above with respect to the first substrate 22 with the first bump 24 and the second substrate with the second bump 28 included in the multilayer substrate 34. Consequently, the bump 54 does not contain any bonding material such as solder in its intermediate portion. Furthermore, for ease of manufacture, it is preferable that the bump 54 has a single composition.

[0045] For example, as shown in Figure 3, the first substrate 22 is preferably a rigid substrate comprising a rigid carrier 12 and a redistribution layer 20 on the rigid carrier 12, and the redistribution layer 20 and the second substrate 52 are preferably bonded by a plurality of bumps 54. Alternatively, the second substrate 52 may be a rigid substrate comprising a rigid carrier 42 and a redistribution layer 50 on the rigid carrier 42. The rigid carriers 12 and 42 are preferably made of glass, silicon, or alumina.

[0046] The bumps 54 have a height of 0.6 μm or more, preferably 1.0 μm to 400 μm, more preferably 1.4 μm to 300 μm, even more preferably 1.8 μm to 200 μm, and most preferably 2 μm to 100 μm. Furthermore, the bumps 54 are preferably arranged regularly with a pitch (center-to-center distance) of 1 μm to 40 μm, more preferably 2 μm to 35 μm, even more preferably 5 μm to 30 μm, particularly preferably 7 μm to 25 μm, and most preferably 8 μm to 20 μm.

[0047] Metal foil with carrier As described above with reference to Figure 1A, the carrier-attached metal foil 18 optionally used in the method of the present invention comprises, in order, a rigid carrier 12, optionally an intermediate layer 14, a release layer 15, and a metal layer 16.

[0048] As described above, the material of the rigid carrier 12 may be any of glass, ceramics, a silicon-containing substrate, resin, or metal. That is, it is preferable that the rigid carrier 12 is capable of functioning as a rigid support such as a glass plate, ceramic plate, silicon wafer, or metal plate. Preferably, the rigid carrier 12 is composed of glass, a silicon-containing substrate, or alumina. More preferably, it is a glass carrier, a single-crystal silicon substrate, or a polycrystalline silicon substrate. Preferred examples of metals constituting the rigid carrier 12 include copper, titanium, nickel, stainless steel, and aluminum. Preferred examples of ceramics include alumina, zirconia, silicon nitride, aluminum nitride, and various other fine ceramics. Preferred examples of resins include polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyamide, polyimide, nylon, liquid crystal polymer, polyether ether ketone (PEEK®), polyamide imide, polyether sulfone, polyphenylene sulfide, polytetrafluoroethylene (PTFE), and ethylene tetrafluoroethylene (ETFE). More preferably, from the viewpoint of preventing warping of the coreless support due to heating, the material has a coefficient of thermal expansion (CTE) of less than 25 ppm / K (typically 1.0 ppm / K to 23 ppm / K). Examples of such materials include the various resins mentioned above (especially low thermal expansion resins such as polyimide and liquid crystal polymer), glass, silicon-containing substrates, and ceramics. Furthermore, from the viewpoint of ensuring handling and flatness during chip mounting, the rigid carrier 12 preferably has an elastic modulus of 30 GPa to 600 GPa, more preferably 40 GPa to 400 GPa, even more preferably 50 GPa to 250 GPa, and particularly preferably 60 GPa to 150 GPa. As a material that satisfies these characteristics, the rigid carrier 12 is preferably composed of glass, a silicon-containing substrate, or ceramics (e.g., alumina), more preferably glass, a silicon-containing substrate, or ceramics, and particularly preferably glass or a silicon-containing substrate. An example of a rigid carrier 12 composed of glass is a glass plate.When glass is used as the rigid carrier 12, it has advantages such as being lightweight, having a low coefficient of thermal expansion, high insulating properties, being rigid and having a flat surface, which allows for an extremely smooth surface on the metal layer 16. Furthermore, when the rigid carrier 12 is glass, it has advantages such as having surface flatness (coplanarity) that is advantageous for microcircuit formation, having chemical resistance in desmear and various plating processes in the wiring manufacturing process, and being able to employ a chemical separation method when peeling the rigid carrier 12 from the carrier-attached metal foil 18. Preferred examples of glass constituting the rigid carrier 12 include quartz glass, borosilicate glass, alkali-free glass, soda-lime glass, aluminosilicate glass, and combinations thereof, more preferably alkali-free glass, soda-lime glass, and combinations thereof, and particularly preferably alkali-free glass. Alkali-free glass is a glass that is substantially free of alkali metals, mainly composed of silicon dioxide, aluminum oxide, boron oxide, and alkaline earth metal oxides such as calcium oxide and barium oxide, and further containing boric acid. This alkali-free glass has the advantage of minimizing glass warping in heating processes because its thermal expansion coefficient is low and stable in the range of 3 ppm / K to 5 ppm / K over a wide temperature range from 0°C to 350°C. When a silicon-containing substrate is used as the rigid carrier 12, it has advantages such as being lightweight like glass, having a low thermal expansion coefficient, high insulation properties, and being rigid with a flat surface, allowing for an extremely smooth surface on the metal layer 16. Furthermore, when the rigid carrier 12 is a silicon-containing substrate, it has advantages such as surface flatness (coplanarity) that is advantageous for fine circuit formation, chemical resistance in desmear and various plating processes in wiring manufacturing processes, and the ability to employ chemical separation methods when peeling the rigid carrier 12 from the carrier-attached metal foil 18. Any substrate containing Si as an element can be used as the silicon-containing substrate that constitutes the rigid carrier 12, such as SiO2 substrates, SiN substrates, Si single crystal substrates, and Si polycrystalline substrates. The thickness of the rigid carrier 12 is preferably 100 μm or more and 2000 μm or less, more preferably 300 μm or more and 1800 μm or less, and even more preferably 400 μm or more and 1100 μm or less.If the rigid carrier 12 has a thickness within this range, it is possible to achieve thinner wiring and reduced warping that occurs when mounting electronic components, while ensuring appropriate strength that does not impede handling.

[0049] The optional intermediate layer 14 may consist of one layer or two or more layers. If the intermediate layer 14 consists of two or more layers, it includes a first intermediate layer provided directly above the rigid carrier 12 and a second intermediate layer provided adjacent to the release layer 15. The first intermediate layer is preferably composed of at least one metal selected from the group consisting of Ti, Cr, Al, and Ni, in order to ensure adhesion with the rigid carrier 12. The first intermediate layer may be a pure metal or an alloy. The thickness of the first intermediate layer is preferably 5 nm to 500 nm, more preferably 10 nm to 300 nm, even more preferably 18 nm to 200 nm, and particularly preferably 20 nm to 100 nm. The second intermediate layer is preferably composed of Cu, in order to control the peel strength with respect to the release layer 15 to a desired value. The thickness of the second intermediate layer is preferably 5 nm to 500 nm, more preferably 10 nm to 400 nm, even more preferably 15 nm to 300 nm, and particularly preferably 20 nm to 200 nm. Another intervening layer may exist between the first intermediate layer and the second intermediate layer. Examples of materials for the intervening layer include alloys of Cu with at least one metal selected from the group consisting of Ti, Cr, Mo, Mn, W, and Ni. On the other hand, if the intermediate layer 14 is a single layer, the first intermediate layer described above may be used as the intermediate layer as is, or the first and second intermediate layers may be replaced with a single intermediate alloy layer. This intermediate alloy layer is preferably composed of a copper alloy having a content of 1.0 at% or more of at least one metal selected from the group consisting of Ti, Cr, Mo, Mn, W, Al, and Ni, and a Cu content of 30 at% or more. The thickness of the intermediate alloy layer is preferably 5 nm to 500 nm, more preferably 10 nm to 400 nm, even more preferably 15 nm to 300 nm, and particularly preferably 20 nm to 200 nm. The thickness of each layer described above is measured by analyzing the cross-section of the layer with an energy-dispersive X-ray spectrometer (TEM-EDX) on a transmission electron microscope. The metal constituting the intermediate layer 14 may contain unavoidable impurities resulting from the raw material components or the film formation process.Furthermore, although not particularly limited, the presence of oxygen introduced when the intermediate layer 14 is exposed to the atmosphere after film formation is acceptable. The intermediate layer 14 may be manufactured by any method, but it is particularly preferable that it be formed by magnetron sputtering using a metal target, as this allows for uniformity of the film thickness distribution.

[0050] The release layer 15 is a layer that enables or facilitates the release of the rigid carrier 12 and, if present, the intermediate layer 14. The release layer 15 may be removable by applying physical force, or it may be removable by a laser (laser lift-off, LLO). If the release layer 15 is made of a material that can be removed by laser lift-off, the release layer 15 may be made of a resin whose interfacial adhesion strength decreases upon laser irradiation after curing, or it may be a layer of silicon or silicon carbide that is modified by laser irradiation. Furthermore, the release layer 15 may be either an organic release layer or an inorganic release layer. Examples of organic components used in the organic release layer include nitrogen-containing organic compounds, sulfur-containing organic compounds, and carboxylic acids. Examples of nitrogen-containing organic compounds include triazole compounds and imidazole compounds. On the other hand, examples of inorganic components used in the inorganic release layer include metal oxides or metal oxynitrides containing at least one of Cu, Ti, Al, Nb, Zr, Cr, W, Ta, Co, Ag, Ni, In, Sn, Zn, Ga, Mo, or carbon. Among these, the release layer 15 is preferably a layer mainly composed of carbon from the viewpoint of ease of release and layer formation, more preferably a layer mainly composed of carbon or hydrocarbons, and even more preferably a layer made of amorphous carbon, which is a hard carbon film. In this case, the carbon concentration of the release layer 15 (i.e., the carbon-containing layer) as measured by XPS is preferably 60 atomic% or more, more preferably 70 atomic% or more, even more preferably 80 atomic% or more, and particularly preferably 85 atomic% or more. The upper limit of the carbon concentration is not particularly limited and may be 100 atomic%, but 98 atomic% or less is more practical. The release layer 15 may contain unavoidable impurities (e.g., oxygen, carbon, hydrogen, etc. originating from the surrounding environment such as the atmosphere). Furthermore, due to the film formation method used for the metal layer 16 and other layers that are later laminated, metal atoms of types other than the metal contained in the release layer 15 may be mixed into the release layer 15.When a carbon-containing layer is used as the release layer 15, the interdiffusivity and reactivity with rigid carriers are low, and even when subjected to press working at temperatures exceeding 300°C, the formation of metallic bonds due to high-temperature heating between the metal layer and the bonding interface is prevented, maintaining a state where the rigid carriers can be easily peeled off. It is preferable that the release layer 15 is formed by a vapor phase method such as sputtering, in terms of suppressing excessive impurities in the release layer 15 and ensuring the continuous productivity of other layers. When a carbon-containing layer is used as the release layer 15, the thickness is preferably 1 nm to 20 nm, and more preferably 1 nm to 10 nm. This thickness is measured by analyzing the cross-section of the layer with an energy-dispersive X-ray spectrometer (TEM-EDX) on a transmission electron microscope.

[0051] The release layer 15 may include a metal oxide layer and a carbon-containing layer, or it may be a layer containing both metal oxide and carbon. In particular, when the carrier-attached metal foil 18 includes an intermediate layer 14, the carbon-containing layer contributes to the stable release of the rigid carrier 12, and the metal oxide layer can suppress the diffusion of metal elements originating from the intermediate layer 14 and the metal layer 16 during heating. As a result, stable release properties can be maintained even after heating to high temperatures of, for example, 350°C or higher. The metal oxide layer is preferably a layer containing an oxide of a metal composed of Cu, Ti, Al, Nb, Zr, Cr, W, Ta, Co, Ag, Ni, In, Sn, Zn, Ga, Mo, or a combination thereof. The metal oxide layer is preferably formed by a reactive sputtering method using a metal target and sputtering in an oxidizing atmosphere, as the film thickness can be easily controlled by adjusting the film formation time. The thickness of the metal oxide layer is preferably 0.1 nm to 100 nm. The upper limit of the thickness of the metal oxide layer is more preferably 60 nm or less, even more preferably 30 nm or less, and particularly preferably 10 nm or less. This thickness is measured by analyzing the cross-section of the layer with an energy-dispersive X-ray spectrometer (TEM-EDX) on a transmission electron microscope. In this case, the order in which the metal oxide layer and the carbon layer are stacked as the release layer 15 is not particularly limited. Furthermore, the release layer 15 may exist in a multiphase state (i.e., a layer containing both metal oxide and carbon) where the boundary between the metal oxide layer and the carbon-containing layer is not clearly defined.

[0052] Similarly, from the viewpoint of maintaining stable release properties even after heat treatment at high temperatures, the release layer 15 may be a metal-containing layer whose surface adjacent to the metal layer 16 is a fluorinated surface and / or a nitrided surface. Preferably, the metal-containing layer has a region (hereinafter referred to as the "(F+N) region") over a thickness of 10 nm or more in which the sum of the fluorine content and nitrogen content is 1.0 atomic% or more, and the (F+N) region is preferably located on the metal layer 16 side of the metal-containing layer. The thickness of the (F+N) region (in terms of SiO2) is determined by performing depth-direction elemental analysis of the carrier-attached metal foil 18 using XPS. The fluorinated surface or nitrided surface can preferably be formed by reactive ion etching (RIE) or reactive sputtering. On the other hand, it is preferable that the metal elements contained in the metal-containing layer have a negative standard electrode potential. Preferred examples of metal elements included in the metal-containing layer include Cu, Ag, Sn, Zn, Ti, Al, Nb, Zr, W, Ta, Mo, and combinations thereof (e.g., alloys and intermetallic compounds). The metal element content in the metal-containing layer is preferably 50 atomic% to 100 atomic%. The metal-containing layer may be a single layer or a multilayer composed of two or more layers. The overall thickness of the metal-containing layer is preferably 10 nm to 1000 nm, more preferably 30 nm to 500 nm, even more preferably 50 nm to 400 nm, and particularly preferably 100 nm to 300 nm. The thickness of the metal-containing layer itself is measured by analyzing the cross-section of the layer with an energy-dispersive X-ray spectrometer (TEM-EDX) on a transmission electron microscope.

[0053] Alternatively, the release layer 15 may be a metal oxynitride-containing layer instead of a carbon layer or the like. The surface of the metal oxynitride-containing layer opposite to the rigid carrier 12 (i.e., the side facing the metal layer 16) preferably contains at least one metal oxynitride selected from the group consisting of TaON, NiON, TiON, NiWON, and MoON. Furthermore, in order to ensure adhesion between the rigid carrier 12 and the metal layer 16, the surface of the metal oxynitride-containing layer facing the rigid carrier 12 preferably contains at least one selected from the group consisting of Cu, Ti, Ta, Cr, Ni, Al, Mo, Zn, W, TiN, and TaN. This suppresses the number of foreign particles on the surface of the metal layer 16, improves circuit formation, and makes it possible to maintain stable release strength even after heating at high temperatures for a long time. The thickness of the metal oxynitride-containing layer is preferably 5 nm to 500 nm, more preferably 10 nm to 400 nm, even more preferably 20 nm to 200 nm, and particularly preferably 30 nm to 100 nm. This thickness is determined by analyzing the layer cross-section using an energy-dispersive X-ray spectrometer (TEM-EDX) on a transmission electron microscope.

[0054] The metal layer 16 is a layer made of metal. The metal layer 16 may be a single layer or a layer of two or more. When the metal layer 16 is made up of two or more layers, the metal layer 16 can be configured such that each metal layer from the first metal layer to the mth metal layer (where m is an integer of 2 or more) is sequentially stacked on the side of the release layer 15 opposite to the rigid carrier 12. The total thickness of the metal layer 16 is preferably 1 nm to 2000 nm, more preferably 100 nm to 1500 nm, more preferably 200 nm to 1000 nm, even more preferably 300 nm to 800 nm, and particularly preferably 350 nm to 500 nm. The thickness of the metal layer 16 is measured by analyzing the cross-section of the layer with an energy-dispersive X-ray spectrometer (TEM-EDX) on a transmission electron microscope. Below, an example in which the metal layer 16 is made up of two layers, a first metal layer and a second metal layer, will be described.

[0055] The first metal layer preferably provides the carrier-attached metal foil 18 with desired functions such as etching stopper function and anti-reflective function. Preferred examples of metals constituting the first metal layer include Ti, Al, Nb, Zr, Cr, W, Ta, Co, Ag, Ni, Mo and combinations thereof, more preferably Ti, Zr, Al, Cr, W, Ni, Mo and combinations thereof, even more preferably Ti, Al, Cr, Ni, Mo and combinations thereof, and particularly preferably Ti, Mo and combinations thereof. These elements have the property of not dissolving in flash etching solutions (e.g., copper flash etching solutions), and as a result, they can exhibit excellent chemical resistance to flash etching solutions. Therefore, the first metal layer is less susceptible to etching by flash etching solutions than the second metal layer described later, and thus can function as an etching stopper layer. Furthermore, since the above-mentioned metals constituting the first metal layer also have the function of preventing light reflection, the first metal layer can also function as an anti-reflective layer to improve visibility in image inspection (e.g., automated image inspection (AOI)). The first metal layer may be a pure metal or an alloy. The metal constituting the first metal layer may contain unavoidable impurities resulting from the raw material components or the film formation process. Furthermore, there is no particular upper limit to the metal content, and it may be 100 atomic percent. The first metal layer is preferably formed by physical vapor deposition (PVD), and more preferably by sputtering. The thickness of the first metal layer is preferably 1 nm to 500 nm, more preferably 10 nm to 400 nm, even more preferably 30 nm to 300 nm, and particularly preferably 50 nm to 200 nm.

[0056] Preferred examples of metals constituting the second metal layer include transition elements of Groups 4, 5, 6, 9, 10, and 11, Al, and combinations thereof (e.g., alloys and intermetallic compounds). More preferably, transition elements of Groups 4 and 11, Al, Nb, Co, Ni, Mo, and combinations thereof. Even more preferably, transition elements of Group 11, Ti, Al, Mo, and combinations thereof. Particularly preferred are Cu, Ti, Mo, and combinations thereof. Most preferably, Cu. The second metal layer may be manufactured by any method, for example, a metal foil formed by wet deposition methods such as electroless metal plating and electrolytic metal plating, physical vapor deposition (PVD) methods such as sputtering and vacuum deposition, chemical vapor deposition, or a combination thereof. A particularly preferred second metal layer is a metal layer formed by physical vapor deposition (PVD) methods such as sputtering or vacuum deposition, from the viewpoint of easily accommodating fine pitch reduction through ultrathinning, and most preferably, a metal layer manufactured by sputtering. Furthermore, while the second metal layer is preferably an unroughened metal layer, it may also be a layer that has undergone secondary roughening due to preliminary roughening, soft etching, cleaning, or oxidation-reduction treatment, as long as it does not hinder the formation of the wiring pattern. From the viewpoint of accommodating fine pitch, the thickness of the second metal layer is preferably 10 nm to 1000 nm, more preferably 20 nm to 900 nm, even more preferably 30 nm to 700 nm, even more preferably 50 nm to 600 nm, particularly preferably 70 nm to 500 nm, and most preferably 100 nm to 400 nm. Metal layers with thicknesses within this range are preferably manufactured by sputtering in terms of in-plane uniformity of film thickness and productivity in sheet or roll form.

[0057] When the metal layer 16 has a single-layer structure, it is preferable to use the second metal layer described above as the metal layer 16. On the other hand, when the metal layer 16 has an n-layer structure (where n is an integer of 3 or more), it is preferable to have the first metal layer to the (n-1)th metal layer of the metal layer 16 have the configuration of the first metal layer described above, and the outermost layer of the metal layer 16, i.e., the nth metal layer, have the configuration of the second metal layer described above.

[0058] It is preferable that the metal layer 16, optionally an intermediate layer 14, and optionally a release layer 15 (i.e., at least the metal layer 16, for example, the metal layer 16 and the intermediate layer 14) extend to the end face of the rigid carrier 12 so that the end face is covered. In other words, it is preferable that not only the surface of the rigid carrier 12 but also the end face is covered with at least the metal layer 16. By covering the end face as well, it is possible to prevent chemicals from penetrating the rigid carrier 12 during the manufacturing process of the wiring board, and it is also possible to firmly prevent chipping due to peeling at the side edges when handling the carrier-attached metal foil 18, i.e., chipping of the film on the release layer 15 (i.e., the metal layer 16). The covered area on the end face of the rigid carrier 12 is preferably an area of ​​0.1 mm or more, more preferably an area of ​​0.2 mm or more, and even more preferably extends over the entire end face of the rigid carrier 12, in the thickness direction (i.e., the direction perpendicular to the rigid carrier surface) from the surface of the rigid carrier 12. [Examples]

[0059] The present invention will be further explained by the following examples.

[0060] Example A1 A multilayer substrate was manufactured by bonding a rigid substrate having a redistribution layer to a semiconductor device at room temperature.

[0061] (1) Preparation of metal foil with carrier A metal foil with a carrier was prepared by sputtering a 200 mm diameter, 0.7 mm thick glass substrate (material: soda-lime glass) as the rigid carrier 12, on which a titanium layer (thickness 50 nm) and a copper layer (thickness 200 nm) as the intermediate layer 14, an amorphous carbon layer (thickness 6 nm) as the release layer 15, and a titanium layer (thickness 100 nm) and a copper layer (thickness 300 nm) as the metal layer 16 were deposited in this order.

[0062] (2) Formation of the first substrate and the first bump A first substrate 22 was obtained by forming a rewiring layer 20 including an insulating layer and a wiring layer on a carrier-attached metal foil 18 by a coreless build-up method. Then, a plurality of first bumps 24 were formed on the rewiring layer 20 of the first substrate 22 (see Fig. 1A(i)). Specifically, a photosensitive resist was applied to the surface of the first substrate 22 on the rewiring layer 20 side, followed by exposure and development to form a photoresist layer with a predetermined pattern. Next, after performing patterned electrolytic copper plating on the exposed surface of the rewiring layer 20 (that is, the portion not masked by the photoresist layer), the photoresist layer was peeled off to form the plurality of first bumps 24. Optical microscope observation images (magnification: 100×) and scanning electron microscope (SEM) observation images (magnification: 2000×) of the first bumps 24 provided on the first substrate 22 are shown in Figs. 4 and 5, respectively. The formed first bumps 24 were cylindrical with a height of 5 µm and a diameter of 5 µm, and were regularly arranged at a pitch (center-to-center distance) of 10 µm.

[0063] (3) Preparation of semiconductor device A Si chip was prepared as the semiconductor device 26. In the same manner as the method for forming the first bumps 24 in (2) above, cylindrical second bumps 28 having a height of 5 µm and a diameter of 5 µm were regularly formed at a pitch of 10 µm on the surface of the semiconductor device 26 (see Fig. 1A(i)).

[0064] (4) Cleaning treatment Pressure 1×10 -5In a vacuum below Pa, the bonding surfaces of the first bump 24 and the second bump 28 were cleaned using a room-temperature wafer bonding apparatus (BOND MEISTER, MWB-06 / 08AX, manufactured by Mitsubishi Heavy Industries Machine Tools Ltd.) (see Figure 1A(ii)). Specifically, the first substrate 22 and semiconductor device 26 obtained in (2) and (3) above were placed in the vacuum chamber 30, and then the gas in the vacuum chamber 30 was discharged to create a vacuum state below the above pressure. Subsequently, the surface of the first substrate 22 on the side where the first bump 24 is provided and the surface of the semiconductor device 26 on the side where the second bump 28 is provided were irradiated for 360 seconds from a high-speed atomic beam source, which served as the beam source 32. This activated the bonding surfaces of the first bump 24 and the second bump 28, respectively.

[0065] (5) Pressure welding The first substrate 22 and the semiconductor device 26 were bonded at room temperature using the above-described room-temperature wafer bonding apparatus (see Figure 1B(iii)). Specifically, a pressure of 1 × 10⁻¹⁰ was applied. -3 In a vacuum of less than Pa, the first substrate 22 and the semiconductor device 26 were stacked and pressed so that the bonding surfaces of the activated first bump 24 and the activated second bump 28 were in contact. At this time, the pressing load was 100kN (140MPa as the surface pressure applied to the bonding surfaces of the first bump 24 and the second bump 28), and the pressing was performed at room temperature (25°C) without heating. In this way, the first bump 24 and the second bump 28 were pressed together, and a multilayer substrate 34 was obtained in which the first substrate 22 and the semiconductor device 26 were bonded.

[0066] (6) Underfill filling and resin sealing In the obtained multilayer substrate 34, a liquid curable epoxy resin (CEL-C-3900, manufactured by Showa Denko Materials Co., Ltd.) was filled into the gap between the first substrate 22 and the semiconductor device 26, and then cured to form a resin layer 36 covering the first bump 24 and the second bump 28 (see Figure 1B(iv)). Subsequently, the surface of the multilayer substrate 34 on the semiconductor device 26 side was resin-sealed with an epoxy resin encapsulant 38 so as to cover the semiconductor device 26 (see Figure 1C(v)).

[0067] Example A2 In Example A1 (2), when forming a redistribution layer 20 including an insulating layer and a wiring layer on the carrier-equipped metal foil 18 using the coreless build-up method, 96 pin-shaped pillars 25 (material: copper) were installed on the periphery of the redistribution layer 20 (the part outside the first bump 24), as shown in Figures 6A and 6B. Otherwise, the process was the same as in Example A1, and a multilayer substrate 34 with the first substrate 22 and semiconductor device 26 bonded to it, as shown in Figure 7, was obtained.

[0068] Examples B1~B8 The first and second substrates were bonded at room temperature, and the bonding strength between the bumps was evaluated.

[0069] (1) Preparation of the first circuit board A substrate was prepared, designated as the first substrate 22, on which a titanium layer (thickness 50 nm) and a copper layer (thickness 200 nm) were deposited by sputtering on a disc-shaped glass sheet (material: soda-lime glass) with a diameter of 200 mm and a thickness of 0.7 mm, which served as the rigid carrier 12.

[0070] (2) Formation of the first bump First bumps 24 were formed in a 100 mm x 100 mm rectangular area in the center of the first substrate 22 using a semi-additive method. Specifically, a photosensitive resist was applied to the copper layer side surface of the first substrate 22, exposed and developed to form a photoresist layer with a predetermined pattern. Next, pattern electrolytic copper plating was performed on the exposed surface of the copper layer (i.e., the part not masked by the photoresist layer), and then the photoresist layer was peeled off to form multiple first bumps 24 in the rectangular area. The formed first bumps 24 were cylindrical with the height and diameter of 6 μm shown in Table 1, and were regularly arranged with a pitch (distance between centers) of 10 μm. In addition to the formation of the first bumps 24, alignment mark circuits were formed on the copper layer side surface of the first substrate 22 using the same method as described above. These circuits were formed at positions (4 locations) 65 mm apart in all directions (up, down, left, and right) from the center of the first substrate 22.

[0071] (3) Fabrication of the second substrate A second substrate with the second bump 28 formed on its surface was fabricated in the same manner as in (1) and (2) above, except that the height of the second bump 28 was set as shown in Table 1.

[0072] (4) Etching process To form alignment marks, the surface of the first substrate 22 on the side where the first bump 24 was formed, and the surface of the second substrate on the side where the second bump 28 was formed, were each etched using a copper etching solution. In the case of examples B1, B3, and B5-B8, a 100mm x 100mm rectangular area in the center of the first substrate 22 and the second substrate was covered with a sheet to prevent the first bump 24 and the second bump 28 from coming into contact with the etching solution, and then the etching process was performed. On the other hand, in the case of examples B2 and B4, the etching process was performed without covering the above area with a sheet. Figure 8 shows the SEM image (magnification: 10,000x) of the bumps after etching in example B1, B3, or B5-B8, and Figure 9 shows the SEM image (magnification: 10,000x) of the bumps after etching in example B2. Furthermore, the surface shape of the joint surface of the first bump 24 and the second bump 28 after etching was measured using a 3D surface roughness measuring instrument (NexView, manufactured by Zygo) in accordance with ISO 25178, under the conditions of a 50x objective lens, a 20x zoom lens, and a measurement range of 89 μm × 87 μm. From the obtained three-dimensional surface shape, a roughness curve of a range of 3 μm × 3 μm was extracted, and the roughness curve was corrected using the analysis program "Mx" attached to the instrument under the following correction conditions, and the arithmetic mean height Sa was calculated. The results are shown in Table 1. <Correction Conditions> -Remove:Form Remove - Filter Type: Spline - Filter: Low Pass - Type: Gaussian Spline Auto

[0073] (5) Cleaning treatment and room temperature bonding The first bump 24 and the second bump 28 were pressed together using the same method as in (4) and (5) of Example A1 to obtain a multilayer substrate 34 in which the first substrate 22 and the second substrate were joined.

[0074] (6) Evaluation of joint strength To evaluate the bonding strength between the first bump 24 and the second bump 28, a peel test was performed as follows. Specifically, after fixing the second substrate side of the multilayer substrate 34, the edge of the first substrate 22 was grasped by hand and peeled off. The multilayer substrate 34 after peeling was observed, and those that had peeled at the bonding surface between the first bump 24 and the second bump 28 were judged as unacceptable, while all others (for example, those that had peeled between the copper layer of the first substrate 22 and the first bump 24) were judged as acceptable. The results are shown in Table 1. Notably, no short circuits between the bumps or warping of the substrate were observed in any of the examples B1 to B7.

[0075] [Table 1]

[0076] Examples C1 and C2 A wiring board was manufactured by joining the first and second circuit boards.

[0077] (1) Preparation of the first substrate and formation of the first bump Except for setting the height of the first bump 24 to 5 μm, the first substrate 22 on which the first bump 24 was formed was manufactured using the same method as in (1) and (2) of Examples B1 to B8.

[0078] (2) Preparation of the second circuit board The substrate prepared in (1) of Examples B1 to B8 was designated as the second substrate 52. No bumps were formed on this second substrate 52.

[0079] (3) Etching process An etching process using a copper etching solution was performed on the surface of the first substrate 22 on the side where the first bump 24 was formed. In example C1, to prevent the first bump 24 from coming into contact with the etching solution, a 100 mm x 100 mm rectangular area in the center of the first substrate 22 was covered with a sheet before the etching process was performed. On the other hand, in example C2, the etching process was performed without covering the above area with a sheet. The second substrate 52 was not etched.

[0080] (4) Cleaning treatment and pressure welding treatment The bonding surface of the first bump 24 and the copper layer surface of the second substrate 52 were cleaned using the same method as in (4) of Example A1. Then, using the same method as in (5) of Example A1, the first substrate 22 and the second substrate 52 were stacked and pressed so that the activated bonding surface of the first bump 24 and the activated copper layer surface of the second substrate 52 were in contact. In this way, a wiring board 56 was obtained in which the first substrate 22 and the second substrate 52 were joined via the first bump 24 (bump 54).

Claims

1. A method for manufacturing a multilayer substrate, A step of preparing a first substrate, which is a rigid substrate having a plurality of first bumps on its surface in a predetermined arrangement, and a second substrate or semiconductor device having a plurality of second bumps on its surface in an arrangement corresponding to the predetermined arrangement, wherein each of the first bumps and the second bumps is made of a metal or alloy having a melting point of 600°C or higher and has a height of 0.3 μm or higher, Pressure 1 x 10 －３ In an atmosphere of Pa or less, the joint surfaces of the first bump and the second bump are subjected to a cleaning treatment. Continue with pressure 1 x 10 －３ A step of forming a multilayer substrate by stacking the first substrate and the second substrate or semiconductor device in an atmosphere of Pa or less such that the bonding surface of the first bump and the bonding surface of the second bump are in contact, and pressing the first bump and the second bump together at a temperature of 90°C or less, Includes, A method for manufacturing a multilayer substrate, wherein the first substrate is a rigid substrate having a thickness of 300 μm or more and 2000 μm or less, a redistribution layer on the rigid carrier, and the plurality of first bumps on the redistribution layer.

2. The method according to claim 1, wherein the second substrate is a rigid substrate comprising a rigid carrier, a redistribution layer on the rigid carrier, and the plurality of second bumps on the redistribution layer.

3. The method according to claim 1 or 2, wherein the cleaning treatment is at least one selected from the group consisting of ion beam irradiation, neutral atom beam irradiation, and inert gas plasma treatment.

4. The method according to any one of claims 1 to 3, wherein the modulus of elasticity of at least one of the first substrate and the second substrate is 30 GPa or more and 600 GPa or less.

5. The method according to any one of claims 1 to 4, wherein at least one of the first substrate and the second substrate contains silicon or alumina.

6. The method according to any one of claims 1 to 5, wherein at least one of the first substrate and the second substrate includes glass.

7. The method according to any one of claims 1 to 6, wherein the first bump and the second bump each have a height of 0.3 μm or more.

8. The method according to any one of claims 1 to 7, wherein the first bump and the second bump are each circular in shape with a diameter of 1 μm or more and 50 μm or less.

9. The method according to any one of claims 1 to 8, wherein the first bump and the second bump are arranged regularly with a pitch (center-to-center distance) of 1 μm or more and 40 μm or less.

10. The method according to any one of claims 1 to 9, wherein the joint surface of the first bump and the joint surface of the second bump each have an arithmetic mean height Sa of 0.1 nm or more and 70 nm or less.

11. The method according to any one of claims 1 to 10, wherein the first bump and the second bump are made of a transition metal.

12. The method according to any one of claims 1 to 11, wherein the first bump and the second bump consist of at least one selected from the group consisting of Au, Ag, and Cu.

13. The method according to any one of claims 1 to 10, wherein the first bump and the second bump are made of Cu.

14. The method according to any one of claims 1 to 13, wherein the pressure welding is performed by applying a surface pressure of 10 MPa or more and 350 MPa or less to the joint surface of the first bump and the joint surface of the second bump.

15. The method according to any one of claims 1 to 14, further comprising the step of filling the gap between the first substrate and the second substrate or semiconductor device with resin after the first bump and the second bump have been pressed together to form a resin layer covering the first bump and the second bump.

16. The method according to any one of claims 1 to 15, wherein the pressure welding is performed in an environment without intentional heating and / or cooling.

17. The first substrate is a rigid substrate, The second circuit board, A plurality of bumps interposed between the first substrate and the second substrate, connecting the first substrate and the second substrate, The bump is made of a metal or alloy having a melting point of 600°C or higher, and has a height of 0.6 μm or higher. The first substrate is a rigid substrate comprising a rigid carrier having a thickness of 300 μm or more and 2000 μm or less, and a redistribution layer on the rigid carrier, wherein the redistribution layer and the second substrate are bonded together by the plurality of bumps, in a wiring substrate.

18. The wiring board according to claim 17, wherein the rigid carrier is composed of glass, a silicon-containing substrate, or alumina.

19. The wiring board according to claim 17 or 18, wherein the bumps are regularly arranged with a pitch (center-to-center distance) of 1 μm or more and 40 μm or less.

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