High frequency, high power thin film components

Abstract

The resistive divider may include a monolithic substrate and a patterned resistive layer formed above the monolithic substrate. The resistive divider may include a first terminal, a second terminal, and a third terminal, each connected to the patterned resistive layer. The resistive divider may include at least one frequency compensation conductive layer formed above a portion of the patterned resistive layer. In some embodiments, the resistive divider may exhibit a first insertion loss response between the first terminal and the second terminal of greater than about -10 dB for frequencies between about 0 GHz and about 30 GHz.

Description

[[Technical Field]]

[0001] Cross-Reference to Related Applications This application claims the benefit of U.S. Provisional Patent Application No. 63 / 154,045 filed on February 26, 2021, the entire content of which is incorporated herein by reference. [[Background Art]]

[0002] High-frequency radio signal communication is growing in popularity. For example, the demand for increased data transfer rates for wireless connections has driven the demand for high-frequency components, including those configured to operate in 5G spectrum frequencies. At the same time, the trend toward miniaturization has increased the demand for smaller passive components.

[0003] High-frequency radio signal communication can include various signal processing operations such as signal distribution. A signal distributor can receive an input signal and split it uniformly into a first output signal and a second output signal. Compact distributors that can operate at high frequencies including 5G frequencies would be welcomed in the art. [[Summary of the Invention]] [[Means for Solving the Problems]]

[0004] According to an embodiment of the present disclosure, a resistive divider may include a monolithic substrate and a patterned resistive layer formed over the monolithic substrate. The resistive divider may include a first terminal, a second terminal, and a third terminal, each connected to the patterned resistive layer. The resistive divider may include at least one frequency compensation conductive layer formed over a portion of the patterned resistive layer.

[0005] According to another embodiment of the present disclosure, the resistor distributor may include a monolithic substrate and a patterned resistive layer formed above the monolithic substrate. The resistor distributor may include a first terminal, a second terminal, and a third terminal, each connected to the patterned resistive layer. The resistor distributor may exhibit a first insertion loss response greater than approximately -10 dB between the first terminal and the second terminal for frequencies from approximately 0 GHz to approximately 30 GHz.

[0006] According to another embodiment of the present disclosure, a method for forming a resistor divider may include the steps of: forming a patterned resistor layer on the surface of a monolithic substrate; depositing a first terminal, a second terminal, and a third terminal on the surface of the monolithic substrate, each connected to the patterned resistor layer; and depositing at least one frequency compensating conductive layer on a portion of the patterned resistor layer.

[0007] Sufficient disclosures, including the best mode, that would make the invention available to those skilled in the art are described in more detail in the remainder of the specification with reference to the accompanying drawings. [Brief explanation of the drawing]

[0008] [Figure 1] This is a perspective view of one embodiment of a resistor divider according to an aspect of the subject matter of this disclosure. [Figure 2A] This is a perspective view of another embodiment of a resistor divider according to aspects of the subject matter of this disclosure. [Figure 2B] This is a top view of the resistor divider shown in Figure 1, according to an aspect of the subject matter of this disclosure. [Figure 3A] This is a perspective view of another embodiment of a resistor divider according to aspects of the subject matter of this disclosure. [Figure 3B] Figure 3A is a top view of a resistor divider according to an aspect of the subject matter of this disclosure. [Figure 3C] This is a top view of another embodiment of a resistor divider according to an aspect of the subject matter of this disclosure. [Figure 3D] This is a top view of another embodiment of a resistor divider according to an aspect of the subject matter of this disclosure. [Figure 4A] This is a perspective view of another embodiment of a resistor divider according to aspects of the subject matter of this disclosure. [Figure 4B] This is a top view of an embodiment of the resistor divider shown in Figure 4A, according to an aspect of the subject matter of this disclosure. [Figure 5A] This is a perspective view of another embodiment of a resistor divider according to an aspect of the subject matter of the present disclosure. [Figure 5B] Figure 5A is a top view of a resistor divider according to an aspect of the subject matter of this disclosure. [Figure 6A] This is a perspective view of another embodiment of a resistor divider according to an aspect of the subject matter of the present disclosure. [Figure 6B] Figure 6A is a top view of a resistor divider according to an aspect of the subject matter of this disclosure. [Figure 7] This figure shows the simulated insertion loss response curve for the resistor divider shown in Figure 1. [Figure 8] Figures 2A and 2B show the simulated insertion loss response curves of the resistor divider. [Figure 9] This is a flowchart of a method for forming a resistance divider according to an aspect of the subject matter of this disclosure. [Modes for carrying out the invention]

[0009] Reference letters used repeatedly in this specification and in the figures are intended to represent the same or similar functions or elements of the present invention.

[0010] Those skilled in the art will understand that this discussion is merely a description of exemplary embodiments and is not intended to limit broader aspects of the invention embodied in the exemplary structures.

[0011] Generally, the present invention relates to a surface-mount resistor distributor having excellent performance characteristics at high frequencies. The resistor distributor can employ a configuration that uniformly distributes an input signal applied to a first terminal to a first output signal at a second terminal and a second output signal at a third terminal.

[0012] The resistor divider may exhibit a first insertion loss response between a first terminal and a second terminal, and a second insertion loss response between a first terminal and a third terminal. The first and / or second insertion loss responses may be greater than approximately -10 dB between the first and second terminals for frequencies from approximately 0 GHz to approximately 30 GHz, greater than approximately -9 dB in some embodiments, greater than -8 dB in some embodiments, greater than approximately -7 dB in some embodiments, and greater than approximately -6 dB in some embodiments.

[0013] The insertion loss response curves can be very well matched overall, such that the input signal is uniformly distributed between the second and third terminals. For example, the change from the first insertion loss to the second insertion loss response may be less than 3 dB for frequencies from about 0 GHz to about 30 GHz, less than about 2 dB in some embodiments, less than about 1 dB in some embodiments, less than about 0.5 dB in some embodiments, less than about 0.3 dB in some embodiments, and less than about 0.1 dB in some embodiments.

[0014] A resistance divider may include a monolithic substrate and a patterned resistance layer formed on top of the monolithic substrate. The monolithic substrate may be or may include a variety of suitable materials. For example, the monolithic substrate may be or may include a variety of ceramic materials such as aluminum oxide (alumina), aluminum nitride, beryllium oxide, boron nitride, silicon nitride, magnesium oxide, zinc oxide, silicon carbide, any suitable ceramic material, and mixtures thereof. The monolithic substrate may be or may include silicon (Si), glass, and glass ceramic materials.

[0015] The resistive layer may be formed using various thin-film techniques including photolithography or other suitable patterning techniques, etching, PECVD (plasma enhanced chemical vapor deposition) processing, or other additive and / or subtractive techniques. The resistive layer may be formed from various suitable resistive materials. For example, the resistive layer may include tantalum nitride (TaN), nickel chromium (NiCr), tantalum aluminide, chromium silicon, titanium nitride, titanium tungsten, tantalum tungsten, oxides and / or nitrides of such materials, and / or other suitable thin-film resistive materials. The resistive layer may have any suitable thickness. For example, in some embodiments, the thickness of the resistive layer may be from about 0.001 μm to about 1,000 μm, in some embodiments from about 0.01 μm to about 100 μm, in some embodiments from about 0.1 μm to about 50 μm, and in some embodiments from about 0.5 μm to about 20 μm.

[0016] The resistive divider may include a first terminal, a second terminal, and a third terminal. Each of the first terminal, the second terminal, and the third terminal may be connected to the patterned resistive layer. One or more frequency compensation conductive layers may be formed over the patterned resistive layer. The frequency compensation conductive layer may contribute to excellent high-frequency response characteristics of the resistive divider.

[0017] In some embodiments, the frequency compensation conductive layer may be formed using thin-film methods. For example, the frequency compensation conductive layer is formed using various thin-film techniques including photolithography or other suitable patterning techniques, etching, PECVD (plasma enhanced chemical vapor deposition) processing, or other additive and / or subtractive techniques. However, the frequency compensation conductive layer may be formed using any suitable technique such as printing, dipping, stripping, or other techniques for forming a conductive layer.

[0018] The frequency-compensating conductive layer can be formed from a variety of suitable conductive materials. For example, the frequency-compensating conductive layer may include aluminum, copper, gold, silver, nickel, mixtures thereof, and / or other suitable metals, metal-filled polymer materials, or other suitable conductive materials.

[0019] The frequency-compensating conductive layer can have any suitable thickness. For example, in some embodiments, the thickness of the frequency-compensating conductive layer may be about 0.001 μm to about 1,000 μm, in some embodiments it may be about 0.01 μm to about 100 μm, in some embodiments it may be about 0.1 μm to about 50 μm, and in some embodiments it may be about 0.5 μm to about 20 μm.

[0020] The patterned resistive layer can form a first resistive path between a first terminal and a second terminal. The patterned resistive layer can form a second resistive path between a first terminal and a third terminal. The ratio of the length of the first resistive path to the length of the second resistive path is 0.9 to 1.1, about 0.95 to 1.05 in some embodiments, about 0.97 to 1.03 in some embodiments, and about 0.98 to 1.02 in some embodiments.

[0021] The patterned resistive layer may include a central portion, a first leg extending and connected between the first terminal and the central portion of the patterned resistive layer, a second leg extending and connected between the second terminal and the central portion of the patterned resistive layer, and a third leg extending and connected between the third terminal and the central portion of the patterned resistive layer.

[0022] In some embodiments, the first, second, and third legs may be arranged at equal angular intervals around a central point. For example, the respective angles with respect to the central point may be formed between the terminals.

[0023] In some embodiments, the first, second, and third legs may form an overall T-shape. In some embodiments, the first, second, and third legs may form an overall triangular shape.

[0024] A first frequency-compensating conductive layer may be formed above the first leg. A second frequency-compensating conductive layer may be formed above the second leg. A third frequency-compensating conductive layer may be formed above the third leg. No conductive layer may be formed above the central portion of the patterned resistive layer.

[0025] In some embodiments, two or more frequency-compensating conductive layers may have the same or similar surface area. For example, a first frequency-compensating conductive layer may have a first surface area. A second frequency-compensating conductive layer may have a second surface area approximately equal to the first surface area. For example, the ratio of the first surface area to the second surface area may be about 0.9 to about 1.1, in some embodiments about 0.95 to about 1.05, in some embodiments about 0.97 to about 1.03, and in some embodiments about 0.98 to about 1.02.

[0026] The third frequency-compensating conductive layer may have a third surface area approximately equal to that of the first surface. For example, the ratio of the first surface area to the third surface area is about 0.9 to about 1.1, about 0.95 to about 1.05 in some embodiments, about 0.97 to about 1.03 in some embodiments, and about 0.98 to about 1.02 in some embodiments.

[0027] According to aspects of the present disclosure, the resistance distributor may include a first terminal, a second terminal, and a third terminal arranged at equal angular intervals around a central point. For example, angles with respect to the central point may be formed between the terminals.

[0028] A frequency-compensating conductive layer may be formed above the central point. The frequency-compensating conductive layer may have a shape that appears identical to each current flowing from each terminal to the central point. For example, the frequency-compensating conductive layer may have a circular shape with a center aligned to the central point. For example, the frequency-compensating conductive layer may have a triangular shape. The resistor distributor may include a monolithic substrate and a patterned resistor layer formed above the monolithic substrate. The frequency-compensating conductive layer is formed above the patterned resistor layer and may have any suitable shape.

[0029] In some embodiments, the frequency compensation conductive layer may have its center around the central point, but is formed above the central point. That is, the frequency compensation conductive layer may be formed above the patterned resistive layer so that it does not overlap the central point even if the frequency compensation conductive layer is centered there. In such embodiments, the frequency compensation conductive layer may have a shape that appears identical to each current flowing from each terminal to the central point. As an example, the frequency compensation conductive layer may have a circular or annular shape with a center aligned to the central point. As another example, the frequency compensation conductive layer may have a hexagonal shape.

[0030] One or more protective or deactivating layers may be formed above the resistive layer and / or frequency compensation structure. The deactivating layer may include a variety of suitable materials such as benzocyclobutene (BCB) polyimide, silicon oxynitride, Al2O3, SiO2, Si3N4, epoxy, glass, or other suitable material. The terminals may include respective vias formed through the deactivating layer.

[0031] In some embodiments, the thin-film component may have a small size, for example, a small footprint. For example, in some embodiments, the total length of the thin-film component may be about 0.1 mm to about 5 mm, in some embodiments about 0.2 mm to about 4 mm, in some embodiments about 0.3 mm to about 3 mm, in some embodiments about 0.4 mm to about 2 mm, and for example, about 1 mm.

[0032] In some embodiments, the overall width of the thin-film component may be approximately 0.05 mm to approximately 2.5 mm, approximately 0.1 mm to approximately 2 mm, approximately 0.15 mm to approximately 1.5 mm, approximately 0.2 mm to approximately 1.3 mm, approximately 0.3 mm to approximately 1 mm, and for example, approximately 0.5 mm.

[0033] In some embodiments, the overall thickness of the thin-film component may be approximately 0.05 mm to approximately 2.5 mm, approximately 0.1 mm to approximately 2 mm, approximately 0.15 mm to approximately 1.5 mm, approximately 0.2 mm to approximately 1.3 mm, approximately 0.3 mm to approximately 1 mm, and for example, approximately 0.5 mm.

[0034] Resistance distributors can be configured in various surface-mount forms. For example, a resistance distributor can be configured in a grid array type mounting such as a land grid array or a ball grid array. However, in other embodiments, the external terminals may be formed partially or entirely on the side of the substrate, such as in castellations. Various arbitrary suitable external terminals can be provided for surface mounting the resistance distributor.

[0035] Figure 1 is a perspective view of one embodiment of the resistor distributor 100. The resistor distributor 100 may include a monolithic substrate 102 and a patterned resistor layer 104 formed on top of the monolithic substrate 102. The resistor distributor 100 may include a first terminal 106, a second terminal 108, and a third terminal 110. Each of the first terminal 106, the second terminal 108, and the third terminal 110 may be connected to the patterned resistor layer 104. One or more frequency-compensating conductive layers 112, 114, 116 may be formed on top of the patterned resistor layer 104. The frequency-compensating conductive layers 112, 114, 116 may include a variety of suitable conductive materials such as aluminum, copper, gold, silver, nickel, or mixtures thereof.

[0036] The patterned resistive layer 104 can form a first resistive path between the first terminal 106 and the second terminal 108. The patterned resistive layer 104 can form a second resistive path between the first terminal 106 and the third terminal 108. The ratio of the length of the first resistive path to the length of the second resistive path is 0.9 to 1.1.

[0037] The patterned resistive layer 104 may include a central portion 118, a first leg 120 extending and connected between the first terminal 106 and the central portion 118 of the patterned resistive layer 104, and a second leg 122 extending and connected between the second terminal 108 and the central portion 118 of the patterned resistive layer 104.

[0038] A first frequency-compensating conductive layer 112 may be formed above the first leg 120. A second frequency-compensating conductive layer 114 may be formed above the second leg 122. A third frequency-compensating conductive layer 116 may be formed above the third leg 124. No conductive layer may be formed above the central portion 118 of the patterned resistive layer 104.

[0039] In some embodiments, two or more of the frequency compensation conductive layers 112, 114, and 116 may have the same or similar surface area. For example, the first frequency compensation conductive layer 112 may have a first surface area. The second frequency compensation conductive layer 114 may have a second surface area approximately equal to the first surface area. For example, the ratio of the first surface area to the second surface area may be about 0.9 to about 1.1. The third frequency compensation conductive layer 116 may have a third surface area approximately equal to the first surface area. For example, the ratio of the first surface area to the third surface area is about 0.9 to about 1.1.

[0040] One or more protective or deactivating layers may be formed above the resistive layer 104 and / or the frequency-compensating conductive layers 112, 114, 116. Bypers 126, 128, 130, which may include terminals 106, 108, 110, respectively, are formed through the deactivating layer and exposed for surface mounting of the resistive distributor 100.

[0041] Figure 2A is a perspective view of one embodiment of the resistor distributor 200. Figure 2B is a top view of the resistor distributor 200 of Figure 2A. The resistor distributor 200 may include a monolithic substrate 202 and a patterned resistor layer 204 formed above the monolithic substrate 202. The resistor distributor 200 may include a first terminal 206, a second terminal 208, and a third terminal 210. Each of the first terminal 206, the second terminal 208, and the third terminal 210 may be connected to the patterned resistor layer 204.

[0042] In some embodiments, terminals 206, 208, and 210 may be arranged at equal angular intervals around the central point 212. For example, angles 214, 216, and 218 may be formed between terminals 208 and 210, between terminals 206 and 208, and between terminals 210 and 206, respectively, with respect to the central point 212.

[0043] A frequency-compensating conductive layer 220 may be formed above the central point 212. One or more protective or deactivating layers may be formed above the resistive layer 204 and / or the frequency-compensating conductive layer 220. Bypers 226, 228, and 230, which may include terminals 206, 208, and 210, are formed through the deactivating layer and exposed for surface mounting of the resistive distributor 200.

[0044] The frequency compensation conductive layer 220 may have a shape that appears identical to each current flowing from terminals 206, 208, and 210 to the central point 212. For example, the frequency compensation conductive layer 220 may have a circular shape with a center aligned to the central point 212.

[0045] Referring to another example, Figures 3A and 3B, the frequency compensation conductive layer 320 may have a triangular shape. In Figures 3A and 3B, reference numbers similar to those in Figures 2A and 2B are used. For example, the resistor distributor 300 in Figures 3A and 3B may include a monolithic substrate 302 and a patterned resistor layer 304 formed above the monolithic substrate 302. The resistor distributor 300 may include a first terminal 306, a second terminal 308, and a third terminal 310. Each of the first terminal 306, the second terminal 308, and the third terminal 310 may be connected to the patterned resistor layer 304.

[0046] Figure 3C shows a further exemplary shape for the frequency compensation conductive layer 360. Figure 3D shows another exemplary shape for the frequency compensation conductive layer 380. However, any suitable shape can be employed that affects the respective currents flowing from each terminal 306, 308, and 310 to the central point 312.

[0047] Next, with reference to Figures 4A, 4B, 5A, and 5B, in some embodiments the resistor distributor may have other configurations. For example, Figure 4A is a perspective view of one embodiment of the resistor distributor 400, and Figure 4B is a top view of the resistor distributor 400 of Figure 4A. The resistor distributor 400 may include a monolithic substrate 402 and a patterned resistive layer 404 formed above the monolithic substrate 402. The resistor distributor 400 may include a first terminal 406, a second terminal 408, and a third terminal 410. Each of the first terminal 406, the second terminal 408, and the third terminal 410 may be connected to the patterned resistive layer 404.

[0048] Furthermore, as shown in Figures 4A and 4B, the patterned resistive layer 404 may include a first leg 404A extending from a first terminal 406 to a central point 412, a second leg 404B extending from a second terminal 408 to a central point 412, and a third leg 404C extending from a third terminal 410 to a central point 412. As shown in Figure 4B, in some embodiments, the first leg 404A, the second leg 404B, and the third leg 404C may be arranged at equal angular intervals around the central point 412. For example, angles 414, 416, and 418 may be formed between leg 404C and leg 404B, between leg 404B and leg 404A, and between leg 404A and leg 404C, respectively, with respect to the central point 412.

[0049] Furthermore, in some embodiments, the patterned resistive layer 404 may include a central portion 419 whose center is above the central point 412. A first leg 404A may extend and connect between the first terminal 406 and the central portion 419 of the patterned resistive layer 404; a second leg 404B may extend and connect between the second terminal 408 and the central portion 419 of the patterned resistive layer 404; and a third leg 404C may extend and connect between the third terminal 410 and the central portion 419 of the patterned resistive layer 404.

[0050] The frequency compensation conductive layer 420 may be formed around the central point 412; that is, the frequency compensation conductive layer 420 may have a center with respect to the central point 412. As shown in the embodiments of Figures 4A and 4B, the shape of the frequency compensation conductive layer 420 is hexagonal. In some embodiments, such as those shown in Figures 4A and 4B, the hexagonal frequency compensation conductive layer 420 may consist only of the hexagonal contour of the material, so that the frequency compensation conductive layer 420 does not overlap the central point 412. That is, in some embodiments, the frequency compensation conductive layer 420 consists of adjacent material only at the edges of the shape, rather than a continuous piece of material from one edge to the opposite edge, with no material at the center of the shape.

[0051] One or more protective or deactivating layers may be formed above the resistive layer 404 and / or the frequency-compensating conductive layer 420. Bypers 426, 428, and 430, which may include terminals 406, 408, and 410, are formed through the deactivating layer and exposed for surface mounting of the resistive distributor 400.

[0052] Comparing the embodiments of Figures 4A and 4B with the embodiments shown in Figures 1 to 3D, terminals 406, 408, and 410 may have different shapes from terminals 106, 108, 110, 206, 208, 210, 306, 308, and 310, and / or vias 426, 428, and 430 may have different shapes from vias 126, 128, 130, 226, 228, 230, 326, 328, and 330. For example, terminals 106, 108, 110, 206, 208, 210, 306, 308, and 310 shown in Figures 1 to 3D are generally square in shape, and the vias 126, 128, 130, 226, 228, 230, 326, 328, and 330 are generally octagonal or circular in shape, while the terminals 406, 408, and 410 and vias 426, 428, and 430 of the resistor distributor 400 are generally rectangular in shape.

[0053] Figures 5A and 5B show a resistor distributor 500 according to another embodiment of the subject. The resistor distributor 500 is generally similar to the resistor distributor 400 shown in the embodiments of Figures 4A and 4B, but has a circular frequency-compensating conductive layer 520 instead of a hexagonal one. More specifically, the resistor distributor 500 may include a monolithic substrate 502 and a patterned resistive layer 504 formed on top of the monolithic substrate 502. The resistor distributor 500 may include a first terminal 506, a second terminal 508, and a third terminal 510. Each of the first terminal 506, the second terminal 508, and the third terminal 510 may be connected to the patterned resistive layer 504. The frequency-compensating conductive layer 520 may be formed on top of the patterned resistive layer 504. One or more protective or inert layers may be formed on top of the resistive layer 504 and / or the frequency-compensating conductive layer 520. vias 526, 528, and 530, which may include terminals 506, 508, and 510 respectively, are formed through an inert layer and exposed for surface mounting of the resistor distributor 500. As described with respect to the resistor distributor 400 shown in Figures 4A and 4B, terminals 506, 508, 510 and / or vias 526, 528, and 530 may have a different shape from terminals 106, 108, 110, 206, 208, 210, 306, 308, 310 and / or vias 126, 128, 130, 226, 228, 230, 326, 328, and 330 shown in Figures 1 to 3D. In other embodiments, one or more of the terminals 406, 408, 410, 506, 508, 510 and / or vias 426, 428, 430, 526, 528, 530 may have the same shape as the terminals 106, 108, 110, 206, 208, 210, 306, 308, 310 and / or vias 126, 128, 130, 226, 228, 230, 326, 328, 330.

[0054] Furthermore, as shown in Figures 5A and 5B, the patterned resistive layer 504 may include a first leg 504A extending from a first terminal 506 to a central point 512, a second leg 504B extending from a second terminal 508 to a central point 512, and a third leg 504C extending from a third terminal 510 to a central point 512. As shown in Figure 5B, in some embodiments, the first leg 504A, the second leg 504B, and the third leg 504C may be arranged at equal angular intervals around the central point 512. For example, angles 514, 516, and 518 may be formed between leg 504C and leg 504B, between leg 504B and leg 504A, and between leg 504A and leg 504C, respectively, with respect to the central point 512.

[0055] Furthermore, in some embodiments, the patterned resistive layer 504 may include a central portion 519 whose center is above the central point 512. A first leg 504A may extend and connect between the first terminal 506 and the central portion 519 of the patterned resistive layer 504, a second leg 504B may extend and connect between the second terminal 508 and the central portion 519 of the patterned resistive layer 504, and a third leg 504C may extend and connect between the third terminal 510 and the central portion 519 of the patterned resistive layer 504.

[0056] The frequency compensation conductive layer 520 may be formed around the central point 512, that is, the frequency compensation conductive layer 520 may have a center with respect to the central point 512. As shown in the embodiments in Figures 5A and 5B, the shape of the frequency compensation conductive layer 520 is circular. In some embodiments, such as those shown in Figures 5A and 5B, the circular frequency compensation conductive layer 520 may consist only of a circular outline of the material, so that the frequency compensation conductive layer 520 does not overlap the central point 512. That is, in some embodiments, the frequency compensation conductive layer 520 is a ring of material centered at the central point 512, and the overall shape of the frequency compensation conductive layer 520 is annular, and it consists of material that is adjacent only at the edges of the shape and not at the center of the shape, rather than a continuous piece of material from one edge to the opposite edge.

[0057] Next, moving to Figures 6A and 6B, a resistor distributor 600 according to another embodiment of the subject is shown in perspective view (Figure 6A) and top view (Figure 6B). The resistor distributor 600 is configured in a similar manner to the exemplary resistor distributor 100 shown in Figure 1, but is triangular in shape rather than the overall T-shape shown in the embodiment of Figure 1. More specifically, the resistor distributor 600 may include a monolithic substrate 602 and a patterned resistive layer 604 formed above the monolithic substrate 602. The resistor distributor 600 may include a first terminal 606, a second terminal 608, and a third terminal 610. Each of the first terminal 606, the second terminal 608, and the third terminal 610 may be connected to the patterned resistive layer 604.

[0058] The patterned resistive layer 604 can form a first resistive path between the first terminal 606 and the second terminal 608. The patterned resistive layer 604 can form a second resistive path between the first terminal 606 and the third terminal 608. The ratio of the length of the first resistive path to the length of the second resistive path is 0.9 to 1.1.

[0059] One or more frequency-compensating conductive layers 612, 614, 616 may be formed above the patterned resistive layer 604. For example, a first frequency-compensating conductive layer 612 may be formed above the first leg 620. A second frequency-compensating conductive layer 614 may be formed above the second leg 622. A third frequency-compensating conductive layer 616 may be formed above the third leg 624. As shown in Figures 6A and 6B, the first leg 620, the second leg 622, and the third leg 624 form an overall triangular shape, whereas the first leg 120, the second leg 122, and the third leg 124 in the embodiment shown in Figure 1 form an overall T-shape.

[0060] As shown in Figures 6A and 6B, in some embodiments, the first leg 620 may extend and connect between the first terminal 606 and the second terminal 608, the second leg 622 may extend and connect between the second terminal 608 and the third terminal 610, and the third leg 624 may extend and connect between the third terminal 610 and the first terminal 606. As described above, in the embodiments shown, the terminals 606, 608, 610 and the legs 620, 622, 624 are arranged such that the legs 620, 622, 624 form an overall triangular shape.

[0061] In some embodiments, two or more of the frequency compensation conductive layers 612, 614, and 616 may have the same or similar surface area. For example, the first frequency compensation conductive layer 612 may have a first surface area. The second frequency compensation conductive layer 614 may have a second surface area approximately equal to the first surface area. For example, the ratio of the first surface area to the second surface area may be approximately 0.9 to approximately 1.1. The third frequency compensation conductive layer 616 may have a third surface area approximately equal to the first surface area. For example, the ratio of the first surface area to the third surface area is approximately 0.9 to approximately 1.1.

[0062] One or more protective or deactivating layers may be formed above the resistive layer 604 and / or the frequency-compensating conductive layers 612, 614, 616. Bypers 626, 628, 630, which may include terminals 606, 608, 610, respectively, are formed through the deactivating layer and exposed for surface mounting of the resistive distributor 600.

[0063] Figure 7 shows the simulated insertion loss response curve 700 for the resistor distributor 100 of Figure 1. The resistor distributor 100 exhibits a first insertion loss response 702 greater than approximately -10 dB between the first terminal 106 and the second terminal 108 for frequencies from approximately 0 GHz to approximately 30 GHz. The resistor distributor 100 exhibits a second insertion loss response 704 greater than approximately -10 dB between the first terminal 106 and the third terminal 110 for frequencies from approximately 0 GHz to approximately 30 GHz. The change from the first insertion loss 702 to the second insertion loss response 704 is less than 3 dB for frequencies from approximately 0 GHz to approximately 30 GHz.

[0064] Figure 8 shows the simulated insertion loss response curve 800 for the resistor distributor 200 in Figures 2A and 2B. The resistor distributor 200 exhibits a first insertion loss response 802 greater than approximately -10 dB between the first terminal 206 and the second terminal 208 for frequencies from approximately 0 GHz to approximately 30 GHz. The resistor distributor 200 exhibits a second insertion loss response 804 greater than approximately -10 dB between the first terminal 206 and the third terminal 210 for frequencies from approximately 0 GHz to approximately 30 GHz. The change from the first insertion loss 802 to the second insertion loss response 804 is less than 3 dB for frequencies from approximately 0 GHz to approximately 30 GHz.

[0065] Referring to Figure 9, aspects of this disclosure relate to a method 900 for forming a resistor divider. Generally, method 900 is described herein in relation to the resistor dividers 100, 200, 300, 400, 500, and 600 described above with reference to Figures 1 to 6B. However, it should be understood that the disclosed method 900 can be implemented for any resistor divider. In addition, Figure 9 shows the steps performed in a particular order for explanatory and discussion purposes, but the methods discussed herein are not limited to any particular order or mechanism. Those skilled in the art using the disclosures provided herein will understand that various steps of the methods disclosed herein can be omitted, rearranged, combined, and / or adapted in various ways without departing from the scope of this disclosure.

[0066] Method 900 may include step 902 of forming patterned resistive layers 104, 204, 304, 404, 504, and 604 on the surface of monolithic substrates 102, 202, 302, 402, 502, and 602. For example, the resistive material may be deposited using various thin-film techniques described herein. The resistive material may be etched to pattern the resistive layers 104, 204, 304, 404, 504, and 604.

[0067] Method 900 may include step 904 of forming first terminals 106, 206, 306, 406, 506, 606, second terminals 108, 208, 308, 408, 508, 608, and third terminals 110, 210, 310, 410, 510, 610 on the surface of monolithic substrates 102, 202, 302, 402, 502, 602, wherein each of the first terminals 106, 206, 306, 406, 506, 606, second terminals 108, 208, 308, 408, 508, 608, and third terminals 110, 210, 310, 410, 510, 610 is connected to patterned resistive layers 204, 304, 344. In some embodiments, terminals 106, 206, 306, 406, 506, 606, 108, 208, 308, 408, 508, 608, 110, 210, 310, 410, 510, and 610 may be arranged on the same surface of their respective monolithic substrates 102, 202, 302, 402, 502, and 602, such that the resistor distributors 100, 200, 300, 400, 500, and 600 are configured for grid array type mountings such as land grid arrays and ball grid arrays.

[0068] Method 900 may include step 906 of depositing at least one frequency-compensating conductive layer on top of portions of the patterned resistive layers 104, 204, 304, 404, 504, and 604. For example, referring to Figure 1, a first frequency-compensating conductive layer 112 may be formed on top of the first leg 120 of the patterned resistive layer 104. A second frequency-compensating conductive layer 114 may be formed on top of the second leg 122 of the patterned resistive layer 104. A third frequency-compensating conductive layer 116 may be formed on top of the third leg 124 of the patterned resistive layer 104. No conductive layer may be formed on top of the central portion 118 of the patterned resistive layer 104. As another example, Figure 6 similarly illustrates the step of depositing one of several frequency-compensating conductive layers 612, 614, and 616 on top of each leg 620, 622, and 624 of the patterned resistive layer 604.

[0069] In other embodiments, the step of depositing frequency-compensating conductive layers may include depositing single frequency-compensating conductive layers 220, 320, 360, 380, 420, 520 on top of patterned resistive layers 204, 304, 404, 504, as described above with reference to Figures 2A to 5B, for example.

[0070] Test method The following paragraphs provide illustrative methods for testing a resistor divider for insertion loss. The insertion loss response curve of the resistor divider can be measured using a Keithley 2400 series source measurement unit (SMU), such as the Keithley 2410C SMU. A first insertion loss curve can be measured between a first terminal and a second terminal. A second insertion loss curve can be measured between a first terminal and a third terminal.

[0071] These and other modifications and variations of the present invention can be practiced by those skilled in the art without departing from the spirit and scope of the invention. In addition, it should be understood that the various embodiments may be interchangeable, either whole or in part. Furthermore, those skilled in the art will understand that the foregoing description is illustrative and not intended to limit the invention as further described in such appended claims. [Explanation of Symbols]

[0072] 100 resistor divider 102 Monolithic PCB 104 Patterned resistive layer 106 First terminal 108 Second terminal 110 Third terminal 112 First frequency compensating conductive layer 114 Second frequency compensating conductive layer 116 Third frequency compensating conductive layer 118 Central part of the resistive layer 104 120 First leg 122 Second leg 124 The third leg 126 Bya 128 Bya 130 Via 200 resistor divider 202 Monolithic PCB 204 Patterned Resistive Layers 206 First terminal 208 Second terminal 210 Third terminal 212 Central Point 214 angle 216 angle 218 angle 220 Frequency Compensating Conductive Layer 226 Byar 228 Byar 230 Byar 300 resistor divider 302 Monolithic PCB 304 Patterned Resistive Layer 306 First terminal 308 Second terminal 310 Third terminal 312 Central Point 314 angle 316 angle 318 angle 320 Frequency Compensated Conductive Layer 326 Byar 328 Byar 330 Byar 360 Frequency Compensated Conductive Layer 380 Frequency Compensated Conductive Layer 400 resistor divider 402 Monolithic PCB 404 Patterned Resistor 404A First leg 404B Second leg 404C Third Leg 406 First terminal 408 Second terminal 410 Third terminal 412 Central Point 414 angle 416 angle 418 angle 419 Central part of the resistive layer 404 420 Frequency Compensating Conductive Layer 426 Bya 428 Byar 430 Byar 500 resistor divider 502 Monolithic PCB 504 Patterned Resistor 504A First leg 504B Second leg 504C Third Leg 506 First terminal 508 Second terminal 510 Third terminal 512 Central Point 514 angle 516 angle 518 angle 519 Central part of the resistive layer 504 520 Frequency Compensating Conductive Layer 526 Bya 528 Bya 530 Bya 600 resistor divider 602 Monolithic PCB 604 Patterned Resistor 606 First terminal 608 Second terminal 610 Third terminal 612 First frequency compensating conductive layer 614 Second frequency compensating conductive layer 616 Third frequency compensating conductive layer 618 Central part of the resistive layer 604 620 First leg 622 Second leg 624 The third leg 626 Bya 628 Byar 630 Bya

Claims

1. Monolithic substrate and A patterned resistive layer formed on top of the monolithic substrate, The first terminal, the second terminal, and the third terminal are connected to the patterned resistive layer, respectively. At least one conductive layer formed above a portion of the patterned resistive layer and Equipped with, The patterned resistive layer The central part, A first leg extending and connected between the first terminal and the central portion of the patterned resistance layer, A second leg extends and is connected between the second terminal and the central portion of the patterned resistance layer, A third leg extending and connected between the third terminal and the central portion of the patterned resistance layer and A resistor divider, including one.

2. The resistance distributor according to claim 1, wherein the patterned resistance layer forms a first resistance path between the first terminal and the second terminal, and a second resistance path between the first terminal and the third terminal, and the ratio of the length of the first resistance path to the length of the second resistance path is 0.9 to 1.

1.

3. The resistance divider according to claim 1 or 2, wherein the at least one conductive layer comprises aluminum, copper, gold, silver, nickel, or a mixture thereof.

4. The at least one conductive layer is A first conductive layer formed above the first leg, A second conductive layer formed above the second leg, A third conductive layer formed above the third leg and A resistance distributor according to claim 1, comprising:

5. The resistance distributor according to claim 4, wherein no conductive layer is formed above the central portion of the patterned resistance layer.

6. The first conductive layer has a first surface area, and the second conductive layer has a second surface area. The resistance divider according to claim 4, wherein the ratio of the first surface area to the second surface area is 0.9 to 1.

1.

7. The resistance divider according to claim 6, wherein the third conductive layer has a third surface area, and the ratio of the first surface area to the third surface area is 0.9 to 1.

1.

8. The resistance distributor according to claim 4, wherein the first leg, the second leg, and the third leg form an overall triangular shape.

9. The resistance distributor according to claim 1, wherein the center of the central part is located at the central point.

10. The resistance distributor according to claim 1, wherein the center of the conductive layer is at the central point and the conductive layer does not overlap the central point.

11. The resistor distributor according to claim 10, wherein the conductive layer has a hexagonal shape.

12. The resistor distributor according to claim 10, wherein the conductive layer has an annular shape.

13. The resistor distributor according to claim 1, 2, or 3, wherein the first terminal, the second terminal, and the third terminal are arranged at equal angular intervals around a central point.

14. The resistance distributor according to claim 13, wherein the patterned resistance layer is formed above the central point, and the at least one conductive layer is formed above the central point.

15. The resistance distributor according to claim 14, wherein the patterned resistance layer has a circular shape with a center aligned to the central point.

16. The resistance distributor according to claim 14, wherein the patterned resistance layer has a triangular shape with a center aligned to the central point.

17. The resistor distributor according to claim 1, 2, or 3, wherein the patterned resistor layer has a hexagonal shape.

18. The resistor divider according to claim 1, wherein the resistor divider exhibits a first insertion loss response greater than -10 dB between the first terminal and the second terminal for frequencies from 0 GHz to 30 GHz.

19. The resistor divider according to claim 18, wherein the resistor divider exhibits a second insertion loss response greater than -10 dB between the first terminal and the third terminal for frequencies from 0 GHz to 30 GHz.

20. The resistor divider according to claim 18, wherein the change in the second insertion loss response from the first insertion loss is less than 3 dB for frequencies from 0 GHz to 30 GHz.

21. The resistor distributor according to claim 1, wherein the first terminal, the second terminal, and the third terminal are arranged on the same side of the monolithic substrate for grid array type mounting of the resistor distributor with respect to the mounting surface.

22. Monolithic substrate and A patterned resistive layer formed on top of the monolithic substrate, The first terminal, the second terminal, and the third terminal are connected to the patterned resistive layer, respectively. Equipped with, The patterned resistive layer comprises a first leg extending from the first terminal, a second leg extending from the second terminal, and a third leg extending from the third terminal. Each of the first leg, the second leg, and the third leg has a center with respect to the central point. At least one conductive layer has a center with respect to the central point. It is a resistance divider, A resistor divider exhibiting a first insertion loss response greater than -10 dB between the first terminal and the second terminal for frequencies from 0 GHz to 30 GHz.

23. The resistor divider according to claim 22, which exhibits a second insertion loss response greater than -10 dB between the first terminal and the third terminal for frequencies from 0 GHz to 30 GHz.

24. The resistor divider according to claim 22, wherein the change in the second insertion loss response from the first insertion loss is less than 3 dB for frequencies from 0 GHz to 30 GHz.

25. The first terminal, the second terminal, and the third terminal are arranged at equal angular intervals around the central point. The patterned resistive layer is formed above the central point. The at least one conductive layer is formed above the central point. The resistance distributor according to claim 22.

26. A method for forming a resistor divider according to any one of claims 1 to 25, The steps include forming a patterned resistive layer on the surface of a monolithic substrate, The steps include depositing a first terminal, a second terminal, and a third terminal on the surface of the monolithic substrate, each connected to the patterned resistive layer, The steps include: depositing at least one conductive layer on top of a portion of the patterned resistive layer; A method that includes this.

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