Semiconductor memory

Abstract

[Problem] To more suitably perform a read-out operation. [Solution] This semiconductor memory device comprises: one or more first memory cells connected in parallel between a first voltage supply line that supplies a first voltage, and a second voltage supply line that supplies a second voltage different than the first voltage; and one or more second memory cells connected in parallel between the second voltage supply line and a third voltage supply line that supplies the first voltage. Each of the first memory cells has a first memory element having a resistance value corresponding to a first state or a second state, and a first cell transistor connected between the first memory element and the first voltage supply line. Each of the second memory cells includes: a second memory element having a resistance value corresponding to a first state or a second state; and a second cell transistor connected between the second memory element and the third voltage supply line.

Description

[Technical Field]

[0001] Embodiments according to the present disclosure relate to semiconductor memory devices. [Background Art]

[0002] Resistance change type memory elements and fuse elements are known as typical memory elements whose resistance values change according to a flowing current. A resistance change type memory element is a memory device that utilizes input / output of conductive ions to / from an insulating film, a change in conductivity according to the magnetization direction of a magnetic film, or a phase change of a crystal structure, and can reversibly change its resistance value.

[0003] In contrast, for fuse elements, in addition to the type that is burned out by laser light, there are known those that control the resistance value by electrically blowing a fuse made of, for example, polysilicon (see, for example, Non-Patent Document 1). As another example of a fuse element, there is also known one that stores data depending on whether or not the gate oxide film of a MOS transistor is electrically dielectrically broken down. These electrically controllable fuse elements are particularly called electrical fuses (eFUSE). [Prior Art Literature] [Non-Patent Literature]

[0004] [Non-Patent Document 1] Greg Uhlmann et al., “A Commercial Field-Programmable Dense eFUSE Array Memory with 99.999% Sense Yield for 45nm SOI CMOS”, Dig. ISSCC pp.406-407, Feb. 2008. [Summary of Invention] [Problem to be Solved by the Invention]

[0005] However, with electrical fuses, for example, depending on the number of bits written, it could be difficult to perform read operations properly.

[0006] Therefore, this disclosure provides a semiconductor memory device that can perform read operations more appropriately. [Means for solving the problem]

[0007] To solve the above problems, according to this disclosure, One or more first memory cells connected in parallel between a first voltage supply line that supplies a first voltage and a second voltage supply line that supplies a second voltage different from the first voltage, One or more second memory cells connected in parallel between the second voltage supply line and the third voltage supply line that supplies the first voltage, Equipped with, Each of the previous 1 memory cells is, A first memory element having a resistance value corresponding to the first or second state, A first cell transistor connected between the first memory element and the first voltage supply line, Each of the second memory cells is A second memory element having a resistance value corresponding to the first or second state, A semiconductor memory device is provided, which includes a second cell transistor connected between the second memory element and the third voltage supply line.

[0008] The number of the first memory cells and the number of the second memory cells may be the same.

[0009] The first memory cell and the second memory cell may be arranged substantially symmetrically with respect to the second voltage supply line.

[0010] A voltage supply unit that, in a read operation of the first memory cell or the second memory cell, supplies a first voltage to the first voltage supply line and the third voltage supply line, supplies a second voltage to the second voltage supply line, and stops supplying the first voltage, A cell transistor control unit that turns on the first cell transistor of the first memory cell to be read, or the second cell transistor of the second memory cell to be read, while the supply of the first voltage is stopped, It may also be provided.

[0011] The potential difference between the first voltage and the second voltage may be a potential difference corresponding to the difference in the rate of voltage change between the first voltage supply line and the third voltage supply line after the cell transistor control unit turns on the first cell transistor or the second cell transistor.

[0012] The second voltage supply line may be fixed to the second voltage.

[0013] A reference voltage generation unit generates a reference voltage having a voltage level between a voltage generated by biasing the first memory element and the second memory element, each having a resistance value corresponding to a first state, based on the first voltage and the second voltage, and a voltage generated by biasing the first memory element and the second memory element, each having a resistance value corresponding to a second state, based on the first voltage and the second voltage. A comparison unit that compares the reference voltage with a voltage generated when the first memory element or the second memory element is biased based on the first voltage and the second voltage, It may also be provided.

[0014] The aforementioned reference voltage generation unit is A first reference voltage generation unit is connected between the first voltage supply line and the second voltage supply line and generates the reference voltage when the second memory cell is read out, a second reference voltage generation unit connected between the second voltage supply line and the third voltage supply line, configured to generate the reference voltage when a read operation of the first memory cell is performed; may be provided.

[0015] the first reference voltage generation unit and the second reference voltage generation unit may be arranged substantially symmetrically with the second voltage supply line interposed therebetween.

[0016] the first reference voltage generation unit includes: a first reference resistance element; a first reference transistor connected between the first reference resistance element and the first voltage supply line; comprising the above, the second reference voltage generation unit includes: a second reference resistance element; a second reference transistor connected between the second reference resistance element and the third voltage supply line; may further comprise the above.

[0017] the comparison unit compares the voltage of the first voltage supply line with the voltage of the third voltage supply line, thereby comparing the reference voltage with a voltage generated by biasing the first storage element or the second storage element based on the first voltage and the second voltage, a comparison control unit that causes the comparison unit to start comparison at a timing corresponding to the voltages of the first voltage supply line and the third voltage supply line may be further provided.

[0018] the comparison control unit: when the first voltage is higher than the second voltage, causes the comparison unit to start comparison at a timing when a voltage of at least one of the first voltage supply line and the third voltage supply line becomes lower than a first predetermined value, when the first voltage is lower than the second voltage, may cause the comparison unit to start comparison at a timing when a voltage of at least one of the first voltage supply line and the third voltage supply line becomes higher than a second predetermined value.

[0019] In the read operation, the first voltage may be higher than the second voltage.

[0020] In the writing operation, the first voltage is lower than the second voltage. The second voltage during the write operation may be higher than the first voltage during the read operation.

[0021] In the writing operation, the first voltage is higher than the second voltage. The first voltage during the write operation may be higher than the first voltage during the read operation.

[0022] In the read operation, the first voltage may be lower than the second voltage.

[0023] In the writing operation, the first voltage is lower than the second voltage. The second voltage during the write operation may be higher than the second voltage during the read operation. [Brief explanation of the drawing]

[0024] [Figure 1] This is a schematic diagram showing an example configuration of a semiconductor memory device according to the first embodiment. [Figure 2] This is a circuit diagram showing a detailed configuration example of a semiconductor memory device according to the first embodiment. [Figure 3] This is a timing chart showing an example of the writing operation of a semiconductor memory device according to the first embodiment. [Figure 4] This is a timing chart showing an example of read operation of a semiconductor memory device according to the first embodiment. [Figure 5] This is a circuit diagram illustrating the bit line capacitance in a semiconductor memory device relating to a comparative example. [Figure 6] This is a circuit diagram illustrating the bit line capacitance in a semiconductor memory device according to the first embodiment. [Figure 7] This figure shows the time variation of the bit line voltage. [Figure 8]This is a circuit diagram showing a detailed configuration example of a semiconductor memory device according to the second embodiment. [Figure 9] This is a timing chart showing an example of the writing operation of a semiconductor memory device according to the second embodiment. [Figure 10] This is a timing chart showing an example of the read operation of a semiconductor memory device according to the second embodiment. [Figure 11] This is a circuit diagram showing a detailed configuration example of a semiconductor memory device according to the third embodiment. [Figure 12] This is a timing chart showing an example of the writing operation of a semiconductor memory device according to the third embodiment. [Figure 13] This is a timing chart showing an example of the read operation of a semiconductor memory device according to the third embodiment. [Figure 14] This is a circuit diagram showing a detailed configuration example of a semiconductor memory device according to the fourth embodiment. [Figure 15] This is a timing chart showing an example of the writing operation of a semiconductor memory device according to the fourth embodiment. [Figure 16] This is a timing chart showing an example of the read operation of a semiconductor memory device according to the fourth embodiment. [Modes for carrying out the invention]

[0025] The following description will focus on the main components of the semiconductor memory device, but there may be components and functions that are not shown or described. The following description does not exclude any components or functions that are not shown or described.

[0026] <First Embodiment> [Example of semiconductor memory device configuration] Figure 1 is a schematic diagram showing an example configuration of the semiconductor memory device 1 according to the first embodiment. However, Figure 1 only shows the main parts of the semiconductor memory device 1.

[0027] The semiconductor memory device 1 shown in Figure 1 includes a memory cell array 2, a decoder 4, a fuse power supply 6, and a read circuit 7.

[0028] The semiconductor memory device 1 has m (rows) × n (columns) memory cells MC arranged in a matrix in the memory cell array 2. In this embodiment, for example, m and n are integers of 2 or more, but for example, m = 1 and n is an integer of 2 or more.

[0029] The semiconductor memory device 1 has the function of selecting a desired memory cell MC from among these multiple memory cell MCs, the function of writing data to the selected memory cell MC, and the function of reading data from the selected memory cell MC.

[0030] Each memory cell MC has a fuse element F as a memory element and stores 1 bit of data ("0" or "1"). The memory cell MC shown in Figure 1 has a simplified illustration of the fuse element F. This fuse element F is, for example, an electric fuse element (eFUSE) whose resistance can be irreversibly controlled electrically. Hereafter, the explanation will assume that the fuse element F is, for example, an electric fuse element made of polysilicon fuse.

[0031] When a large current flows through a fuse element F, its resistance increases dramatically by changing the composition of the wiring material. Hereafter, passing a large current through the fuse element F will also be referred to as "blowing" it. For example, blowing the fuse element F changes its resistance from a low resistance (e.g., around 100Ω) to a high resistance (e.g., around 5kΩ).

[0032] In this embodiment as well, the low resistance value refers to the initial resistance value before current is passed through the fuse element F. The high resistance value refers to the resistance value after the fuse element F has been blown out. When the fuse element F is blown out, its resistance value may be comparable to that of the reference resistance elements (first reference resistance element RF1 and second reference resistance element RF2) (see Figure 2), which will be described later.

[0033] Here, the state in which the resistance value of fuse element F is low (first state) is associated with "0" and is also called the "unwritten state". Conversely, the state in which the resistance value of fuse element F is high (second state) is associated with "1" and is also called the "written state".

[0034] Thus, a memory cell MC stores one bit of data, either "0" or "1," based on the resistance value of the fuse element F. For this reason, changing the resistance value of the fuse element F from a low resistance value to a high resistance value is simply called "writing (to the memory cell MC)" or "programming."

[0035] When reading from the memory cell MC, the fuse element F is biased. Then, by comparing the voltages output to the first lead bit line RBLL and the second lead bit line RBLR (see Figure 2) on the bit line BL[n] with the reference voltage, the resistance value of the fuse element F of the memory cell MC, i.e., "0" or "1", is read by the read circuit 7.

[0036] Decoder 4 controls the operation of each memory cell MC in the memory cell array 2. Basically, decoder 4 selects the memory cell MC to be read from and the memory cell MC to be written to.

[0037] The fuse power supply 6 is connected to the bit line BL[n]. When writing to the memory cell MC, the fuse power supply 6 supplies the fuse power supply voltage VDDFIL (> power supply voltage VDD) to the fuse element F to bias the fuse element F.

[0038] The read circuit 7 includes, for example, a function to select the bit line BL[n], a comparison unit 72 (see Figure 2), and a reference voltage generation unit 71 (see Figure 2). When reading, the read circuit 7 reads data from the memory cell MC to be read.

[0039] [Details of semiconductor memory devices] Next, we will explain the m x n memory cell MC and its related components in relation to Figure 2.

[0040] Figure 2 is a circuit diagram showing a detailed configuration example of a semiconductor memory device according to the first embodiment.

[0041] As shown in Figure 2, the bit line BL[n] includes the first lead bit line RBLL, the second lead bit line RBLR, and the write bit line WBL.

[0042] The first lead bit line (first voltage supply line) RBLL supplies a predetermined voltage (first voltage) so that the fuse element F and the reference resistor element can be biased. Biasing is, for example, applied voltage. The fuse element F includes the first fuse element F1 and the second fuse element F2 shown in Figure 2. The reference resistor element includes the first reference resistor element RF1 and the second reference resistor element RF2 shown in Figure 2.

[0043] The second lead bit line (third voltage supply line) RBLR supplies a first voltage so that the fuse element F and the reference resistor element can be biased.

[0044] The light bit line (second voltage supply line) WBL supplies a predetermined voltage (second voltage) different from the first voltage, so that the fuse element F and the reference resistor element can be biased.

[0045] In the example shown in Figure 2, the first voltage during the write operation is, for example, the ground voltage (0V). The second voltage during the write operation is, for example, the fuse power supply voltage VDDFIL. Therefore, during the write operation, the first voltage is lower than the second voltage. During the read operation, the first voltage is, for example, the power supply voltage (reference voltage) VDD. The second voltage during the read operation is, for example, the ground voltage. Therefore, during the read operation, the first voltage is higher than the second voltage. Note that the second voltage during the write operation (fuse power supply voltage VDDFIL) is higher than the first voltage during the read operation (power supply voltage VDD). The fuse power supply voltage VDDFIL is, for example, approximately 1.8V. The power supply voltage VDD is, for example, approximately 0.8V.

[0046] The memory cell MC comprises a first memory cell MC1 and a second memory cell MC2. The first memory cell MC1 is located in the left column of the two rows of memory cell MCs shown in Figure 2. The second memory cell MC2 is located in the right column of the two rows of memory cell MCs shown in Figure 2.

[0047] One or more first memory cells MC1 are connected in parallel between the first read bit line RBLL and the write bit line WBL. One or more second memory cells MC2 are connected in parallel between the write bit line WBL and the second read bit line RBLR. Figure 2 illustrates a case where four memory cells MC are arranged in 2 columns (2 bits) x 2 rows (2 rows), but the arrangement of multiple memory cells MC is not limited to the configuration in Figure 2; for example, it may be in a single row. In the following, unless otherwise specified, it is assumed that the arrangement of multiple memory cells MC is in multiple columns x multiple rows.

[0048] Furthermore, the number of first memory cells MC1 and the number of second memory cells MC2 are the same. The first memory cells MC1 and the second memory cells MC2 are arranged approximately symmetrically (for example, approximately left-right symmetrically) with respect to the write bit line WBL. As a result, as will be explained later, the capacitance between the first read bit line RBLL and the second read bit line RBLR is approximately the same.

[0049] As shown in Figure 2, the first memory cell MC1 and the second memory cell MC2, arranged in two columns, constitute a single unit. The first memory cell MC1 and the second memory cell MC2, arranged in two columns, may be further arranged in multiple units in the row direction.

[0050] A configuration in which multiple memory cells (MCs) are arranged in a column direction is hereafter referred to as a bit configuration. Figure 2 illustrates one bit configuration with two columns. However, other bit configurations do not necessarily have to be the same as each other. In the following, we will explain one bit configuration assuming that multiple bit configurations are the same as each other.

[0051] The first memory cell MC1 includes a first fuse element F1 and a first access transistor TRA1.

[0052] The first fuse element (first memory element) F1 is connected between the first read bit line RBLL (first access transistor TRA1) and the write bit line WBL. The first fuse element F1 has a resistance value corresponding to the first or second state.

[0053] The first access transistor (first cell transistor) TRA1 is connected between the first fuse element F1 and the first lead bit line RBLL. Therefore, the first fuse element F1 is connected to the first lead bit line RBLL via the first access transistor TRA1, rather than being directly connected to the first lead bit line RBLL. This allows for more efficient read operations, as will be explained later.

[0054] Furthermore, the gate of the first access transistor TRA1 is connected to the word lines WL1, WL3, ... respectively. When the first access transistor TRA1 is turned on, the first fuse element F1 is biased by the fuse power supply voltage VDDFIL or the power supply voltage VDD. The first access transistor TRA1 is, for example, an NMOS (n-channel metal oxide semiconductor) transistor.

[0055] In the example shown in Figure 2, the first fuse element F1 and the first access transistor TRA1 are connected in series.

[0056] The second memory cell MC2 includes a second fuse element F2 and a second access transistor TRA2.

[0057] The second fuse element (second memory element) F2 is connected between the write bit line WBL and the second read bit line RBLR (second access transistor TRA2). The second fuse element F2 has a resistance value corresponding to the first or second state.

[0058] The second access transistor (second cell transistor) TRA2 is connected between the second fuse element F2 and the second lead bit line RBLR. Therefore, the second fuse element F2 is connected to the second lead bit line RBLR via the second access transistor TRA2, rather than being directly connected to the second lead bit line RBLR. This allows for more efficient read operations, as will be explained later.

[0059] Furthermore, the gate of the second access transistor TRA2 is connected to the word lines WL0, WL2, ... respectively. When the second access transistor TRA2 is turned on, the second fuse element F2 is biased by the fuse power supply voltage VDDFIL or the power supply voltage VDD. The second access transistor TRA2 is, for example, an NMOS transistor.

[0060] In the example shown in Figure 2, the second fuse element F2 and the second access transistor TRA2 are connected in series.

[0061] The semiconductor memory device of this embodiment has a plurality of word lines WL0, WL1, WL2, ... extending in the row direction. Each word line WL0, WL1, WL2, ... turns on or off the first access transistor TRA1 and the second access transistor TRA2 in each memory cell MC.

[0062] In the example shown in Figure 2, word lines WL0 and WL2 turn on or off the second access transistor TRA2 of the second memory cell MC2 on the right. Word lines WL1 and WL3 turn on or off the first access transistor TRA1 of the first memory cell MC1 on the left.

[0063] The readout circuit 7 includes a reference voltage generation unit 71, a comparison unit 72, a comparison control unit 73, and a bit line separation unit 74. The comparison unit 72 is sometimes also called a sense amplifier (SA).

[0064] The reference voltage generation unit 71 generates a reference voltage that is compared with the voltage generated when the fuse element F is biased during the read operation. The reference voltage has a voltage level between the voltage generated when the first fuse element F1 and the second fuse element F2, which have resistance values ​​corresponding to the first state, are biased based on the first and second voltages, and the voltage generated when the first fuse element F1 and the second fuse element F2, which have resistance values ​​corresponding to the second state, are biased based on the first and second voltages.

[0065] The reference voltage generation unit 71 includes a first reference voltage generation unit 711 and a second reference voltage generation unit 712.

[0066] The first reference voltage generation unit 711 is connected between the first read bit line RBLL and the write bit line WBL. The first reference voltage generation unit 711 generates a reference voltage when a read operation is performed on the second memory cell MC2. The second reference voltage generation unit 712 is connected between the write bit line WBL and the second read bit line RBLR. The second reference voltage generation unit 712 generates a reference voltage when a read operation is performed on the first memory cell MC1. In the example shown in Figure 2, the first reference voltage generation unit 711 and the second reference voltage generation unit 712 are arranged approximately symmetrically (for example, approximately left-right symmetrically) with respect to the write bit line WBL.

[0067] The first reference voltage generation unit 711 includes a first reference resistor element RF1 and a first reference transistor TRF1.

[0068] The first reference resistor RF1 is connected between the first lead bit line RBLL (first reference transistor TRF1) and the write bit line WBL.

[0069] The first reference transistor TRF1 is connected between the first reference resistor RF1 and the first lead bit line RBLL. Therefore, the first reference resistor RF1 is connected to the first lead bit line RBLL via the first reference transistor TRF1, without being directly connected to the first lead bit line RBLL.

[0070] Furthermore, the gate of the first reference transistor TRF1 is connected to the word line RWL1. When the first reference transistor TRF1 is turned on, the first reference resistor RF1 is biased by the power supply voltage VDD. The first reference transistor TRF1 is, for example, an NMOS transistor.

[0071] In the example shown in Figure 2, the first reference resistor RF1 and the first reference transistor TRF1 are connected in series.

[0072] The second reference voltage generation unit 712 includes a second reference resistor element RF2 and a second reference transistor TRF2.

[0073] The second reference resistor RF2 is connected between the write bit line WBL and the second lead bit line RBLR (second reference transistor TRF2).

[0074] The second reference transistor TRF2 is connected between the second reference resistor RF2 and the second lead bit line RBLR. Therefore, the second reference resistor RF2 is connected to the second lead bit line RBLR via the second reference transistor TRF2, without being directly connected to the second lead bit line RBLR.

[0075] Furthermore, the gate of the second reference transistor TRF2 is connected to the word line RWL0. When the second reference transistor TRF2 is turned on, the second reference resistor RF2 is biased by the power supply voltage VDD. The second reference transistor TRF2 is, for example, an NMOS transistor.

[0076] In the example shown in Figure 2, the second reference resistor RF2 and the second reference transistor TRF2 are connected in series.

[0077] The first reference resistor RF1, the second reference resistor RF2, the first reference transistor TRF1, and the second reference transistor TRF2 are arranged approximately symmetrically on either side of the write bit line WBL.

[0078] Furthermore, the first reference resistor RF1 and the second reference resistor RF2 have, for example, approximately the same resistance value.

[0079] The comparison unit 72 compares the reference voltage with the voltage generated when the first fuse element F1 or the second fuse element F2 is biased to the first and second voltages. More specifically, the comparison unit 72 compares the voltage of the first lead bit line RBLL with the voltage of the second lead bit line RBLR. That is, when the first memory cell MC1 is read, the decoder 4 selects the first memory cell MC1 and the second reference voltage generation unit 712, and the comparison unit 72 compares the voltages of the two bit lines. When the second memory cell MC2 is read, the decoder 4 selects the second memory cell MC2 and the first reference voltage generation unit 711, and the comparison unit 72 compares the voltages of the two bit lines. This reads the resistance value of the fuse element F of the memory cell MC to be read, i.e., the unwritten state ("0") or the written state ("1"). More specifically, the comparison unit 72 amplifies and compares the potential difference between the two bit lines.

[0080] The comparison control unit 73 causes the comparison unit 72 to start the comparison at a timing corresponding to the voltages of the first lead bit line RBLL and the second lead bit line RBLR.

[0081] The comparison control unit 73 includes a NAND circuit ND1 and a comparison control transistor TRC.

[0082] The two inputs of the NAND circuit ND1 are electrically connected to the first lead bit line RBLL and the second lead bit line RBLR. The output of the NAND circuit ND1 is electrically connected to the gate of the comparison control transistor TRC. The NAND circuit ND1 outputs a high signal when the voltage of at least one of the first lead bit line RBLL and the second lead bit line RBLR is lower than a first predetermined value.

[0083] The comparison control transistor TRC is connected between the comparison unit 72 and ground. The gate of the comparison control transistor TRC is connected to the output of the NAND circuit ND1, and the signal SE is input to it. When the NAND circuit ND1 outputs a high signal SE, the comparison control transistor TRC turns on. When the comparison control transistor TRC turns on, it causes the comparison unit 72 to start the comparison.

[0084] The bit line isolation unit 74 electrically isolates the bit lines. This suppresses the effect of the bit line capacitance when the comparison unit 72 amplifies the potential difference. As a result, power consumption can be reduced.

[0085] The bit line separation unit 74 includes a first separation transistor TRS1 and a second separation transistor TRS2.

[0086] The first isolation transistor TRS1 is connected between the first lead bit line RBLL and the first isolation lead bit line LBLL. The signal CS is input to the gate of the first isolation transistor TRS1. When the first isolation transistor TRS1 is turned on, it electrically connects the first lead bit line RBLL and the first isolation lead bit line LBLL, and when it is turned off, it electrically disconnects the first lead bit line RBLL and the first isolation lead bit line LBLL. The first isolation transistor TRS1 is, for example, an NMOS transistor.

[0087] Furthermore, signal CS has a signal level corresponding to the signal level of signal SE output from NAND circuit ND1, for example, via wiring not shown in the diagram.

[0088] The second isolation transistor TRS2 is connected between the second lead bit line RBLR and the second isolation lead bit line LBLR. The signal CS is input to the gate of the second isolation transistor TRS2. When the second isolation transistor TRS2 is turned on, it electrically connects the second lead bit line RBLR and the second isolation lead bit line LBLR, and when it is turned off, it electrically disconnects the second lead bit line RBLR and the second isolation lead bit line LBLR. The second isolation transistor TRS2 is, for example, an NMOS transistor.

[0089] The semiconductor memory device 1 further includes a voltage supply unit 8. Note that the voltage supply unit 8 is omitted in Figure 1. The voltage supply unit 8 is connected between the fuse power supply 6 and the memory cell array 2. The voltage supply unit 8 controls the supply of voltage via the write bit line WBL, the first read bit line RBLL, and the second read bit line RBLR. The operation of the voltage supply unit 8 is controlled, for example, by the decoder 4.

[0090] The voltage supply unit 8 includes a first blow transistor TRB1, a second blow transistor TRB2, a third blow transistor TRB3, a lead transistor TRR, a first precharge transistor TRP1, and a second precharge transistor TRP2.

[0091] The first blow transistor TRB1 is connected between node N1 and ground. Node N1 is located on the first lead bit line RBLL, between the power supply voltage node VDD (first precharge transistor TRP1) and the memory cell array 2. A BLOW signal is input to the gate of the first blow transistor TRB1. When the first blow transistor TRB1 is turned on, a write operation is performed on the first memory cell MC1. The first blow transistor TRB1 is, for example, an NMOS transistor.

[0092] The second blow transistor TRB2 is connected between node N2 and ground. Node N2 is located on the second lead bit line RBLR, between the power supply voltage node VDD (second precharge transistor TRP2) and the memory cell array 2. A BLOW signal is input to the gate of the second blow transistor TRB2. When the second blow transistor TRB2 is turned on, the writing operation of the second memory cell MC2 is performed. The second blow transistor TRB2 is, for example, an NMOS transistor.

[0093] The third blow transistor TRB3 is connected between node N3 and the fuse power supply voltage node VDDFIL. Node N3 is located on the write bit line WBL, between the fuse power supply voltage node VDDFIL and the memory cell array 2. A / BLOW signal is input to the gate of the third blow transistor TRB3. When the third blow transistor TRB3 is turned on, a write operation is performed on the first memory cell MC1 or the second memory cell MC2. The third blow transistor TRB3 is, for example, a PMOS (p-channel metal oxide semiconductor) transistor.

[0094] The lead transistor TRR is connected between node N3 and ground. Node N3 is located on the write bit line WBL, between the fuse power supply voltage node VDDFIL (third blow transistor TRB3) and the memory cell array 2. A READ signal is input to the gate of the lead transistor TRR. When the lead transistor TRR is turned on, a read operation is performed on the first memory cell MC1 or the second memory cell MC2. The lead transistor TRR is, for example, an NMOS transistor.

[0095] The first precharge transistor TRP1 is connected between the power supply voltage node VDD and the memory cell array 2 (node ​​N1). The gate of the first precharge transistor TRP1 is input with the / PRE signal. When the first precharge transistor TRP1 is turned on, the first read bit line RBLL is precharged during the read operation. Details of the precharge will be explained later, referring to Figure 4. The first precharge transistor TRP1 is, for example, a PMOS transistor.

[0096] The second precharge transistor TRP2 is connected between the power supply voltage node VDD and the memory cell array 2 (node ​​N2). The gate of the second precharge transistor TRP2 is input with the / PRE signal. When the second precharge transistor TRP2 is turned on, the second read bit line RBLR is precharged during the read operation. Details of the precharge will be explained later, referring to Figure 4. The second precharge transistor TRP2 is, for example, a PMOS transistor.

[0097] [Writing operation of semiconductor memory devices] Figure 3 is a timing chart showing an example of the write operation of a semiconductor memory device according to the first embodiment. Figure 3 shows the timing chart of the write operation of the second memory cell MC2.

[0098] In the initial state, the BLOW signal is high. Therefore, the first blow transistor TRB1 and the second blow transistor TRB2 are ON. The BLOW signal is high. Therefore, the third blow transistor TRB3 is OFF. The signals on the word lines WL0 and RWL1 are low. Therefore, the second access transistor TRA2 and the first reference transistor TRF1 are OFF.

[0099] First, at time t1, the signal on word line WL0 goes high. This turns on the second access transistor TRA2.

[0100] Next, at time t2, the / BLOW signal becomes low. This turns on the third blow transistor TRB3. As a result, the voltage of the write bit line WBL rises, and the second fuse element F2 is biased by the fuse power supply voltage VDDFIL, putting it into write mode.

[0101] Subsequently, the / BLOW signal goes high, and the signal on the word line WL0 goes low. This turns off the third blow transistor TRB3 and the second access transistor TRA2.

[0102] During the write operation, signal SE is low. Therefore, the comparison control transistor TRC is off. Signal CS is low. Therefore, the first isolation transistor TRS1 and the second isolation transistor TRS2 are off. In other words, the first lead bit line RBLL and the second lead bit line RBLR are electrically disconnected from the first isolation lead bit line LBLL and the second isolation lead bit line LBLR, respectively.

[0103] Furthermore, although the READ and / PRE signals are not shown in Figure 3, the read transistor TRR, the first precharge transistor TRP1, and the second precharge transistor TRP2 are in the off state during the write operation.

[0104] [Read operation of semiconductor memory devices] Figure 4 is a timing chart showing an example of the read operation of a semiconductor memory device according to the first embodiment. Figure 4 shows the timing chart of the read operation of the second memory cell MC2.

[0105] During the read operation, charge is drawn from the first lead bit line RBLL and the second lead bit line RBLR, which are precharged to the power supply voltage VDD, to the write bit line WBL, which is discharged to 0V. The voltage of the fuse element F and the voltage of the reference resistor element are compared when the charge is drawn. This allows the write state (0 / 1) of the memory cell MC to be read.

[0106] In the read operation of the first memory cell MC1 or the second memory cell MC2, the voltage supply unit 8 pre-supplies a first voltage to the first read bit line RBLL and the second read bit line RBLR, and pre-supplies a second voltage to the write bit line WBL. This pre-charges the memory cells. Subsequently, the voltage supply unit 8 stops supplying the first voltage to the first read bit line RBLL and the second read bit line RBLR.

[0107] The decoder (cell transistor control unit) 4 turns on the first access transistor TRA1 of the first memory cell MC1 to be read, or the second access transistor TRA2 of the second memory cell MC2 to be read, while the supply of the first voltage is stopped. In this way, charge is extracted.

[0108] In the initial state, the READ signal is high. Therefore, the lead transistor TRR is ON. As a result, the write bit line WBL is discharged to, for example, 0V. The / PRE signal is low. Therefore, the first precharge transistor TRP1 and the second precharge transistor TRP2 are ON. The signals on the word lines WL0 and RWL1 are low. Therefore, the second access transistor TRA2 and the first reference transistor TRF1 are OFF.

[0109] Furthermore, in the initial state, signal SE is low. Therefore, the comparison control transistor TRC is off. Signal CS is high. Therefore, the first isolation transistor TRS1 and the second isolation transistor TRS2 are on. That is, the first lead bit line RBLL and the second lead bit line RBLR are electrically connected to the first isolation lead bit line LBLL and the second isolation lead bit line LBLR, respectively.

[0110] In the initial state, the voltages of the first isolation lead bit line LBLL (first lead bit line RBLL) and the second isolation lead bit line LBLR (second lead bit line RBLR) are pre-charged to the power supply voltage VDD. As shown in Figure 2, all first access transistors TRA1, all second access transistors TRA2, the first reference transistor TRF1, and the second reference transistor TRF2 are in the off state. Therefore, regardless of whether the memory cell MC is in the write state ("1") or the unwrite state ("0"), charge is accumulated in the first isolation lead bit line LBLL and the second isolation lead bit line LBLR without being discharged.

[0111] First, at time t11, the / PRE signal goes high. This turns off the first precharge transistor TRP1 and the second precharge transistor TRP2. The signals for word lines WL0 and RWL1 go high almost simultaneously. This turns on the second access transistor TRA2 and the first reference transistor TRF1 almost simultaneously. As a result, after time t11, the voltages of the first isolated lead bit line LBLL and the second isolated lead bit line LBLR decrease. This is because the charge accumulated in the first isolated lead bit line LBLL and the second isolated lead bit line LBLR flows through the write bit line WBL. The current flowing through the write bit line WBL flows to ground connected to the source of the lead transistor TRR.

[0112] Here, the voltage decay rate differs between the first isolation lead bit line LBLL and the second isolation lead bit line LBLR. The voltage decay rate of the first isolation lead bit line LBLL is determined by the resistance value of the first reference resistor element RF1. Therefore, the voltage decay rate of the first isolation lead bit line LBLL does not change depending on the state (0 / 1) of the second fuse element F2 in the second memory cell MC2. On the other hand, the voltage decay rate of the second isolation lead bit line LBLR changes depending on the state (0 / 1) of the second fuse element F2 in the second memory cell MC2.

[0113] First, we will explain the read operation when the second memory cell MC2 is in the write state (1-read).

[0114] Since the resistance of the second fuse element F2 of the second memory cell MC2 is higher than the resistance of the first reference resistor element RF1, the rate of voltage decrease of the second isolation lead bit line LBLR is slower than the rate of voltage decrease of the first isolation lead bit line LBLL.

[0115] At time t15, the voltage of the first isolation lead bit line LBLL becomes lower than the logic threshold (first predetermined value) of the NAND circuit ND1. As a result, at time t16, the NAND circuit ND1 inputs the signal SE, which changes from low to high, to the gate of the comparison control transistor TRC. Also, as the signal SE becomes high, at time t17, the signal CS becomes low. As a result, the first isolation transistor TRS1 and the second isolation transistor TRS2 are turned off. Consequently, the first lead bit line RBLL and the second lead bit line RBLR are electrically disconnected from the first isolation lead bit line LBLL and the second isolation lead bit line LBLR, respectively.

[0116] At time t16, the comparison control transistor TRC is turned on, and the comparison unit 72 performs a voltage comparison. That is, the comparison control unit 73 causes the comparison unit 72 to start the comparison when the voltage of at least one of the first lead bit line RBLL and the second lead bit line RBLR falls below a first predetermined value. After time t16, the comparison unit 72 amplifies and compares the potential difference between the first isolated lead bit line LBLL and the second isolated lead bit line LBLR.

[0117] Subsequently, the / PRE signal goes low, and the signals on word lines WL0 and RWL1 also go low. This turns on the first precharge transistor TRP1 and the second precharge transistor TRP2, and turns off the second access transistor TRA2 and the first reference transistor TRF1.

[0118] Next, we will describe the read operation when the second memory cell MC2 is in an unwritten state (0-read).

[0119] Since the resistance of the second fuse element F2 of the second memory cell MC2 is lower than the resistance of the first reference resistor RF1, the voltage drop rate of the second isolation lead bit line LBLR is faster than the voltage drop rate of the first isolation lead bit line LBLL.

[0120] At time t12, the voltage of the second isolation lead bit line LBLR becomes lower than the logic threshold (first predetermined value) of the NAND circuit ND1. As a result, at time t13, the NAND circuit ND1 inputs the signal SE, which changes from low to high, to the gate of the comparison control transistor TRC. Also, as the signal SE becomes high, at time t14, the signal CS becomes low. As a result, the first isolation transistor TRS1 and the second isolation transistor TRS2 are turned off. Consequently, the first lead bit line RBLL and the second lead bit line RBLR are electrically disconnected from the first isolation lead bit line LBLL and the second isolation lead bit line LBLR, respectively.

[0121] At time t13, the comparison control transistor TRC is turned on, and the comparison unit 72 performs a voltage comparison. That is, the comparison control unit 73 causes the comparison unit 72 to start the comparison when the voltage of at least one of the first lead bit line RBLL and the second lead bit line RBLR falls below a first predetermined value. After time t13, the comparison unit 72 amplifies and compares the potential difference between the first isolated lead bit line LBLL and the second isolated lead bit line LBLR.

[0122] Subsequently, the / PRE signal goes low, and the signals on word lines WL0 and RWL1 also go low. This turns on the first precharge transistor TRP1 and the second precharge transistor TRP2, and turns off the second access transistor TRA2 and the first reference transistor TRF1.

[0123] As shown in Figure 4, the timing at which the comparison unit 72 starts comparing differs depending on the state (0 / 1) of the second memory cell MC2. That is, the timing from the rise of the word line voltage to the activation of the sense amplifier is determined self-aligned by the speed at whichever of the first isolated lead bit line LBLL and the second isolated lead bit line LBLR falls below the logic threshold (first predetermined value) of the NAND circuit ND1 first.

[0124] Although the BLOW and / BLOW signals are not shown in Figure 4, the first blow transistor TRB1, the second blow transistor TRB2, and the third blow transistor TRB3 are in the OFF state.

[0125] As described above, according to the first embodiment, the first memory cell MC1 is connected between the first read bit line RBLL and the write bit line WBL. The first access transistor TRA1 is connected between the first fuse element F1 and the first read bit line RBLL. The second memory cell MC2 is connected between the write bit line WBL and the second read bit line RBLR. The second access transistor TRA2 is connected between the second fuse element F2 and the second read bit line RBLR. As a result, as will be explained later with reference to Figures 5 and 6, the capacitances of the first read bit line RBLL and the second read bit line RBLR can be kept approximately constant regardless of the state of the first fuse element F1 and the second fuse element F2. As a result, the read operation of the first memory cell MC1 or the second memory cell MC2 can be performed more appropriately.

[0126] Furthermore, the connection relationship (arrangement) of the first reference transistor TRF1 and the second reference transistor TRF2 corresponds to the connection relationship of the first access transistor TRA1 and the second access transistor TRA2. This allows for a more appropriate comparison of characteristics such as the potential difference between the memory cell MC and the reference voltage generation unit 71. However, this is not limited to this configuration, and the first reference transistor may be connected between the first reference resistor RF1 and the write bit line WBL. The second reference resistor RF2 may be connected between the second reference resistor RF2 and the write bit line WBL.

[0127] [Comparative Example] Figure 5 is a circuit diagram illustrating the bit line capacitance in a semiconductor memory device 1a according to a comparative example. Figure 6 is a circuit diagram illustrating the bit line capacitance in a semiconductor memory device 1 according to the first embodiment.

[0128] The comparative example differs from the first embodiment in the arrangement of the fuse element and access transistor within the memory cell MC. In Figure 5, the first lead bit line RBLL and the second lead bit line RBLR are replaced by the first bit line BLL and the second bit line BLR. Similarly, the write bit line WBL is replaced by the ground line GND.

[0129] The first access transistor TRA1 of the first memory cell MC1 is connected between the first fuse element F1 and the ground line GND. Therefore, the first fuse element F1 is directly connected to the first bit line BLL.

[0130] The second access transistor TRA2 of the second memory cell MC2 is connected between the second fuse element F2 and the ground line GND. Therefore, the second fuse element F2 is directly connected to the second bit line BLR.

[0131] [Comparison of bit line capacities] In Figures 5 and 6, the first fuse element F1 (filament) of the first memory cell MC1 located on the left side is blown. That is, all first memory cells MC1 are in a written state. On the other hand, the second fuse element F2 of the second memory cell MC2 located on the right side is not blown. That is, all second memory cells MC2 are in an unwritten state.

[0132] The total capacitance of the first bit line BLL shown in Figure 5 is expressed by Equation 1, using the bit line wiring capacitance of the first bit line BLL. Total capacity = bit line wiring capacity (Equation 1)

[0133] The total capacitance of the second bit line BLR shown in Figure 5 is expressed by Equation 2, using the bit line wiring capacitance of the second bit line BLR, the fuse element capacitance of the second fuse element F2, and the transistor diffusion capacitance of the second access transistor TRA2. Total capacity = Bit line wiring capacity + (Fuse element capacity + Transistor diffusion capacity) × Number of bits (Equation 2)

[0134] As shown in Equations 1 and 2, the total capacitance of the second bit line BLR is greater than the total capacitance of the first bit line BLL. Furthermore, because the total capacitance of the bit lines can vary significantly depending on the pattern of the data to be written, the time it takes to extract the precharged charge from the bit lines (the rate at which the bit line voltage drops) can also vary significantly depending on the pattern of the data to be written. In this case, it may become difficult to stably perform the read operation using precharge shown in Figure 4 in the comparative example.

[0135] In contrast, the total capacitances of the first lead bit line RBLL and the second lead bit line RBLR, as shown in Figure 6, are expressed by Equation 3. Total capacitance = bit line wiring capacitance + transistor diffusion capacitance × number of bits (Equation 3)

[0136] In other words, the total capacitance of the first lead bit line RBLL and the second lead bit line RBLR is approximately constant regardless of the pattern of the data to be written. Therefore, the time it takes to extract the precharged charge from the bit lines (the rate at which the voltage of the bit lines drops) is also approximately constant regardless of the pattern of the data to be written. This allows for more stable read operations using precharge.

[0137] [Comparison of operations] In the circuit configuration shown in the comparative example, a potential difference is typically generated between the voltage of the first bit line BLL and the voltage of the second bit line BLR by applying a DC current. This potential difference is amplified and read out by the comparison unit 72.

[0138] Figure 7 shows the time variation of the bit line voltage. The upper part of Figure 7 is a graph showing the time variation of the word line voltage. The middle part of Figure 7 is a graph showing the time variation of the bit line voltage in a comparative example. The lower part of Figure 7 is a graph showing the time variation of the bit line voltage in the first embodiment. The vertical axis of the graphs in Figure 7 represents voltage. The horizontal axis of the graphs in Figure 7 represents time. Note that the time shown on the horizontal axis is common to all graphs.

[0139] The word line voltages include, for example, word lines RWL0, RWL1, WL0, and WL1. The bit line voltages Vb0 and Vb1 of the bit lines electrically connected to the memory cell MC are shown by solid lines. Bit line voltage Vb0 indicates the voltage when the memory cell MC is in an unwritten state. Bit line voltage Vb1 indicates the voltage when the memory cell MC is in a written state. The reference voltage Vref of the reference bit line electrically connected to the reference voltage generation unit 71 is shown by a dashed line.

[0140] In the comparative example, the bit line and reference bit line correspond to the second bit line BLR and the first bit line BLL shown in Figure 5, respectively. In the first embodiment, the bit line and reference bit line correspond to the second lead bit line RBLR and the first lead bit line RBLL shown in Figure 6, respectively.

[0141] The voltage on the word line is low in the initial state. The voltage on the word line becomes high at time ta. This activates the word line. The second fuse element F2 is biased by the power supply voltage VDD, and a DC current continues to flow through the second fuse element F2.

[0142] In the initial state of the comparative example, the bit line voltages Vb0, Vb1, and reference voltage Vref are, for example, zero.

[0143] In the comparative example, at time tb after time ta, the bit line voltages Vb0, Vb1, and reference voltage Vref rise. The bit line voltage Vb1 is higher than the bit line voltage Vb0 because the fuse element has melted, and it takes time for the voltage to stabilize.

[0144] In the comparative example, at time tc, for example, the bit line voltage Vb1 exceeds the reference voltage Vref. That is, after time tc, the reference voltage Vref becomes a voltage level between the bit line voltage Vb0 and the bit line voltage Vb1. Therefore, in the comparative example, the comparison unit 72 needs to wait at least until time tc has elapsed before performing the comparison.

[0145] Thus, in the comparative example, it is necessary to continuously supply DC current from word line activation to sense amplifier activation. Also, it takes a relatively long time for the potential difference between the bit line voltages Vb0 and Vb1 and the reference voltage Vref to open sufficiently.

[0146] Note that the time variations of the bit line voltages Vb0, Vb1, and reference voltage Vref in the comparative example are just one example.

[0147] In the initial state of the first embodiment, the bit line voltages Vb0, Vb1 and the reference voltage Vref are pre-charged to the power supply voltage VDD.

[0148] At time ta in the first embodiment, the word line voltage becomes high. Also at time ta, the bit line voltages Vb0, Vb1 and the reference voltage Vref decrease. This is because the first access transistor TRA1 and the second access transistor TRA2 turn on, and charge is drawn from the first lead bit line RBLL and the second lead bit line RBLR. The rate at which the reference voltage Vref decreases after time ta is between the rate at which the bit line voltage Vb0 decreases and the rate at which the bit line voltage Vb1 decreases.

[0149] In the first embodiment, compared to the comparative example, it is not necessary to continuously supply DC current. This is because the pre-charged charge is extracted. This enables lower power consumption. Furthermore, a large potential difference can be easily obtained between the bit line voltages Vb0 and Vb1 and the reference voltage Vref, ensuring a read margin. In addition, the access transistor is placed between the fuse element and the lead bit line. This suppresses variations in the rate of change (decrease rate) of the bit line voltage when charge is extracted, depending on the pattern of the written data. As a result, the read operation can be performed stably. Also, as shown in Figure 7, in the first embodiment, compared to the comparative example, the potential difference between the bit line voltages Vb0 and Vb1 and the reference voltage Vref widens more quickly. This shortens the time from word line activation to sense amplifier activation. As a result, high-speed read operation becomes possible.

[0150] Furthermore, as shown in the lower part of Figure 7, in the first embodiment, a potential difference is generated between the bit line voltages Vb0 and Vb1 and the reference voltage Vref relatively quickly after word line activation due to the difference in the rate at which charge is extracted. Since the rate at which charge is extracted is caused by the difference in resistance, a sufficient potential difference can be obtained regardless of the magnitude of the precharge voltage at the start of reading. For example, the power supply voltage VDD can be lowered within a range in which the comparison unit 72 can perform a proper comparison. This allows for lower voltage operation. In other words, the potential difference between the first voltage and the second voltage is a potential difference corresponding to the difference in the rate of voltage change between the first lead bit line RBLL and the second lead bit line RBLR after the decoder 4 turns on the first access transistor TRA1 or the second access transistor TRA2.

[0151] <Second Embodiment> Figure 8 is a circuit diagram showing a detailed configuration example of the semiconductor memory device 1 according to the second embodiment. The second embodiment differs from the first embodiment in that the write bit line WBL is connected to ground. In the second embodiment, the write bit line WBL corresponds to the ground line GND in the comparative example.

[0152] In the example shown in Figure 8, the first voltage during the write operation is, for example, the fuse power supply voltage VDDFIL. The second voltage during the write operation is, for example, the ground voltage (0V). Therefore, during the write operation, the first voltage is higher than the second voltage. During the read operation, the first voltage is, for example, the power supply voltage VDD. The second voltage during the read operation is, for example, the ground voltage. Therefore, during the read operation, the first voltage is higher than the second voltage. Note that the first voltage during the write operation (fuse power supply voltage VDDFIL) is higher than the first voltage during the read operation (power supply voltage VDD).

[0153] In the second embodiment, the voltage supply unit 8 is not provided with the third blow transistor TRB3 and the lead transistor TRR, compared to the first embodiment.

[0154] The first blow transistor TRB1 is connected between node N4 on the first lead bit line RBLL and the fuse power supply voltage node VDDFIL. The gate of the first blow transistor TRB1 is input to the / BLOWL signal. The first blow transistor TRB1 is, for example, a PMOS transistor.

[0155] The second blow transistor TRB2 is connected between node N5 on the second lead bit line RBLR and the fuse power supply voltage node VDDFIL. The gate of the second blow transistor TRB2 is input to the / BLOWR signal. The second blow transistor TRB2 is, for example, a PMOS transistor.

[0156] The first precharge transistor TRP1 is connected between node N4 on the first lead bit line RBLL and the power supply voltage node VDD.

[0157] The second precharge transistor TRP2 is connected between node N5 on the second lead bit line RBLR and the power supply voltage node VDD.

[0158] The write bit line WBL is connected to ground and fixed to the ground voltage. In other words, the voltage supply unit 8 fixes the write bit line WBL to the second voltage (ground voltage).

[0159] [Writing operation of semiconductor memory devices] Figure 9 is a timing chart showing an example of the writing operation of the semiconductor memory device 1 according to the second embodiment.

[0160] In the initial state, the / BLOWL and / BLOWR signals are high. Therefore, the first blow transistor TRB1 and the second blow transistor TRB2 are off. The signals on the word lines WL0 and RWL1 are low. Therefore, the second access transistor TRA2 and the first reference transistor TRF1 are off.

[0161] First, at time t21, the signal on word line WL0 goes high. This turns on the second access transistor TRA2.

[0162] Next, at time t22, the / BLOWR signal goes low. This turns on the second blow transistor TRB2. As a result, the voltage of the second lead bit line RBLR rises, and the second fuse element F2 is biased by the fuse power supply voltage VDDFIL, entering the write state.

[0163] Subsequently, the / BLOWR signal goes high, and the signal on the word line WL0 goes low. This turns off the second blow transistor TRB2 and the second access transistor TRA2.

[0164] [Read operation of semiconductor memory devices] Figure 10 is a timing chart showing an example of the read operation of the semiconductor memory device 1 according to the second embodiment.

[0165] In Figure 10, no READ signal is input. Other read operations of the semiconductor memory device 1 according to the second embodiment are the same as those described in Figure 4 of the first embodiment.

[0166] As in the second embodiment, the write bit line WBL may be connected to ground. In this case as well, the same effects as in the first embodiment can be obtained.

[0167] <Third Embodiment> Figure 11 is a circuit diagram showing a detailed configuration example of the semiconductor memory device 1 according to the third embodiment. The third embodiment differs from the first embodiment in that the precharge levels of the first lead bit line RBLL and the second lead bit line RBLR are 0V.

[0168] In the example shown in Figure 11, the first voltage during the write operation is, for example, the ground voltage (0V). The second voltage during the write operation is, for example, the fuse power supply voltage VDDFIL. Therefore, during the write operation, the first voltage is lower than the second voltage. During the read operation, the first voltage is, for example, the ground voltage. The second voltage during the read operation is, for example, the power supply voltage VDD. Therefore, during the read operation, the first voltage is lower than the second voltage. Note that the second voltage during the write operation (fuse power supply voltage VDDFIL) is higher than the second voltage during the read operation (power supply voltage VDD).

[0169] In the third embodiment, the voltage supply unit 8 is not provided with the first blow transistor TRB1 and the second blow transistor TRB2, compared to the first embodiment.

[0170] The third blow transistor TRB3 is connected between node N6 on the write bit line WBL and the fuse power supply voltage node VDDFIL.

[0171] The lead transistor TRR is connected between node N6 on the write bit line WBL and the power supply voltage node VDD. The gate of the lead transistor TRR is input to the / READ signal. The lead transistor TRR is, for example, a PMOS transistor.

[0172] The first precharge transistor TRP1 is connected between one end of the first lead bit line RBLL and ground. The gate of the first precharge transistor TRP1 is input to the PRE signal. The first precharge transistor TRP1 is, for example, an NMOS transistor.

[0173] The second precharge transistor TRP2 is connected between one end of the second lead bit line RBLR and ground. The gate of the second precharge transistor TRP2 is input to the PRE signal. The second precharge transistor TRP2 is, for example, an NMOS transistor.

[0174] The comparison control unit 73 has an OR circuit OR1 instead of the NAND circuit ND1 in the first embodiment.

[0175] The two inputs of OR circuit OR1 are electrically connected to the first lead bit line RBLL and the second lead bit line RBLR. The output of OR circuit OR1 is electrically connected to the gate of the comparison control transistor TRC. OR circuit OR1 outputs a high signal if the voltage of at least one of the first lead bit line RBLL and the second lead bit line RBLR is higher than a second predetermined value.

[0176] [Writing operation of semiconductor memory devices] Figure 12 is a timing chart showing an example of the writing operation of the semiconductor memory device 1 according to the third embodiment.

[0177] In the initial state, the PRE signal is high. Therefore, the first precharge transistor TRP1 and the second precharge transistor TRP2 are in the ON state.

[0178] During the write operation, the first precharge transistor TRP1 and the second precharge transistor TRP2 operate substantially the same as the first blow transistor TRB1 and the second blow transistor TRB2 in the first embodiment. Other operations of the semiconductor memory device 1 according to the third embodiment are the same as those shown in Figure 3 of the first embodiment.

[0179] During the write operation, the / READ signal (not shown in the diagram) is in the high state. Therefore, the lead transistor TRR is in the off state.

[0180] [Read operation of semiconductor memory devices] Figure 13 is a timing chart showing an example of the read operation of the semiconductor memory device 1 according to the third embodiment.

[0181] In the initial state, the / READ signal is low. Therefore, the read transistor TRR is ON. As a result, the write bit line WBL is precharged to the power supply voltage VDD. As shown in Figure 11, all first access transistors TRA1, all second access transistors TRA2, first reference transistor TRF1, and second reference transistor TRF2 are OFF. Therefore, regardless of whether the memory cell MC is in the write state ("1") or the unwritten state ("0"), charge is accumulated on the write bit line WBL without being lost.

[0182] In the initial state, the PRE signal is high. Therefore, the first precharge transistor TRP1 and the second precharge transistor TRP2 are ON. As a result, the voltages of the first lead bit line RBLL (first isolated lead bit line LBLL) and the second lead bit line RBLR (second isolated lead bit line LBLR) are discharged to, for example, 0V.

[0183] First, at time t51, the PRE signal goes low. This turns off the first precharge transistor TRP1 and the second precharge transistor TRP2. The signals on the word lines WL0 and RWL1 go high almost simultaneously. This turns on the second access transistor TRA2 and the first reference transistor TRF1 almost simultaneously. As a result, after time t51, the voltages of the first isolated lead bit line LBLL and the second isolated lead bit line LBLR rise. This is because the first isolated lead bit line LBLL and the second isolated lead bit line LBLR, which were discharged to 0V, are charged to the level of the power supply voltage VDD via the lead transistor TRR and the write bit line WBL.

[0184] Here, the voltage rise rate differs between the first isolation lead bit line LBLL and the second isolation lead bit line LBLR. The voltage rise rate of the first isolation lead bit line LBLL is determined by the resistance value of the first reference resistor element RF1. Therefore, the voltage rise rate of the first isolation lead bit line LBLL does not change depending on the state (0 / 1) of the second fuse element F2 in the second memory cell MC2. On the other hand, the voltage rise rate of the second isolation lead bit line LBLR changes depending on the state (0 / 1) of the second fuse element F2 in the second memory cell MC2.

[0185] First, we will explain the read operation when the second memory cell MC2 is in the write state (1-read).

[0186] Since the resistance of the second fuse element F2 of the second memory cell MC2 is higher than the resistance of the first reference resistor RF1, the rate at which the voltage rises across the second isolation lead bit line LBLR is slower than the rate at which the voltage rises across the first isolation lead bit line LBLL.

[0187] At time t52, the voltage of the first isolation lead bit line LBLL becomes higher than the logic threshold (second predetermined value) of the OR circuit OR1. As a result, at time t53, the OR circuit OR1 inputs the signal SE, which changes from low to high, to the gate of the comparison control transistor TRC. Also, as the signal SE becomes high, at time t54, the signal CS becomes low. As a result, the first isolation transistor TRS1 and the second isolation transistor TRS2 are turned off. Consequently, the first lead bit line RBLL and the second lead bit line RBLR are electrically disconnected from the first isolation lead bit line LBLL and the second isolation lead bit line LBLR, respectively.

[0188] At time t53, the comparison control transistor TRC is turned on, and the comparison unit 72 performs a voltage comparison. That is, the comparison control unit 73 causes the comparison unit 72 to start the comparison when the voltage of at least one of the first lead bit line RBLL and the second lead bit line RBLR becomes higher than a second predetermined value. After time t53, the comparison unit 72 amplifies and compares the potential difference between the first isolated lead bit line LBLL and the second isolated lead bit line LBLR.

[0189] Subsequently, the PRE signal goes high, and the signals on word lines WL0 and RWL1 go low. This turns on the first precharge transistor TRP1 and the second precharge transistor TRP2, and turns off the second access transistor TRA2 and the first reference transistor TRF1.

[0190] Next, we will describe the read operation when the second memory cell MC2 is in an unwritten state (0-read).

[0191] Since the resistance of the second fuse element F2 of the second memory cell MC2 is lower than the resistance of the first reference resistor RF1, the rate of voltage rise of the second isolation lead bit line LBLR is faster than the rate of voltage rise of the first isolation lead bit line LBLL.

[0192] At time t55, the voltage of the second isolation lead bit line LBLR becomes higher than the logic threshold (second predetermined value) of the OR circuit OR1. As a result, at time t55, the OR circuit OR1 inputs the signal SE, which changes from low to high, to the gate of the comparison control transistor TRC. Also, as the signal SE becomes high, the signal CS becomes low at time t57. As a result, the first isolation transistor TRS1 and the second isolation transistor TRS2 are turned off. Consequently, the first lead bit line RBLL and the second lead bit line RBLR are electrically disconnected from the first isolation lead bit line LBLL and the second isolation lead bit line LBLR, respectively.

[0193] At time t56, the comparison control transistor TRC is turned on, and the comparison unit 72 performs a voltage comparison. That is, the comparison control unit 73 causes the comparison unit 72 to start the comparison when the voltage of at least one of the first lead bit line RBLL and the second lead bit line RBLR becomes higher than a second predetermined value. After time t56, the comparison unit 72 amplifies and compares the potential difference between the first isolated lead bit line LBLL and the second isolated lead bit line LBLR.

[0194] Subsequently, the PRE signal goes high, and the signals on word lines WL0 and RWL1 go low. This turns on the first precharge transistor TRP1 and the second precharge transistor TRP2, and turns off the second access transistor TRA2 and the first reference transistor TRF1.

[0195] As shown in Figure 13, the timing at which the comparison unit 72 starts comparing differs depending on the state (0 / 1) of the second memory cell MC2. That is, the timing from the rise of the word line voltage to the activation of the sense amplifier is determined self-aligned by the speed at whichever of the first isolated lead bit line LBLL and the second isolated lead bit line LBLR exceeds the logic threshold (second predetermined value) of the OR circuit OR1 first.

[0196] As in the third embodiment, the precharge levels of the first lead bit line RBLL and the second lead bit line RBLR may be 0V. In this case as well, the same effects as in the first embodiment can be obtained.

[0197] <Fourth Embodiment> Figure 14 is a circuit diagram showing a detailed configuration example of the semiconductor memory device 1 according to the fourth embodiment. The fourth embodiment differs from the second embodiment in that the transistors included in the memory cell MC and the reference voltage generation unit 71 are PMOS transistors.

[0198] The first access transistor TRA1, the second access transistor TRA2, the first reference transistor TRF1, and the second reference transistor TRF2 are, for example, PMOS transistors.

[0199] [Writing operation of semiconductor memory devices] Figure 15 is a timing chart showing an example of the writing operation of the semiconductor memory device 1 according to the second embodiment.

[0200] In the fourth embodiment, the relationship between the high and low signals of the word lines WL0 and RWL1 is reversed compared to the second embodiment. Other writing operations of the semiconductor memory device 1 according to the fourth embodiment are the same as those described in Figure 9 of the second embodiment.

[0201] [Read operation of semiconductor memory devices] Figure 16 is a timing chart showing an example of the read operation of the semiconductor memory device 1 according to the fourth embodiment.

[0202] In the fourth embodiment, the relationship between the high and low signals of the word lines WL0 and RWL1 is reversed compared to the second embodiment. Other read operations of the semiconductor memory device 1 according to the fourth embodiment are the same as those described in Figure 10 of the second embodiment.

[0203] As in the fourth embodiment, the transistors included in the memory cell MC and the reference voltage generation unit 71 may be PMOS transistors. In this case as well, the same effects as in the second embodiment can be obtained. In addition, in the first or third embodiment, the transistors included in the memory cell MC and the reference voltage generation unit 71 may also be PMOS transistors.

[0204] Furthermore, this technology can take the following configuration. (1) One or more first memory cells connected in parallel between a first voltage supply line that supplies a first voltage and a second voltage supply line that supplies a second voltage different from the first voltage, One or more second memory cells connected in parallel between the second voltage supply line and the third voltage supply line that supplies the first voltage, Equipped with, Each of the previous 1 memory cells is, A first memory element having a resistance value corresponding to the first or second state, A first cell transistor connected between the first memory element and the first voltage supply line, Each of the second memory cells is A second memory element having a resistance value corresponding to the first or second state, A semiconductor memory device having a second cell transistor connected between the second memory element and the third voltage supply line. (2) The semiconductor memory device according to (1), wherein the number of first memory cells and the number of second memory cells are the same. (3) The semiconductor memory device according to (1) or (2), wherein the first memory cell and the second memory cell are arranged substantially symmetrically across the second voltage supply line. (4) A voltage supply unit that, in a read operation of the first memory cell or the second memory cell, supplies a first voltage to the first voltage supply line and the third voltage supply line, supplies a second voltage to the second voltage supply line, and stops supplying the first voltage, A cell transistor control unit that turns on the first cell transistor of the first memory cell to be read, or the second cell transistor of the second memory cell to be read, while the supply of the first voltage is stopped, A semiconductor memory device according to any one of (1) to (3), further comprising the above. (5) The semiconductor memory device according to (4), wherein the potential difference between the first voltage and the second voltage is a potential difference corresponding to the difference in the rate of voltage change between the first voltage supply line and the third voltage supply line after the cell transistor control unit turns on the first cell transistor or the second cell transistor. (6) The semiconductor memory device according to (4) or (5), wherein the second voltage supply line is fixed to the second voltage. (7) A reference voltage generation unit generates a reference voltage having a voltage level between a voltage generated by biasing the first memory element and the second memory element, each having a resistance value corresponding to a first state, based on the first voltage and the second voltage, and a voltage generated by biasing the first memory element and the second memory element, each having a resistance value corresponding to a second state, based on the first voltage and the second voltage. A comparison unit that compares the reference voltage with a voltage generated when the first memory element or the second memory element is biased based on the first voltage and the second voltage, A semiconductor memory device according to any one of (1) to (6), further comprising the above. (8) The aforementioned reference voltage generation unit is A first reference voltage generation unit is connected between the first voltage supply line and the second voltage supply line and generates the reference voltage when the second memory cell is read out, A second reference voltage generation unit is connected between the second voltage supply line and the third voltage supply line and generates the reference voltage when the first memory cell is read out, A semiconductor memory device according to (7), having the following characteristics. (9) The semiconductor memory device according to (8), wherein the first reference voltage generation unit and the second reference voltage generation unit are arranged substantially symmetrically across the second voltage supply line. (10) The first reference voltage generation unit is, First reference resistor element, A first reference transistor connected between the first reference resistor element and the first voltage supply line, It has, The second reference voltage generation unit is, The second reference resistor element, A second reference transistor connected between the second reference resistor element and the third voltage supply line, A semiconductor memory device according to (8) or (9), having the following: (11) The comparison unit compares the voltage of the first voltage supply line with the voltage of the third voltage supply line, thereby comparing the reference voltage with the voltage generated when the first memory element or the second memory element is biased based on the first voltage and the second voltage. The semiconductor memory device according to any one of (7) to (10), further comprising a comparison control unit that causes the comparison unit to start a comparison at a timing corresponding to the voltages of the first voltage supply line and the third voltage supply line. (12) The comparison control unit, If the first voltage is higher than the second voltage, the comparison unit is instructed to start the comparison when the voltage of at least one of the first voltage supply line and the third voltage supply line falls below a first predetermined value. The semiconductor memory device according to (11), wherein, when the first voltage is lower than the second voltage, the comparison unit is instructed to start the comparison when the voltage of at least one of the first voltage supply line and the third voltage supply line becomes higher than a second predetermined value. (13) In a read operation, the first voltage is higher than the second voltage, according to any one of (1) to (12) of the semiconductor memory device. (14) In the writing operation, the first voltage is lower than the second voltage. The semiconductor memory device according to (13), wherein the second voltage during the write operation is higher than the first voltage during the read operation. (15) In the writing operation, the first voltage is higher than the second voltage. The semiconductor memory device according to (13), wherein the first voltage during a write operation is higher than the first voltage during a read operation. (16) In a read operation, the first voltage is lower than the second voltage, according to any one of (1) to (12) of the semiconductor memory device. (17) In the writing operation, the first voltage is lower than the second voltage. The semiconductor memory device according to (16), wherein the second voltage during the write operation is higher than the second voltage during the read operation.

[0205] The aspects of this disclosure are not limited to the individual embodiments described above, but include various modifications that a person skilled in the art could conceive, and the effects of this disclosure are not limited to those described above. In other words, various additions, modifications, and partial deletions are possible, as long as they do not depart from the conceptual idea and spirit of this disclosure derived from the claims and their equivalents. [Explanation of Symbols]

[0206] 1 Semiconductor memory device, 2 Memory cell array, 4 Decoder, 7 Read circuit, 71 Reference voltage generation unit, 711 First reference voltage generation unit, 712 Second reference voltage generation unit, 72 Comparison unit, 73 Comparison control unit, 8 Voltage supply unit, F Fuse element, F1 First fuse element, F2 Second fuse element, MC Memory cell, MC1 First memory cell, MC2 Second memory cell, TRA1 First access transistor, TRA2 Second access transistor, RBLL First lead bit line, RBLR Second lead bit line, LBLL First isolated lead bit line, LBLR Second isolated lead bit line, WBL Write bit line, RF1 First reference resistor element, RF2 Second reference resistor element, TRF1 First reference transistor, TRF2 Second reference transistor, VDD Power supply voltage, VDDFIL Fuse power supply voltage

Claims

1. One or more first memory cells connected in parallel between a first voltage supply line that supplies a first voltage and a second voltage supply line that supplies a second voltage different from the first voltage, One or more second memory cells connected in parallel between the second voltage supply line and the third voltage supply line that supplies the first voltage, Equipped with, Each of the first memory cells is A first memory element having a resistance value corresponding to the first or second state, A first cell transistor connected between the first memory element and the first voltage supply line, It has, Each of the second memory cells is A second memory element having a resistance value corresponding to the first or second state, A second cell transistor connected between the second memory element and the third voltage supply line, It has, The number of the first memory cells and the number of the second memory cells are the same. The first memory cell and the second memory cell are arranged substantially symmetrically across the second voltage supply line. A reference voltage generation unit generates a reference voltage having a voltage level between a voltage generated by biasing the first memory element and the second memory element, each having a resistance value corresponding to a first state, based on the first voltage and the second voltage, and a voltage generated by biasing the first memory element and the second memory element, each having a resistance value corresponding to a second state, based on the first voltage and the second voltage. A comparison unit that compares the reference voltage with a voltage generated when the first memory element or the second memory element is biased based on the first voltage and the second voltage, Furthermore, The aforementioned reference voltage generation unit is A first reference voltage generation unit is connected between the first voltage supply line and the second voltage supply line and generates the reference voltage when the second memory cell is read out, A second reference voltage generation unit is connected between the second voltage supply line and the third voltage supply line and generates the reference voltage when the first memory cell is read out, It has, The first reference voltage generation unit and the second reference voltage generation unit are arranged substantially symmetrically with respect to the second voltage supply line. The comparison unit compares the voltage of the first voltage supply line with the voltage of the third voltage supply line, thereby comparing the reference voltage with the voltage generated when the first memory element or the second memory element is biased based on the first voltage and the second voltage. The comparison control unit further comprises a timing corresponding to the voltages of the first voltage supply line and the third voltage supply line, which causes the comparison unit to start the comparison. The comparison control unit, If the first voltage is higher than the second voltage, the comparison unit is instructed to start the comparison when the voltage of at least one of the first voltage supply line and the third voltage supply line falls below a first predetermined value. A semiconductor memory device that, when the first voltage is lower than the second voltage, causes the comparison unit to start a comparison when the voltage of at least one of the first voltage supply line and the third voltage supply line becomes higher than a second predetermined value.

2. A voltage supply unit that, in a read operation of the first memory cell or the second memory cell, supplies a first voltage to the first voltage supply line and the third voltage supply line, supplies a second voltage to the second voltage supply line, and stops supplying the first voltage, A cell transistor control unit that turns on the first cell transistor of the first memory cell to be read, or the second cell transistor of the second memory cell to be read, while the supply of the first voltage is stopped, The semiconductor memory device according to claim 1, further comprising:

3. The semiconductor memory device according to claim 2, wherein the potential difference between the first voltage and the second voltage is a potential difference corresponding to the difference in the rate of voltage change between the first voltage supply line and the third voltage supply line after the cell transistor control unit turns on the first cell transistor or the second cell transistor.

4. The semiconductor memory device according to claim 2, wherein the second voltage supply line is fixed to the second voltage.

5. The first reference voltage generation unit is, First reference resistor element, A first reference transistor connected between the first reference resistor element and the first voltage supply line, It has, The second reference voltage generation unit is, The second reference resistor element, A second reference transistor connected between the second reference resistor element and the third voltage supply line, A semiconductor memory device according to claim 1, having the following features.

6. The semiconductor memory device according to claim 1, wherein in a read operation, the first voltage is higher than the second voltage.

7. In the writing operation, the first voltage is lower than the second voltage. The semiconductor memory device according to claim 6, wherein the second voltage during the write operation is higher than the first voltage during the read operation.

8. In the writing operation, the first voltage is higher than the second voltage. The semiconductor memory device according to claim 6, wherein the first voltage during a write operation is higher than the first voltage during a read operation.

9. The semiconductor memory device according to claim 1, wherein in a read operation, the first voltage is lower than the second voltage.

10. In the writing operation, the first voltage is lower than the second voltage. The semiconductor memory device according to claim 9, wherein the second voltage during the write operation is higher than the second voltage during the read operation.

11. The semiconductor memory device according to claim 1, wherein the first memory element and the second memory element are electric fuse elements.

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