Optical path tracing in optical circuit design

Abstract

A photonic integrated circuit (PIC) design includes various paths. During the design process, characteristics of the paths of the PIC design are determined and used to analyze the PIC design. Determining the characteristics of the paths includes receiving a PIC design including a plurality of devices. Further, a first path between a first pin of a first device of the plurality of devices and a second pin of a second device of the plurality of devices is determined. One or more characteristics of the first path are determined based on a wavelength of the optical signal, a characteristic of the first device, and a characteristic of the second device. The first path and the one or more characteristics are output.

Description

[Technical Field]

[0001] The present disclosure relates to an optical device design system, and more specifically, to systems and methods for determining optical paths and characteristics of optical paths in optical device design. [Background Art]

[0002] In a photonic integrated circuit (PIC), optical signals are used to communicate information. PICs are used in optical communication systems for demultiplexing communication signals, processing light detection and ranging (LiDAR) optical signals, or processing microwave signals. PICs are designed to reduce optical loss (i.e., signal loss) during signal processing and improve the communication of information between devices. For example, a PIC may limit timing differences between signals on different channels (waveguides), or may be designed to delay a signal by a predetermined amount such that errors in received or transmitted signals are mitigated. Furthermore, PICs are designed to control the phase of optical signals during communication. [Summary of the Invention]

[0003] In one example, the method includes receiving a photonic integrated circuit (PIC) design that includes a plurality of devices. The method further includes determining a first path between a first pin of a first one of the plurality of devices and a second pin of a second one of the plurality of devices. The method further includes determining one or more characteristics of the first path based on the wavelength of the optical signal, the characteristics of the first device, and the characteristics of the second device, and outputting, by a processor, the first path and the one or more characteristics.

[0004] In one example, the system includes a memory for storing instructions and a processor. The processor is coupled to the memory and executes instructions that cause the processor to receive an optical integrated circuit (PIC) design including multiple devices. The processor further determines a first path between a first pin of a first device of the multiple devices and a second pin of a second device of the multiple devices. The processor further determines one or more characteristics of the first path based on the wavelength of the optical signal, the characteristics of the first device, and the characteristics of the second device, and outputs the first path and one or more paths.

[0005] In one example, a computer implementation for displaying characteristics of an optical integrated circuit (PIC) design within a user interface includes receiving a PIC design that includes multiple devices. The multiple devices include a first device, a second device, and a third device. The third device is a hierarchical device that includes two or more hierarchical levels. The method further includes determining a first path between a first pin of the first device and a second pin of the second device. The first path traverses two or more hierarchical levels of the third device. Furthermore, the method includes determining one or more characteristics of the first path based on the wavelength of an optical signal, the first device, and the second device, and displaying one or more characteristics within a user interface on a display device.

[0006] This disclosure will be better understood from the detailed description given below and the accompanying drawings of embodiments of this disclosure. These drawings are used to provide knowledge and understanding of embodiments of this disclosure and do not limit the scope of this disclosure to these specific embodiments. Furthermore, the drawings are not necessarily drawn to a certain scale. [Brief explanation of the drawing]

[0007] [Figure 1] This is a block diagram of an optical integrated circuit (PIC) design system, with one or more examples. [Figure 2]This is a schematic block diagram of a PIC design, using one or more examples. [Figure 3] This is a schematic block diagram of a PIC design, using one or more examples. [Figure 4] This is a schematic block diagram illustrating the hierarchy levels of a PIC design device, with one or more examples. [Figure 5] This is a flowchart for determining the design path of a PIC using one or more examples. [Figure 6A] This is another flowchart of a method for determining the path of PIC design, using one or more examples. [Figure 6B] This is another flowchart of a method for determining the path of PIC design, using one or more examples. [Figure 6C] This is another flowchart of a method for determining the path of PIC design, using one or more examples. [Figure 7A] This is exemplary pseudocode for determining the path of PIC design, using one or more examples. [Figure 7B] This is exemplary pseudocode for determining the path of PIC design, using one or more examples. [Figure 7C] This is exemplary pseudocode for determining the path of PIC design, using one or more examples. [Figure 8] This is an exemplary user interface, consisting of one or more examples. [Figure 9] This is a flowchart of various processes used during the design and manufacture of an integrated circuit, according to some embodiments of the present disclosure. [Figure 10] This is a diagram of an exemplary computer system in which embodiments of the present disclosure may operate. [Modes for carrying out the invention]

[0008] Aspects of this disclosure relate to optical path tracing in optical circuit design. Optical integrated circuits (PICs) are used in devices that transmit information via optical signals (e.g., optical signals). When designing a PIC, a large amount of information can be lost due to improper timing between signals (e.g., different arrival times of signals and / or improper signal delays), which can lead to errors in the transmitted and / or received optical signals. Furthermore, any error in the phase of an optical signal can lead to errors in the transmitted and / or received optical signals.

[0009] A PIC design includes optical devices interconnected via optical paths. The input-to-output path of a PIC design passes through one or more devices and one or more paths connecting these devices. One or more devices in a PIC design may include one or more hierarchical levels, or hierarchical devices. In a PIC design that includes hierarchical devices, one or more paths in the PIC design may pass through many hierarchical levels.

[0010] During the PIC design process, the path of light through the PIC design and the devices along that path are used to determine the functionality of the PIC design. In PIC designs that include hierarchical devices, each level of the hierarchy in each hierarchical device is investigated to determine the path through the PIC design and each device along that path. However, due to the large number of hierarchy levels in different devices, it becomes difficult for designers to manually identify the path within the PIC device and all the devices along that path, increasing the likelihood of design errors during the design process. Furthermore, optical properties (e.g., optical length, delay, and loss) depend on the device parameters of the PIC design and the wavelength of the optical signal. Therefore, since it is extremely difficult to identify all devices in the PIC through which the optical signal passes, the process of acquiring optical properties is cumbersome and prone to errors. This disclosure describes a design system and design method for identifying paths, corresponding devices, optical signals passing through a PIC design, and the optical properties of the paths. As will be described in more detail below, a PIC design system uses a PIC design to obtain paths between two optical networks, highlight the paths, identify corresponding devices, and determine one or more properties of the paths (e.g., geometric or optical path length, optical delay, or optical loss). In one or more examples, performing such a process includes determining whether the identified paths are correctly unique. Furthermore, the properties of the identified paths may be analyzed to determine whether the identified properties are within the parameters of the corresponding design. In addition, path tracing may be combined with the determination of the optical properties of multiple paths. The technical benefits of this disclosure include, but are not limited to, reducing the speed at which paths can be adjusted to satisfy the parameters of the corresponding design and freeing up computer resources used for the design of other devices and / or other processes.

[0011] Figure 1 is a block diagram of a PIC design system 100 in one or more examples. The PIC design system 100 receives a PIC design (e.g., a PIC design file), determines the path that light takes through the devices in the PIC design, and outputs that path, as will be described in more detail below. The PIC design system 100 includes one or more processors (e.g., processing device 1002 in Figure 10) that execute instructions (e.g., instruction 1026 in Figure 10) stored in memory (e.g., memory 120, main memory 1004 in Figure 10, and / or machine-readable medium 1024 in Figure 10) to receive a PIC design, determine the path that light takes within the PIC design, and output that path. In one example, the PIC design is received from memory (e.g., memory 120) or another system. Furthermore, the PIC design system 100 stores the determined path in memory (e.g., memory 120) and / or outputs the determined path to another system. The PIC design system 100 further identifies one or more characteristics of the PIC design based on the determined path, the devices determined to be along the path, and the wavelength of light.

[0012] The PIC design system 100 includes a path tracing engine 110, memory 120, and a user interface 130. The path tracing engine 110 includes one or more processors (e.g., processing device 1002 in Figure 10) that receive a PIC design diagram, execute instructions (e.g., instruction 1026 in Figure 10) stored in memory (e.g., memory 120, main memory 1004 in Figure 10, and / or machine-readable medium 1024 in Figure 10), and analyze the PIC design diagram to identify paths in the PIC design diagram through which light travels. Furthermore, the path tracing engine 110 determines and outputs a list of devices and corresponding input / output pins for unique paths between nets in the PIC design diagram. In one or more examples, as will be described in more detail below, each path is queried to determine the geometric length, optical length, optical delay, and / or optical loss. Paths may be stored in memory (e.g., memory 120). In one or more examples, the paths are highlighted in the schematic editor of the user interface 130 or identified by some other means and displayed on a display device (e.g., the video display unit 1010 in Figure 10). In one example, the user can select source and destination nets in the user interface 130 via an input device (e.g., the alphanumeric input device 1012 and / or the cursor control device 1014 in Figure 10). Based on the selection of source and destination nets, the details of the optical path and the corresponding optical characteristics are output via the user interface 130 to the display device (e.g., the video display unit 1010 in Figure 10).

[0013] Memory 120 is configured similarly to the main memory 1004 and / or the machine-readable medium 1024 in Figure 10. Memory 120 includes a process design kit (PDK) 122 and a design database 124 stored therein. The PDK 122 and the design database 124 are accessible by the path tracing engine 110. In one or more examples, a PIC design 126 is stored in memory 120.

[0014] PDK122 stores the device characteristics of each device that may be used within a PIC or other electronic device. In one example, a device may include an optical device. For example, an optical device may include, among other things, a waveguide, a filter, a splitter, and a mixer. The device characteristics in PDK122 define the input pins and output pins of the device, which are the pins that are interconnected within the device, and among other things, the path length between the pins of the device. In one or more examples, PDK122 is a file that contains information corresponding to which particular pin of a device (e.g., a component) in the PIC design diagram transmits the optical signal when the optical signal is received by a particular pin of the device. In one example, a device may include multiple input pins and multiple output pins.

[0015] The PDK122 can be used to determine which output pin outputs an optical signal when an optical signal is received by a specific pin among several input pins. In various examples, information on which output pin outputs an optical signal when a specific input pin receives an optical signal can be used by the path tracing engine 110 to determine the path the optical signal takes through the corresponding PIC design.

[0016] Furthermore, in one or more examples, PDK122 includes models that describe the geometric length and / or optical length or each device in the PIC design diagram (e.g., PIC design 126). As described in more detail below, the path tracing engine 110 uses PDK122 to determine the characteristics of the optical path in the PIC design diagram (e.g., PIC design 126). The characteristics may be a function of the wavelength of the optical signal. In one or more examples, the models in PDK122 describe the time delay and power loss of the optical signal as the optical signal moves from one pin of the device to another pin of the device. Geometric length relates to the physical length along the path. Optical length is the effective refractive index integrated along the path. Furthermore, optical length describes the phase of the optical signal based on the formula "phase = 2 * π / wavelength * optical length".

[0017] As will be described in more detail below, the path tracing engine 110 uses the PDK 122 to identify the path within the PIC design along which an optical signal travels and the characteristics of that path.

[0018] The design database 124 provides functional information for each device within the PIC device. For example, in the case of a PIC design, the design database 124 includes device functions for optical devices such as waveguides, filters, splitters, and mixers, among others. In other examples, the design database 124 includes functional information associated with devices of other types of IC circuit designs. For example, the design database 124 may include functional information associated with multipliers, adders, buffers, inverters, multiplexers, latches, flip-flops, and gate logic, among others.

[0019] The user interface 130 displays one or more characteristics of the PIC design determined by the path tracing engine 110. In one or more examples, the user interface 130 is configured similarly to the graphics processing unit 1022 in FIG. 10. For example, the user interface 130 illustrates the number of identified paths and corresponding characteristics of the PIC design, such as geometric length, optical length, and / or delay, among others. In one example, the user interface 130 allows a user to identify a start device and a destination device in the PIC design. The user interface 130 is displayed on a display device (e.g., the video display unit 1010 in FIG. 10) and receives input from one or more input devices (e.g., the alphanumeric input device 1012 in FIG. 10 and / or the cursor control device 1014 in FIG. 10). In one or more examples, the PIC design includes a bus (e.g., a bus net or a net bundle). In such examples, the bus includes a plurality of signal paths. A user may select bits or signals to be analyzed by the path tracing engine 110 via the user interface 130.

[0020] Figure 2 illustrates schematic diagrams of PIC design 200 in one or more examples. PIC design 200 includes an optical device. In one example, PIC design 200 may also include one or more electronic elements (e.g., devices or components). Furthermore, Figure 2 is a schematic diagram of PIC design 200; in other examples, the schematic diagrams may be for other types of electronic ICs. PIC design 200 includes devices interconnected via paths. For example, PIC design 200 includes an optical device, or devices 210-220, and paths 230-236 forming a net. The net is represented by wires connecting two or more of devices 210-220 and connecting the optical device. Each of devices 210-220 may be referred to as an instance. A PIC device may include multiple instances of the same device type. Each device (e.g., an instance) includes one or more input pins (e.g., input terminals) and one or more output pins (e.g., output terminals). The number of input pins in devices 210–220 may be greater than, less than, or equal to the number of output pins. The input and output pins of PIC design 200 are optical pins. In one or more examples, one or more input and output pins are electrical pins. Each of devices 210–220 may be referred to as a subcell of PIC design 200.

[0021] PIC design 200 includes nets 230-236. Nets 230-236 are the interconnections between devices 210-220. In PIC design 200, devices 210-218 have input and output pins connected by nets 230-236. Nets 230-236 identify which pins of the devices are physically connected to each other.

[0022] In PIC design 200, devices 210 and 212 are connected via net 230, devices 212 and 214 are connected via net 231, devices 214 and 218 are connected via net 233, devices 212 and 218 are connected via net 232, devices 218 and 216 are connected via net 234, devices 216 and 212 are connected via net 235, and devices 218 and 220 are connected via net 236.

[0023] In one or more examples, one or more of devices 210-220 are a single non-hierarchical cell (e.g., a leaf cell) in the design database 124. In addition, or instead, one or more of devices 210-218 are hierarchical devices. Hierarchical devices contain one or more levels of hierarchy. Each level of hierarchy contains corresponding devices and paths.

[0024] In one or more examples, depending on the function of devices 210-220, an optical signal received by one pin of a device may pass through one or more other pins and be output by the device, or it may be completely absorbed within the device. In one example, the function of devices 210-220 is defined by the design database 124.

[0025] In one example, within each device 210-220, the physical implementation of the paths between the input and output (receive and transmit) pins of devices 210-220 is associated with the geometric and optical properties of devices 210-220. In one or more examples, the geometric and optical properties are unique to each device.

[0026] In one example, an optical signal can exit a device (e.g., devices 210-220) by passing through multiple output pins of that device. Therefore, the path an optical signal takes from one device to another does not necessarily have to be unique. A unique path is one in which at least one of the following is different from other paths: input pins, output pins, different devices, or a different order of devices. For example, the first and second paths between a first device and a second device may be determined to be unique if the first and second paths involve different input pins of the devices, different output pins of the devices, different intermediate devices, and / or a different order of devices between the first and second devices. As illustrated in Figure 2, each path through the net and devices (210, 230, 212, 231, 214, 233, 218, 236, 220) and (210, 230, 212, 235, 216, 234, 218, 236, 220) is a unique path from left to right. If a path is identical to another path, it is determined to be a non-unique path. In one or more examples, identical paths between a first device and a second device have the same input and output pins and include intermediate devices in the same order. In one example, a path may branch (e.g., split into multiple paths) and recombine by passing through the input pins of a single device. Such paths may be determined to be unique if each path includes different devices, input pins, and / or output pins. Furthermore, a path may include a feedback loop, in which an optical signal may periodically move within the loop. In the following, only the first loop is counted as a unique path.

[0027] In one or more examples, the schematic diagram of the PIC design includes one or more hierarchical components. In such examples, one or more components in the schematic diagram (e.g., one or more symbols) include the hierarchical design. Thus, each level of the hierarchy is traced to determine the path from the first device to the second device, and all possible paths are discovered.

[0028] Figure 3 illustrates a schematic diagram of PIC design 300 having a hierarchical design. PIC design 300 includes devices 310, 312, 314, 318, 320, 322, and 324. One or more of devices 310, 312, 314, 316, 318, 320, 322, and 324 are hierarchical devices. A hierarchical device includes one or more levels of hierarchy. In one example, device 314 is a hierarchical device having a design as illustrated by PIC design 200 in Figure 2. Therefore, each level of the hierarchy of device 314 is extended and analyzed to determine each device in the path between device 310 and device 320, and the corresponding connected pins. The path is determined for each level of hierarchy. In one example, each level of hierarchy is extended, and the path passing through the lowest level of the hierarchy is determined first before the path for the next level of the hierarchy is determined. A list of device paths and devices at each level of the hierarchy is output (for example, stored in memory 120 or displayed within the user interface 130).

[0029] As illustrated in Figure 3, the first path between device 310 and device 324 includes device 310 connected to device 312 via net 330, device 312 connected to device 314 via net 332, device 314 connected to device 316 via net 334, and device 316 connected to device 324 via net 336. As illustrated in Figure 3, the second path between device 310 and device 324 includes device 310 connected to device 318 via net 340, device 318 connected to device 320 via net 342, device 320 connected to device 322 via net 344, and device 322 connected to device 324 via net 346.

[0030] The first and second paths between device 310 and device 324 differ in at least one of the following: the number of devices between device 310 and device 324, the set of devices between device 310 and device 324, and / or the order of devices between device 310 and device 320. For example, the first path between device 310 and the second device 324 includes device 312, and the second path between device 310 and the second device 324 includes device 318, which is different from device 312. However, due to the hierarchy present in devices 314 and 320, there are even more unique paths between device 310 and device 324.

[0031] Figure 4 illustrates schematic diagram 400 of the extended hierarchy of devices 314 and 320. In schematic diagram 400, the extended hierarchy of devices 314 and 320 includes devices 410, 412, 414, 416, 418, and 420. The path from input 402 to output 404 is determined by the path tracing engine 110 in Figure 1 based on the device characteristics in the PDK 122 in Figure 1. In the example in Figure 4, it is determined that there are two paths from input 402 to output 404. One path includes net 430 connecting device 410 to device 412, net 432 connecting device 412 to device 416, net 434 connecting device 416 to device 418, and net 436 connecting devices 418 and 420. The other path includes net 430 connecting device 410 to device 412, net 438 connecting device 412 to device 414, net 440 connecting device 414 to device 418, and net 436 connecting devices 418 and 420. The path through the hierarchy of device 400 is determined based on PDK122.

[0032] In one or more examples, there are two paths passing through each of device 314 and device 320, so the total number of unique paths from device 310 to device 324 is four.

[0033] In one example, the path between device 410 and device 420 may include devices and networks other than those described above. For example, the path between device 410 and device 420 may include devices 412, 416, 418, 414, and 418, and networks 430, 432, 434, 436, 438, 440, and 442. In such an example, the path travels along networks 430, 432, 434, and 442 and their corresponding devices before traveling along networks 438, 440, and 436 and their corresponding devices.

[0034] Figure 5 illustrates flowcharts for determining the paths of a PIC design, the devices along the paths, and the characteristics of the paths, using one or more examples. Method 500 can be performed by the PIC design system 100. For example, one or more processors of the PIC design system 100 perform Method 500 by executing instructions stored in memory. In one example, Method 500 is performed as part of the layout or physical implementation 924 in Figure 9.

[0035] In method 500, 510, a PIC design is received. In one example, the PIC design 126 in Figure 1 is received by the path tracing engine 110 in Figure 1. The PIC design 126 may be configured similarly to the PIC design 200 in Figure 2, or the PIC design 300 in Figure 3. In other examples, the path tracing engine 110 receives the PIC design from a system outside the PIC design system 100, or from another engine within the PIC design system 100.

[0036] In step 520, the path between the pins of the first device and the pins of the second device is determined. In one example, as shown with reference to Figures 1 and 3, the path tracing engine 110 determines the path between the pins of device 310 and the pins of device 312. Determining the path between the pins of device 310 and device 312 is part of the process of determining the path from device 310 to device 324 (for example, path 330). Device 310 may be referred to as the source device, and device 324 may be referred to as the destination device. In one example, devices 310 and 324 are shown as the source device and destination device via the user interface 130. The path tracing engine 110 retrieves devices 310 and 324 as the source device and destination device from memory 120.

[0037] The path tracing engine 110 determines, based on the characteristics in the PDK 122 in Figure 1, that net 330 connects the output pins of device 310 to the input pins of device 312, and the connections between the respective input and output pins of device 310 and device 312. In one example, the path tracing engine 110 obtains details about the optical paths within each of device 310 and device 312 to determine the input and output pins associated with net 330. The characteristics of each device in the PDK 122 are used by the path tracing engine 110 to determine the connected input and output pins of each of device 310 and device 312. The characteristics of the PDK 122 identify the connections between the input and output pins within each of device 310 and device 312. The characteristics in the PDK 122 are used by the path tracing engine 110 to determine which input pins of a device are connected to which output pins of a device. In one example, the output pins of device 310 are connected to the input pins of device 312 via net 330. In such an example, the path tracing engine 110 determines, based on the characteristics in the PDK 122, which input pins of device 310 are connected to the output pins of device 310. Furthermore, the path tracing engine 110 determines, based on the characteristics in the PDK 122, which output pins of device 312 are connected to the inputs of the path tracing engine 110. Similarly, for each of devices 312, 314, 316, and 324, the path tracing engine 110 determines, based on the characteristics in the PDK 122, the input and output pins of the devices associated with nets 332, 334, and 336. Nets 330, 332, 334, and 336 form a first path from device 310 to device 324. The first path further includes paths within the hierarchy levels of devices 310, 312, 314, 316, and 324. For example, the path between device 310 and device 324 includes the path connecting device 410 to device 420 in Figure 4.

[0038] In one or more examples, the route tracking engine 110 determines that device 310 is connected to device 318 via net 340, device 318 is connected to device 320 via net 342, device 320 is connected to device 322 via net 344, and device 322 is connected to device 324 via net 346. Nets 340, 342, 344, and 346 form a second route between device 310 and device 324. Although device 310 is illustrated in Figure 3 as being connected to device 324 via two routes, in other examples, device 310 is connected to device 324 via three or more routes. In one or more examples, multiple routes exist between any two adjacent devices, forming multiple devices between a source device and a destination device.

[0039] In one example, the device characteristics of PDK122 indicate that the input pins of device 310 are connected to one or more output pins of device 310. Based on the device characteristics of device 310 in PDK122, the path tracing engine 110 determines that the input pins of device 310 are connected to the first output pin of device 310. Therefore, the optical signal received at the input pins of device 310 is output from the output pins of device 310 along the net 330. In one example, based on the device characteristics stored in PDK122, the path tracing engine 110 determines which pins of each device are output pins reachable from any input pin, and determines possible paths between devices in the corresponding PIC design. The path tracing engine 110 accesses PDK122 and the design database 124 to analyze each device and determine paths within and between devices.

[0040] In one or more examples, the path tracing engine 110 performs a recursive procedure to determine the paths between devices in the PIC design (e.g., the PIC design 300 in Figure 3). For example, when determining the path from device 310, the path tracing engine 110 performs the task of determining each candidate pin of each device (e.g., 310-324) that can be connected to a pin of device 310 (e.g., the first pin) (521). In one example, for the first pin of device 310 in Figure 3, the path tracing engine 110 queries the PDK 122 to determine which pins can be reached from that pin. For example, the path tracing engine 110 determines which pins of devices 310-324 can be connected to the first pin.

[0041] In step 522, the path tracking engine 110 analyzes each pin that can be connected to a pin on device 310 (e.g., the first pin) to determine whether each pin is connected to a pin on device 310 and indicates each analyzed pin as visited (e.g., marked). The pin analysis includes determining whether the net connects the pin to a pin on device 310. A visited pin is a pin identified by the path tracking engine 110. Furthermore, if a visited pin is identified a second time, the path tracking engine 110 stops tracking that particular path. Therefore, loops or parts of a path may not be reported multiple times.

[0042] The path tracking engine 110 marks each analyzed pin of each device connected to device 310 as "visited," one by one, and identifies the pins of the next device (for example, device 312 in Figure 3) that are connected to the pins of device 310. Device 310 may be referred to as the device under inspection. In the case where device 310 is under inspection, if it is determined that a path exists to connect the pins of the device, the pins of device 312 are identified as connected to the pins of device 310. The path tracking engine 110 analyzes the pins of device 310 and the pins of device 312 to determine whether these pins are connected. The pins of device 310 and device 312 are determined to be connected if it is determined that device 310 and device 210 are on the same net based on the design database 124.

[0043] In one example, determining the path between a pin of a first device and a pin of a second device involves determining, in 523, that the device is a hierarchical device. In one or more examples, the path-tracing engine 110 performs path-tracing using a depth-first search format with the design database 124 of Figure 1. The design database 124 of Figure 1 describes the hierarchical characteristics of each device in a PIC design (e.g., PIC design 300). The path-tracing engine 110 uses the hierarchical characteristics of the design database 124 to determine, based on the design database 124, which of the devices 310-324 are hierarchical devices and the paths that pass through those devices at each level of the hierarchy. In one example, for each device determined to be a hierarchical device, each level of the hierarchy within the device is extended to determine the corresponding path and the devices along the path.

[0044] In step 524, the path through each level of the hierarchy of each hierarchical device is determined. For example, based on the determination that a device (e.g., device 314) is connected to a pin under analysis that has a hierarchy, the hierarchy is opened, each level of the hierarchy and the corresponding device are analyzed, and the path through each level of the hierarchy of the hierarchical device is determined. The path tracing procedure then continues from the output of that device. In one example, the path tracing engine 110 analyzes each device having a PIC design that includes hierarchy information to determine which devices include additional layers (e.g., levels) of hierarchy. In one example, if the path tracing engine 110 determines that the current pin is connected to an external pin of a hierarchy level, the path tracing process either terminates (if this pin is at the base level of the design's hierarchy) or continues on the corresponding net at the next (e.g., higher) hierarchy level.

[0045] In one example, when analyzing the next output pins of a device within a device hierarchy level, the set of visited pins is reset to its state when entering a hierarchical device or another layer of hierarchy within a hierarchical device. Furthermore, each pin reachable to a destination net returns a set of all possible paths. All paths from all output pins are collected and returned in the set.

[0046] In step 525, devices along the path are identified and added to a list (results list). The results list is stored in memory, for example, memory 120 in Figure 1. Devices include devices along the path at each level of the hierarchy within each hierarchical device. In one example, the output pins of the current device being examined (e.g., device 310) are analyzed to determine if they are connected to the input pins of other devices. This process is completed when it reaches the connection between the output pins of the first device (e.g., device 310) and the input pins of the second device (e.g., device 324). The process terminates when the destination device or destination net is reached. Each device determined to be connected along the path from the first device to the second device is added to the list or results list. As shown with reference to Figure 3, devices 312, 314, and 316 are determined to be along the path from device 310 to device 324. Furthermore, devices 410, 412, 416, 418, and 420 of hierarchical device 314 are determined to be along the path and are added to the results list.

[0047] In step 530, one or more characteristics of the path are determined. For example, the path tracking engine 110 determines the geometric length and / or optical length based on the model in PDK 122 and / or the device features in the design database 124. In one example, the path tracking engine 110 further determines the optical length based on the wavelength of the optical signal. The wavelength is obtained from memory 120. In one example, the wavelength is provided via the user interface 130. Furthermore, the path tracking engine 110 determines the characteristics of the path based on the characteristics of the devices in the path. For example, a model in PDK 122 associated with the devices in the path is selected. As described above, the model in PDK 122 describes the characteristics of each device (e.g., geometric length and / or optical length). The path delay, geometric length, and / or optical length are determined based on the PDK 122 and the wavelength model.

[0048] In method 500, step 540, the route and corresponding characteristics are output. For example, the route and corresponding characteristics are output via the user interface 130 and displayed on the display. In another example, the route and corresponding characteristics are stored in memory 120.

[0049] Figures 6A, 6B, and 6C illustrate another flowchart for determining the paths between devices in a schematic diagram of a PIC design. Method 600 is performed by the PIC design system 100 in Figure 1, or by another design system configured to design a PIC device. For example, one or more processors in the PIC design system 100 execute Method 600 by executing instructions stored in memory. In one example, Method 600 is performed as part of the layout or physical implementation 924 in Figure 9.

[0050] Furthermore, as shown with reference to Figure 6A, in 610 a recursive procedure is defined that returns all paths from a first pin or terminal of a first device (e.g., term1) to a second pin or terminal of a second device (e.g., term2). The recursive procedure in 610 of method 600 includes 611. In 611, the first terminal and the second terminal (e.g., term1, term2) are defined for path tracing to be performed by the path tracing engine 110. Furthermore, the recursive procedure in 610 includes in 612 setting the results list (e.g., results) to an empty list (e.g., results are reset to a known quantity). The results list corresponds to the results of paths discovered during the path tracing process. In 613 a determination is made as to whether the first terminal (term1) is equal to the second terminal (term2). In one example, the path tracing engine 110 makes a determination as to whether the first terminal is equal to the second terminal. In step 614, based on the determination that the first terminal is not equal to the second terminal, the path tracing engine 110 identifies the net under analysis as a net connected to the first terminal. A net corresponds to a wire (e.g., a connection) between terminals of two devices in a PIC design. Furthermore, in step 615, the pins within the net are selected by the path tracing engine 110. The pins are the hierarchy boundaries between the first and second devices. If, in step 613, the first terminal is determined to be equal to the second terminal, then in step 680, an empty list is returned.

[0051] In step 620, a determination is made (for example, in step 622) as to whether each pin in the current net has been visited. If all pins in the current net have not been visited, the next pin in the current net (for example, an unanalyzed pin) is selected (for example, in step 624) and visited in step 630. Based on the determination in step 620 that all pins in the current net have been analyzed, method 600 proceeds to step 640 of method 600.

[0052] In step 630, it is determined whether the current level of the hierarchy is at the base level. If it is determined that the current level is at the base level of the device hierarchy, it is determined that the analysis of the currently selected pin is complete, and method 600 returns to 620. If it is determined that the current level of the hierarchy is not at the base level of the device hierarchy being analyzed, then each higher level of the hierarchy is analyzed, and paths through each level of the hierarchy are determined until the top level of the hierarchy is reached, or until one or more paths to a second terminal (or destination term) are found.

[0053] In one example, 630 includes a determination in 631 as to whether the selected pin is at the base level of the hierarchy of the selected device. If it is determined in 631 that the selected pin is at the base level of the hierarchy of the selected device, method 600 returns to 620. If it is determined in 631 that the pin is not at the base level of the device hierarchy, then in 632, a pin (e.g., a terminal) at a lower level of the hierarchy (e.g., a layer) is selected. In one or more examples, pins at subsequent lower levels of the hierarchy are selected until it is determined that the current level is the base level. In 633 of method 600, a determination is made as to whether the selected pin at a lower level of the hierarchy is visited. If it is determined in 633 that the selected pin is visited, then in 634, the selected pin is added to the list of visited pins (e.g., terminals). Adding the selected pin to the list of visited pins may include indicating the selected pin as a visited pin. In step 635, a path is determined between the selected pin (lower term) and the second pin (term2). In step 636 of method 600, a determination is made as to whether a path has been found between the selected pin (lower term) and the second pin (term2). If a path has been found between the selected pin (lower term) and the second pin (term2) in step 636 (for example, the path is not equal to -1, or it is not associated with another indication that a path has been found between the selected pin and the second pin), the path is added to the result list in step 637 and stored in memory 120. Method 600 returns to step 620 after step 636. If a path has not been found between the selected pin (lower term) and the second pin (term2) in step 636 (for example, the path is equal to -1), method 600 returns to step 620.

[0054] If, in 620, it is determined that each of the pins of the currently selected net has been analyzed, method 600 proceeds to 640. In block 640, it is determined whether the current net is connected to one or more pins (or instance terminals) of an instance of a device (e.g., instTerm) in the PIC design. In one example, these terminals are logical connection points of the block representing the instance of the device. The pins associated with the terminals represent physical connection points. In one example, the net associated with a terminal is logically exported through the terminal to the next higher level in the design hierarchy. In an example where multiple physical connections can correspond to one logical connection, a terminal can have multiple pins. An instance terminal represents the connection between a net and a terminal in the design of the instance. For each instance terminal determined to be unvisited, method 600 performs the process in 650. In one example, 640 of method 600 includes, in 641, detecting the instance terminals of the instance of a device in the PIC design connected to the current net. Step 641 is performed based on the determination in step 622 as to whether all pins have been visited. Step 642 determines whether all instance terminals of the device instance in the PIC design have been visited. If step 642 determines that all instance terminals have been visited, step 600 proceeds to step 670. If step 642 determines that all instance terminals have not been analyzed, step 643 selects an instance terminal to be analyzed. Step 644 determines whether the selected instance terminal has been visited. If step 644 determines that the selected instance terminal has been visited, step 600 returns to step 642. If step 644 determines that the selected instance terminal has not been visited, step 600 proceeds to step 650.

[0055] In 650, the instance of the PIC design device to which the selected instance pin is connected (e.g., a second instance) is determined. Furthermore, in 650, it is determined whether the second instance is a leaf cell. A leaf cell is an instance without an internal hierarchy. If the second instance is not a leaf cell, the instance hierarchy is opened (e.g., expanded), and a recursive call to 610 continues the path-tracing process at each level of the hierarchy, resulting in a list of paths containing instances that are added to the result list and stored in memory 120. In one example, 650 of method 600 includes selecting a second instance connected to the current instance in 651. In 652, it is determined whether the instance is a leaf cell. If in 652 the instance is determined to be a leaf cell, the method proceeds to 660. If in 652 the instance is determined not to be a leaf cell, in 653 a pin at a higher level of hierarchy of the selected instance is selected. In step 654, the third terminal (term) is set to a terminal connected to a pin at a higher hierarchy level of the instance. In step 655, a determination is made as to whether a path exists between the third terminal (e.g., term) and the second terminal (e.g., term2). If no path is found in step 655, the method returns to step 640. If a path is found in step 655, the found path is added to the result list and stored in memory 120.

[0056] If the current instance is determined to be a leaf cell in 652, 660 is executed to determine the permitted connections from the selected instance terminal (instTerm) to other instance terminals (instTerm) of the selected instance. For each unvisited instance terminal, the path leading the unvisited instance terminal to the destination terminal is determined (calculated by a recursive call to 610). Before each call to 610, the current set of visited terminals is stored in memory 120. In one example, the set of visited terminals is stored in a stack in memory 120. The stack consists of contiguous blocks in memory 120. In other examples, other memory configurations may be used to store the set of visited terminals. Once a path is determined, it is added to the result list, and the set of visited terminals is restored from the stack. Once all instance terminals (instTerm) of this instance have been analyzed, the system returns to 640 of method 600.

[0057] In one example, at 661, the instance terminals of the second instance of the PIC design are obtained. At 662, a determination is made as to whether each of the second instance terms has been analyzed. If at 662 it is determined that each of the second instance terminals has been analyzed, method 600 returns to 642. If at 662 it is determined that each of the second instance terminals has not been analyzed, method 600 proceeds to 663, where the second instance terminals are set to the third terminal (for example, term). At 664, it is determined as to whether the third terminal has been visited. If at 664 it is determined that the third terminal has been visited, method returns to 662. If at 664 it is determined that the terminal has not been visited, method proceeds to 665 of method 600. At 665 the terminal is added to the list of visited terminals, and at 666 the list of visited terminals is backed up. Backing up the list (set) of visited terminals includes creating a copy of the list of visited terminals and saving that list to memory 120. In 667, a determination is made as to whether a path is determined between a third terminal (for example, between the first terminal and the second terminal). In 667, if a path is not determined, method 600 returns to 662. In 667, if a path is determined, in 668, a determination is made as to whether each of the paths has been analyzed. In 668, if it is determined that all paths have been analyzed, method 600 proceeds to 669, the list of visited terminals is updated, and method 600 returns to 662. In 668, if it is determined that all paths have not been analyzed, in 670, the next path (for example, an unanalyzed path) is selected, and in 671 of method 600, the path is set to include the selected instance and path. The path is added to the results list in 672, and method 600 returns to 668.

[0058] In 680, the result (e.g., identified route) is output. If no route is found, -1 (or another value or indication representing no route) is output. In one example, the result may be output to memory (e.g., memory 120 in Figure 1). In addition to, or instead of, the result may be displayed by a display device (e.g., video display unit 1010 in Figure 10) and / or provided to another computer system via a network device (e.g., network interface device 1008 in Figure 10) over a network (e.g., network 1020 in Figure 10).

[0059] In one example, in method 600, 680, outputting a result includes returning a result (681). Returning a result includes outputting a result, as described above. In one example, in 682, based on the determination that the result is not empty, in 681 the result is returned. If in 682 the result is determined to be empty, in 683 -1 is returned. In other examples, in method 600, 683 a value other than -1 may be used to indicate that the result is empty.

[0060] Figures 7A, 7B, and 7C illustrate exemplary pseudocode 700 for determining paths between devices in a schematic diagram of a PIC design. The pseudocode 700 is executed by one or more processors of the path tracing engine 110 in Figure 1 to determine paths traversing the schematic diagram of a PIC design (e.g., PIC design 126). In one or more examples, the pseudocode 700 corresponds to 610, 620, 630, 640, 650, 660, and 680 in Figures 6A, 6B, and 6C.

[0061] Figure 8 illustrates a user interface 800 illustrating the paths identified by method 500 in Figure 5 and / or method 600 in Figures 6A, 6B, and 6C (e.g., paths 430, 432, 434, and 436). The user interface 800 is displayed on a display device (e.g., video display unit 1010 in Figure 10). As illustrated by the user interface 800, paths 0, 1, 2, 3 and their corresponding characteristics are output for the associated wavelengths. In the example in Figure 8, characteristics including the geometric length, optical length, delay, and loss for each path are output (e.g., displayed).

[0062] Figure 9 illustrates an exemplary set of processes 900 used to translate and verify design data and instructions representing an integrated circuit during the design, verification, and manufacturing of a manufactured product such as an integrated circuit. Each of these processes can be structured and enabled as multiple modules or operations. The term “EDA” means “Electronic Design Automation.” These processes begin with creating a product idea (910) using information supplied by the designer, which is then translated to create a manufactured product using a set of EDA processes (912). Once the design is complete, it is tapeped out (934), at which point the artwork of the integrated circuit (e.g., geometric patterns) is sent to a manufacturing facility to produce a mask set, which is then used for manufacturing the integrated circuit. After tape-out, the semiconductor die is manufactured (936), and packaging and assembly processes (938) are performed to produce the finished integrated circuit (940).

[0063] Circuit or electronic structure specifications can range from low-level transistor material layouts to high-level descriptive languages. Hardware description languages ​​("HDL") such as VHDL, Verilog, SystemVerilog, SystemC, MyHDL, or OpenVera can be used to design circuits and systems at high levels of representation. HDL descriptions can be translated into logic-level register transfer-level ("RTL") descriptions, gate-level descriptions, layout-level descriptions, or mask-level descriptions. Each lower level of representation, being a more detailed description, adds more useful details to the design description, for example, further details of the module containing that description. Lower-level representations, being more detailed descriptions, can be generated by a computer, derived from a design library, or created by another design automation process. An example of a lower-level specification language for specifying more detailed descriptions is SPICE, which is used for detailed descriptions of circuits with many analog components. The description at each level of representation is enabled for use by the corresponding system at that level (e.g., a formal verification system). The design process may use the sequence depicted in Figure 9. The described process can be enabled by an EDA product (or EDA system).

[0064] During system design (914), the function of the integrated circuit to be manufactured is specified. The design can be optimized to meet desired characteristics such as power consumption, performance, area (physical and / or lines of code), and cost reduction. At this stage, the design can be divided into different types of modules or components.

[0065] During logical design and functional verification (916), modules or components within a circuit are specified in one or more descriptive languages, and the functional accuracy of their specifications is checked. For example, components of a circuit may be verified to produce outputs that match the specifications requirements of the circuit or system being designed. Functional verification may use simulators or other programs such as testbench generators, static HDL checkers, and formal verifiers. In some embodiments, a special system of components, referred to as an “emulator” or “prototyping system,” is used to speed up functional verification.

[0066] During test synthesis and design (918), the HDL code is converted into a netlist. In some embodiments, the netlist may be a graph structure in which the edges of the graph structure represent the components of the circuit, and the nodes of the graph structure represent how the components are interconnected. Both the HDL code and the netlist are hierarchical manufactured articles that can be used by EDA products to verify that the integrated circuit performs according to a specified design during manufacturing. The netlist can be optimized to suit the target semiconductor manufacturing technology. In addition, the finished integrated circuit can be tested to verify that the integrated circuit meets the requirements of the specification.

[0067] During netlist verification (920), the netlist is checked for compliance with timing constraints and correspondence with the HDL code. During design planning (922), the overall floor plan of the integrated circuit is constructed and analyzed for timing and top-level routing.

[0068] During layout or physical implementation (924), physical placement (positioning of circuit components such as transistors or capacitors) and routing (connection of circuit components with multiple conductors) occur, and the selection of cells from a library to enable specific logic functions can be performed. As used herein, the term “cell” may refer to a set of transistors, other components, and interconnections that provide Boolean logic functions (e.g., AND, OR, NOT, XOR) or storage functions (e.g., flip-flops or latches). As used herein, a circuit “block” may refer to two or more cells. Both cells and circuit blocks may be referred to as modules or components and are enabled both in physical structures and in simulations. Parameters such as size are specified for selected cells (based on “standard cells”) and become accessible in a database for use by EDA products.

[0069] During analysis and extraction (926), circuit functionality is verified at the layout level, allowing for improvements to the layout design. During physical verification (928), the layout design is checked to ensure that manufacturing constraints such as DRC constraints, electrical constraints, and lithography constraints are correct, and that the circuit configuration functionality matches the HDL design specifications. During resolution enhancement (930), the layout geometry is transformed to improve the manufacturing method of the circuit design.

[0070] During tape-out, data is created that will be used to generate the lithography mask (after lithography enhancements are applied, if appropriate). During mask data preparation (932), the “tape-out” data is used to generate the lithography mask used to manufacture the finished integrated circuit.

[0071] The storage subsystem of a computer system (such as computer system 1000 in Figure 10) may be used to store programs and data structures, libraries, and products used for developing cells for physical and logical designs that utilize some or all of the EDA products described herein.

[0072] Figure 10 illustrates an exemplary machine of computer system 1000 in which a set of instructions for causing the machine to perform any one or more of the methodologies discussed herein can be executed. In alternative implementations, the machine may be connected to other machines in a LAN, intranet, extranet, and / or the Internet (e.g., network connectivity). The machine may operate as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or client machine in a client-server network environment, or as a server or client machine in a cloud computing infrastructure or environment.

[0073] A machine can be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular phone, web appliance, server, network router, switch or bridge, or any machine capable of executing a set of instructions (sequential or otherwise) that specify actions to be taken by such machine. Furthermore, although a single machine is given as an example, the term “machine” shall also be interpreted to include any set of machines that individually or collectively execute a set (or set) of instructions in order to perform one or more of the methodologies discussed herein.

[0074] An exemplary computer system 1000 includes a processing device 1002, main memory 1004 (e.g., read-only memory (ROM), flash memory, synchronous DRAM, or other dynamic random access memory (DRAM)), static memory 1006 (e.g., flash memory, static random access memory (SRAM), etc.), and data storage device 1018, which communicate with each other via a bus 1030.

[0075] The processing device 1002 represents one or more processors, such as a microprocessor or a central processing device. More specifically, the processing device may be a composite instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor that implements other instruction sets, or a processor that implements a combination of instruction sets. The processing device 1002 may also be one or more dedicated processing devices, such as an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a digital signal processor (DSP), or a network processor. The processing device 1002 may be configured to execute instruction 1026 for performing the operations and steps described herein.

[0076] The computer system 1000 may further include a network interface device 1008 for communication via a network 1020. The computer system 1000 may also include a video display unit 1010 (e.g., a liquid crystal display (LCD) or a cathode ray tube (CRT)), an alphanumeric input device 1012 (e.g., a keyboard), a cursor control device 1014 (e.g., a mouse), a graphics processing unit 1022, a signal generation device 1016 (e.g., a speaker), another graphics processing unit 1022, a video processing unit 1028, and an audio processing unit 1032.

[0077] The data storage device 1018 may include a machine-readable storage medium 1024 (also known as a non-temporary computer-readable medium) that stores one or more instruction sets 1026, or software that embodies one or more of the methodologies or functions described herein. The instructions 1026 may also reside, all or at least partially, in the main memory 1004 and / or the processing device 1002 during execution by the computer system 1000, and the main memory 1004 and the processing device 1002 also constitute a machine-readable storage medium.

[0078] In some implementations, instruction 1026 includes instructions for performing the functions corresponding to the disclosure. Although the machine-readable storage medium 1024 is illustrated as a single medium in exemplary implementations, the term “machine-readable storage medium” should be interpreted to include a single or multiple mediums (e.g., a centralized or distributed database, and / or associated caches and servers) that store one or more sets of instructions. The term “machine-readable storage medium” should also be interpreted to include any medium that can store or encode a set of instructions for machine execution, causing a machine and processing device 1002 to perform one or more of the methodologies of the disclosure. Accordingly, the term “machine-readable storage medium” should be interpreted to include, but not limited to, solid-state memory, optical media, and magnetic media.

[0079] Some parts of the detailed explanation above have been presented in terms of algorithms and symbolic representations of operations on data bits in computer memory. The descriptions and representations of these algorithms are methods used by those skilled in the field of data processing to communicate the nature of their work to others skilled in the field in the most effective way. An algorithm can be a set of operations that lead to a desired result. These operations require the physical manipulation of physical quantities. Such quantities may take the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. Such signals may be referred to as bits, values, elements, symbols, characters, terms, digits, and so on.

[0080] However, it should be noted that all these terms and similar terms are associated with appropriate physical quantities and are merely convenient labels applied to those quantities. As is evident from this disclosure, unless otherwise stated, throughout this description, certain terms are understood to refer to the operation and processes of a computer system or similar electronic computing device that manipulates data represented as physical (electronic) quantities within the registers and memory of a computer system and converts it into other data similarly represented as physical quantities within the memory and registers of a computer system or other such information storage devices.

[0081] This disclosure also relates to apparatus for performing the operations described herein. Such apparatus may include a computer that can be specifically constructed for the intended purpose or that can be selectively started or reconfigured by a computer program stored in the computer. Such computer programs may be stored in any type of disk, including but not limited to floppy disks, optical disks, CD-ROMs, and magneto-optical disks, or in computer-readable storage media such as read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic or optical cards, or any type of medium suitable for storing electronic instructions, each of which is connected to a computer system bus.

[0082] The algorithms and representations presented herein are not inherently related to any particular computer or other device. Various other systems may be used with the program in accordance with the teachings herein, or it may prove convenient to construct a more specialized device for performing this method. Furthermore, this disclosure is not described with reference to any particular programming language. It will be understood that the teachings of the disclosure described herein can be implemented using a variety of programming languages.

[0083] This disclosure may be provided as a computer program product or software which may include a machine-readable medium storing instructions that can be used to program a computer system (or other electronic device) to perform processing in accordance with this disclosure. The machine-readable medium includes any mechanism for storing information in a form that can be read by a machine (e.g., a computer). For example, machine-readable (e.g., computer-readable) medium includes machine-readable storage media such as read-only memory ("ROM"), random-access memory ("RAM"), magnetic disk storage media, optical storage media, and flash memory devices.

[0084] In the aforementioned disclosure, the implementation of the disclosure was described with reference to a specific exemplary implementation. It will be apparent that various modifications can be made without departing from the broader spirit and scope of implementation of the disclosure as set forth in the following claims. Where the disclosure refers to some elements in the singular, multiple elements may be depicted in the drawings, and similar elements will be given similar numbers. Thus, the disclosure and drawings should be considered in an exemplary sense, not in an restrictive sense.

Claims

1. It is a method, To receive an optical integrated circuit (PIC) design comprising multiple devices, wherein the multiple devices comprise a first device, a second device, and a third device, Determining that the third device is a hierarchical device having two or more hierarchical levels, where each hierarchical level includes a corresponding device and path, Determining a first path between a first pin of the first device among the plurality of devices and a second pin of the second device among the plurality of devices by traversing the two or more hierarchical levels of the third device, wherein determining the first path comprises unfolding each of the two or more hierarchical levels, selecting a pin of the third device at each of the two or more hierarchical levels, and determining that the first selected pin is included in the first path based on the determination that a path exists from the first selected pin to the second pin among the selected pins, Determining one or more characteristics of the first path based on the wavelength of the optical signal, the characteristics of the first device, and the characteristics of the second device, A method comprising outputting the first path and one or more characteristics by a processor.

2. Determining the first path between the first pin of the first device and the second pin of the second device is: Detecting a net that connects the first pin of the first device to the input pin of a third device among the plurality of devices, The method according to claim 1, further comprising determining, based on the characteristics of the third device, that the input pin of the third device is connected to the output pin of the third device.

3. Determining whether the PIC design has one or more levels of hierarchy, The method according to claim 1, further comprising determining a path from the first pin of the first device to the second pin of the second device, passing through each of the one or more levels of hierarchy.

4. Determining the first path between the first pin of the first device and the second pin of the second device is: Analyzing each of the multiple candidate pins, and determining one or more candidate pins connected to the first pin of the first device via the corresponding net, The method according to claim 1, further comprising marking each analyzed candidate pin as visited.

5. To determine a second path between the first pin of the first device and the second pin of the second device, passing through the plurality of devices, Determining one or more second characteristics of the second path, The method according to claim 1, further comprising outputting the second path and one or more of the second characteristics.

6. The method according to claim 5, wherein the first path and the second path differ in at least one or more of the number of devices, the set of devices, and the order of the devices.

7. The method according to claim 1, wherein the one or more characteristics include one or more of the geometric length of the first path, the optical length of the first path, the optical delay of the first path, and the optical loss associated with the first path.

8. The method according to claim 1, further comprising determining all of one or more devices along the first path, wherein the one or more characteristics of the first path are further based on the one or more devices.

9. The method according to claim 1, wherein outputting the first path and the one or more characteristics is further comprising storing the first path and the one or more characteristics in memory.

10. It is a system, Memory for storing instructions, The system comprises a processor coupled to the memory and executing the instruction, and when the instruction is executed, it provides the processor with respect to the instruction. Receiving a design for an optical integrated circuit (PIC) with multiple devices, Determining a first path between a first pin of a first device among the plurality of devices and a second pin of a second device among the plurality of devices by traversing two or more hierarchical levels of a third device among the plurality of devices, wherein determining the first path comprises unfolding each of the two or more hierarchical levels, selecting a pin of the third device at each of the two or more hierarchical levels, and determining that the first selected pin is included in the first path based on the determination that a path exists from the first selected pin to the second pin among the selected pins, Determining one or more characteristics of the first path based on the wavelength of the optical signal, the characteristics of the first device, the characteristics of the second device, and one or more characteristics of one or more devices along the first path, A system that causes the system to output the first path and one or more of the characteristics.

11. Determining the first path between the first pin of the first device and the second pin of the second device is: Detecting a net that connects the first pin of the first device to the input pin of a third device among the plurality of devices, The system according to claim 10, further comprising determining, based on the characteristics of the third device, that the input pin of the third device is connected to the output pin of the third device.

12. The aforementioned processor further, It is determined that the PIC design has one or more levels of hierarchy, The system according to claim 10, configured to determine a path from the first pin of the first device to the second pin of the second device, passing through each of the one or more levels of hierarchy.

13. Determining the first path between the first pin of the first device and the second pin of the second device is: Analyzing each of the multiple candidate pins, and determining one or more candidate pins connected to the first pin of the first device via the corresponding net, The system according to claim 10, further comprising marking each analyzed candidate pin as visited.

14. The aforementioned processor further, Determine the second path between the first pin of the first device and the second pin of the second device, passing through the plurality of devices. Determine one or more of the second characteristics of the second path, It is configured to output the second path and one or more of the second characteristics, The system according to claim 10, wherein the first path and the second path differ in at least one or more of the number of devices, the set of devices, or the order of devices.

15. The system according to claim 10, wherein the one or more characteristics include one or more of the geometric length of the first path, the optical length of the first path, the optical delay of the first path, or the optical loss associated with the first path.

16. The system according to claim 10, wherein the processor is further configured to determine one or more of the plurality of devices along the first path, and the one or more characteristics of the first path are further based on the one or more devices.

17. Outputting the first path and the one or more characteristics comprises storing the first path and the one or more characteristics in memory, according to claim 10.

18. A computer implementation method for displaying the characteristics of an optical integrated circuit (PIC) design within a user interface, wherein the computer implementation method is: Receiving the PIC design comprising multiple devices, wherein the multiple devices comprise a first device, a second device, and a third device, and the third device is a hierarchical device having two or more hierarchical levels, each of which includes a corresponding device and path, Determining a first path between a first pin of the first device and a second pin of the second device, wherein the first path traverses two or more levels of hierarchy of the third device, and determining the first path comprises unfolding each of the two or more levels of hierarchy, selecting a pin of the third device at each of the two or more levels of hierarchy, and determining that the first selected pin is included in the first path based on the determination that a path exists from a first selected pin to the second pin among the selected pins, Determining one or more characteristics of the first path based on the wavelength of the optical signal, the first device, the second device, and one or more characteristics of one or more devices along the first path, A computer implementation method comprising a processor displaying one or more of the aforementioned characteristics within a user interface on a display device.

19. The method of claim 18, further comprising determining a path through each of the two or more hierarchical levels of the third device.

20. Determining the first path between the first pin of the first device and the second pin of the second device is: Detecting a net that connects the first pin of the first device to the input pin of the third device, The method according to claim 18, further comprising determining, based on the characteristics of the third device, that the input pin of the third device is connected to the output pin of the third device.

Images