High transconductance input stage for comparators and amplifiers

Abstract

To provide a high trans conductance input stage for a comparator and an amplifier.SOLUTION: A low input capacitance input stage for a high voltage amplifier includes a first input transistor that receives a first part of a differential input signal and is configured to provide a first part of an output signal, and a second input transistor that receives a second part of the differential input signal and is configured to provide a second part of the output signal. The amplifier can include a negative feedback stage including a bias generator circuit. The negative feedback stage can include a first negative feedback transistor and a second negative feedback transistor that are coupled in series. The bias generator circuit provides a first bias signal and a second bias signal to gate terminals of the first negative feedback transistor and the second negative feedback transistor, respectively, so as to be able to control the impedance of a signal route coupling source terminals of the first input transistor and the second input transistor.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] This disclosure relates, in general, to transconductance circuits, and more specifically to high transconductance input stages for comparators and amplifiers. [Background technology]

[0002] A transconductance circuit (also called a "transconductor" or "voltage-current converter") is a circuit that generates an output current that corresponds to or is proportional to an input voltage. Transconductance circuits can be used in many modern electronic systems across a wide range of markets, including industrial, military, automotive, and automated test (e.g., pin electronics) environments. For example, one or more transconductance circuits may be used in an amplifier or comparator circuit. [Overview of the project] [Problems that the invention aims to solve]

[0003] The inventors recognize that the problem to be solved involves providing an input stage for a comparator or amplifier having high transconductance, large differential voltage compliance and reliability, and high bandwidth characteristics. The input stage may have relatively low input capacitance characteristics. The input stage can optionally be used as an interface for a comparator or other automated test equipment. [Means for solving the problem]

[0004] In one example, the solution may include or be used a system comprising a transconductance circuit with a negative feedback transistor. In some examples, the transconductance circuit with a negative feedback transistor may be used as the transconductance input stage of an amplification stage, which is configured to convert an input voltage signal into an output current signal. In some examples, the amplification stage may further include a load stage configured to inversely convert the output current of the input stage into an output voltage. One or more of such amplification stages may be included in a device such as an amplifier or comparator.

[0005] In one example, the input stage circuit has a first gate terminal (V IP The first portion of the differential input signal is received at the first drain terminal (I) of the first input transistor. OP A first input transistor (M) configured to provide a first portion of the output signal in ) P ) may include, and the input stage circuit may include the second gate terminal (V IM The second portion of the differential input signal is received at the second drain terminal (I) of the second input transistor. OM A second input transistor (M) is configured to provide a second portion of the output signal. N ) may include. The input stage circuit includes a first negative feedback transistor and a second negative feedback transistor (M) coupled in series. DP M DM The circuit may further include a negative feedback stage circuit having a bias generator circuit. The bias generator circuit may be configured to control the impedance of the signal path coupling the source terminals of the first input transistor and the second input transistor by providing a first bias signal and a second bias signal, respectively, to the gate terminals of the first and second negative feedback transistors.

[0006] For example, a method for controlling the gain characteristics and bandwidth characteristics of an input stage circuit may include receiving a first input stage input signal and a second input stage input signal at the first and second input nodes of the respective first and second input transistors; providing a first bias signal to the gate terminal of the first negative feedback transistor and the source terminal of the first input transistor using a first bias circuit; providing a second bias signal to the gate terminal of the second negative feedback transistor and the source terminal of the second input transistor using a second bias circuit; adjusting the impedance characteristics of the signal path coupling the first input transistor and the second input transistor in response to the reception of the first and second bias signals at the first and second negative feedback transistors; providing a first input stage output signal using a first output terminal of the first input transistor; and providing a second input stage output signal using a second output terminal of the second input transistor.

[0007] This summary is not intended to provide an exclusive or exhaustive description of the present invention. A more detailed description is included to provide further information relating to this patent application. [Brief explanation of the drawing]

[0008] To facilitate the identification of any particular element or action, one or more of the most significant digits of the reference number refer to the figure number in which that element is first introduced.

[0009] [Figure 1] Generally, we will illustrate an example of a first test system including a pin driver. [Figure 2] Generally, we will illustrate an example of a multi-stage comparator circuit. [Figure 3] Generally, we will illustrate an example of the first transconductance circuit. [Figure 4] In general, we will illustrate an example of a second transconductance circuit. [Figure 5]Generally, we will illustrate with an example of the first exemplary transconductance stage of an amplifier. [Figure 6] Generally, we will illustrate an example of the second exemplary transconductance stage of an amplifier. [Figure 7] Generally, we will illustrate an example of the transconductance stage, which is a third example of an amplifier. [Figure 8] Generally, we will illustrate with an example of the fourth exemplary transconductance stage of an amplifier. [Figure 9] In general, this paper illustrates an example of a method for controlling the gain characteristics and bandwidth characteristics of an input stage circuit. [Modes for carrying out the invention]

[0010] High-voltage comparators or amplifiers are essential components in many modern electronic systems. Such amplifiers are applied, among other things, to industrial, medical, automotive, and automated test equipment (ATE) devices. Certain end-uses can have various requirements, such as specific voltage compliance levels, and therefore, a variety of amplifier systems are needed, including systems that can operate over a wide input / output voltage range, including a range that can exceed the breakdown voltage of individual devices containing such amplifier systems.

[0011] For example, ATE applications use high-voltage amplifiers to provide a Time Management Unit (TMU) and / or High-Voltage Driver (HVD), where three key performance indicators are a wide input / output voltage range (e.g., several hundred volts), relatively high speed (e.g., tens of megahertz), and low power consumption (e.g., in the milliwatt range, enabling high-capacitance device testing). Source impedance, for example, the source impedance of the preceding stage driving the amplifier, can also affect the system's bandwidth characteristics. In applications with high source impedance, subsequent amplifier stages may be configured to have characteristically low input capacitance to ensure adequate bandwidth performance. Additionally, when the amplifier is used in a feedback configuration, a low-capacitance input stage may be desired, for example, to achieve the maximum possible bandwidth with the minimum power consumption.

[0012] In one example, lateral diffusion MOSFET (LDMOS) devices can be used in the input stage of a high-voltage amplifier. Such devices may have characteristically high blocking voltages due to the diffused p-type channel region within the low-doped n-type drain region. Due to the relatively large size of such devices, they may have characteristically high parasitic capacitance values ​​compared to other non-LDMOS or low-voltage devices.

[0013] The inventors recognize that the problem to be solved involves providing an input stage or transconductance stage having low input capacitance, high differential voltage compliance, and high bandwidth characteristics. This problem involves providing a differential input stage with high tolerance to large common-mode (CM) and differential-mode (DM) input voltages. The inventors recognize that a problem with a typical differential pair input stage, such as one that can use a DMOS device (e.g., a double-spread MOSFET device), is that while the differential pair can handle a large CM range, such an input stage may be limited by a relatively low (e.g., 5V) Vgs (gate-source voltage) limit beyond which the device gate oxide can be destroyed and device damage can occur. This limitation means that while the DMOS device can withstand high Vds (drain-source voltage) and high Vdg (drain-gate voltage), it has low Vgs tolerance, resulting in a circuit that can handle high CM voltages but has low DM voltage tolerance. Furthermore, the inventors recognize that using high-voltage diodes at the tail node to improve DM immunity (e.g., provided in series with the source of a DMOS device with a differential pair) is not always feasible, as not all processes provide high-voltage diodes. Moreover, even when high-voltage diodes are available, they may have inherently slow reverse recovery time characteristics, which can hinder their use in high-speed circuits such as comparators.

[0014] Other solutions that use transistors at the tail node (e.g., in series with the differential pair device source; see Figure 4) to achieve high CM and DM voltage tolerance may result in relatively lower performance in terms of gain and bandwidth. Specifically, certain transistor-based approaches use physically large transistors to achieve high gain, thereby capacitively loading the amplifier input and reducing the input stage bandwidth. To achieve high bandwidth, physically small transistors are generally required, which reduces gain. The inventors recognize that a solution to these problems and limitations may involve or be used with bias generator circuits to control the transistors at the tail node. By controlling the operation of these transistors, CM and DM voltage tolerance can be improved, and high gain and high bandwidth can be achieved.

[0015] Figure 1 illustrates a first exemplary test system 100, which generally shows a test system topology including multiple driver stages, loads, and comparator stages. The first exemplary test system 100 includes a driver system comprising a first driver AB 102, which may include a Class AB driver circuit, and a first driver A 104, which may include a Class A driver circuit. The first exemplary test system 100 may further include output elements, such as a first resistor 106, which can be configured to provide a specified output or load impedance. In one example, the first exemplary test system 100 includes a first load circuit 108, which may include a comparator circuit 122, or an active load or other load device. In one example, the test system is configured to provide a first output current 120, i_OUT, at a DUT interface or DUT node 132. The DUT node 132 can be coupled to a DUT 124 using a loaded signal path 134. In some examples, the first resistor 106 and the loaded signal path 134 have matching impedance characteristics.

[0016] In one example, the first driver AB102 can be configured to generate a voltage stimulus signal by selecting between parallel-connected diode bridges, each driven by its own dedicated DC voltage level. In the first exemplary test system 100 in Figure 1, DC voltages Vih110 and Vil112 drive the diode bridges in the first driver AB102. The switching stage may be followed by a voltage buffering stage that can provide power gain, such as that which can be used to generate a large current to supply a 50Ω DUT environment.

[0017] In contrast to the first driver AB102, the first driver A104 can be configured to generate transitions in the DUT node 132 using a relatively large current switching stage that can be directly coupled to the DUT node 132. The current switching stage of the first driver A104 can alternately switch current to and from the DUT node 132 in response to a control signal Swing 118, which may be a voltage control signal.

[0018] Figure 1 includes a comparator circuit 122. The comparator circuit 122 may include a single-stage or multi-stage comparator configured to receive signals from the DUT 124, such as via the DUT node 132 and the loaded signal path 134. The comparator circuit 122 can compare the received signal with a comparator reference signal 128 (e.g., Vth) and, in response, provide a differential comparator output signal 130 (e.g., OP).

[0019] Figure 2 illustrates a comparator example 200 that generally includes a comparator circuit 122. The comparator circuit 122 may include a comparator input node 210, a reference signal input node 212, a first output node 214, and a second output node 216. The comparator circuit 122 may include several different circuit stages provided in series. For example, the comparator circuit 122 may include a high-voltage-tolerant input stage 206, one or more gain stages such as a first gain stage 202 to an nth gain stage 208, and an output stage 204. In one example, the first gain stage 202 may include a comparator stage, or the input stage 206 may be configured to perform a comparator function.

[0020] In one example, the input stage 206 may be configured to receive information from the DUT 124 via a loaded signal path 134, for example, through the DUT node 132, using the comparator input node 210. The input stage 206 may also receive a comparator reference signal 128Vth using the reference signal input node 212. Generally, the input stage 206 is configured to perform a signal comparison operation to determine which of the signals from the comparator input node 210 and the reference signal input node 212 has a larger or smaller signal amplitude characteristic, for example, at a specific time or a specified time. The comparison result or output of the input stage 206 may be provided to the first gain stage 202. In one example, the comparison result may include a differential signal or a logic signal, i.e., a signal having two signal components.

[0021] In one example, the input stage 206 includes a differential amplifier that amplifies a differential voltage received at a comparator input node 210 and a reference signal input node 212, and suppresses common mode signal components. Various other input stage 206 circuits may be used. The first gain stage 202 may include various gain circuits or amplifier circuits. A plurality of gain stage entities may be provided in series such that each gain stage further amplifies or buffers the output of a preceding gain stage. In the example of FIG. 2, the first gain stage 202 provides a first gain stage output signal to one or more intermediate gain stages, which provide a gain stage output using a last or nth gain stage 208. The nth gain stage 208 may be configured to provide an output signal to a relatively high input impedance receiver in the output stage 204.

[0022] In one example, the output stage 204 provides a differential comparator output signal 130 including a first signal component Q and a second signal component Qb at a first output node 214 and a second output node 216, respectively. That is, the comparator stage output signal components may be used to provide a digital output signal indicating a magnitude relationship between input signals received at the comparator input node 210 and the reference signal input node 212.

[0023] FIG. 3 generally illustrates an example of a first amplification stage 302. The first amplification stage 302 may include a first transconductance circuit 304 having a plurality of follower circuits. In the example of FIG. 3, the first transconductance circuit 304 includes a pair of source follower circuits arranged as a differential pair. In one example, the first amplification stage 302 includes a comparator or an amplifier, such as may include the input stage 206 of the example comparator 200 of FIG. 2. The first amplification stage 302 may be a first preamplifier stage, and may be followed by one or more other gain stages. In the example of FIG. 3, the first amplification stage 302 may include a load circuit 306, and the load circuit 306 may provide an output to a subsequent gain stage or output stage.

[0024] The example of FIG. 3 includes a first input transistor M including a first portion of the first transconductance circuit 304 PAnd the second input transistor M, which includes the second part of the first transconductance circuit 304. M This shows that, for example, the input transistor M P and M M It includes a differential pair circuit. Input transistor M P and M M Each of these can include its respective high-voltage transistor (e.g., an LDMOS transistor). The common-mode voltage range of the differential pair can be equal to the LDMOS drain-source (DS) breakdown voltage (BV), or BVDS (e.g., 24V or higher). However, the differential input voltage range can be approximately equal to the gate-source breakdown voltage plus the gate-source voltage, or VGS (e.g., 6V).

[0025] In the first transconductance circuit 304, the first input transistor M P One of its terminals (for example, transistor M P The gate terminal of the first input transistor M is coupled to the first input transistor M. P The first input voltage V IP It receives the signal. Second input transistor M M One of its terminals (for example, transistor M M The gate terminal of is coupled to the second input 310, and the second input transistor M M This is the second input voltage V IM Receives the signal. First input transistor M P The second terminal (for example, transistor M P The drain terminal of the first output current I OP The first output 312 is coupled to the second input transistor M to provide the following: M The second terminal (for example, transistor M M The drain terminal of the second output current I OM It is coupled to a second output 314 to provide the first input transistor M P The third terminal (for example, transistor M P The source terminal of the second input transistor M is connected, for example, via the intermediate node NCM.M The third terminal (for example, transistor M M It is connected to the source terminal of transistor M. P and M M For each of these, the source terminal of the transistor can be connected to the back gate terminal of the transistor.

[0026] In one example, the first transconductance circuit 304 may include tail current sources such as a first current source 316 and a second current source 318. The first current source 316 is connected to the first input transistor M P The second current source 318 can be connected to the source terminal, and the second input transistor M M It can be coupled to the source terminal. The first current source 316 and the second current source 318 together power the input transistor M of the first transconductance circuit 304. P and M M The total tail current I in the differential pair Tail Provides, in one example, the first current source 316 and the second current source 318 each provide a tail current I Tail Provides / 2.

[0027] In some examples, the first transconductance circuit 304 includes a portion of a comparator circuit, such as that found in comparator example 200. In this case, V IP and V IM This can be the input to the comparator. The input can be provided or driven by an external source such as a DUT. Therefore, the first transconductance circuit 304 receives the input V IP and V IM Evaluate the difference between the voltage levels and generate an output current that indicates whether the difference is positive or negative (for example, input V IP and V IM It can be configured to generate a logic 1 or logic 0 output indicating whether the difference between the voltage levels is positive or negative. For example, difference I OP -I OM If the result is positive, then the difference V IP -V IM is positive, and difference I OP -IOM If the difference is negative, IP -V IM It is negative. OP and I OM The magnitude of the difference between the two is V IP and V IM It can be a function of the difference in magnitude between the two.

[0028] In one example, the first transconductance circuit 304 includes an amplifier that can be used in a feedback circuit. Such an example of the first transconductance circuit 304 can be modified by changing the output IOP and IOM, thereby changing the input V IP and V IM They can be configured to be substantially equal, and their outputs can then be coupled to the amplifier input through a feedback path.

[0029] The voltage at the NCM node is such that the input transistor M has the maximum input voltage at its own gate. P and M M Since it is set by one of the input transistors M, a problem may arise with the first transconductance circuit 304. P and M M The differential pair of tail current I T When completely switching to one of the first output 312 and the second output 314, the turned-off input transistor (i.e., the input transistor M having the lowest input signal at its own gate terminal) P and M M One of these may experience gate breakdown at its own source terminal boundary. For example, when the first transconductance circuit 304 is used as a comparator (e.g., a high-voltage comparator), V IP and V IM The difference between the input transistor M P and M M The gate oxide reliability voltage rating may be exceeded. When the first transconductance circuit 304 is used in the amplifier, and the amplifier input signal range is such that the input transistor M P and M MIf the voltage is greater than the breakdown rating, the amplifier may have the same reliability problems as a high-voltage comparator. In a steady state, such as when the amplifier settles to the amplifier's final output level or waveform, the two input V IP and V IM They would be practically equal and would not have reliability issues, but input V IP and V IM This can vary significantly at the start of settling, which can lead to amplifier reliability issues. Therefore, the differential pair-based first transconductance circuit 304 may be insufficient or unreliable for high-voltage applications where the differential input voltage range exceeds the limits of device gate oxide reliability.

[0030] Figure 4 illustrates an example of a second transconductance circuit 404 in which a differential pair is generally included in the second amplification stage 402. In one example, the second amplification stage 402 includes a comparator or amplifier, such that it may include the input stage 206 of comparator example 200. The second amplification stage 402 may be a first preamplifier stage, followed by one or more other gain stages.

[0031] The example in Figure 4 shows an input transistor M that includes each follower circuit. P and M M The differential pair is shown, and each of the input transistors may include a high-voltage transistor (e.g., an LDMOS transistor). The common-mode voltage range of the input differential pair is equal to that of an LDMOS BVDS, for example, 24 volts (V). However, the differential input voltage range can be approximately equal to the gate-source breakdown voltage + gate-source voltage (VGS) (e.g., about 6V).

[0032] In the second transconductance circuit 404, the first input transistor M is provided, similarly to the first transconductance circuit 304. P One of its terminals (for example, transistor M P The gate terminal of the first input transistor M is coupled to the first input transistor M. P The first input voltage VIP receives the signal. The second input transistor M M has one terminal (e.g., transistor M M gate terminal) coupled to the second input 310, and the second input transistor M M receives the second input voltage V IM . The first input transistor M P has a second terminal (e.g., transistor M P drain terminal) coupled to a first output 312 for providing a first output current I OP , and a second terminal of the second input transistor M M (e.g., transistor M M drain terminal) is coupled to a second output 314 for providing a second output current I OM .

[0033] In contrast to the example of the first transconductance circuit 304 from FIG. 3, the second transconductance circuit 404 in FIG. 4 includes a negative feedback stage circuit 420. The negative feedback stage circuit 420 includes a first input transistor M P and the second input transistor M M and is configured to provide an adjustable impedance signal path that isolates the first input transistor M and the second input transistor M. The negative feedback stage circuit 420 includes a first negative feedback transistor M DP and a second negative feedback transistor M DM . The first negative feedback transistor M DP and the second negative feedback transistor M DM can function as a non-linear negative feedback resistor. That is, transistors M DP and M DM each operate as a resistor between their drain terminal and source terminal, and the value of the drain-source resistance is based on the voltage difference between the first input voltage and the second input voltage. In some examples, the variation of the drain-source resistance can be a non-linear function of the voltage difference between the first voltage input and the second voltage input. Transistors M DP and M DM operate like resistors, so they are connected to the first input transistor and the second input transistor MP and M M The input differential pair formed by this is subjected to negative feedback. As a result, transistor M DP and M DM In this specification, this is referred to as a "negative feedback transistor."

[0034] In the example in Figure 4, the first input transistor M P The third terminal (for example, transistor M P The source terminal of the first negative feedback transistor M DP The third terminal (for example, the first negative feedback transistor M) DP This is the source terminal, and this source terminal is connected to the first negative feedback transistor M DP It is connected to the back gate terminal of the second input transistor M. M The third terminal (for example, transistor M M The source terminal of the second negative feedback transistor M DM The third terminal (for example, the second negative feedback transistor M) DM This is the source terminal, and this source terminal is connected to the second negative feedback transistor M DM The first negative feedback transistor M is coupled to the back gate terminal of the first negative feedback transistor M. DP The second terminal (for example, the first negative feedback transistor M) DP The drain terminal of the second negative feedback transistor M at node NCM. DM The second terminal (for example, the second negative feedback transistor M) DM The first negative feedback transistor M is connected to the drain terminal of the first negative feedback transistor. DP The first terminal (for example, the first negative feedback transistor M) DP The gate terminal of the first negative feedback transistor M DP The first input voltage V IP The first input 308 that receives the signal is coupled to the second negative feedback transistor M DM The first terminal (for example, negative feedback transistor M) DM The gate terminal of the second input 310 is coupled to the second negative feedback transistor M DM This is the second input voltage VIM Receive.

[0035] In the operation of the second transconductance circuit 404, the first input transistor M P and the second input transistor M M Each of these can operate in the saturation region. First negative feedback transistor M DP and the second negative feedback transistor M DM It can be configured to operate in either the linear (triode) region or the saturation region, and the negative feedback transistor M DP and M DM When one of the transistors enters the saturation region, the other negative feedback transistor can continue to operate in the linear region.

[0036] During the operation of the second transconductance circuit 404, the first negative feedback transistor M DP The negative feedback resistor provided at the source terminal (for example, node NCMP shown in Figure 4) and the second negative feedback transistor M DM The negative feedback resistor at the source terminal (e.g., node NCMM) is V IP and V IM The input signal difference between, i.e., ΔV I It can be symmetric with respect to V. That is, the resistance between nodes NCMP and NCMM is the applied input signal difference V. IP -V IM This value of resistance can change in accordance with the change in transconductance G. M The value of can be changed accordingly, and that change is G M (V IP -V IM )=G M (V IM -V IP It is symmetrical in that respect. Therefore, the second transconductance circuit 404 accepts a voltage difference of 100mV or a voltage difference of -100mV from the input V. IP and V IM When applied to the same output current I OP and I OM It can generate [this].

[0037] In one example, the total negative feedback resistance between nodes NCMP and NCMM is equal to the first input voltage V IP The second input voltage V IM It can be minimized when it is substantially equal to . Furthermore, the first negative feedback transistor M DP The source terminal and the second negative feedback transistor M DM The equivalent resistance between the source terminal and the input voltage V IP and V IM It may increase as the absolute value (or magnitude) of the difference between them increases. The gate terminal is at the lowest input voltage (first negative feedback transistor M DP or a second negative feedback transistor M DM When the negative feedback transistor coupled to (which may be either) transitions to the saturation region, the positive and negative signal processing portions of the second transconductance circuit 404 are effectively isolated from each other. Thus, the exemplary input stage can tolerate a wide range of input differential voltages without requiring other protection devices.

[0038] Next, regarding the aspect ratios of various transistors included in transconductance circuits, the aspect ratio of FETs (A x ) is the channel length (l) of the FET. x ) for the channel width (w x This refers to the ratio of ). In some embodiments of the transconductance circuit, the first input transistor M P The first negative feedback transistor M with respect to the aspect ratio DP The aspect ratio ratio is determined by the second input transistor M M The second negative feedback transistor M with respect to the aspect ratio DM The aspect ratio ratio can be substantially equal to the ratio of the first input transistor M P The aspect ratio of the second input transistor M M The aspect ratio of the first negative feedback transistor M can be substantially equal to, or equivalently, the aspect ratio of the first negative feedback transistor M DP The aspect ratio of the second negative feedback transistor M DMThe aspect ratio can be substantially equal to that of the first input transistor M. P and the second input transistor M M The aspect ratio of each of them can be approximately 1, while the first negative feedback transistor M DP and the second negative feedback transistor M DM Each aspect ratio can be approximately N, where N is any positive real number. However, in other embodiments, these aspect ratios are determined by the first negative feedback transistor M DP and the first input transistor M P The aspect ratio ratio of the second negative feedback transistor M DM and the second input transistor M M They can be different, as long as their aspect ratios are substantially equal.

[0039] In the example in Figure 4, the first negative feedback transistor M DP and the second negative feedback transistor M DM The first input transistor M P and the second input transistor M M Equivalent transconductance G of the differential pair M Reduce the equivalent transconductance G at ΔV=0. M It can be shown that this can be reduced by N / (1+N). Therefore, the equivalent transconductance G M When N=4, this value can be reduced to 80% of the value in the case of zero negative feedback at the same power level.

[0040] First negative feedback transistor M DP and the second negative feedback transistor M DM When one of them enters the saturation region, the drain current of the corresponding input transistor reaches the minimum level of drain current, I TailThis is substantially equal to / 2*(N+1). The remainder of each input tail current can then be carried to the complementary half of the input side through a negative feedback transistor operating in the saturation region. Under these conditions, the ratio of the output currents can be substantially equal to 2N+1. If desired, these values ​​can be arbitrarily set by appropriately selecting the ratio of the aspect ratio of the input transistor to the aspect ratio of the negative feedback transistor, i.e., by selecting N.

[0041] In some examples, high small-signal gain and small input signal difference for the switching target of total tail current may favor a relatively large N value, while delay variation targets associated with reduced large signal overdrive and reduced NCMP / NCMM node capacitance may favor a relatively small N value. The exact value of N used for the transistor in the second transconductance circuit 404 can be determined, for example, using simulation. In some implementations, when N is selected to be approximately 1.5 or greater, the first negative feedback transistor M DP and the second negative feedback transistor M DM It can be shown that when one of the negative feedback transistors transitions to the saturation region, the other negative feedback transistor remains in the linear operating region. The large voltage drop between the NCMP node and the NCMM node may mainly appear between the drain-source terminals of the negative feedback transistor operating in the saturation region.

[0042] Therefore, the second transconductance circuit 404 is substantially symmetrical with respect to the input terminals and can thus handle both single-ended and differential input signals. First negative feedback transistor M DP and the second negative feedback transistor M DM By including this, the second transconductance circuit 404 can operate up to the BVDS of the transistors included in the second transconductance circuit 404 without reliability issues and in the absence of additional protection mechanisms.

[0043] However, the inventors recognize that the second transconductance circuit 404 exhibits relatively low gain (transconductance) and low bandwidth while providing high common-mode voltage tolerance and differential-mode voltage tolerance. For example, high gain is generally achieved by the first negative feedback transistor M DP and the second negative feedback transistor M DM This requires the use of a physically large implementation (e.g., N>4) and the first negative feedback transistor M DP and the second negative feedback transistor M DM These apply capacitive loads to the first input 308 and the second input 310, respectively, reducing the bandwidth of the circuit. Conversely, high bandwidth is generally achieved by the first negative feedback transistor M DP and the second negative feedback transistor M DM This requires the use of a physically small implementation configuration, which reduces the gain of this circuit. Consequently, this circuit may not achieve high gain and high bandwidth simultaneously, which is undesirable for an ideal input stage. The inventors have found a solution to these and other problems with the first negative feedback transistor M DP and the second negative feedback transistor M DM It is recognized that the system includes or uses a bias generator circuit to control its operation, thereby allowing for a more precise approximation of the behavior of an ideal input stage.

[0044] Figures 5 and 6 illustrate examples of transconductance stages that generally use LDMOS devices for input and negative feedback. Each exemplary stage is symmetrical and shows, for example, CM and DM voltage tolerances limited by the drain terminal breakdown voltage of the LDMOS device. Each of these transconductance stage examples utilizes a current mirror containing a low-voltage device in the bias circuit for the high-voltage LDMOS negative feedback device.

[0045] Figure 5 illustrates a first exemplary transconductance stage 500 in general terms. In one example, the first exemplary transconductance stage 500 includes a comparator or amplifier, such that it may include the input stage 206 of comparator example 200.

[0046] The example in Figure 5 shows input transistor M P and M M The differential pair is shown, and each of the input transistors may include a high-voltage transistor (e.g., an LDMOS transistor). In the first exemplary transconductance circuit 500, the first input transistor M is provided, as similarly provided in the first transconductance circuit 304 and the second transconductance circuit 404. P One of its terminals (for example, transistor M P The gate terminal of the first input transistor M is coupled to the first input transistor M. P The first input voltage V IP It receives the signal. Second input transistor M M One of its terminals (for example, transistor M M The gate terminal of is coupled to the second input 310, and the second input transistor M M This is the second input voltage V IM Receives the signal. First input transistor M P The second terminal (for example, transistor M P The drain terminal of the first output current I OP The first output 312 is coupled to the second input transistor M to provide the following: M The second terminal (for example, transistor M M The drain terminal of the second output current I OM It is coupled to a second output 314 to provide the following.

[0047] In contrast to the examples in Figures 3 and 4, the first exemplary transconductance stage 500 may include a first negative feedback transistor and a second negative feedback transistor M, such as an LDMOS device. DP and M DM The LDMOS device M includes a first bias circuit 502 and a second bias circuit 504 configured to control its operation or bias. DP and M DNThis can be used as a negative feedback transistor for high-voltage protection when large differential signals are present at the first input 308 and the second input 310.

[0048] The first bias circuit 502 includes a current mirror, which includes low-voltage MOS devices M1 and M2 and a cascode transistor. The cascode transistor is an LDMOS device M CP The second bias circuit 504 also includes low-voltage MOS devices M3 and M4 and an LDMOS cascode transistor M CM It includes a current mirror, each of which may have a mirroring ratio of K. In one example, the supply voltage V CC and V EE The potential difference between them can be up to several hundred volts. Therefore, transistor M CP and M CN This is used as a high-voltage cascode for current mirror output devices M2 and M3, protecting these low-voltage devices of each current mirror from drain-to-source damage when the input stage is exposed to large differential input signals.

[0049] Figure 6 illustrates a second exemplary transconductance stage 600 in general terms. The second exemplary transconductance stage 600 comprises a first negative feedback transistor and a second negative feedback transistor M DP and M DM The system includes a third bias circuit 602 and a fourth bias circuit 604 configured to control the operation or bias of the system. Each bias circuit includes a current mirror containing a low-voltage device.

[0050] For example, the third bias circuit 602 has low-voltage MOS devices M1 and M2 and an LDMOS cascode transistor M CP The fourth bias circuit 604 also includes low-voltage MOS devices M3 and M4 and an LDMOS cascode transistor M CMIt includes a current mirror, which includes a transistor M. Each current mirror may have a mirroring ratio of K. In one example, transistor M CP and M CN This is used as a high-voltage cascode for M2 and M3 to protect the low-voltage devices of each current mirror from drain-to-source damage, and the supply voltage V CC and V EE The potential difference between them can be up to several hundred volts.

[0051] In the second exemplary transconductance stage 600, the negative feedback transistor M DP and M DN The gate terminal is an LDMOS cascode device M CP and M CN It is connected to the respective source terminals of the negative feedback transistor M. DP and M DN In contrast to the first exemplary transconductance stage 500, the gate terminals of are connected to diode-connected low-voltage devices M1 and M4, respectively. The second exemplary transconductance stage 600 is M P and M M vs M CP and M CM The aspect ratios of the low-voltage MOS devices M 1 / 4 and M 2 / 3 If it is equal to the Miller ratio (K), it may be functionally identical to the first exemplary transconductance stage 500.

[0052] The first exemplary transconductance stage 500 and the second exemplary transconductance stage 600 utilize low-voltage current mirrors in their respective bias circuits for various reasons. Firstly, the diode-connected transistors of the current mirrors (e.g., M1 and M4) are negative feedback transistors (M DP and M DNIt provides the respective bias voltage signals or gate-source voltages to the inputs. Thus, the gate terminals of the negative feedback transistors are isolated from the transconductance stage inputs at the first input 308 and the second input 310. As a result, the total input capacitance at the input stage inputs is lower, in particular, compared to the example of the second transconductance circuit 404 from Figure 4. In the first exemplary transconductance stage 500 and the second exemplary transconductance stage 600, the negative feedback transistors operate in either the saturation region or the linear region, but M DP and M DN Because it is in series with the diode-connected transistors M1 and M4 of the current mirror, the total effective negative feedback impedance increases.

[0053] Secondly, the current mirror helps compensate for the reduction in overall transconductance of the circuit caused by the increased negative feedback effect. As an example, a low-signal test voltage source is used with transistor M P We consider the gate terminal to be connected to the first input 308. Transistor M P The small signal current flowing through is mirrored by the low-voltage transistors (M1 and M2) according to the Miller ratio K, and the input transistor M P and cascode transistor M CP The sum is calculated at the drain terminal.

number

[0054] The overall transconductance (G) of the first exemplary transconductance stage 500 or the second exemplary transconductance stage 600 m )teeth,

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number

[0055] In one example, the transistor M of the current mirror 1 / 4 To minimize the effects of negative feedback caused by current flow in these transistors, a large aspect ratio can be used. Transistor M 1 / 4 Increasing the aspect ratio of the low-voltage mirror device increases the transconductance

number

number

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[0056] In some cases, a threshold mismatch between high-voltage LDMOS and low-voltage MOS devices can lead to negative feedback from the transistor M DP / DM This can provide a gate-source voltage sufficient to fully turn on the negative feedback transistor M. DP / DM Lower on-resistance

number

[0057] Figure 7 shows, in general, the negative feedback transistor M DP and M DM A third exemplary transconductance stage 700 is illustrated, which includes a voltage source configured to apply the respective voltage signals to the gate terminals of the first exemplary transconductance stage 500. In one example, the third exemplary transconductance stage 700 includes an instance of the first exemplary transconductance stage 500 having a first bias circuit 502 and a second bias circuit 504, but the third exemplary transconductance stage 700 includes a first input transistor M P The first voltage source 702 and the second input transistor M at the source terminal M The system further includes a second voltage source 704 at the source terminal.

[0058] In one example, the voltage signals from the first voltage source 702 and the second voltage source 704 are fed to a negative feedback transistor M DP and M DMIt can be used to increase the gate-source voltage applied at the gate terminal. One potential drawback of the third exemplary transconductance stage 700 is the reduction in overall headroom due to the diode-connected low-voltage devices and voltage sources used to overcome the threshold voltage mismatch. However, the reduction in headroom is generally due to the available supply range (e.g., V) which can be up to several hundred volts. EE ~V CC ) is not important.

[0059] Figure 8 illustrates the fourth exemplary transconductance stage 800 in general terms. The fourth exemplary transconductance stage 800, like the first exemplary transconductance stage 500, the second exemplary transconductance stage 600, and the third exemplary transconductance stage 700, does not include or use the same bias circuitry as the LDMOS cascode device and low-voltage current mirror to compensate for transconductance losses due to the negative feedback effect. Instead, the fourth exemplary transconductance stage 800 uses a negative feedback transistor M DP and M DM The gate terminals are controlled using the first isolation circuit 802 and the second isolation circuit 804, respectively.

[0060] The first isolation circuit 802 includes a transistor M1 connected to a low-voltage diode, and optionally, the first input transistor M P A series voltage source V connected to the source terminal. DC The second isolation circuit 804 also includes a transistor M3 connected to a low-voltage diode, and optionally a second input transistor M M A series voltage source V connected to the source terminal. DC This includes the bias current (I Tail Half of ) is the input transistor M P and M M and diode-connected transistors M1And flows through each of M3. Unlike the first exemplary transconductance stage 500 and the second exemplary transconductance stage 600, the fourth exemplary transconductance stage 800 has an input transistor M P and M M The bias current is not divided between the input transistor M and the corresponding LDMOS cascode device, and therefore the larger portion of the bias current remains with the input transistor M P and M M It flows through.

[0061] For example, input transistor M P and M M Each of these can comprise a combination of multiple parallel-connected LDMOS devices. Similarly, each of the diode-connected transistors M1 and M3 can include a combination of multiple parallel-connected low-voltage devices. In this example, and due to the parallel connection of multiple LDMOS devices in the input differential pair, the aspect ratio of the input device can be larger than, for example, the input device of the third exemplary transconductance stage 700. As a result, the fourth exemplary transconductance stage 800 can provide better performance in terms of flicker noise and offset compared to the third exemplary transconductance stage 700.

[0062] The bias and isolation circuits discussed herein for various input stage examples provide improvements in both common-mode (CM) voltage tolerance and differential-mode (DM) voltage tolerance. These circuits, for example, maximize the Vgs of a negative feedback transistor M DP and M DMImprovements are achieved by actively controlling the gate voltage. These circuits establish the negative feedback transistor Vgs at the maximum allowable voltage, minimizing the impedance in the linear region of the negative feedback transistor and thus maximizing the gain. Minimizing the impedance in this linear region allows for a reduction in the size of the transistor, thereby increasing the bandwidth while maintaining sufficient gain. These circuits can also help avoid load effects at the input node that may be caused, for example, by coupling a negative feedback transistor to the input. Thus, the circuits considered herein help optimize the function of transconductance circuits by enabling bandwidth and gain manipulation while providing an excellent gain-bandwidth product.

[0063] In one example, bias and isolation circuits help a negative feedback transistor smoothly transition between the linear and saturation regions of operation based on the differential input signal. When the inputs are substantially equal, these circuits maintain the negative feedback transistor in the linear region, which acts as a low-impedance path and allows for high transconductance and high bandwidth. When the inputs are unequal, the circuits cause one of the negative feedback transistors to enter the saturation region, effectively making it a current source that holds off the differential voltage across its drain-gate junction. This allows the input stage to withstand large differential input voltages without the risk of exceeding the transistor's voltage rating.

[0064] By decoupling the input signal from the direct control of the negative feedback transistor, the bias and isolation circuits help reduce the capacitive load effect at the input, thereby providing a superior gain-bandwidth product compared to other solutions.

[0065] In summary, bias and isolation circuits provide the following dual function: they help optimize the Vgs characteristics of the negative feedback transistor while isolating its control from the input signal, thereby helping to maximize the gain and bandwidth performance of the transconductance circuit or input stage. This, combined with the inherent voltage handling advantages of LDMOS devices, results in a transconductance circuit with improved CM and DM voltage tolerance and improved gain-bandwidth product, making the gain stage circuit highly suitable for applications requiring robust performance across a wide range of operating conditions.

[0066] Figure 9 illustrates an example of the first method 900, which generally involves operating an input stage having improved gain and bandwidth characteristics. In one example, the input stage may include, among other things, a portion of a comparator circuit, such as one used in a pin driver or other automated test equipment (ATE).

[0067] In operation 902, the first method 900 includes receiving the first input stage input signal and the second input stage input signal at the first input node and the second input node of each of the first and second input transistors. In one example, the input transistors comprise each LDMOS device arranged as a differential pair.

[0068] In operation 904, the first method 900 includes using a first bias circuit to provide a first bias signal to the gate terminal of a first negative feedback transistor and the source terminal of a first input transistor. In operation 906, the first method 900 includes using a second bias circuit to provide a second bias signal to the gate terminal of a second negative feedback transistor and the source terminal of a second input transistor. In one example, the first and second negative feedback transistors comprise respective LDMOS devices arranged in series. In one example, each bias circuit comprises a current mirror coupled between one of the input transistors and its corresponding negative feedback transistor. The bias circuit may further comprise each cascode transistor coupled to the output of the current mirror and the output of the corresponding input transistor (e.g., the drain terminal). In one example, the first method 900 may include receiving a first input stage input signal and a second input stage input signal at the gate terminal of the cascode transistor. In various examples, the gate terminal of the negative feedback transistor may be driven by a signal at the input node or output node of the current mirror.

[0069] In one example, in addition to or alternative to using the first and second bias circuits, one or more isolation circuits may be provided to help isolate the control of the negative feedback transistor from the input transistor. These isolation circuits may include, for example, a voltage source configured to drive the negative feedback transistor.

[0070] In operation 908, the first method 900 includes adjusting the impedance characteristics of a signal path coupling a first input transistor and a second input transistor in response to receiving a first bias signal and a second bias signal at a first negative feedback transistor and a second negative feedback transistor. In one example, the signal path includes a first negative feedback transistor and a second negative feedback transistor arranged in series. When the first bias signal and the second bias signal exceed a threshold voltage value, the signal path coupling the first input transistor and the second input transistor has lower impedance characteristics, and when at least one of the first bias signal and the second bias signal does not exceed a threshold voltage value, the signal path coupling the first input transistor and the second input transistor has higher impedance characteristics.

[0071] In operation 910, the first method 900 includes providing a first output signal of the input stage using a first output terminal of a first input transistor and providing a second output signal of the input stage using a second output terminal of a second input transistor.

[0072] Various embodiments of transconductance circuits having negative feedback transistors as described herein can be implemented in any type of system in which voltage-to-current conversion may be used. An example of such a system is shown in Figure 2, in which the transconductance circuit includes part of an amplification stage and may further include a load as illustrated in any of Figures 3 to 8. Optionally, one or more other gain stages may follow the transconductance circuit. In some embodiments, the transconductance circuit may include part of a comparator or amplifier.

[0073] In some examples, transconductance circuits may be included in wireless systems, such as RF transmitters in cellular wireless communication systems. In yet other examples, transconductance circuits may be used in variable gain amplifiers, continuous-time filters, delta-sigma modulators, or data converters.

[0074] Furthermore, various embodiments of transconductance circuits having negative feedback transistors can be implemented in various electronic devices. Examples of electronic devices include, but are not limited to, electronic products, components of electronic products such as integrated circuits, and automotive electronic equipment such as automotive electronics. Moreover, the electronic device may include an unfinished product or other intermediate product.

[0075] Various aspects of this disclosure, as described in the following embodiments, can help provide solutions to the amplifier input stage gain and bandwidth-related problems identified herein.

[0076] Embodiment 1 is an input stage circuit comprising: a first input transistor configured to receive a first portion of a differential input signal at its first gate terminal and to provide a first portion of an output signal at its first drain terminal; a second input transistor configured to receive a second portion of a differential input signal at its second gate terminal and to provide a second portion of an output signal at its second drain terminal; and a negative feedback stage circuit including a bias generator circuit, a first negative feedback transistor, and a second negative feedback transistor, wherein the first negative feedback transistor and the second negative feedback transistor are coupled in series, and the bias generator circuit is configured to provide a first bias signal and a second bias signal to the gate terminals of the first negative feedback transistor and the second negative feedback transistor, respectively, in order to control the impedance of the signal path coupling the source terminals of the first input transistor and the second input transistor.

[0077] In Embodiment 2, the subject matter of Embodiment 1 is optionally configured such that the bias generator circuit provides a first bias signal at the source terminal of a first input transistor and a second bias signal at the source terminal of a second input transistor.

[0078] In Example 3, the subject matter of either Example 1 or 2 is included in which the drain terminals of the first negative feedback transistor and the second negative feedback transistor are coupled at an intermediate node.

[0079] In Embodiment 4, any one of the themes from Embodiments 1 to 3 is optionally configured such that the bias generator circuit includes a first current mirror coupled to a first input transistor, a first negative feedback transistor, and a first cascode transistor, and the bias generator circuit includes a second current mirror coupled to a second input transistor, a second negative feedback transistor, and a second cascode transistor, wherein the first cascode transistor and the second cascode transistor are coupled to the first drain terminal and the second drain terminal of the first input transistor and the second input transistor, respectively.

[0080] In Example 5, the subject of Example 4 is optionally extended to include the first and second negative feedback transistors operating within the linear region to provide a low-impedance signal path in the negative feedback stage circuit when the first and second portions of the differential input signal are substantially equal in magnitude.

[0081] In Example 6, the subject matter of either Example 4 or 5 is optionally configured such that, when the first and second portions of the differential input signal are substantially not equal in magnitude, the first negative feedback transistor operates in the saturation region and the second negative feedback transistor operates in the linear region to provide a high-impedance signal path in the negative feedback stage circuit.

[0082] In Example 7, any one of the themes from Examples 1 to 6 optionally includes a first tail current source coupled to the drain terminal of a first negative feedback transistor and a second tail current source coupled to the drain terminal of a second negative feedback transistor.

[0083] In Example 8, the subject matter of Example 7 is optionally configured such that the tail current signals from the first tail current source and the second tail current source maintain the operation of the first input transistor and the second input transistor within their respective saturation regions.

[0084] Embodiment 9 is a system comprising: a first part, which is a transconductance circuit and includes a first negative feedback transistor and a first input transistor configured to receive a first portion of a differential input signal at a first input node and, in response thereto, provide a first output current at a first output node, wherein the first input transistor is coupled to the gate terminal of the first negative feedback transistor and a first bias circuit configured to provide a first bias signal at the gate terminal of the first negative feedback transistor; and a second part, which is a transconductance circuit and includes a second negative feedback transistor coupled to the first negative feedback transistor and a second input transistor configured to receive a second portion of a differential input signal at a second input node and, in response thereto, provide a second output current at a second output node, wherein the second input transistor is coupled to the gate terminal of the second negative feedback transistor and a second bias circuit configured to provide a second bias signal at the gate terminal of the second negative feedback transistor.

[0085] In Example 10, the subject of Example 9 optionally includes a voltage source configured such that the first bias circuit provides a first bias signal at the gate terminal of the first negative feedback transistor and the source terminal of the first input transistor.

[0086] In Example 11, the subject of Example 10 optionally includes a first bias circuit which is coupled between a voltage source and the source terminal of a first negative feedback transistor, or a diode-connected transistor.

[0087] In Example 12, the subject matter of either Example 9 or 11 optionally includes the fact that the drain terminals of the first negative feedback transistor and the second negative feedback transistor are coupled at an intermediate node.

[0088] In Example 13, any one of the themes from Examples 9 to 12 is optionally used, and the first bias circuit includes a current mirror coupled between the gate and source terminals of the first negative feedback transistor.

[0089] In Example 14, the subject of Example 13 is optionally coupled to the source terminal of the first input transistor and the gate terminal of the first negative feedback transistor.

[0090] In Example 15, the subject matter of either Example 13 or 14 optionally includes the first input transistor and the second input transistor, as well as the first negative feedback transistor and the second negative feedback transistor, comprising high-voltage LDMOS transistors, and the transistor comprising the current mirror of the first bias circuit comprising a low-voltage MOS transistor.

[0091] In Example 16, any one of the themes from Examples 13 to 15 optionally includes a first cascode transistor coupled between a first output node and a first bias circuit.

[0092] Embodiment 17 is a method for controlling the gain characteristics and bandwidth characteristics of an input stage circuit, the method comprising: receiving a first input stage input signal and a second input stage input signal at the first input node and the second input node of the respective first input transistor and the respective second input transistor; using a first bias circuit to provide a first bias signal to the gate terminal of a first negative feedback transistor and the source terminal of a first input transistor; using a second bias circuit to provide a second bias signal to the gate terminal of a second negative feedback transistor and the source terminal of a second input transistor; adjusting the impedance characteristics of a signal path coupling the first input transistor and the second input transistor in response to the reception of the first bias signal and the second bias signal at the first negative feedback transistor and the second negative feedback transistor; providing a first input stage output signal using a first output terminal of the first input transistor; and providing a second input stage output signal using a second output terminal of the second input transistor.

[0093] In Example 18, the subject of Example 17 is optionally extended to include receiving a first input stage input signal and a second input stage input signal at each of the first and second cascode transistors, wherein the first cascode transistor is coupled between a first output terminal and a first bias circuit, and the second cascode transistor is coupled between a second output terminal and a second bias circuit.

[0094] In Example 19, the subject matter of either Example 17 or 18 optionally includes the fact that when the first bias signal and the second bias signal exceed a threshold voltage value, the signal path coupling the first input transistor and the second input transistor has lower impedance characteristics, and when at least one of the first bias signal and the second bias signal does not exceed a threshold voltage value, the signal path coupling the first input transistor and the second input transistor has higher impedance characteristics.

[0095] In Example 20, any one of the themes from Examples 17 to 19 optionally includes receiving the first input stage input signal and the second input stage input signal at the respective first input transistor and second input transistor, or receiving the first input stage input signal and the second input stage input signal at the respective gate terminals of the respective LDMOS devices.

[0096] Example 21 is an apparatus equipped with any of the implementation means of Examples 1 to 20.

[0097] Example 22 is an implementation system of any of Examples 1 to 20.

[0098] Example 23 is an implementation method of any of Examples 1 to 20.

[0099] Each of these non-limiting embodiments may stand alone, be combined in various substitutions, or be combined with one or more of the other embodiments or features discussed elsewhere in this specification.

[0100] This detailed description includes references to accompanying drawings that form part of the detailed description. The drawings illustrate specific embodiments in which the present invention may be carried out. These embodiments are also referred to herein as “examples.” Such examples may include elements in addition to those illustrated or described. However, the inventors also intend examples in which only the illustrated or described elements are provided. The inventors intend examples in which any combination or substitution of those illustrated or described elements (or one or more embodiments thereof) is used, either with respect to a particular example (or one or more embodiments thereof) or with respect to other examples (or one or more embodiments thereof) illustrated or described herein.

[0101] In this document, the terms "a" or "an" are used to include one or more, independently of other instances or uses of "at least one" or "one or more," as is common in patent documents. In this document, the term "or" is used to refer to non-exclusive "or" such that "A or B" includes "A but not B," "B but not A," and "A and B." In this document, the terms "including" and "in which" are used as plain English synonyms for the terms "equipped with" and "therefore."

[0102] In the following claims, the terms “includes” and “equipment” are open-ended; that is, any system, device, article, composition, formulation, or process containing elements other than those enumerated after such terms in the claim is still considered to be within the scope of that claim. Furthermore, in the following claims, “first,” “second,” and “third,” etc., are used merely as symbols and are not intended to impose numerical requirements on their subjects.

[0103] Examples of methods described herein can be implemented at least partially by machine or computer. Some examples may include computer-readable or machine-readable media encoded with instructions that can be used to configure an electronic device to perform a method or circuit operation or circuit configuration instruction, as described in the examples above. Implementations of such methods may include microcode, assembly language code, high-level language code, etc. Such code may include computer-readable instructions for performing various methods. The code may form part of a computer program product. Furthermore, in one example, the code may be tangibly stored on one or more volatile, non-temporary, or non-volatile tangible computer-readable media during execution or at other times. Examples of these tangible computer-readable media include, but are not limited to, hard disks, removable magnetic disks, removable optical disks (e.g., compact disks and digital video disks), magnetic cassettes, memory cards or sticks, random access memory (RAM), read-only memory (ROM), etc.

[0104] The above description is illustrative and not limiting. For example, the above examples (or one or more of them) may be used in combination with each other. Other embodiments may be used by those skilled in the art, for example, by reviewing the above description. The abstract is provided to enable the reader to quickly confirm the nature of the technical disclosure. It is presented with the understanding that it is not to be used to interpret or limit the scope or meaning of the claims. Also, in the forms for carrying out the above invention, various features may be grouped together to simplify the disclosure. This should not be interpreted as meaning that any disclosed features not claimed are essential to any claim. Rather, the subject matter of the invention may lie in less than all of the features of a particular disclosed embodiment. Accordingly, the following claims are incorporated herein as examples or embodiments in forms for carrying out the invention, and each claim stands alone as a separate embodiment, and it is intended that such embodiments may be combined with each other in various combinations or substitutions. The scope of the present invention should be determined by reference to the appended claims, along with the entire scope of equivalents to which such claims are granted.

Claims

1. An input stage circuit, A first input transistor, configured to receive a first portion of a differential input signal at its first gate terminal and to provide a first portion of an output signal at its first drain terminal, A second input transistor, configured to receive a second portion of a differential input signal at its second gate terminal and to provide a second portion of the output signal at its second drain terminal, An input stage circuit comprising a bias generator circuit, a first negative feedback transistor, and a second negative feedback transistor, wherein the first negative feedback transistor and the second negative feedback transistor are coupled in series, and the bias generator circuit is configured to control the impedance of the signal path coupling the source terminals of the first input transistor and the second negative feedback transistor by providing a first bias signal and a second bias signal using a first current mirror coupled to the source terminal of the first input transistor and the gate terminal of the first negative feedback transistor, and a second current mirror coupled to the source terminal of the second input transistor and the gate terminal of the second negative feedback transistor.

2. The input stage circuit according to claim 1, wherein the bias generator circuit is configured to provide the first bias signal at the source terminal of the first input transistor and the second bias signal at the source terminal of the second input transistor.

3. The input stage circuit according to claim 1, wherein the drain terminals of the first negative feedback transistor and the second negative feedback transistor are coupled to each other.

4. The first current mirror is further coupled to the first cascode transistor. The second current mirror is further coupled to the second cascode transistor. The input stage circuit according to claim 1, wherein the first cascode transistor and the second cascode transistor are coupled to the first drain terminal and the second drain terminal of the first input transistor and the second input transistor, respectively.

5. The input stage circuit according to claim 4, wherein when the first and second portions of the differential input signal are substantially equal in magnitude, the first negative feedback transistor and the second negative feedback transistor operate within the linear region to provide a low impedance signal path in the negative feedback stage circuit.

6. The input stage circuit according to claim 4, wherein when the first and second portions of the differential input signal are not substantially equal in magnitude, the first negative feedback transistor operates in the saturation region and the second negative feedback transistor operates in the linear region to provide a high-impedance signal path in the negative feedback stage circuit.

7. The input stage circuit according to claim 1, comprising a first tail current source coupled to the drain terminal of the first negative feedback transistor, and a second tail current source coupled to the drain terminal of the second negative feedback transistor.

8. The input stage circuit according to claim 7, wherein the first tail current source and the second tail current source are configured to provide tail current signals necessary for the first input transistor and the second input transistor to operate within their respective saturation regions.

9. It is a system, The first part of the transconductance circuit, The first negative feedback transistor, A first input transistor configured to receive a first portion of a differential input signal at a first input node and, in response, provide a first output current at a first output node, wherein the source terminal of the first input transistor is coupled to the gate terminal of the first negative feedback transistor, A first bias circuit configured to provide a first bias signal at the gate terminal of the first negative feedback transistor, the first bias circuit comprising a first current mirror coupled between the gate terminal and the source terminal of the first negative feedback transistor, is included as a first part, The second part of the transconductance circuit, A second negative feedback transistor coupled to the first negative feedback transistor, A second input transistor configured to receive a second portion of the differential input signal at a second input node and, in response, provide a second output current at a second output node, wherein the source terminal of the second input transistor is coupled to the gate terminal of the second negative feedback transistor, A system comprising: a second part, which includes a second bias circuit configured to provide a second bias signal at the gate terminal of the second negative feedback transistor, wherein the second bias circuit comprises a second current mirror coupled between the gate terminal and the source terminal of the second negative feedback transistor.

10. The system according to claim 9, wherein the first bias circuit comprises a voltage source configured to provide the first bias signal at the gate terminal of the first negative feedback transistor and the source terminal of the first input transistor.

11. A system, The first part of the transconductance circuit, The first negative feedback transistor, A first input transistor configured to receive a first portion of a differential input signal at a first input node and, in response, provide a first output current at a first output node, wherein the source terminal of the first input transistor is coupled to the gate terminal of the first negative feedback transistor, A first bias circuit configured to provide a first bias signal at the gate terminal of the first negative feedback transistor, the first bias circuit comprising: a voltage source configured to provide the first bias signal at the gate terminal of the first negative feedback transistor and the source terminal of the first input transistor; and a diode or diode-connected transistor coupled between the voltage source and the source terminal of the first negative feedback transistor, the first part of the first bias circuit, The second part of the transconductance circuit, A second negative feedback transistor coupled to the first negative feedback transistor, A second input transistor configured to receive a second portion of the differential input signal at a second input node and, in response, provide a second output current at a second output node, wherein the source terminal of the second input transistor is coupled to the gate terminal of the second negative feedback transistor, A system comprising: a second part including: a second bias circuit configured to provide a second bias signal at the gate terminal of the second negative feedback transistor.

12. The system according to claim 9 or 11, wherein the drain terminals of the first negative feedback transistor and the second negative feedback transistor are coupled to each other.

13. The system according to claim 9, wherein the first input transistor and the second input transistor, and the first negative feedback transistor and the second negative feedback transistor each comprise a high-voltage LDMOS transistor, and the transistor comprising the first current mirror of the first bias circuit comprises a low-voltage MOS transistor.

14. The system according to claim 9, comprising a first cascode transistor coupled between the first output node and the first bias circuit.

15. A method for controlling the gain characteristics and bandwidth characteristics of an input stage circuit, wherein the method is The first input stage input signal and the second input stage input signal are received at the first input node and the second input node of the respective first input transistor and second input transistor, respectively. A first bias circuit is used to provide a first bias signal to the gate terminal of a first negative feedback transistor and the source terminal of a first input transistor, wherein the first bias circuit comprises a first current mirror coupled to the source terminal of the first input transistor and the gate terminal of the first negative feedback transistor. A second bias circuit is used to provide a second bias signal to the gate terminal of a second negative feedback transistor and the source terminal of the second input transistor, wherein the second bias circuit comprises a second current mirror coupled to the source terminal of the second input transistor and the gate terminal of the second negative feedback transistor. In response to receiving the first bias signal and the second bias signal in the first negative feedback transistor and the second negative feedback transistor, the impedance characteristics of the signal path coupling the first input transistor and the second input transistor are adjusted, The first output terminal of the first input transistor is used to provide the first input stage output signal, A method comprising providing a second input stage output signal using the second output terminal of the second input transistor.

16. The method according to claim 15, comprising receiving the first input stage input signal and the second input stage input signal at each of the first cascode transistor and the second cascode transistor, wherein the first cascode transistor is coupled between the first output terminal and the first bias circuit, and the second cascode transistor is coupled between the second output terminal and the second bias circuit.

17. The method according to claim 15, wherein when the first bias signal and the second bias signal exceed a threshold voltage value, the signal path coupling the first input transistor and the second input transistor has lower impedance characteristics, and when at least one of the first bias signal and the second bias signal does not exceed the threshold voltage value, the signal path coupling the first input transistor and the second input transistor has higher impedance characteristics.

18. The method according to claim 15, wherein receiving the first input stage input signal and the second input stage input signal at the respective first input transistor and second input transistor includes receiving the first input stage input signal and the second input stage input signal at the respective gate terminals of the respective LDMOS devices.

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