Chip-on-submount structure

Abstract

The present invention provides a chip-on-submount structure which is capable of suppressing strains that can be generated in a semiconductor laser chip. This chip-on-submount structure (1) is provided with: a chip (10) which comprises a current injection stripe (161) that injects an electric current into an active layer (13); a strain suppression layer (20) which is formed of a metal and covers the current injection stripe (161); a submount (40) which comprises an electrode layer (electrode pattern 42); and a solder layer (30) which is interposed between the strain suppression layer (20) and the electrode layer (electrode pattern 42). The thickness of an unreacted layer (201), in which a component of the solder layer (30) is not diffused, in the strain suppression layer (20) is 1.4 µm or more.

Description

[Technical Field]

[0001] The present invention relates to a chip-on-submount structure in which a semiconductor laser chip is mounted on a submount. [Background Art]

[0002] High-power semiconductor laser chips with an output exceeding 10 W are known (see, for example, FIG. 9 in Patent Document 1). Such semiconductor lasers achieve higher output by expanding the width of a current injection stripe, which is an electrode for injecting current into an active layer. Such chips achieve higher output by expanding the width of a current injection stripe for injecting current into an active layer. [Prior Art Documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Unexamined Patent Publication No. 9-36493 [Summary of the Invention] [Problems to be Solved by the Invention]

[0004] Furthermore, when manufacturing semiconductor laser chips, it is important to suppress manufacturing costs. One of the methods for suppressing chip manufacturing costs is to reduce the size of the chip. However, it is undesirable to avoid a reduction in output accompanying the downsizing of the chip. Therefore, for downsizing a chip, reducing the width of the chip, rather than shortening the length of the chip that is determined depending on the length of the current injection stripe, is a practical option. However, the narrower the chip width is, the higher the difficulty in manufacturing the chip-on-submount structure becomes.

[0005] In a chip-on-submount structure, an electrode layer is formed on one of the main surfaces of the submount. The chip is positioned so that the current injection stripe is in close proximity to the aforementioned electrode layer. The current injection stripe and the electrode layer are then joined together using solder in a electrically conductive manner.

[0006] During the process of bonding this chip to the submount, distortion may occur in the chip. Furthermore, distortion may also occur in the chip when the semiconductor laser is driven after manufacturing. These distortions are more likely to occur as the chip width narrows. This distortion in the chip destabilizes the emission shape of the laser beam emitted from the semiconductor laser. In other words, the narrower the chip width, the more unstable the emission shape of the laser beam emitted from the semiconductor laser becomes.

[0007] A chip-on-submount structure according to one aspect of the present invention has been made in view of the above-mentioned problems, and its objective is to provide a chip-on-submount structure that can suppress distortion that may occur in the chip. [Means for solving the problem]

[0008] To solve the above problems, a chip-on-submount structure according to one aspect of the present invention comprises a broad-area type chip including an active layer and a current injection stripe for injecting current into the active layer; a submount including a metallic strain-suppressing layer covering the current injection stripe, a substrate, and an electrode layer provided on one main surface of the substrate; and a solder layer interposed between the strain-suppressing layer and the electrode layer to join the chip and the submount. In this chip-on-submount structure, the strain-suppressing layer consists of a reaction layer in which the components of the solder layer are diffused and an unreacted layer in which the components of the solder layer are not diffused, and the thickness of the unreacted layer is 1.4 μm or more. [Effects of the Invention]

[0009] According to one aspect of the present invention, a chip-on-submount structure is provided that can suppress distortion that may occur in the chip of a semiconductor laser. [Brief explanation of the drawing]

[0010] [Figure 1] This is a perspective view of a chip-on-submount structure according to one embodiment of the present invention. [Figure 2] Figure 1 is a cross-sectional view of the chip-on-submount structure shown. [Figure 3] (a) is a plan view of the chip provided in the chip-on-submount structure shown in Figure 1, as seen from the current injection stripe side. (b) is a plan view of a modified example of the chip shown in (a), as seen from the current injection stripe side. [Figure 4] (a) to (f) are cross-sectional views showing a manufacturing method for a first specific example of the chip shown in Figure 2. [Figure 5] This is a plan view showing multiple chips manufactured using the manufacturing method shown in Figure 4. [Figure 6] (a) to (c) are cross-sectional views showing a manufacturing method for a second specific example of the chip shown in Figure 2. [Figure 7] (a) is a plan view of a chip manufactured using the manufacturing method shown in Figure 6, as seen from the current injection stripe side. (b) is a plan view of a modified example of the chip shown in (a), as seen from the current injection stripe side. [Modes for carrying out the invention]

[0011] [Configuration of chip-on-submount structure] A chip-on-submount structure 1 according to an embodiment of the present invention will be described with reference to FIGS. 1 to 3. FIG. 1 is a perspective view of the chip-on-submount structure 1. FIG. 2 is a cross-sectional view of the chip-on-submount structure 1. The cross-sectional view of FIG. 2 is a cross-sectional view taken along the A-A' cross-section that passes through the A-A' line shown in FIG. 1 and is orthogonal to the main surface of the substrate 11. FIG. 3(a) is a plan view of the chip 10 included in the chip-on-submount structure 1 when viewed in plan from the current injection stripe 161 side. FIG. 3(b) is a plan view of a chip 10A, which is a modification of the chip 10, when viewed in plan from the current injection stripe 161A side. Note that each of the chip 10 and the chip 10A is an example of a semiconductor laser chip.

[0012] Note that, in the chip-on-submount structure 1 shown in FIGS. 1 to 3, the chip-on-submount structure 1 according to an embodiment of the present invention will be described using the chip 10 with a simplified structure. A more specific structure of the chip will be described later with reference to FIGS. 4 and 6.

[0013] As shown in FIGS. 1 and 2, the chip-on-submount structure 1 includes a chip 10, a strain suppression layer 20, a solder layer 30, and a submount 40.

[0014] <Submount> The submount 40 is a base material for mounting the chip 10 on one main surface thereof. As shown in FIGS. 1 and 2, the submount 40 includes a substrate 41 and electrode patterns 42 and 43. The electrode pattern 42 is an example of an electrode layer of the submount 40.

[0015] The substrate 41 is a plate-shaped member having a pair of flat main surfaces. The substrate 41 is made of a high thermal conductivity material. In the present embodiment, as the high thermal conductivity material forming the substrate 41, ceramics having low conductivity (preferably an insulator) and high thermal conductivity is employed. However, the high thermal conductivity material forming the substrate 41 is not limited to materials with high conductivity, and can be appropriately selected according to the configuration of the chip 10, the desired thermal conductivity of the substrate 41, and the like. When the substrate 41 is made of a conductor, a configuration that insulates an electrode pattern 42 and an electrode pattern 43, which will be described later, may be employed. To insulate the electrode pattern 42 and the electrode pattern 43, an insulating layer may be provided respectively between the substrate 41 and the electrode pattern 42, and between the substrate 41 and the electrode pattern 43, or a configuration in which current flows in a direction perpendicular to the substrate may be used.

[0016] The electrode pattern 42 and the electrode pattern 43 are formed on one main surface of the substrate 41. Each of the electrode patterns 42 and 43 is formed of a thin film made of a conductive material. In the present embodiment, gold, which is a type of metal, is employed as the material forming each of the electrode patterns 42 and 43. However, the material forming each of the electrode patterns 42 and 43 can be appropriately selected from among conductive materials. It is preferable that the material forming each of the electrode patterns 42 and 43 has good conductivity. Examples of materials having good conductivity include gold, copper, silver, and aluminum. Further, each of the electrode patterns 42 and 43 may be a single-layer film made of these materials, or a multi-layer film in which each layer is made of these materials. Since the electrode patterns 42 and 43 are provided spaced apart from each other, they are insulated from each other.

[0017] <Chip> Chip 10, an example of a semiconductor laser chip, employs a length L (see Figure 3(a)) of 4 mm, which is the total length of the current injection stripe 161 described later. That is, the resonator length of chip 10 is 4 mm. Furthermore, chip 10 is a broad-area type chip in which the width W (see Figure 3(a)) of the current injection stripe 161 is 75 μm or more over its entire length. A broad-area type chip 10 with a length L of 4 mm can emit laser light with an output of 10 W or more. Note that the minimum width of the current injection stripe 161 is not limited to 75 μm, and similarly, the output of chip 10 is not limited to 10 W. Also, when referring to the output of the laser light in chip 10 in this embodiment, it means the maximum output of chip 10. In this embodiment, the length L and width W are 4 mm and 220 μm, respectively, and the output exceeds 20 W. In the chip-on-submount structure 1, if the heat generated in the chip 10 during operation is sufficiently dissipated, a 13W laser beam can be stably emitted for a width W of 100μm. In other words, when a width W of 220μm is used, by selecting a length L within the range of approximately 4mm to 6mm, a laser beam with an output of approximately 25W to 28W can be stably emitted.

[0018] As shown in Figures 1 and 2, the chip 10 comprises a substrate 11, an n-type layer 12, an active layer 13, a p-type layer 14, a block layer 15, an electrode layer 16, and an electrode layer 17.

[0019] (substrate) The substrate 11 is a semiconductor plate-shaped member having a pair of flat main surfaces 111 and 112. In this embodiment, the substrate 11 is made of GaAs. However, the material constituting the substrate 11 can be selected as appropriate.

[0020] An electrode layer 17 is formed on one of the main surfaces of the substrate 11, which is the upper surface 111 in Figure 2. The electrode layer 17 is a thin metallic film formed to cover the main surface 111. In this embodiment, a three-layer film of Ni / Ge / Au is used as the electrode layer 17. However, the electrode layer 17 is not limited to this.

[0021] On the other main surface of the substrate 11, the main surface 112 located on the lower side in Figure 2, an n-type layer 12, an active layer 13, a p-type layer 14, and an electrode layer 16 are stacked in this order. A block layer 15 is embedded in the inner layer of the p-type layer 14.

[0022] (n-type layer) The n-type layer 12 is composed of an n-type semiconductor. An example of an n-type semiconductor that constitutes the n-type layer 12 is a GaAs-based semiconductor (e.g., AlGaAs). The n-type layer 12 may also be a multilayer structure in which each layer is made up of a different type of n-type semiconductor. In this case, each layer of the n-type layer 12 may be configured to have a different function, such as a layer that functions as a buffer layer, a layer that functions as a cladding layer, and a layer that functions as a guide layer.

[0023] (active layer) Examples of semiconductors constituting the active layer 13 include GaAs-based semiconductors (e.g., InGaAs). However, the material can be appropriately selected depending on the desired oscillation wavelength.

[0024] (p-type layer) The p-type layer 14 is composed of a p-type semiconductor. An example of a p-type semiconductor that constitutes the p-type layer 14 is a GaAs-based semiconductor (e.g., AlGaAs). The p-type layer 14 may also be a multilayer structure in which each layer is made up of a different type of p-type semiconductor. In this case, each layer of the active layer 13 may be configured to have different functions, such as a layer that functions as a guide layer, a layer that functions as a cladding layer, and a layer that functions as a contact layer.

[0025] An electrode layer 16 is formed on the main surface of the p-type layer 14 that is opposite to the active layer 13 (the lower main surface in Figure 2). The electrode layer 16 is a thin metallic film formed to cover the main surface of the p-type layer 14 that is opposite to the active layer 13. In this embodiment, a Ti / Au two-layer film is used as the electrode layer 16. However, the electrode layer 16 is not limited to this.

[0026] (electrode layer) Electrode layer 16 and electrode layer 17 function as an electrode pair that conducts current into the active layer 13. In the following, when the main surface of electrode layer 16 is viewed in plan, the region into which current is injected into the active layer 13 will be referred to as the current injection stripe 161.

[0027] (Block layer) As shown in Figure 2, the block layer 15 is provided to limit the region in which current can be injected from the electrode layer 16 to the active layer 13. The block layer 15 is embedded in the inner layer of the p-type layer 14 so as to separate the electrode layer 16 and the active layer 13. The block layer 15 is made of an n-type semiconductor with lower conductivity than the p-type semiconductor that makes up the p-type layer 14. An example of the material that makes up the block layer 15 is n-type GaAs. An opening 151 is formed in the block layer 15 to limit the region in which the current injected from the electrode layer 16 flows (see Figure 2). In this embodiment, when the main surface of the block layer 15 is viewed from above, the shape of the opening 151 is rectangular (see Figure 3(a)). However, the shape of the opening 151 is not limited to a rectangle, and may be, for example, a shape like the opening 151A shown in Figure 3(b). The opening 151A will be described later. Furthermore, when viewing the main surface of the electrode layer 16 from a plan view, the region overlapping with the opening 151 and into which current is injected into the active layer 13 is the current injection stripe 161. In other words, the current injection stripe 161 also includes the region of the p-type layer 14 interposed between the electrode layer 16 and the active layer 13 that overlaps with the opening 151.

[0028] Thus, in the chip 10, an opening 151 is formed in the block layer 15. Therefore, the region of the block layer 15 that corresponds to the opening 151, on the main surface opposite the active layer 13 (the lower main surface in Figure 2), is recessed compared to the region of the block layer 15 where no opening is formed (see Figure 2). Consequently, the surface of the current injection stripe 161, which overlaps with the opening 151 in a plan view, is recessed compared to the surface of the electrode layer 16 that does not overlap with the opening 151 in a plan view (see Figure 2). The surface of the electrode layer 16 that does not overlap with the opening 151 in a plan view is the outermost surface of the chip 10, and is the outermost surface on the side where the strain suppression layer 20 is provided.

[0029] (reflective film) In the chip 10, a pair of reflective films are formed on each of the pair of end faces that constitute the resonator. Of the pair of end faces of the resonator shown in Figure 1, a low-reflectivity film 18 is formed on one end face (the end face located on the left in Figure 1), and a high-reflectivity film 19 is formed on the other end face (the end face located on the right in Figure 1). That is, the distance between the low-reflectivity film 18 and the high-reflectivity film 19 is equal to the resonator length of the chip 10. Furthermore, the reflectivity of the low-reflectivity film 18 for light of the oscillation wavelength is lower than the reflectivity of the high-reflectivity film for the same light.

[0030] The reflectivity of the high-reflectivity and low-reflectivity films can be appropriately set according to the design of the chip 10. The configurations of the high-reflectivity and low-reflectivity films can be appropriately selected from existing configurations. For example, as a low-reflectivity film with relatively low reflectivity, a single layer film of Al2O3, AlN, Si, SiO2, or TiO2, or a multilayer film made of these materials can be used. As a high-reflectivity film with relatively high reflectivity, a multilayer film obtained by repeatedly stacking two layers made of these materials can be used.

[0031] <Strain suppression layer and solder layer> As shown in Figure 2, the strain suppression layer 20 is a metallic film formed on the main surface of the electrode layer 16 that is opposite to the active layer 13 (the lower main surface in Figure 2). The strain suppression layer 20 covers the current injection stripe 161 and the region surrounding the current injection stripe 161 of the electrode layer 16.

[0032] Furthermore, the solder layer 30 is a metallic layer interposed between the strain suppression layer 20 and the electrode pattern 42.

[0033] In this embodiment, gold is used as the material constituting the strain-suppressing layer 20. However, the material constituting the strain-suppressing layer 20 can be appropriately selected from among metals that have good conductivity and are relatively soft. Examples of materials that have good conductivity and are relatively soft include gold, copper, silver, and aluminum. Alternatively, the material constituting the strain-suppressing layer 20 may be an alloy in which gold, copper, silver, or aluminum is the main component. In this embodiment, the main component refers to the component having the highest composition ratio in the alloy constituting the strain-suppressing layer 20.

[0034] In this embodiment, the strain-suppressing layer 20 is formed using a plating method. However, the method for forming the strain-suppressing layer 20 is not limited to plating. The method for forming the strain-suppressing layer 20 can be appropriately selected from among methods capable of forming a film of a desired thickness (e.g., 2 μm or 3 μm). Another method for forming the strain-suppressing layer 20 is, for example, sputtering.

[0035] The materials constituting the solder before forming the solder layer 30 are not particularly limited. The materials constituting the solder can be appropriately selected according to the desired properties.

[0036] The chip 10 is joined to the submount 40 by bonding the strain suppression layer 20 and the electrode pattern 42 via the solder layer 30.

[0037] In the process of joining the chip 10 to the submount 40 using this solder, the solder melts and then solidifies again to form a solder layer 30, thereby joining the strain suppression layer 20 and the electrode pattern 42. When this solder transforms into the solder layer 30, the components of the solder layer 30 diffuse into the interior of the strain suppression layer 20. Therefore, near the interface between the strain suppression layer 20 and the solder layer 30, an alloy is formed between the material constituting the strain suppression layer 20 (gold in this embodiment) and the components of the solder layer 30.

[0038] In the following, the layer of the strain suppression layer 20 in which the components of the solder layer 30 have diffused will be called the reaction layer 202, and the layer in which the components of the solder layer 30 have not diffused will be called the unreacted layer 201. Furthermore, the thicknesses of the unreacted layer 201 and the reaction layer 202 in the region overlapping with the current injection stripe 161 when viewed from above will be called thickness t1 and thickness t2, respectively. In the chip 10, the thickness of the strain suppression layer 20 (sum of thickness t1 and thickness t2) is determined such that the thickness t1 is 1.4 μm or more when the strain suppression layer 20 and the electrode pattern 42 are joined via the solder layer 30. It is preferable that the thickness t1 is 2.0 μm or more.

[0039] The materials that make up the strain suppression layer 20, such as gold, copper, silver, and aluminum, are known to be relatively soft among metals. Because the strain suppression layer 20 is made of soft materials, it is possible to mitigate the strain that may occur when joining the chip 10 to the submount 40 using the solder layer 30. As a result, the effects of strain caused by joining can be reduced on the chip 10. However, materials such as gold, copper, silver, and aluminum may harden when they react with solder. In such cases, it is important for the unreacted layer 201, which has not reacted with the solder, to be interposed between the electrode layer 16 and the reaction layer 202 with sufficient thickness in order to suppress strain. The inventors of the present invention investigated the thickness of the unreacted layer 201 in chips 10 that were sampled from a group of chips 10 that were considered to have statistically no failures caused by strain during joining. As a result, the thickness of the unreacted layer 201 in chips 10 that were considered to have no failures caused by strain was found to be an average of 2030 nm, with a standard deviation σ of 207 nm. Considering the various variations in the process, it is estimated that in this group, there was a probabilistically present unreacted layer 201 thicker than 3σ, i.e., an unreacted layer 201 with a thickness of 1.4 μm or more. Therefore, if there is an unreacted layer 201 of at least 1.4 μm, the stress generated by the reaction between plating and solder can be relieved in the strain suppression layer 20.

[0040] <Symmetry of current-injected stripes> As shown in Figure 1, the chip-on-submount structure 1 consists of a columnar chip 10 and a submount 40 joined together via a strain suppression layer 20 and a solder layer 30. A low-reflection film 18 and a high-reflection film 19 are formed on each of the pair of end faces of the columnar chip 10, respectively. Furthermore, an electrode layer 16 and an electrode layer 17 are formed on each of the pair of side surfaces of the columnar chip 10, respectively (see Figure 2). The electrode layer 16 is connected to an electrode pattern 42 via the strain suppression layer 20 and the solder layer 30.

[0041] When the chip-on-submount structure 1 configured in this manner is viewed from above in the direction normal to the main surface of the active layer 13 (the same as the direction normal to the main surface of the electrode layer 17 in Figure 1), the chip 10 has a strip-like shape (see Figure 3(a)). In this embodiment, the axis parallel to the longitudinal direction of the chip 10, which bisects the active layer 13 in the above-mentioned plan view, is called the central axis AC of the chip 10 (see Figures 2 and 3(a)). In the chip 10, the current injection stripe 161 is provided so as to overlap with the central axis AC in the above-mentioned plan view.

[0042] Furthermore, in the A-A' cross-section shown in Figure 2, the current injection stripe 161 is symmetrical with respect to the axis (B-B' line) that passes through the central axis AC and is perpendicular to the main surface of the active layer 13. Thus, in one embodiment of the present invention, it is preferable that the chip 10 including the current injection stripe 161 is symmetrical with respect to the above axis of symmetry. Similarly, it is preferable that the strain suppression layer 20 and the solder layer 30 are also symmetrical with respect to the above axis of symmetry. However, the submount 40 does not have to be symmetrical with respect to the above axis of symmetry. <Variations of the chip> Referring to Figure 3(b), a modified example of chip 10, chip 10A, will be described. Chip 10A is obtained by changing the shape of the opening 151 (see Figure 3(a)) provided in the block layer 15 of chip 10 to the shape of opening 151A (see Figure 3(b)). Except for the shape of opening 151A, chip 10A is the same as chip 10. In this modified example, the electrode layer 16 and the current injection stripe 161 in chip 10 are read as electrode layer 16A and current injection stripe 161A, respectively. That is, the current injection stripe 161A is the region that overlaps with opening 151A when the main surface of electrode layer 16A is viewed from above, and is the region into which current is injected into the active layer 13. The current injection stripe 161A also includes the region of the p-type layer 14 interposed between electrode layer 16A and active layer 13 that overlaps with opening 151A.

[0043] For the sake of clarity, components having the same function as those described in tip 10 will be denoted by the same reference numeral and their descriptions will not be repeated.

[0044] Each of the pair of end faces of the chip 10A has a low-reflection film 18 and a high-reflection film 19 formed on it, similar to the chip 10. The low-reflection film 18 and the high-reflection film 19 constitute a resonator.

[0045] In chip 10A, the current injection stripe 161A is composed of a first section 161A1 and a second section 161A2. In the following, the widths of the first section 161A1 and the second section 161A2 are denoted as width W1 and width W2, respectively. The first section 161A1 is a section in which width W1 is constant and is located on the side of the high-reflectivity film 19. The second section 161A2 is a section in which width W2 tapers as it moves away from the first section 161A1 and is located on the side of the low-reflectivity film 18. As can be seen from Figure 3(b), width W2 is maximum at the boundary between the first section 161A1 and the second section 161A2 and coincides with width W1. In this modified example, width W1 is set to 220 μm, the maximum value of width W2 is set to 220 μm, and the minimum value of width W2 is set to 180 μm. Another example of the minimum value of the width W2 is 150 μm. In this modified example, as shown in Figure 3(b), a trapezoid (more specifically, an isosceles trapezoid) is adopted as the shape of the second section 161A2.

[0046] In the following, the total length of the current injection stripe 161A will be referred to as length L, the length of the first section 161A1 will be referred to as length L1, and the length of the second section 161A2 will be referred to as length L2. In the chip 10A, length L is approximately equal to the length of the resonator.

[0047] In chip 10A, the length L is 4 mm, the length L1 is 3200 μm, and the length L2 is 800 μm. In this modified example, in the second section 161A2, where the length L2 is 800 μm, the width W2 narrows by 40 μm, from 220 μm to 180 μm. Therefore, the ratio of the area of ​​the second section 161A2 to the area of ​​the current injection stripe 161A is 18.5%, and the narrowing angle θ of the second section 161A2 when the current injection stripe 161 is viewed from above is 1.43°. Another parameter relating to the shape of the second section 161A2 can also be expressed as the ratio of the area of ​​the second section 161A2 to the area of ​​the current injection stripe 161 in chip 10 where the second section 161A2 is not provided (see Figure 3(a)). In the chip 10A described above, this ratio is 18.2%. Furthermore, another parameter relating to the shape of the second section 161A2 is to calculate the difference between the area of ​​the current injection stripe 161 and the area of ​​the current injection stripe 161A in the chip 10, and then use the ratio of this difference to the area of ​​the current injection stripe 161. This difference corresponds to the area of ​​the tapered portion, such that the width W2 of the second section 161A2 narrows as it moves away from the first section 161A1, assuming deformation from the current injection stripe 161 to the current injection stripe 161A. In chip 10A, the ratio of this difference to the area of ​​the current injection stripe 161 is 1.82%. In the following, the values ​​of the ratio and the tapering angle θ are shown with three significant figures. Here, the tapering angle θ is the angle between each leg of the trapezoidal (isosceles trapezoidal in this embodiment) second section 161A2 and the central axis AC. However, the minimum values ​​of length L, length L1, length L2, width W1, width W2, and the constriction angle θ are not limited to these values.

[0048] When a length L2 of 800 μm is adopted and a minimum width W2 of 150 μm is adopted, the ratio of the area of ​​the second section 161A2 to the area of ​​the current injection stripe 161A is 17.4%, the tapering angle θ of the second section 161A2 when the current injection stripe 161 is viewed from above is 2.51°, and the ratio of the area of ​​the second section 161A2 to the area of ​​the current injection stripe 161 in the chip 10 where the second section 161A2 is not provided (see Figure 3(a)) is 16.8%. Furthermore, the ratio of the difference between the area of ​​the current injection stripe 161 and the area of ​​the current injection stripe 161A in the chip 10 to the area of ​​the current injection stripe 161 is 3.18%.

[0049] Furthermore, the inventors of the present invention conducted simulations for the minimum values ​​of length L, length L1, length L2, width W1, width W2, and tapering angle θ, and the following was found.

[0050] First, by increasing the aperture angle θ, the coupling efficiency, or in other words, the laser light extraction efficiency, can be improved when optically coupling the laser light emitted from the chip-on-submount structure 1 with the core of the optical fiber. However, it has been found that if the aperture angle θ is too large, the radiation shape of the laser light becomes disordered. The inventors have found that if the aperture angle θ is less than 2.51°, the disorder that may occur in the radiometer shape of the laser light is tolerable. Therefore, it is preferable that the aperture angle θ is less than 2.51° (first condition).

[0051] Furthermore, if the diaphragm angle θ is kept constant, the minimum value of the width W2 can be reduced by increasing the length L2. In other words, the coupling efficiency mentioned above can be increased. However, as the length L2 increases, the area of ​​the current injection stripe 161 decreases, which increases the operating voltage when driving the chip 10, and consequently increases the power consumption of the chip 10. In order to achieve both high coupling efficiency and low power consumption, the inventors found that when a width W1 of 220 μm is used, it is preferable that the width W2 be 150 μm or more. In other words, they found that it is preferable that the minimum value of the width W2 be 68.2% or more of the maximum value of the width W2 (second condition). They also found that if the ratio of the area of ​​the second section 161A2 to the area of ​​the current injection stripe 161A is 17.4% or more, an increase in the operating voltage when driving can be tolerated. In other words, we found that if the ratio of the area of ​​the second section 161A2 to the area of ​​the current injection stripe 161 in chip 10 where the second section 161A2 is not provided is 16.8% or more, then an increase in the operating voltage during operation is acceptable. To put it another way, we found that if the ratio of the difference between the area of ​​the current injection stripe 161 and the area of ​​the current injection stripe 161A in chip 10 to the area of ​​the current injection stripe 161 is 3.18% or less, then an increase in the operating voltage during operation is acceptable. Therefore, when viewing the current injection stripe 161A in plan view, it is preferable that at least one of the following conditions is met: (1) the ratio of the area of ​​the second section 161A2 to the area of ​​the current injection stripe 161A is 17.4% or more; (2) the ratio of the area of ​​the second section 161A2 to the area of ​​the current injection stripe 161 in chip 10 where the second section 161A2 is not provided is 16.8% or more; and (3) the ratio of the difference between the area of ​​the current injection stripe 161 and the area of ​​the current injection stripe 161A in chip 10 to the area of ​​the current injection stripe 161 is 3.18% or less (third condition).

[0052] In one embodiment of the present invention, by satisfying the three conditions described above (the first to the third conditions), it is possible to improve the beam quality of the laser light while suppressing power loss.

[0053] Furthermore, as shown in Figure 4(f), one modified version of the chip 10 may further include a reaction control layer 21 that covers the main surface of the strain suppression layer 20 opposite to the active layer 13. The reaction control layer 21 is configured to suppress the diffusion of components of the solder layer 30 into the interior of the strain suppression layer 20 when the chip 10 is joined to the submount 40 using the solder layer 30. Examples of reaction control layers 21 include two-layer films such as Pt / Au and Ti / Au, and three-layer films such as Ti / Pt / Au.

[0054] When the strain suppression layer 20 is formed by a plating method, and the reaction control layer 21 is also formed by a plating method thereafter, it can be selected from platinum, palladium, copper, nickel, a two-layer film of Pt / Au, etc. However, the method of forming the reaction control layer 21 and its composition are not limited and can be selected as appropriate.

[0055] Compared to chip 10 shown in Figure 3(a), chip 10A (see Figure 3(b)), which includes the second section 161A2, is more prone to distortion when bonded to the submount 40 because the width W2 gradually narrows towards the tip of the current injection stripe 161. Therefore, the effect of providing the distortion suppression layer 20 is greater in the case of chip 10A than in the case of chip 10.

[0056] [Method of manufacturing chips] The manufacturing method for chip 10A will be described with reference to Figures 4 and 5. In this description of the manufacturing method, the first specific example of chip 10 shown in Figures 1 to 3 will be used. Figures 4(a) to 4(f) are cross-sectional views showing the manufacturing method of the first specific example of chip 10 shown in Figure 2. This manufacturing method includes a lamination step, an opening formation step, a contact layer lamination step, a first electrode layer lamination step, a mask formation step, a strain suppression layer lamination step, a window formation step, a second electrode layer lamination step, and a cleavage step. Figure 5 is a plan view showing multiple chips 10 manufactured by this manufacturing method.

[0057] Figure 4(a) shows the substrate 11 after the lamination process. The lamination process involves laminating a buffer layer 121, an n-type cladding layer 122, an n-type guide layer 123, an active layer 13, a p-type guide layer 141, a p-type cladding layer 142, and a block layer 150 onto the main surface 112 of the substrate 11. In this manufacturing method, each of these layers is laminated using the MOCVD method.

[0058] The buffer layer 121, the n-type cladding layer 122, and the n-type guide layer 123 correspond to the n-type layer 12 shown in Figures 1 and 2. The p-type guide layer 141 and the p-type cladding layer 142, along with the p-type contact layer 143 described later, correspond to the p-type layer 14 shown in Figures 1 and 2.

[0059] In this manufacturing method, a GaAs wafer is used as the substrate 11. Furthermore, GaAs is used as the material constituting the buffer layer 121, and Al is used as the material constituting the n-type cladding layer 122. x1 Ga 1-x1A Using s, Al is used as the material to constitute the n-type guide layer 123. x2 Ga 1-x2 As is used, undoped InGaAs is used as the material constituting the active layer 13, and Al is used as the material constituting the p-type guide layer 141. x3 Ga 1-x3 As is used, and Al is used as the material to constitute the p-type cladding layer 142. x4 Ga 1-x4 As is used, and n-type GaAs is used as the material constituting the block layer 150. Here, x1 > x2 and x4 > x3. Note that since the block layer 150 is a solid film without openings, it is designated as 150 to distinguish it from the block layer 15 described later. The composition and film thickness of the active layer 13 can be appropriately adjusted to obtain the desired oscillation wavelength.

[0060] Figure 4(b) shows the substrate 11 after the aperture formation process. The aperture formation process is a process of forming an aperture 151 in the solid block layer 150. In this manufacturing method, the aperture 151 is formed using photolithography and etching. If surface treatment is required in the aperture formation process, shallow etching with HF or an inorganic acid may be performed.

[0061] Figure 4(c) shows the substrate 11 after the contact layer lamination process. The contact layer lamination process involves laminating a p-type contact layer 143 on top of the p-type cladding layer 142 and the block layer 15. In this manufacturing method, p-type GaAs is used as the material for the p-type contact layer 143. By performing the above steps, a Self-aligned Structure (SAS) chip is obtained.

[0062] Furthermore, regarding the composition, thickness, and doping variations of each layer described above, there are countless combinations suitable for laser oscillation. Therefore, one should select the combination that yields the desired laser oscillation characteristics. The layers described above can be appropriately selected as long as they have similar functions. Each of the layers described above may be a single layer or a multilayer.

[0063] Furthermore, in this manufacturing method, GaAs-based materials were used as the materials constituting the n-type layer 12, the active layer 13, and the p-type layer 14. However, AlInGaP-based materials that are lattice-matched with the GaAs substrate 11 can also be used as the materials constituting the n-type layer 12, the active layer 13, and the p-type layer 14.

[0064] Figure 4(d) shows the substrate 11 after the first electrode layer lamination process. The first electrode layer lamination process involves laminating an electrode layer 16 on top of the p-type contact layer 143. In this manufacturing method, a Ti / Au two-layer film is used as the electrode layer 16. The region of the electrode layer 16 that overlaps with the opening 151 functions as a current injection stripe 161. By performing the above steps, a chip 10 is obtained.

[0065] Figure 4(e) shows the substrate 11 after the mask formation process. The mask formation process is a process of forming a photomask M on the electrode layer 16. The photomask M has openings that correspond to the region where the strain suppression layer 20 will be formed.

[0066] Figure 4(f) shows the substrate 11 after the strain suppression layer lamination process. The strain suppression layer lamination process is a process of laminating a strain suppression layer 20 and a reaction control layer 21 on the electrode layer 16 and the photomask M. In this manufacturing method, the strain suppression layer 20 and the reaction control layer 21 are laminated using a plating method. In this manufacturing method, Au is used as the material constituting the strain suppression layer 20, and a Pt / Au two-layer film is used as the reaction control layer 21. Then, by lifting off the photomask M, a chip 10 equipped with the strain suppression layer 20 and the reaction control layer 21 is obtained.

[0067] The growth methods for each layer described above are not limited to the MOCVD method; liquid-phase epitaxy and molecular beam epitaxy may also be used.

[0068] Figure 5 shows multiple chips 10A manufactured on the main surface of a single GaAs substrate S. Three laser bars are provided in Figure 5. Note that in Figure 5, a portion of the substrate S (the area containing the three laser bars) is shown in an enlarged view for illustrative purposes. Many more laser bars are provided on the main surface of the substrate S. Each laser bar is composed of multiple chips 10A. Note that since the shape of the aperture 151A of chip 10 differs only in the shape of the aperture 151 of chip 10, chip 10A can be manufactured using the manufacturing method described above.

[0069] The second electrode layer lamination process involves laminating an electrode layer 17 onto the main surface 111 of the substrate 11. In the second electrode layer lamination process, the main surface 111 is ground and polished to adjust the thickness of the substrate 11, and then an electrode layer 17 made of Ni / Ge / Au is laminated. The method for laminating the electrode layer 17 is not limited, but examples include electron beam deposition and sputtering.

[0070] Furthermore, in the second electrode layer lamination process, heat treatment may be performed after the lamination of the electrode layer 17. The temperature of the heat treatment can be determined as appropriate, but for example, it is 400°C.

[0071] Alternatively, a metallized layer (e.g., Ti / Pt / Au) with an Au surface may be provided on the electrode layer 17. This improves the wire bonding properties between the electrode pattern 43 of the submount 40 and the external electrode.

[0072] The cleavage process is a process of obtaining individual laser bars by cleaving the substrate S shown in Figure 5, for example, at the positions of the C-C' line and the D-D' line. Furthermore, when obtaining individual chips 10A from a single laser bar, adjacent chips 10A can be separated. This separation may be performed by cleaving the substrate S constituting each laser bar, or by dicing.

[0073] [Second example of a tip] A second specific example of the chip 10 will be described with reference to Figures 6 and 7. Figures 6(a) to 6(c) are cross-sectional views showing the manufacturing method of the second specific example of the chip 10. The manufacturing method of the second specific example differs from the manufacturing method shown in Figure 4 in terms of the lamination process. The method for forming the block layer 15 following the lamination process is also different. Figure 7(a) is a plan view of the second specific example of the chip 10 as seen from the current injection stripe 161B side. Figure 7(b) is a plan view of a modified example of the second specific example shown in Figure 7(a) as seen from the current injection stripe 161C side.

[0074] For the sake of clarity, components having the same function as those described in tip 10 will be denoted by the same reference numeral and their descriptions will not be repeated.

[0075] Figure 6(a) shows the state of the substrate 11 after the lamination process and the mask formation process. The lamination process involves laminating a buffer layer 121, an n-type cladding layer 122, an n-type guide layer 123, an active layer 13, a p-type guide layer 141, a p-type cladding layer 142, an etching stop layer 14s, and a p-type contact layer 143 onto the main surface 112 of the substrate 11. The mask formation process involves forming a photomask M on the p-type contact layer 143. The etching stop layer 14s is composed of a material with a slower etching rate compared to the p-type contact layer 143. There are countless suitable combinations of materials constituting the etching stop layer 14s and methods used for etching the p-type contact layer 143. Therefore, a suitable combination of materials constituting the etching stop layer 14s and methods used for etching the p-type contact layer 143 can be appropriately selected from existing suitable combinations. For example, AlGaAs can be used as the material constituting the etching stop layer 14s, and a citric acid-based etching solution can be used as the method for etching the p-type contact layer 143.

[0076] Figure 6(b) shows the substrate 11 after the etching process. The etching process is a process of forming two grooves 14t by etching the p-type contact layer 143 to a depth that reaches the etching stop layer 14s. As a result, the region of the p-type contact layer 143 sandwiched between the two grooves 14t is patterned in a ridge shape. Note that Figure 6(b) shows the substrate 11 after the photomask M has been removed following the etching process.

[0077] Figure 6(c) shows the state of the substrate 11 after the dielectric layer formation process. The dielectric layer formation process is a process of forming a dielectric layer 15A on the p-type contact layer 143 and the etching stop layer 14s. The dielectric layer 15A is made of a dielectric with lower conductivity than the p-type semiconductor that makes up the p-type contact layer 143.

[0078] Although the explanation is omitted here, a second specific example of the chip 10 can be obtained by performing the first electrode layer lamination process, the mask formation process, the strain suppression layer lamination process, the window formation process, the second electrode layer lamination process, and the cleavage process described above, after the block layer formation process.

[0079] In the following, the second specific example of chip 10 will be referred to as chip 10B (see Figure 7(a)). A modified example of chip 10B will be referred to as chip 10C (see Figure 7(b)). The chip provided in the chip-on-submount structure 1 may be a chip in which two grooves are not formed in the p-type contact layer 143, as in chip 10 (see Figure 3(a) and Figure 4) and chip 10A (see Figure 3(b)), or it may be a chip in which two grooves 14t are formed, thereby forming the p-type contact layer 143 into a ridge shape, as in chip 10B and chip 10C. Furthermore, in the chip provided in the chip-on-submount structure 1, a current injection stripe 161 with a constant width W may be adopted in a chip equipped with a ridge-shaped p-type contact layer 143, as in chip 10.

[0080] 〔summary〕 To solve the above problems, a chip-on-submount structure according to a first aspect of the present invention comprises a broad-area type chip including an active layer and a current injection stripe for injecting current into the active layer; a submount including a metallic strain-suppressing layer covering the current injection stripe, a substrate, and an electrode layer provided on one main surface of the substrate; and a solder layer interposed between the strain-suppressing layer and the electrode layer to join the chip and the submount. In this chip-on-submount structure, the strain-suppressing layer consists of a reaction layer in which the components of the solder layer are diffused and an unreacted layer in which the components of the solder layer are not diffused, and the thickness of the unreacted layer is 1.4 μm or more.

[0081] The strain-suppressing layer in the chip-on-submount structure according to the first embodiment has an unreacted layer thickness of 1.4 μm or more, which suppresses strain that may occur during the process of joining the chip to the submount using solder. Therefore, this chip-on-submount structure can stabilize the emission shape of the laser beam.

[0082] Furthermore, in the chip-on-submount structure according to the second aspect of the present invention, in addition to the configuration of the chip-on-submount structure according to the first aspect described above, the main component of the strain suppression layer is gold.

[0083] Gold is a relatively soft metal. With the above configuration, a relatively soft metal is interposed between the chip and the submount, thus reliably suppressing the aforementioned distortion. Furthermore, gold has high electrical and thermal conductivity. Therefore, this chip-on-submount structure can reduce power loss that may occur when supplying drive current to the chip, and efficiently dissipate heat generated in the chip to the submount.

[0084] Furthermore, in the chip-on-submount structure according to the third aspect of the present invention, in addition to the configuration of the chip-on-submount structure according to the first or second aspect described above, the chip has a strip-like shape when the main surface of the active layer is viewed in plan from the direction normal to the main surface, and the current injection strip is provided so as to overlap with the central axis of the strip-shaped chip.

[0085] The heat generated when driving the chip tends to occur near the active layer that overlaps with the current injection stripe when viewed from above. The above configuration enhances the symmetry of the current injection stripe within the chip. Therefore, this chip-on-submount structure can suppress thermal distortion that may occur when driving the chip.

[0086] Furthermore, in the chip-on-submount structure according to the fourth aspect of the present invention, in addition to the configuration of the chip-on-submount structure according to the third aspect described above, the current injection stripe is line-symmetric with respect to the axis passing through the central axis and perpendicular to the main surface of the active layer in the cross-section of the chip, which is parallel to each of the pair of end faces constituting the resonator of the chip.

[0087] The above configuration allows for further enhancement of the symmetry of the current injection stripe within the chip. Therefore, this chip-on-submount structure can further suppress thermal stress that may occur in the chip when it is driven.

[0088] Furthermore, in the chip-on-submount structure according to the fifth aspect of the present invention, in addition to the configuration of the chip-on-submount structure according to the third aspect described above, the current injection stripe is located on the outermost surface of the chip and is recessed compared to the outermost surface on the side where the strain suppression layer is provided.

[0089] With the above configuration, compared to the case where the current injection stripe is on the outermost surface of the chip and protrudes beyond the outermost surface on the side where the distortion suppression layer is provided, distortion that may occur during the process of joining the chip to the submount using solder can be suppressed. Therefore, this chip-on-submount structure can further stabilize the emission shape of the laser beam.

[0090] Furthermore, in the chip-on-submount structure according to the sixth aspect of the present invention, in addition to the configuration of the chip-on-submount structure according to any one of the first to third aspects described above, the chip further comprises a highly reflective film that constitutes the resonator of the chip, and a low-reflective film that has a lower reflectivity than the highly reflective film. In this chip-on-submount structure, the current injection stripe is composed of a first section having a constant width and located on the side of the highly reflective film, and a second section whose width narrows as it moves away from the first section and located on the side of the low-reflective film.

[0091] The above configuration improves the beam quality of the laser light emitted by the chip. Therefore, this chip-on-submount structure can increase the coupling efficiency, or in other words, the laser light extraction efficiency, when optically coupling the laser light with the core of the optical fiber.

[0092] Furthermore, in the chip-on-submount structure according to the seventh aspect of the present invention, in addition to the configuration of the chip-on-submount structure according to the sixth aspect described above, when the main surface of the current injection stripe is viewed in plan from the direction normal to the main surface, the chip has a strip-like shape, the second section has a trapezoidal shape that narrows in width as it moves away from the first section, the ratio of the minimum value of the width in the second section to the maximum value is 68.2% or more, the ratio of the area of ​​the second section to the area of ​​the current injection stripe is 17.4% or more, and the tapering angle θ, which is the angle between the legs of the trapezoid that constitute the second section and the central axis of the strip-shaped chip, is 0° or more and less than 2.51°.

[0093] By satisfying the two conditions mentioned above, it is possible to improve the beam quality of the laser light while suppressing power loss that may occur when driving the chip.

[0094] Furthermore, in the eighth aspect of the present invention, in addition to the configuration of the chip-on-submount structure according to any one of the first to seventh aspects described above, a further configuration is adopted in which a reaction control layer made of a metallic multilayer film is provided between the strain suppression layer and the solder layer.

[0095] According to the above configuration, the interposition of a reaction control layer between the strain suppression layer and the solder layer suppresses the diffusion of components from the solder layer into the interior of the strain suppression layer. Therefore, compared to the case where the strain suppression layer and the solder layer are directly bonded, this chip-on-submount structure can easily secure an unreacted layer with a thickness of 1.4 μm or more.

[0096] Furthermore, in the chip-on-submount structure according to the ninth aspect of the present invention, in addition to the configuration of the chip-on-submount structure according to any one of the first to eighth aspects described above, a configuration is adopted in which the width of the current injection stripe is 75 μm or more over the entire length.

[0097] A configuration in which the thickness of the unreacted layer in the strain suppression layer is 1.4 μm or more is suitable for a chip-on-submount structure equipped with a broad-area type chip in which the width of the current injection stripe is 75 μm or more throughout the entire section. Such a broad-area type chip can emit laser light with an output of 10 W or more.

[0098] [Additional Notes] The present invention is not limited to the embodiments described above, and various modifications are possible within the scope of the claims. Embodiments obtained by appropriately combining the technical means disclosed in different embodiments are also included in the technical scope of the present invention. [Explanation of Symbols]

[0099] 1. Chip-on-submount structure 10,10A chip 11 circuit boards 12 n-type layer 121 Buffer Layer 122 n-type cladding layer 123 n-type guide layer 13 Active layer 14 p-type layer 14t groove 141 p-type guide layer 142 p-type cladding layer 143 p-type contact layer 15 block layers 15A Dielectric layer 16,17 Electrode layer 161 Current Injection Stripe 18 Low reflective coating 19 Highly reflective coating 20 Distortion suppression layer 21 Reaction control layer 30 Handa Formation 40 Submount 41 circuit boards 42,43 Electrode Patterns

Claims

1. A broad-area chip including an active layer and a current-injection stripe for injecting current into the active layer, A metal strain-suppressing layer covering the current injection stripe, A submount including a substrate and an electrode layer provided on one main surface of the substrate, The solder layer is interposed between the strain suppression layer and the electrode layer and joins the chip and the submount, The strain-suppressing layer consists of a reaction layer in which the components of the solder layer are diffused, and an unreacted layer in which the components of the solder layer are not diffused. The thickness of the unreacted layer is 1.4 μm or more. The chip further comprises a highly reflective film and a less reflective film with a lower reflectivity than the highly reflective film, which constitute the resonator of the chip. The current injection stripe is composed of a first section having a constant width and located on the side of the high-reflectivity film, and a second section whose width narrows as it moves away from the first section and located on the side of the low-reflectivity film. When the main surface of the current injection stripe is viewed in plan from the direction normal to the main surface, the ratio of the minimum value of the width to the maximum value in the second section is 68.2% or more. When the main surface of the current injection stripe is viewed in plan from the direction normal to the main surface, The aforementioned chip has a strip-like shape, The second section has a trapezoidal shape, which narrows in width as it moves away from the first section. The ratio of the area of ​​the second section to the area of ​​the current injection stripe is 17.4% or more. The constriction angle θ, which is the angle between the trapezoidal legs constituting the second section and the central axis of the strip-shaped tip, is 0° or more and less than 2.51°. A chip-on-submount structure is a key feature.

2. The main component of the aforementioned strain-suppressing layer is gold. The chip-on-submount structure according to feature 1.

3. When the main surface of the active layer is viewed in plan from the direction normal to the main surface, The aforementioned chip has a strip-like shape, The current injection stripe is provided so as to overlap with the central axis of the strip-shaped chip. The chip-on-submount structure according to claim 1 or 2.

4. In the cross-section of the chip, in a cross-section parallel to each of the pair of end faces constituting the resonator of the chip, The current injection stripe is symmetrical with respect to the axis passing through the central axis and perpendicular to the main surface of the active layer. The chip-on submount structure according to feature 3.

5. The current injection stripe is on the outermost surface of the chip and is recessed compared to the outermost surface on the side where the distortion suppression layer is provided. The chip-on submount structure according to feature 3.

6. A reaction control layer provided between the strain suppression layer and the solder layer, further comprising a reaction control layer made of a multilayer film of metal. The chip-on-submount structure according to feature 1.

7. The width of the current injection stripe is 75 μm or more throughout the entire section. The chip-on-submount structure according to feature 1.

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