Control method

Abstract

To provide a control method and the like which can suppress a flicker phenomenon even when a frame period fluctuates.SOLUTION: There is provided a control method of controlling a light emission period and an extinction period of a frame period being a period in which the same image is continuously displayed. When a signal indicating the start of the frame period is detected, after a prescribed time from the time point at which the signal is detected, n (n is an integer equal to or greater than 2) sub-frame periods constituting the frame period are sequentially started from the first sub-frame period as the frame period. All of the n sub-frame periods are controlled to be the predetermined same length periods. Also, the duty ratio being the ratio of the light emission period and the extinction period in the n sub-frame periods is controlled to be the predetermined same ratio.SELECTED DRAWING: Figure 9

Description

[[Technical Field]]

[0001] The present disclosure relates to a control method and a control device, and particularly relates to a control method and a control device for controlling display luminance of a display. [[Background Art]]

[0002] For example, in displays using liquid crystal, organic EL and the like, it is known that when the refresh rate is lowered, flicker (flickering) becomes visible, whereas when the refresh rate is increased to about 72 Hz, flicker becomes almost invisible.

[0003] Furthermore, in a display using organic EL, in order to update pixel information, it is necessary to once turn off the display and reset the pixels, so a non-light-emitting period occurs. This non-light-emitting period occupies a fixed period relative to one frame period. One frame period is a period in which the same screen (image) is continuously displayed. Although luminance can also be adjusted by changing the ratio of the light-emitting period to the non-light-emitting period, in a display using organic EL, even if an image is displayed at a refresh rate of 60 Hz, for example, flicker may be visible depending on the ratio (duty ratio) of the light-emitting period to the non-light-emitting period in one frame period.

[0004] Accordingly, for example, Patent Document 1 discloses a technique in which the number of subframes constituting one frame period is changed according to a duty ratio set corresponding to luminance information, and the duty ratio within each subframe is made the same as the duty ratio of one frame period. Accordingly, even when the light-emitting period is changed for luminance adjustment or the like, flicker occurring on the display screen can be suppressed. [[Prior Art Literature]] [[Patent Literature]]

[0005] [[Patent Document 1]] Japanese Unexamined Patent Application Publication No. 2006-30516 [[Summary of the Invention]] [Problems that the invention aims to solve]

[0006] Incidentally, in recent years, image rendering on displays of personal computers and mobile devices has increasingly been performed by image processing units called GPUs (Graphics Processing Units). Furthermore, the display speed is increasingly determined by the performance of the GPU. In other words, in recent years, the frame rate has come to fluctuate depending on what the GPU is processing.

[0007] However, the prior art disclosed in Patent Document 1 has the problem that it is based on the premise that the frame period is constant.

[0008] More specifically, in the prior art disclosed in Patent Document 1, a duty cycle for the frame period is set based on the predetermined number of vertical lines and brightness information of the display screen, and the number of subframes constituting one frame period is determined according to the set duty cycle ratio. However, when the frame period fluctuates, for example, when the frame period is long (frame rate is low), the subframe period also becomes longer, and the illumination period and extinction period also become longer. As a result, the human eye can easily perceive the switching between illumination and non-illumination (extinction), i.e., flashing, which leads to the problem of flicker being visible.

[0009] This disclosure is made in view of the circumstances described above, and aims to provide a control method and control device that can suppress the flicker phenomenon even when the frame duration fluctuates. [Means for solving the problem]

[0010] To achieve the above objective, a control method according to one aspect of the present disclosure is a control method for a case where the frame period, which is the period during which the same image is continuously displayed, fluctuates within a certain range or temporarily stabilizes for each frame, but the exact frame period is not known in advance, and the number of subframes is changed so as to reconstruct the frame period with n (where n is an integer of 2 or more) subframes, regardless of the input frame period, and the image is displayed.

[0011] This makes it possible to prevent flicker from being visible on the display panel showing the image, even if the frame duration fluctuates significantly. In other words, it can suppress the flicker phenomenon even when the frame duration changes.

[0012] Furthermore, in a control method for when the frame period, which is the period during which the same image is continuously displayed, fluctuates or temporarily stabilizes within a certain range for each frame, but the exact frame period is unknown in advance, the number of subframes is changed so that the frame period is reconstructed with n (where n is an integer of 2 or more) subframes, regardless of the input frame period. However, if a signal indicating the start of the next frame period is detected during the additional subframe period after the execution of the last subframe, and the detection timing is below a certain threshold time from the start of one subframe period, the additional subframe period may be terminated midway and the next frame period may be started.

[0013] In this way, if a signal such as a vertical synchronization signal is detected within a time period below a threshold from the start of the added subframe period, the added subframe period is terminated midway, and the first subframe period constituting the next frame period is started. This extends the frame period, but if the extension is small, the change in brightness becomes sufficiently small. As a result, the flicker phenomenon can be suppressed even when the frame period fluctuates.

[0014] Here, each of the n subframe periods may be controlled to consist of a predetermined period of approximately the same length.

[0015] Furthermore, if a signal indicating the start of a frame period is detected during a subframe period, the frame period may be defined as a predetermined time period from the time the signal is detected, and the n (where n is an integer of 2 or more) subframe periods constituting the frame period may be executed sequentially starting from the first subframe period.

[0016] Furthermore, the predetermined time may be the period from the time of detection of the frame start signal for the last subframe period to the end of the subframe period, when a signal indicating the start of the next frame period of the frame period is detected during the execution of the last subframe period of the n subframe periods.

[0017] Furthermore, the frame period start detection signal may be a vertical synchronization signal or a video period signal at the beginning of the frame.

[0018] This allows a frame duration to be defined starting from the detection of the vertical synchronization signal or the video duration at the beginning of the frame.

[0019] Furthermore, if no signal indicating the start of the next frame period is detected during the execution of the last of the n subframe periods, it may be determined that the frame period is not an integer multiple of the subframe period, and one additional subframe period may be started at the end of the last subframe period.

[0020] Furthermore, if no signal indicating the start of the next frame period is detected during the execution of the last of the n subframe periods, it may be determined that the frame period has not yet ended, and one more subframe period may be started after the end of the last subframe period.

[0021] Furthermore, the aforementioned subframe period may be repeated if the start of the next frame period is not detected.

[0022] As described above, even if the frame period is not an integer multiple of a predetermined subframe period, the light emission period and the light extinction period can be repeated at regular intervals using a plurality of subframe periods, thereby making flicker not visually recognizable. That is, the flicker phenomenon can be suppressed even if the frame period fluctuates.

[0023] Further, for the frame period, the number of subframes constituting the frame period may be dynamically changed in accordance with an input video signal, corresponding to a standard that makes a drawing start timing variable according to the processing time of a GPU.

[0024] Accordingly, the present disclosure is compatible with specifications that define the specifications of a video synchronization signal when the frame period is variable such as the Adaptive-Sync standard, and G-SYNC and FreeSync defined as authentication standards by GPU vendors, and can suppress the occurrence of flicker while following large synchronization fluctuations.

[0025] Further, the n subframe periods may each have a light emission period and a light extinction period.

[0026] Further, a duty ratio that is a ratio of the light emission period to the light extinction period may be controlled to be a predetermined substantially identical ratio.

[0027] Further, the duty ratio of each of the n subframe periods constituting the frame period may be adjusted in accordance with light emission characteristics of a display panel on which an image is displayed.

[0028] Accordingly, by adjusting the duty ratio of each of the plurality of subframe periods, it is possible to suppress deviation of an average luminance from a target luminance in each of the plurality of subframe periods constituting one frame period due to light emission characteristics unique to a display panel. Therefore, the flicker phenomenon can be suppressed while suppressing the influence of the light emission characteristics unique to the display panel.

[0029] Furthermore, when adjusting the duty cycle of each of the n subframe periods, the duty cycle may be adjusted such that the emission period following the extinction period in the first of the n subframe periods is shorter than the length determined by the substantially same ratio.

[0030] This makes it possible to suppress the effects of overshoot caused by the display panel's unique light emission characteristics. Therefore, it is possible to suppress the flicker phenomenon while suppressing the effects of the display panel's unique light emission characteristics.

[0031] Furthermore, the extinction period in the first subframe period of the n subframe periods may include an initialization period for initializing a plurality of pixel circuits arranged in a matrix, which are present in the display panel that displays the image.

[0032] In this way, by including an initialization period for initializing multiple pixel circuits in the extinction period placed at the beginning of the frame period, the image display during that frame period can be performed appropriately.

[0033] Furthermore, the pixels constituting the display panel that displays the image may consist of light-emitting elements that emit light by current drive, including organic EL elements.

[0034] This makes it possible to prevent flicker from being visible on OLED display panels even if the frame duration fluctuates significantly due to factors such as the processing power of the GPU. In other words, it is possible to suppress the flicker phenomenon on OLED display panels even when the frame duration fluctuates.

[0035] Furthermore, the pixels constituting the display panel that displays the image may consist of liquid crystal elements, the light emission period may be the period during which the backlight is turned on in the backlight scan, and the extinguishing period may be the period during which the backlight is turned off.

[0036] This makes it possible to prevent flicker from being visible on a liquid crystal display panel even if the frame duration of the backlight scan fluctuates significantly. In other words, it is possible to suppress the flicker phenomenon on a liquid crystal display panel even if the frame duration of the backlight scan fluctuates.

[0037] Furthermore, in order to achieve the above objective, a control device according to one aspect of the present disclosure is a control device that controls the light emission period and the extinction period of a frame period, which is a period during which the same image is continuously displayed, and comprises a duty control unit that, when it detects a signal indicating the start of a frame period, sequentially starts a plurality of subframe periods constituting the frame period, starting from the first subframe period, after a predetermined time from the time the signal is detected, wherein the duty control unit controls all of the plurality of subframe periods to be a predetermined substantially identical length, and controls the duty ratio, which is the ratio of the light emission period to the extinction period in the plurality of subframe periods, to be a predetermined substantially identical ratio.

[0038] This allows the extinction period within a frame to be distributed using multiple subframe periods; that is, the illumination and extinction periods can be repeated at regular intervals using multiple subframe periods. Therefore, even if the frame period fluctuates significantly, flicker can not be seen on the display panel showing the image. In other words, the flicker phenomenon can be suppressed even if the frame period fluctuates. [Effects of the Invention]

[0039] According to the control method and control device described herein, flicker phenomena can be suppressed even when the frame duration fluctuates. [Brief explanation of the drawing]

[0040] [Figure 1] This is a schematic diagram showing an example configuration of a display device according to an embodiment. [Figure 2] This is a schematic circuit diagram showing the configuration of a pixel circuit according to the embodiment. [Figure 3A] Figure 2 is a timing chart showing the initialization operation of the pixel circuit. [Figure 3B] Figure 2 is a timing chart showing the extinction operation of the pixel circuit. [Figure 4] This is a block diagram showing the configuration of a control device provided in a display device according to an embodiment. [Figure 5] This diagram shows an overview of the duty control performed by the duty control unit according to the embodiment. [Figure 6] This is a block diagram showing the detailed configuration of the duty control unit according to the embodiment. [Figure 7] This flowchart outlines the operation of controlling the light emission period and extinction period of the frame period of the control device according to the embodiment. [Figure 8A] Figure 7 is a flowchart showing the detailed operation of step S2. [Figure 8B] Figure 7 is a flowchart detailing the operation of step S3. [Figure 9] This figure shows an example of the detailed operation performed by the control device according to the embodiment to control the light emission period and the extinction period of the frame period. [Figure 10] This figure shows the case where one frame period begins based on the detection of the vertical synchronization signal according to the embodiment. [Figure 11] This diagram shows the case where one frame period begins based on the detection of the video period signal according to the embodiment. [Figure 12] This figure shows the number of subframe periods configured when the frame period according to the embodiment varies. [Figure 13] This figure shows a detailed example of the operation performed by the control device to control the light emission period and extinction period of the frame period when the frame period according to the embodiment fluctuates. [Figure 14] This figure shows a detailed example of the operation performed by the control device to control the light emission period and extinction period of the frame period when the frame period according to the embodiment fluctuates. [Figure 15]This figure shows a detailed example of the operation performed by the control device to control the light emission period and extinction period of the frame period when the frame period according to the embodiment fluctuates. [Figure 16] This figure shows a detailed example of the operation performed by the control device to control the light emission period and extinction period of the frame period when the frame period according to the embodiment fluctuates. [Figure 17] This figure shows a detailed example of the operation performed by the control device to control the light emission period and extinction period of the frame period when the frame period according to the embodiment fluctuates. [Figure 18] This figure shows a detailed example of the operation performed by the control device to control the light emission period and extinction period of the frame period when the frame period according to the embodiment fluctuates. [Figure 19] This diagram shows an overview of the duty cycle control performed by the duty cycle control unit according to Embodiment 2 of the embodiment. [Figure 20] This figure shows a specific example of duty control performed by the duty control unit according to Embodiment 2 of the embodiment. [Figure 21A] This is a schematic diagram showing an example configuration of a display device related to a comparative example. [Figure 21B] Figure 21A shows the gate waveform output by the synchronous control unit to the gate drive circuit. [Figure 22A] This figure shows the light emission period and extinction period for each frame period when the control device for the comparative example keeps the extinction period constant regardless of variations in the frame period. [Figure 22B] This figure shows the light emission period and extinction period for each frame period when the control device according to the comparative example changes the extinction period in accordance with the variation in the frame period to keep the duty cycle constant. [Figure 23A] This is a schematic circuit diagram showing an example of the configuration of a pixel circuit according to a modified example 1 of the embodiment. [Figure 23B] This is a schematic circuit diagram showing another example of the configuration of a pixel circuit according to the first modified embodiment. [Figure 24] This is a schematic circuit diagram showing an example of the configuration of a pixel circuit according to a modified example 2 of the embodiment. [Figure 25] This is an example of a timing chart for the frame duration of a backlight scan according to a modified example 2 of the embodiment. [Figure 26] This figure shows an example of the detailed operation of a control device that controls the light emission period and extinction period of a frame period when the frame period fluctuates according to other embodiments. [Figure 27A] This figure shows an example of a duty cycle waveform in multiple subframe periods when the frame duration is 144 Hz. [Figure 27B] This figure shows an example of an actual light emission waveform relative to the duty cycle waveform shown in Figure 27A. [Figure 28] Figure 27B shows the actual emission waveform and its average brightness when the extinction period is excluded from the actual emission waveform during one frame period shown. [Figure 29] This figure illustrates a method for adjusting the duty cycle of multiple subframe periods according to other embodiments. [Modes for carrying out the invention]

[0041] The embodiments of this disclosure will be described below with reference to the drawings. The embodiments described below are all preferred specific examples of this disclosure. Therefore, the numerical values, shapes, materials, components, arrangement positions of components, and connection configurations shown in the following embodiments are examples and are not intended to limit this disclosure. Accordingly, among the components in the following embodiments, those components that are not described in the independent claims representing the highest-level concepts of this disclosure will be described as optional components.

[0042] Please note that each figure is a schematic diagram and not necessarily a strictly accurate representation. Furthermore, the same reference numerals are used for substantially identical components in each figure, and redundant explanations are omitted or simplified.

[0043] (Embodiment) First, the configuration of a display device including the control device of this disclosure will be described. In this embodiment, the case in which an organic electroluminescent (EL) element is used in the display device will be described as an example.

[0044] [1. Display device configuration] Figure 1 is a schematic diagram showing an example configuration of the display device 1 according to this embodiment. As shown in Figure 1, the display device 1 consists of a display panel 10 and a control device 20. The display device 1 is driven, for example, by a progressive drive method of an organic EL light-emitting panel.

[0045] [2. Display Panel Configuration] As shown in Figure 1, the display panel 10 includes a display unit 12 having a plurality of pixel circuits 30, and also includes a gate drive circuit 14 and a source drive circuit 16 as peripheral circuits to the display unit 12. The display unit 12, gate drive circuit 14, source drive circuit 16, scan lines 40, and signal lines 42 are mounted on a panel substrate (not shown) made of, for example, glass or acrylic resin.

[0046] The display unit 12 displays an image based on a video signal input to the display device 1 from an external source. As shown in Figure 1, the display unit 12 comprises a plurality of pixel circuits 30 arranged in a matrix, with row-shaped scan lines 40 and column-shaped signal lines 42 wired to them. The display unit 12 performs initialization, writing, and light emission operations row by row of the plurality of pixel circuits 30.

[0047] Multiple pixel circuits 30 are provided on the display panel 10 and are arranged in a matrix. More specifically, each of the multiple pixel circuits 30 is positioned where the scan lines 40 and signal lines 42 intersect. Further details will be described later.

[0048] The scan lines 40 are arranged for each row of multiple pixel circuits 30. One end of the scan line 40 is connected to the pixel circuit 30, and the other end of the scan line 40 is connected to the gate drive circuit 14.

[0049] The signal line 42 is arranged for each row of multiple pixel circuits 30. One end of the signal line 42 is connected to the pixel circuit 30, and the other end of the signal line 42 is connected to the source drive circuit 16.

[0050] The gate drive circuit 14, also called a scan line drive circuit, is composed of, for example, a shift register. The gate drive circuit 14 is connected to the scan line 40 and controls the on / off state of each transistor in the pixel circuit 30 by outputting gate control signals to the scan line 40. In this embodiment, the gate drive circuit 14 outputs, for example, control signal WS, control signal REF, control signal INI, and extinction signal EN to the gates of each transistor in the pixel circuit 30 as gate control signals to control the on / off state of each transistor in the pixel circuit 30.

[0051] The source drive circuit 16 is also called the signal line drive circuit. The source drive circuit 16 is connected to the signal line 42 and supplies the video signal, which is supplied from the control device 20 in frame units, to each pixel circuit 30 by outputting it to the signal line 42. The source drive circuit 16 writes brightness information based on the video signal to each of the pixel circuits 30 in the form of a current value or voltage value through the signal line 42. The video signal input to the source drive circuit 16 is, for example, digital serial data for each of the three primary colors of RGB (video signals R, G, B). The video signals R, G, B input to the source drive circuit 16 are converted into line-by-line parallel data inside the source drive circuit 16. Furthermore, the line-by-line parallel data is converted into line-by-line analog data inside the source drive circuit 16 and output to the signal line 42 as a video signal.

[0052] [3. Pixel Circuit Configuration] Multiple pixel circuits 30 are arranged, for example, in an N row and M column configuration. N and M vary depending on the size and resolution of the display screen. For example, at a resolution called HD (High Definition), where pixel circuits 30 corresponding to the three primary colors RGB are adjacent within a row, N is at least 1080 rows and M is at least 1920 × 3 columns. In this embodiment, each pixel circuit 30 has an organic EL element as a light-emitting element.

[0053] Figure 2 is a schematic circuit diagram showing the configuration of the pixel circuit 30 according to this embodiment.

[0054] As shown in Figure 2, the pixel circuit 30 comprises a light-emitting element 32, a drive transistor 33, a selection transistor 35, switch transistors 34, 36, and 37, and a pixel capacitance 38. In Figure 2, the pixel capacitance 38 is also denoted as Cs.

[0055] The light-emitting element 32 has its cathode connected to the power supply Vcath (negative power line) and its anode connected to the source of the drive transistor 33. The light-emitting element 32 emits light with a brightness corresponding to the signal voltage of the video signal supplied from the drive transistor 33. The light-emitting element 32 is, for example, an organic EL element such as an OLED (Organic Light Emitting Diode). However, the light-emitting element 32 is not limited to an organic EL element; it may also be an inorganic EL element or a self-emitting element such as a QLED, or any element that is controlled by current drive, even if it is not a self-emitting element.

[0056] The drive transistor 33 has its gate connected to one electrode of the pixel capacitor 38, its drain connected to the source of the switch transistor 34, and its source connected to the anode of the light-emitting element 32. In Figure 2, the source is further connected to the other electrode of the pixel capacitor 38. The drive transistor 33 converts the signal voltage applied between the gate and source into a current corresponding to that signal voltage (referred to as the drain-source current). When the drive transistor 33 turns on, it supplies the drain-source current to the light-emitting element 32, causing the light-emitting element 32 to emit light. The drive transistor 33 is composed of, for example, an n-type thin-film transistor (n-type TFT).

[0057] The switch transistor 34 has its gate connected to the scan line 40, one of its source and drain connected to the power supply Vcc, and the other of its source and drain connected to the drain of the drive transistor 33. The switch transistor 34 is either ON or OFF in response to the extinction signal EN supplied from the scan line 40. When the switch transistor 34 is ON, it connects the drive transistor 33 to the power supply Vcc, causing the current between the drain and source of the drive transistor 33 to be supplied to the light-emitting element 32. The switch transistor 34 is composed of, for example, an n-type thin-film transistor (n-type TFT).

[0058] The selection transistor 35 has its gate connected to the scan line 40, one of its source and drain connected to the signal line 42, and the other of its source and drain connected to one electrode of the pixel capacitor 38. The selection transistor 35 is ON or OFF in response to the control signal WS supplied from the scan line 40. When the selection transistor 35 is ON, it applies the signal voltage of the video signal supplied from the signal line 42 to the electrode of the pixel capacitor 38, and accumulates a charge in the pixel capacitor 38 corresponding to the signal voltage. The selection transistor 35 is composed of, for example, an n-type thin-film transistor (n-type TFT).

[0059] The switch transistor 36 has its gate connected to the scan line 40, one of its source and drain connected to the power supply Vref, and the other of its source and drain connected to one electrode of the pixel capacitor 38. The switch transistor 36 is ON or OFF in response to the control signal REF supplied from the scan line 40. When the switch transistor 36 is ON, it sets the electrode of the pixel capacitor 38 to the voltage of the power supply Vref (reference voltage). The switch transistor 36 is composed of, for example, an n-type thin-film transistor (n-type TFT).

[0060] The switch transistor 37 has its gate connected to the scan line 40, one of its source and drain connected to the source of the switch transistor 34 and the drain of the drive transistor, and the other of its source and drain connected to the power supply Vini. The switch transistor 37 is ON or OFF in response to the control signal INI supplied from the scan line 40. The switch transistor 37 turns ON when the drive transistor 33 is ON and the switch transistor 34 is ON and the connection to the power supply Vcc is interrupted, thereby setting the anode of the light-emitting element 32 to the voltage of the power supply Vini (reference voltage). The switch transistor 37 is composed of, for example, an n-type thin-film transistor (n-type TFT).

[0061] The pixel capacitor 38 is a capacitor in which one electrode is connected to the gate of the drive transistor 33, the source of the selection transistor 35, and the source of the switch transistor 36, and the other electrode is connected to the source of the drive transistor 33. The pixel capacitor 38 stores charge corresponding to the signal voltage supplied from the signal line 42. The pixel capacitor 38 stably maintains the voltage between the gate and source electrodes of the drive transistor 33, for example, after the selection transistor 35 and the switch transistor 36 are turned off. In this way, when the selection transistor 35 and the switch transistor 36 are turned off, the pixel capacitor 38 applies a voltage between the gate and source of the drive transistor 33 according to the signal potential due to the stored charge.

[0062] The EL capacitance 39 is a parasitic capacitance inherent in the EL element. After this capacitance charges and the voltage between the electrodes rises, current flows to the EL element, and the EL element begins to emit light.

[0063] Furthermore, the conductivity types of the drive transistor 33, selection transistor 35, switch transistor 36, and switch transistor 37 are not limited to those described above, and n-type and p-type TFTs may be mixed as appropriate. In addition, each transistor is not limited to polysilicon TFTs, but may be composed of amorphous silicon TFTs or the like.

[0064] Next, the operation of the pixel circuit 30 will be described.

[0065] Figure 3A is a timing chart showing the initialization operation of the pixel circuit 30 shown in Figure 2.

[0066] Initialization of the pixel circuit 30 involves applying a reverse bias to the light-emitting element 32 and the EL capacitor 39 to initialize them, and correcting (resetting) the electrode voltage of the pixel capacitor 38 to match the characteristic deviation of the drive transistor 33, before accumulating (writing) the charge corresponding to the signal voltage in the pixel capacitor 38. The initialization period of the pixel circuit 30 is the period during which the light-emitting element 32 and the EL capacitor 39 are initialized by applying a reverse bias, and the electrode voltage of the pixel capacitor 38 is corrected (reset) to match the characteristic deviation of the drive transistor 33. In this embodiment, the light-emitting element 32 is extinguished during the initialization period of the pixel circuit 30. In other words, the initialization period of the pixel circuit 30 is included in the extinguishing period (also called the non-emitting period).

[0067] More specifically, in the pixel circuit 30, as shown in Figure 3A, at time t01 before the extinction period begins, all control signals WS, REF, INI and the extinction signal EN are at a low level. In this state, the selection transistor 35, switch transistor 36, and switch transistor 37 are in the off state because they are n-type transistors. On the other hand, the switch transistor 34 is in the on state because it is a p-type transistor. In other words, in the drive transistor 33, the drain is connected to the power supply Vcc via the on-state switch transistor 34, the source is connected to the anode of the light-emitting element 32, and the gate and source are connected to the electrodes of the pixel capacitor 38. Since charge corresponding to the signal voltage is stored in the pixel capacitor 38, the drive transistor 33 supplies a gate-source current corresponding to the signal voltage to the light-emitting element 32, causing the light-emitting element 32 to emit light.

[0068] Next, at time t02, the start of the extinction period, the extinction signal EN and the control signal INI switch from low level to high level. As the extinction signal EN becomes high level, the switch transistor 34 turns off, and the drain of the drive transistor 33 is disconnected from the power supply Vcc. Therefore, the light emission of the light-emitting element 32 stops (extinguishing). Also, as the control signal INI becomes high level, the switch transistor 37 turns on. When the switch transistor 37 turns on, the anode of the light-emitting element 32 and one electrode of the EL capacitor 39 are connected to the power supply Vini via the drive transistor 33, and the EL capacitor 39 is reverse-biased, causing the capacitor to discharge and be initialized. Note that the selection transistor 35, switch transistor 36, and switch transistor 34 all remain in the off state.

[0069] Next, at time t03, the start of the initialization period, the control signal REF switches from a low level to a high level. As the control signal REF becomes high, the switch transistor 36 turns on, and the gate of the drive transistor 33 and one electrode of the pixel capacitor 38 are connected to the power supply Vref. Since the control signal INI remains high, the switch transistor 37 also remains on. As a result, the gate of the drive transistor 33 is connected to the power supply Vref and the source is connected to the power supply Vini. Similarly, one electrode of the pixel capacitor 38 is connected to the power supply Vref and the other electrode is connected to the power supply Vini, causing the pixel capacitor 38 to discharge and enter an initialized state.

[0070] Subsequently, with switch transistor 36 remaining ON, switch transistors 34 and 37 are turned OFF, and one side of the pixel capacitor 38 is connected to Vref, while the other side is connected to Vcath via EL capacitor 39. The electrode voltage of the pixel capacitor 38 then settles at the threshold voltage of the drive transistor 33.

[0071] Next, at time t04, the end of the initialization period, the control signal REF switches from a high level to a low level. As the control signal REF becomes low, the switch transistor 36 turns off. Furthermore, at time t04, the control signal INI and the extinction signal EN are also low levels, so the switch transistor 34 is on and the switch transistor 37 is off. In other words, the drain of the drive transistor 33 is connected to the power supply Vcc via the on-state switch transistor 34, and the gate and source of the drive transistor 33 are connected to the electrodes of the pixel capacitor 38. However, as described above, the pixel capacitor 38 has been initialized, so the drive transistor 33 does not cause the light-emitting element 32 to emit light.

[0072] Next, at time t05, the control signal WS switches from a low level to a high level. As the control signal WS becomes high, the selection transistor 35 turns on, and the signal voltage of the video signal transmitted via the signal line 42 is written to the pixel capacitor 38. Then, at time t06, the charge corresponding to the signal voltage of the video signal has finished accumulating in the pixel capacitor 38, and the control signal WS switches from a high level to a low level, turning the selection transistor 35 off. As a result, the light-emitting element 32 starts to emit light. In other words, the quenching period ends.

[0073] Figure 3B is a timing chart showing the extinction operation of the pixel circuit 30 shown in Figure 2. Figure 3B shows the case where the pixel circuit 30 performs only the extinction operation and does not perform an initialization operation during the extinction period.

[0074] More specifically, in the pixel circuit 30, as shown in Figure 3B, at time t11 before the extinction period begins, all control signals WS, REF, INI and the extinction signal EN are at a low level. In this state, the selection transistor 35, switch transistor 36, and switch transistor 37 are in the off state. On the other hand, switch transistor 34 is in the on state. In other words, in the drive transistor 33, the drain is connected to the power supply Vcc via the on-state switch transistor 34, the source is connected to the anode of the light-emitting element 32, and the gate and source are connected to the electrodes of the pixel capacitor 38. Since charge corresponding to the signal voltage is stored in the pixel capacitor 38, the drive transistor 33 supplies a gate-source current corresponding to the signal voltage to the light-emitting element 32, causing the light-emitting element 32 to emit light.

[0075] Next, at time t12, the start of the extinction period, the extinction signal EN and the control signal INI switch from low level to high level. As the extinction signal EN becomes high level, the switch transistor 34 turns off, and the drain of the drive transistor 33 is disconnected from the power supply Vcc. Also, as the control signal INI becomes high level, the switch transistor 37 turns on. With the switch transistor 37 turned on, the drain of the drive transistor is connected to the power supply Vini. As a result, the drive transistor 33 no longer supplies current to the light-emitting element 32, so the light emission of the light-emitting element 32 stops and it is extinct. Note that the selection transistor 35, the switch transistor 36, and the switch transistor 34 all remain in the off state.

[0076] Next, at time t13, the end of the extinction period, the extinction signal EN and the control signal INI switch from high level to low level. As the extinction signal EN becomes low level, the switch transistor 34 turns on, and the drain of the drive transistor 33 is connected to the power supply Vcc. Also, as the control signal INI becomes low level, the switch transistor 37 turns off. As a result, the drain of the drive transistor 33 is connected to the power supply Vcc via the ON switch transistor 34, and the gate and source of the drive transistor 33 are connected to the electrodes of the pixel capacitor 38. Since the pixel capacitor 38 still has charge accumulated corresponding to the signal voltage, the drive transistor 33 supplies a gate-source current corresponding to the signal voltage to the light-emitting element 32, causing the light-emitting element 32 to start emitting light.

[0077] [4. Configuration of the control device 20] The control device of this disclosure controls the display of an image by changing the frame length of n (where n is an integer of 2 or more) subframes to reconstruct the frame period, which is the period during which the same image is displayed, when the exact frame period is unknown in advance, even though the frame period fluctuates within a certain range or temporarily stabilizes for each frame. Hereinafter, a control device 20 according to an embodiment of this disclosure will be described as one aspect of this disclosure.

[0078] Next, the configuration of the control device 20 according to this embodiment will be described.

[0079] Figure 4 is a block diagram showing the configuration of the control device 20 provided in the display device 1 according to this embodiment.

[0080] The control device 20 is located outside the display panel 10, for example, on an external system circuit board (not shown). The control device 20 functions as a Timing Controller (TCON) and controls the overall operation of the display device 1. Specifically, the control device 20 outputs gate control signals generated based on the vertical synchronization signal VS, horizontal synchronization signal HS, and video duration signal DE supplied from an external source to the gate drive circuit 14. The control device 20 also supplies digital serial data of video signals R, G, and B to the source drive circuit 16.

[0081] In this embodiment, the control device 20 controls at least the illumination period and the extinction period of a frame period, which is the period during which the same image is continuously displayed. The control device 20 distributes (divides) the extinction period of each frame period by configuring each frame period into a plurality of subframe periods in which the illumination period and the extinction period are repeated at regular intervals. As shown in Figure 4, the control device 20 includes a line buffer 26, a synchronization control unit 28, and a duty control unit 50.

[0082] The line buffer 26 is a buffer that temporarily holds video signals R, G, and B. The line buffer 26 sequentially holds the video signals R, G, and B for each line received from the outside and outputs them to the source drive circuit 16 at a predetermined timing. For example, when the light emission period begins, the line buffer 26 reads the held video signals and outputs them to the source drive circuit 16.

[0083] The synchronization control unit 28 is a control unit for controlling the timing at which video signals R, G, and B are displayed on the display unit 12. The synchronization control unit 28 receives a vertical synchronization signal VS, a horizontal synchronization signal HS, and a video duration signal DE from an external source and outputs them to the duty cycle control unit 50 and the line buffer 26.

[0084] The duty control unit 50 generates gate control signals to control the gate drive circuit 14 so that the video signals R, G, and B are displayed on the display unit 12 at the desired timing. The duty control unit 50 outputs the generated gate control signals to the gate drive circuit 14. In this embodiment, the duty control unit 50 detects the reception of the vertical synchronization signal VS or the video period signal DE. The duty control unit 50 also generates gate control signals to execute multiple subframe periods that repeat the light emission period and the extinction period at regular intervals. As will be described in detail later, when the duty control unit 50 detects a signal indicating the start of a frame period, it generates gate control signals to execute an initialization period during the extinction period in the subframe period following the subframe period executed at the time of detection. Otherwise, when the duty control unit 50 does not detect a signal indicating the start of a frame period, it generates gate control signals to repeatedly execute subframe periods consisting of light emission periods and extinction periods at regular intervals.

[0085] [5. Details of the Duty Control Unit] The details of the duty control unit 50 according to this embodiment will be described below.

[0086] Figure 5 is a diagram illustrating the overview of the duty control performed by the duty control unit 50 according to this embodiment.

[0087] The duty cycle control unit 50 detects a signal indicating the start of a frame period. The signal indicating the start of a frame period may be a vertical synchronization signal VS or a video period signal DE. Hereafter, the frame period will be described as variable, but it may also be fixed.

[0088] The duty control unit 50 generates a gate control signal to cause the gate drive circuit 14 to perform duty control as shown in Figure 5. More specifically, when the duty control unit 50 detects the signal, it generates a gate control signal that, after a predetermined time from the time the signal is detected, sequentially starts n (where n is an integer of 2 or more) subframe periods that constitute the frame period, starting from the first subframe period. This gate control signal controls all of the subframe periods to have a predetermined length, and the duty ratio, which is the ratio of the light emission period to the extinction period in the subframe periods, to be the same predetermined ratio.

[0089] Furthermore, each of the multiple subframe periods is not limited to a predetermined period of the same length, but may consist of periods of approximately the same length (not necessarily exactly the same, but including a range that can be considered the same with a certain margin of error). Similarly, the duty cycle is not limited to a predetermined identical ratio, but may be approximately the same ratio (not necessarily exactly the same ratio, but including a range that can be considered the same ratio with a certain margin of error).

[0090] Furthermore, the duty control unit 50 generates a gate control signal that controls the extinction period in the first subframe period of the n subframe periods to include an initialization period for initializing the multiple pixel circuits 30.

[0091] Furthermore, if a signal indicating the start of the next frame period is detected during the execution of the last subframe period of n subframe periods, this predetermined time will be the period from the time the signal is detected during the last subframe period to the end of that last subframe period.

[0092] As illustrated in the example shown in Figure 5, the duty control unit 50 generates a gate control signal that sets the same duty cycle for each subframe period so that one frame period is composed of multiple subframe periods of the same length, and each subframe period has the same extinction period length. However, the duty control unit 50 generates a gate control signal that includes an initialization period in the extinction period of the first subframe period that constitutes one frame period. Figure 5 shows an example where one frame period is 144 Hz, the subframe period is 720 Hz (1.39 ms), and one frame period is composed of five subframe periods. In the gate control signal shown in Figure 5, the ON state period corresponds to the extinction period, and the hatched ON state period corresponds to the extinction period including the initialization period.

[0093] Next, the detailed configuration of the duty control unit 50 according to this embodiment will be described.

[0094] Figure 6 is a block diagram showing the detailed configuration of the duty control unit 50 according to this embodiment.

[0095] In this embodiment, the duty cycle control unit 50 includes, for example, a light emission control unit 52 and a sequencer 54, as shown in Figure 6.

[0096] The sequencer 54 sets the subframe period to a predetermined length and the duty cycle during the subframe period to a predetermined ratio, and outputs a sequence to the light emission control unit 52 indicating that the subframe periods will be executed continuously. Furthermore, if the sequencer 54 detects a signal indicating the start of a frame period, it outputs to the light emission control unit 52 a sequence indicating that the next subframe period to be executed at the time of detection should include an initialization period in the extinction period.

[0097] As shown in Figure 6, the sequencer 54 includes a sequence control unit 541, a line counter 542, an initialization period counter 543, and an extinction period counter 544.

[0098] The sequence control unit 541 generates a sequence that controls the display timing of video signals R, G, and B based on the vertical synchronization signal VS, horizontal synchronization signal HS, and video duration signal DE supplied from an external source.

[0099] In this embodiment, the sequence control unit 541 detects a signal indicating the start of a frame period. The sequence control unit 541 also acquires the count values ​​output by the line counter 542, the initialization period counter 543, and the extinction period counter 544. Based on the input subframe period length, initialization parameters, and extinction parameters, the presence or absence of the signal detection, and the acquired count values, the sequence control unit 541 generates a sequence to be output to the light emission control unit 52.

[0100] Here, the length of the subframe period is predetermined and fixed by the user. The subframe period is, for example, 720Hz (1.39ms), but is not limited to this. The extinction parameter indicates the extinction period and the start timing of the extinction operation within the subframe period, and is predetermined and fixed by the user. The initialization parameter indicates the initialization period and the start timing of the initialization operation within the subframe period, and is predetermined and fixed by the user. The presence or absence of signal detection refers to whether or not the vertical synchronization signal VS or the video period signal DE has been detected.

[0101] The sequence control unit 541 then generates a sequence from the count values ​​output by the line counter 542, etc., indicating the start timing of a continuous subframe period, and the start and end timings of the extinguishing operation and initialization operation during that subframe period, and outputs it to the light emission control unit 52.

[0102] The line counter 542 is, for example, a timer, and counts independently for each line. The line counter 542 outputs the count value it has counted to the sequence control unit 541. The sequence control unit 541 then uses the count value output by the line counter 542 to determine, for example, the count value indicating the start and end of a subframe period.

[0103] The initialization period counter 543 is, for example, a timer. The initialization period counter 543 counts from the start to the end of the extinction period, which includes the initialization period of the subframe period. The initialization period counter 543 outputs a count value to the sequence control unit 541 when counting begins. The initialization period counter 543 is reset to 0 at the end of the subframe period. The sequence control unit 541 then obtains count values ​​from the count values ​​output by the initialization period counter 543 that indicate the start and end of the extinction period of the subframe period, the start and end of the initialization period, and so on.

[0104] The extinction period counter 544 is, for example, a timer. The extinction period counter 544 counts from the start to the end of the extinction period of the subframe period. The extinction period counter 544 outputs the count value to the sequence control unit 541 when counting begins. The extinction period counter 544 is reset to 0 at the end of the subframe period. The sequence control unit 541 then determines the count values ​​indicating the start and end of the extinction period of the subframe period from the count values ​​output by the extinction period counter 544.

[0105] The light emission control unit 52 generates a gate control signal to control the light emission and extinction of the light-emitting element 32 according to the sequence input by the sequencer 54, and outputs it to the gate drive circuit 14.

[0106] In this embodiment, the light emission control unit 52 generates control signals WS, REF, INI, and quench signal EN as gate control signals according to the sequence input by the sequencer 54, and supplies them to the gate drive circuit 14. For example, the light emission control unit 52 generates gate control signals as shown in the timing chart of Figure 3A or Figure 3B. In this case, time t01 in Figure 3A corresponds to the start of the first subframe period of the frame period. Time t11 in Figure 3B corresponds to the start of the subframe period.

[0107] [6. Operation of the control device] Next, the operation of the control device 20 according to this embodiment will be described.

[0108] Figure 7 is a flowchart illustrating the overview of the operation of the control device 20 according to this embodiment, which controls the light emission period and the extinction period of the frame period.

[0109] As shown in Figure 7, first, the control device 20 constantly checks whether it has detected a signal indicating the start of a frame period (S1). As mentioned above, the signal indicating the start of a frame period is either the vertical synchronization signal VS or the video period signal DE.

[0110] In step S1, if the control device 20 detects a signal indicating the start of a frame period (Yes in S1), it executes a subframe period (initialization) that includes an initialization period in the extinction period after a predetermined time from the time the signal was detected (S2). The subframe period (initialization) is the first subframe period among a plurality of subframe periods that constitute the frame period, and is considered as a frame period.

[0111] Next, the control device 20 executes a subframe period (extinction) (S3). The subframe period (extinction) is a subframe period that, as a frame period, excludes the first subframe period from among the multiple subframe periods that constitute the frame period.

[0112] Next, if the control device 20 detects a signal indicating the start of a frame period while executing the subframe period (extinction) in step S3 (Yes in S4), it returns to step S2 and, after a predetermined time, executes the subframe period (initialization) after the end of the currently executing subframe period (extinction). On the other hand, if the control device 20 does not detect a signal indicating the start of a frame period while executing the subframe period (extinction) (No in S4), it returns to step S3 and executes the subframe period (extinction) after the end of the currently executing subframe period (extinction).

[0113] Next, we will explain the detailed operation when executing the subframe period (initialization) and the subframe period (extinction).

[0114] Figure 8A is a flowchart showing the detailed operation of step S2 shown in Figure 7. Figure 8B is a flowchart showing the detailed operation of step S3 shown in Figure 7. Figure 9 is a diagram showing an example of the detailed operation of the control device 20 according to this embodiment to control the light emission period and extinction period of the frame period. In Figure 9, as an example, an example is shown in which one frame period is 144 Hz, the subframe period is 720 Hz (1.39 ms), and one frame period consists of five subframe periods.

[0115] First, the detailed operation of step S2 shown in Figure 8A will be explained. That is, as shown in Figure 8A, in step S2, the control device 20 starts the subframe period (initialization) after a predetermined time from the time it detects the signal indicating the start of the frame period (S21). In this embodiment, the control device 20 starts the subframe period (initialization) using the count value of the line counter 542. In the example shown in Figure 9, the control device 20 starts SubFrame1 (initialization) after a predetermined time from the time it detects the vertical synchronization signal VS. SubFrame1 (initialization) corresponds to the subframe period (initialization).

[0116] Next, the control device 20 determines whether an offset time of 1 has elapsed since the start of the subframe period (initialization) (S22).

[0117] In step S22, the control device 20 determines from the count value of the line counter 542 that an offset time of 1 has elapsed since the start of the subframe period (initialization) (Yes in S22), and starts the initialization sequence (S23). If the offset time of 1 has not elapsed (No in S22), the control device 20 waits until the offset time of 1 has elapsed. In this embodiment, the control device 20 starts the initialization sequence using the count value of the initialization period counter 543. In the example shown in Figure 9, in SubFrame 1 (initialization), after the offset time of 1 has elapsed, the control device 20 generates a gate control signal with the extinction signal EN and the control signal INI set to high levels and outputs it to the gate drive circuit 14, thereby starting the initialization sequence. This allows the light-emitting element 32 of the pixel circuit 30 of the display panel 10 to be extinguished. The extinction signal EN and the control signals INI, REF, and WS are as explained in Figure 3A, so their explanation is omitted here.

[0118] Next, the control device 20 determines whether initialization is complete (S24). In this embodiment, the control device 20 uses the count value of the initialization period counter 543 to determine that the initialization of the pixel circuit 30 is complete. In the example shown in Figure 9, the control device 20 completes the initialization in SubFrame1 (initialization) according to the count value of the initialization period counter 543, thereby indicating that initialization is complete. After the start of the initialization sequence, the control device 20 generates a gate control signal by setting the extinction signal EN and the control signal INI to a low level, setting the control signal REF to a high level for a certain period of time, and then setting it to a low level, and outputs this to the gate drive circuit 14 to complete the initialization.

[0119] In step S24, the control device 20 determines that initialization is complete based on the count value of the initialization period counter 543 (Yes in S24), and then starts writing to the pixel circuit 30 (S25). In this embodiment, the control device 20 uses the count value of the initialization period counter 543 to perform the writing to the pixel circuit 30. In the example shown in Figure 9, in SubFrame1 (initialization), the control device 20 generates a gate control signal that sets the control signal REF to a low level and then the control signal WS to a high level for a certain period of time, according to the count value of the initialization period counter 543. The control device 20 then outputs the generated gate control signal to the gate drive circuit 14 to start writing.

[0120] Next, the control device 20 determines whether the writing is complete (S26). In this embodiment, the control device 20 uses the count value of the initialization period counter 543 to determine that the writing to the pixel circuit 30 is complete. In the example shown in Figure 9, the control device 20 completes the writing to the pixel circuit 30 in SubFrame1 (initialization) according to the count value of the initialization period counter 543, indicating that the writing is complete.

[0121] In step S26, the control device 20 determines from the count value of the initialization period counter 543 that the write operation is complete (Yes in S26), and then determines whether an offset time of 2 has elapsed since the completion of the write operation (S27).

[0122] In step S27, the control device 20 determines from the count value of the line counter 542 that an offset time of 2 has elapsed since the completion of the write operation (Yes in S27), and terminates the subframe period (initialization) (S28). If the offset time of 2 has not elapsed (No in S27), the control device 20 will wait until the offset time of 2 has elapsed. In this embodiment, the control device 20 terminates the subframe period (initialization) using the count values ​​of the line counter 542 and the initialization period counter 543. In the example shown in Figure 9, the control device 20 terminates SubFrame1 (initialization) when an offset time of 2 has elapsed since the completion of the write operation.

[0123] Next, the detailed operation of step S3 shown in Figure 8B will be described. That is, as shown in Figure 8B, in step S3, the control device 20 starts a subframe period (extinction) following the subframe period (initialization) or the previous subframe period (extinction) (S31). In this embodiment, the control device 20 starts the subframe period (extinction) using the count value of the line counter 542. In the example shown in Figure 9, the control device 20 starts SubFrame2 (extinction) from the end of SubFrame1 (initialization). The control device 20 also starts SubFrame3 (extinction) from the end of SubFrame2 (extinction). The same applies to SubFrame4 (extinction) and SubFrame5 (extinction).

[0124] Next, the control device 20 determines whether an offset time 1 has elapsed since the start of the subframe period (extinction) (S32). Note that the offset time 1 may be set to the same time as the offset time 1 in step S22, or it may be set to a different time.

[0125] In step S32, the control device 20 determines from the count value of the line counter 542 that an offset time of 1 has elapsed since the start of the subframe period (extinction) (Yes in S32), and starts the extinction operation (S33). If the offset time of 1 has not elapsed (No in S32), the control device 20 waits until the offset time of 1 has elapsed. In this embodiment, the control device 20 uses the count value of the extinction period counter 544 to start the extinction operation of the pixel circuit 30. In the example shown in Figure 9, for example, in SubFrame2 (extinction), after the offset time of 1 has elapsed, the control device 20 generates a gate control signal with the extinction signal EN and the control signal INI set to high levels, and outputs it to the gate drive circuit 14 to start the extinction operation (extinction period). This makes it possible to extinguish the light-emitting element 32 of the pixel circuit 30 of the display panel 10. The extinction signal EN and the control signals INI, REF, and WS are as explained in Figure 3B, so their explanation is omitted here.

[0126] Next, the control device 20 determines whether the quenching period has elapsed (S34).

[0127] In step S34, the control device 20 determines from the count value of the extinction period counter 544 that the extinction period of the pixel circuit 30 has ended (Yes in S34), and then causes the light-emitting element 32 of the pixel circuit 30 to emit light again (S35).

[0128] In this embodiment, the control device 20 uses the count value of the extinction period counter 544 to determine when the extinction period of the pixel circuit 30 has elapsed. In the example shown in Figure 9, the control device 20 completes the extinction period of the pixel circuit 30 in SubFrame2 (Extinction) according to the count value of the extinction period counter 544, thereby indicating that the extinction period has been completed. After the extinction period ends, the control device 20 generates a gate control signal that sets the extinction signal EN and the control signal INI to a low level and outputs it to the gate drive circuit 14, thereby completing the extinction period. This allows the control device 20 to re-illuminate the light-emitting element 32 of the pixel circuit 30. In the example shown in Figure 9, the control device 20 generates a gate control signal that sets the extinction signal EN and the control signal INI to a low level in SubFrame2 (Extinction) according to the count value of the extinction period counter 544 and outputs it to the gate drive circuit 14. As a result, the control device 20 can complete the quenching period in SubFrame 2 (quenching) and re-illuminate the light-emitting element 32 of the pixel circuit 30.

[0129] Next, the control device 20 determines whether the offset time 2 has elapsed since the extinction period ended (S36).

[0130] In step S36, the control device 20 determines from the count value of the line counter 542 that an offset time 2 has elapsed since the end of the extinction period (Yes in S36), and terminates the subframe period (extinction) (S37). If the offset time 2 has not elapsed (No in S36), the control device 20 will wait until the offset time 2 has elapsed. In this embodiment, the control device 20 terminates the subframe period (extinction) using the count values ​​of the line counter 542 and the extinction period counter 544. In the example shown in Figure 9, the control device 20 terminates SubFrame2 (extinction) when an offset time 2 has elapsed since the end of the extinction period.

[0131] Note that while Figure 9 above uses the vertical synchronization signal VS as an example to explain the signal indicating the start of a frame period, it is not limited to this. The video period signal DE may also be used. The relationship between the signal indicating the start of a frame period and the duration of one frame will be explained below.

[0132] Figure 10 shows the case in which one frame period is started based on the detection of the vertical synchronization signal VS according to this embodiment. Figure 11 shows the case in which one frame period is started based on the detection of the video period signal DE according to this embodiment. That is, when the vertical synchronization signal VS is detected as a signal indicating the start of a frame period, the frame period should be started in response to the detection of the vertical synchronization signal VS. In this embodiment, when the vertical synchronization signal VS is detected, the first subframe period constituting the frame period indicated by the vertical synchronization signal VS should be started after a predetermined time has elapsed since the detection of the vertical synchronization signal VS (after the end of the subframe period at that time).

[0133] On the other hand, if a video period signal DE is detected as a signal indicating the start of a frame period, the frame period should be started in response to the detection of the video period signal DE. In this embodiment, when the video period signal DE is detected, the first subframe period constituting the frame period indicated by the video period signal DE should be started after a predetermined time has elapsed since the detection of the video period signal DE (after the end of the subframe period at that time).

[0134] (Example 1) The above example uses a frame duration of 144Hz, a subframe duration of 720Hz (1.39ms), and a frame duration composed of five subframe durations, but this is not the only example. Below, we will explain the number of subframe durations when the frame duration varies.

[0135] Figure 12 shows the number of subframe periods that are configured when the frame period according to the embodiment varies. In Figure 12, the frame period is represented by the frame rate, and the subframe period is assumed to be 720 Hz (1.39 ms).

[0136] As shown in Figure 12(a), when the frame period is 144Hz, one frame period consists of 5 subframe periods. Similarly, as shown in Figure 12(b), when the frame period is 120Hz, one frame period consists of 6 subframe periods. As shown in Figure 12(c), when the frame period is 90Hz, one frame period consists of 8 subframe periods. Also, as shown in Figure 12(d), when the frame period is 60Hz, one frame period consists of 12 subframe periods. As shown in Figure 12(e), when the frame period is 48Hz, one frame period consists of 15 subframe periods. As shown in Figure 12(f), when the frame period is 40Hz, one frame period consists of 18 subframe periods.

[0137] Next, we will specifically explain the multiple subframe periods shown in Figures 12(a) to (f) using Figures 13 to 18. Figures 13 to 18 show an example of the detailed operation performed by the control device 20 to control the light emission period and extinction period of the frame period when the frame period according to this embodiment fluctuates. Note that explanations will be omitted for parts that are the same as in Figure 9.

[0138] Figure 13 shows the multiple subframe periods that make up a frame duration of 144Hz. As shown in Figure 13, when the frame duration is 144Hz, one frame duration consists of five subframe periods: SubFrame1 (initialization), SubFrame2 (extinction) to SubFrame5 (extinction).

[0139] Figure 14 shows the multiple subframe periods that are configured when the frame duration is 120 Hz. As shown in Figure 14, when the frame duration is 120 Hz, one frame duration consists of six subframe periods: SubFrame1 (initialization), SubFrame2 (extinction) to SubFrame6 (extinction).

[0140] Figure 15 shows the multiple subframe periods that are configured when the frame duration is 90Hz. As shown in Figure 15, when the frame duration is 90Hz, one frame duration consists of eight subframe periods: SubFrame1 (initialization), SubFrame2 (extinction) to SubFrame8 (extinction).

[0141] Figure 16 shows the multiple subframe periods that are configured when the frame duration is 60Hz. As shown in Figure 16, when the frame duration is 60Hz, one frame duration consists of 12 subframe periods: SubFrame1 (initialization), SubFrame2 (extinction) to SubFrame12 (extinction).

[0142] Figure 17 shows the multiple subframe periods that are configured when the frame duration is 48 Hz. As shown in Figure 17, when the frame duration is 48 Hz, one frame duration consists of 15 subframe periods: SubFrame1 (initialization), SubFrame2 (extinction) to SubFrame15 (extinction).

[0143] Figure 18 shows the multiple subframe periods that are configured when the frame duration is 40 Hz. As shown in Figure 18, when the frame duration is 40 Hz, one frame duration consists of 18 subframe periods: SubFrame1 (initialization), SubFrame2 (extinction) to SubFrame18 (extinction).

[0144] (Example 2) In Example 1, we provided an example where the variable 1-frame duration is divisible by the sub-frame duration, that is, the frame duration is an integer multiple of the sub-frame duration. However, we are not limited to these examples. The frame duration does not have to be an integer multiple of the sub-frame duration.

[0145] The following example of this case will be explained as Example 2.

[0146] Figure 19 is a diagram illustrating the overview of the duty cycle control performed by the duty control unit 50 according to Embodiment 2 of this embodiment. In the example shown in Figure 19, the subframe period is 720 Hz (1.39 ms), but an example is shown where the frame rate representing one frame period is less than 144 Hz and greater than 120 Hz. Also, in the example shown in Figure 19, no signal indicating the start of a frame period, such as the vertical synchronization signal VS, has been detected by the end of the five subframe periods that constitute FrameX, which is the Xth frame period. In this case, the control device 20 executes one additional subframe period (extra in the figure) at the end of the fifth subframe period, which is the last subframe period.

[0147] Figure 20 shows a specific example of duty cycle control performed by the duty control unit 50 according to Embodiment 2 of this embodiment. In the example shown in Figure 20, the subframe period is 720 Hz (1.39 ms), and the example shows a case where one frame period consists of (5 + 1 / 5) subframe periods.

[0148] In this case, the duty control performed by the duty control unit 50 is to add one extra subframe period to the five subframe periods once every five frame periods. In other words, as shown in Figure 20, every five frame periods, the signal indicating the start of a frame period is not detected during the execution of the last (fifth) subframe period. In this case, after the end of the last (fifth) subframe period of the five frame periods, one more subframe period (extra in the figure) should be executed.

[0149] More specifically, when the duty control unit 50 detects a signal indicating the start of a frame period, it sequentially starts n (where n is an integer of 2 or more) subframe periods that constitute the frame period, starting from the first subframe period, after a predetermined time from the time the signal was detected. Here, the duty control unit 50 does not detect a signal indicating the start of the next frame period during the execution of the last subframe period of the n subframe periods. In this case, the duty control unit 50 determines that the frame period is not an integer multiple of the subframe periods and starts one additional subframe period at the end of the last subframe period. Note that all of the one subframe period and the n subframe periods are controlled to be of the same predetermined length. Also, the duty ratio, which is the ratio of the light emission period to the extinction period in the one subframe period and the n subframe periods, is controlled to be the same predetermined ratio.

[0150] In this embodiment as well, when the duty control unit 50 detects a signal indicating the start of a frame period, it generates a gate control signal that includes an initialization period in the extinction period of the subframe period following the subframe period executed at the time of detection. On the other hand, when the duty control unit 50 does not detect a signal indicating the start of a frame period, it only needs to generate a gate control signal that repeatedly executes subframe periods consisting of illumination periods and extinction periods at regular intervals. By performing this control, the duty control unit 50 can distribute the extinction period in the frame period using multiple subframe periods, and repeat the illumination period and extinction period at regular intervals, even when the frame period is not an integer multiple of the subframe period.

[0151] Furthermore, the duty control unit 50 is not limited to determining that a frame period is not an integer multiple of a subframe period when it does not detect a signal indicating the start of the next frame period during the execution of the last subframe period of n subframe periods. In this case, it may determine that the frame period has not yet ended. Specifically, the duty control unit 50 does not detect a signal indicating the start of the next frame period during the execution of the last subframe period of n subframe periods. In this case, the duty control unit 50 determines that the frame period has not yet ended and may start one more subframe period after the end of the last subframe period. Moreover, if the duty control unit 50 does not detect the start of the next frame period by the end of that one subframe period, it may repeatedly execute the subframe period until it detects the start of the next frame period.

[0152] [7. Effects, etc.] First, let me explain the comparative example.

[0153] Figure 21A is a schematic diagram showing an example configuration of the display device 9 according to a comparative example. Figure 21B is a diagram showing the gate waveform output by the synchronous control unit 98 shown in Figure 21A to the gate drive circuit. The same reference numerals are used for elements similar to those in Figure 4, etc., and detailed explanations are omitted.

[0154] As shown in Figure 21A, the comparative example display device 9 comprises a display panel 10 and a control device consisting of a line buffer 26 and a synchronization control unit 98.

[0155] The synchronization control unit 98 starts with the input of the vertical synchronization signal VS and generates a gate driver waveform that includes extinguishing, initialization, and writing operations as shown in Figure 21B.

[0156] However, when generating a gate driver waveform as shown in Figure 21B, if the duration of one frame fluctuates, the period from the extinguishing operation to the writing operation will also fluctuate, making flicker visible. This problem will be explained below with an example.

[0157] Figures 22A and 22B are diagrams illustrating the problems of the comparative example display device 9. Figure 22A shows the light emission period and extinction period for each frame period when the control device of the comparative example keeps the extinction period constant regardless of fluctuations in the frame period. In other words, Figure 22A shows an example in which the length of the extinction period is kept constant even when the frame rate, i.e., the number of vertical lines in one frame period, is changed.

[0158] As shown in Figure 22A, if the extinction period is kept constant regardless of the variation in frame duration, the illumination period becomes longer as the frame rate decreases and shorter as the frame rate increases. Because the illumination period is not repeated at regular intervals, the brightness of the screen is not constant, and the screen appears to flicker, making flicker visible.

[0159] Figure 22B also shows the light emission period and extinction period for each frame period when the control device in the comparative example changes the extinction period in accordance with the variation in the frame period to keep the duty cycle constant. In other words, Figure 22B shows an example in which the length of the extinction period is changed to keep the duty cycle constant when the frame rate is changed.

[0160] As shown in Figure 22B, when the extinction period is changed according to the variation in the frame duration and the duty cycle is kept constant, both the illumination period and the extinction period become longer as the frame rate decreases. As a result, the human eye becomes more likely to perceive flashing, and the screen appears to flicker, making it visible. Furthermore, if the frame duration varies and the number of vertical lines is not known in advance, the total illumination period in one frame is unknown, which presents the problem of not knowing what off-duty cycle should be set.

[0161] In contrast, the control device 20 according to this embodiment divides one frame period into multiple subframe periods of a fixed length and executes them, thereby distributing the extinction period within the frame period and repeating the light emission period and extinction period at fixed intervals. Furthermore, even if the number of vertical lines is not known in advance, and the frame period always or sometimes fluctuates greatly, it is possible to repeat on-duty and off-duty periods of predetermined lengths at a fixed period called a subframe period.

[0162] This makes it possible to prevent flicker from being visible on the display panel showing the image, even if the frame duration fluctuates significantly. In other words, it can suppress the flicker phenomenon even when the frame duration changes.

[0163] Furthermore, according to the control device 20 of this embodiment, if a signal indicating the start of the next frame period is detected during the execution of the last subframe period constituting the frame period, the first subframe period of the next frame period is started immediately following the last subframe period. This allows for easy tracking of fluctuations in the frame period, thereby suppressing the flicker phenomenon even when the frame period fluctuates.

[0164] Furthermore, according to the control device 20 of this embodiment, even if the frame period is not an integer multiple of a predetermined subframe period, multiple subframe periods can be used to repeat the light emission period and the extinction period at regular intervals, thereby preventing flicker from being visible.

[0165] Furthermore, according to the control device 20 of this embodiment, by including an initialization period for initializing multiple pixel circuits in the extinction period placed at the beginning of the frame period, the image display during the frame period can be performed appropriately.

[0166] Furthermore, the control device 20 according to this embodiment may support Adaptive-Sync. In other words, the control device 20 according to this embodiment may dynamically change the number of subframe periods that constitute the frame period in accordance with the input video signal, in accordance with a standard that makes the rendering start timing variable according to the processing time of the GPU. More specifically, the frame period may be variable, and furthermore, the frame period may be dynamically changed in accordance with Adaptive-Sync. Here, Adaptive-Sync is a technology for avoiding stuttering or tearing issues by rendering the screen in accordance with the completion timing of the GPU's frame processing, and can adjust the refresh rate of the display device in real time. By the control device 20 according to this embodiment supporting Adaptive-Sync, for example, when the frame rate does not reach the fastest frame rate of the display device, the display start timing can be delayed to wait for the GPU to finish processing, and rendering can be started as soon as possible after processing is completed, thereby maintaining the highest possible frame rate. In addition to what is defined as the Adaptive-Sync standard, G-SYNC and FreeSync, which are defined as certification specifications by GPU vendors, are also known.

[0167] Thus, the control device 20 according to this embodiment may support certification standards such as G-SYNC and FreeSync, as well as the Adaptive-Sync standard. In this case, it is possible to suppress the occurrence of flicker while following large synchronization fluctuations.

[0168] (Variation 1) The configuration of the pixel circuit 30 in the above embodiment has been explained with reference to Figure 2, but is not limited to this. Hereinafter, a configuration example different from the pixel circuit 30 shown in Figure 2 will be described as Modification Example 1.

[0169] Figure 23A is a schematic circuit diagram showing an example of the configuration of the pixel circuit 30A according to Modification 1 of this embodiment. Figure 23B is a schematic circuit diagram showing another example of the configuration of the pixel circuit 30B according to Modification 1 of this embodiment. The same reference numerals are used for elements similar to those in Figure 2, and detailed explanations are omitted.

[0170] In other words, the pixel circuit 30 shown in Figure 2 may be the pixel circuit 30A shown in Figure 23A, or the pixel circuit 30B shown in Figure 23B.

[0171] Pixel circuit 30A differs from pixel circuit 30 shown in Figure 2 in that it does not include switch transistors 34 and 36.

[0172] Since the pixel circuit 30A does not have a switch transistor 34, the switch transistor 37 controls the illumination or extinction of the light-emitting element 32, i.e., the illumination or extinction operation of the pixel circuit 30A. Also, since the pixel circuit 30A does not have a switch transistor 36, the switch transistor 37 controls the initialization operation.

[0173] More specifically, the extinguishing operation of the pixel circuit 30A is performed as follows: When the control signal AZ is applied from the gate drive circuit 14 to the gate of the switch transistor 37, and the switch transistor 37 is turned ON, the drain-source current of the drive transistor 33 flows to the switch transistor 37 and does not flow to the light-emitting element 32. As a result, the light-emitting element 32 is extinguished. The light-emitting operation of the pixel circuit 30A is performed as follows: When the application of the control signal AZ to the gate of the switch transistor 37 is stopped, and the switch transistor 37 is turned OFF, the drain-source current of the drive transistor 33 flows to the light-emitting element 32. As a result, the light-emitting element 32 emits light.

[0174] Furthermore, the pixel circuit 30B differs from the pixel circuit 30 shown in Figure 2 in that it does not have a switch transistor 34. Since the pixel circuit 30B does not have a switch transistor 34, the switch transistor 37 controls the illumination or extinction of the light-emitting element 32, that is, the illumination or extinction operation of the pixel circuit 30A.

[0175] More specifically, the extinguishing operation of the pixel circuit 30B is performed as follows: When the control signal INI is applied from the gate drive circuit 14 to the gate of the switch transistor 37, and the switch transistor 37 is turned on, the drain-source current of the drive transistor 33 flows to the switch transistor 37 and does not flow to the light-emitting element 32. Therefore, the light-emitting element 32 is extinguished. The light-emitting operation of the pixel circuit 30B is performed as follows: When the application of the control signal INI to the gate of the switch transistor 37 is stopped, and the switch transistor 37 is turned off, the drain-source current of the drive transistor 33 flows to the light-emitting element 32. As a result, the light-emitting element 32 emits light.

[0176] The configuration of the pixel circuit of the display device 1 is not limited to the configuration described above. For example, as long as the configuration includes a drive transistor, a selection transistor, and a pixel capacitor, the arrangement of other switch transistors may be changed as appropriate. Also, the multiple transistors provided in the pixel circuit may be polysilicon TFTs, or they may be composed of other transistors such as amorphous silicon TFTs. Furthermore, the conductivity type of the transistors may be n-type, p-type, or a combination of both.

[0177] (Modification 2) In the above embodiment, the pixel circuit of the display device 1 was described as comprising an organic EL element light-emitting element, but it is not limited to this. The pixel circuit may also comprise a liquid crystal.

[0178] Figure 24 is a schematic circuit diagram showing an example of the configuration of a pixel circuit 30C according to a modified example 2 of this embodiment. As shown in Figure 24, the pixel circuit 30C does not have a light-emitting element, but includes a capacitor, liquid crystal, diode, and drive transistor. In other words, the pixels constituting the display panel 10 that displays images may be made of liquid crystal elements, and the pixel circuit of the display device 1 may also be applied to liquid crystal.

[0179] Furthermore, if liquid crystal is applied to the display device 1, the display device 1 may also have a backlight that performs backlight scanning. Here, backlight scanning is a technique that sequentially turns off the backlight near the line containing the pixel to be rewritten. Also, the backlight of a liquid crystal is not usually synchronized with the video. However, in this modified example, when performing backlight scanning, it is operated in synchronization with the video, and the illumination period is defined as the period during which the backlight is lit during backlight scanning, and the extinguishing period is defined as the period during which the backlight is turned off.

[0180] This makes it possible to prevent flicker from being visible on a liquid crystal display panel even if the frame duration of the backlight scan fluctuates significantly. In other words, it is possible to suppress the flicker phenomenon on a liquid crystal display panel even if the frame duration fluctuates.

[0181] Figure 25 shows an example of a frame duration timing chart for backlight scanning according to Modification 2 of this embodiment. In Figure 25, an example is shown where one frame duration is 144 Hz, the subframe duration is 720 Hz (1.39 ms), and one frame duration consists of five subframe durations. In Figure 25, the ON state of the backlight signal corresponds to the illumination period, and the OFF state of the backlight signal corresponds to the extinguishing period. In Figure 25, a timing chart for the leading line is shown, with the backlight turned off before and after the line is rewritten.

[0182] Thus, even when liquid crystal is applied to the display device 1, by repeating on-duty and off-duty cycles of predetermined lengths at a fixed period called the subframe period, it is possible to prevent flicker from being visible on the display panel that displays the image, even if the frame period fluctuates significantly.

[0183] (Other embodiments) (1) In the above embodiments and modifications, the fluctuating frame period is reconfigured into a plurality of subframe periods, each having approximately the same length, and executed, with the light emission period and extinction period repeated at approximately constant intervals. However, the invention is not limited to this. If a signal indicating the start of a frame period is detected during the execution of a subframe period added after the end of the last subframe period, the added subframe period may be terminated midway and the next frame period may be started.

[0184] Figure 26 shows an example of the detailed operation of a control device that controls the light emission period and extinction period of a frame period when the frame period fluctuates according to another embodiment.

[0185] In Figure 26, a signal indicating the start of a frame period is detected within a threshold (a time below the threshold) after the start of the added subframe period. Then, the added subframe period is terminated midway, and the next frame period begins.

[0186] More specifically, the frame length of a subframe period is changed so that the frame period is reconstructed with n (where n is an integer greater than or equal to 2) subframe periods, regardless of the input frame period. Then, if a signal indicating the start of the next frame period is detected during a subframe period added after the execution of the last subframe period, and the detection timing is less than or equal to a certain threshold time from the start of the added subframe period, the added subframe period may be terminated midway and the next frame period may start.

[0187] In this way, if a signal such as a vertical synchronization signal is detected within a time period below a threshold from the start of the added subframe period, the added subframe period is terminated prematurely, and the first subframe period constituting the next frame period is started. This extends the frame period, but if the extension is small, the change in brightness becomes sufficiently small. As a result, the flicker phenomenon can be suppressed even when the frame period fluctuates.

[0188] (2) In addition, although it has been explained that in the above embodiments and modifications the duty cycles of each of the multiple subframe periods constituting the fluctuating frame period are controlled to be substantially the same ratio as predetermined, the invention is not limited thereto. Depending on the unique light emission characteristics of the display panel 10, the duty cycles of each of the multiple subframe periods constituting the frame period may be finely adjusted.

[0189] This will be explained below using Figures 27A to 29, with the example of a frame duration of 144Hz.

[0190] Figure 27A shows an example of duty cycle waveforms in multiple subframe periods when the frame duration is 144 Hz. Explanations of aspects similar to those in Figure 13 are omitted.

[0191] In the example shown in Figure 27A, each of the five subframe periods—SubFrame1 (initialization), SubFrame2 (extinction) to SubFrame5 (extinction)—has a roughly constant extinction period. In other words, in each of the five subframe periods, the duty cycle, which is the ratio of the illumination period to the extinction period, is controlled to be the same predetermined ratio. If we represent this using a duty cycle waveform with the illumination period as high and the extinction period as low, we get the duty cycle waveform shown at the bottom of Figure 27A.

[0192] Figure 27B shows an example of an actual light emission waveform relative to the duty cycle waveform shown in Figure 27A. In the above embodiments and modifications, the display panel 10 was described as displaying an image (video) using a light emission waveform that follows the duty cycle waveform shown in Figure 27A. However, since the display panel 10 actually has its own unique light emission characteristics, it will display an image (video) using the actual light emission waveform shown in Figure 27B.

[0193] Figure 28 shows the actual emission waveform and its average brightness when the extinction period is excluded from the actual emission waveform during one frame period shown in Figure 27B. The actual emission waveform shown in Figure 28 is distorted, with an upward deviation (overshoot) in the first emission period and a gradual decrease (not constant) in subsequent emission periods.

[0194] More specifically, in Figure 28, the light emission waveform overshoots in the s region during the first light emission period. This occurs because the pixels of the display panel 10 (pixel circuit 30 in Figure 2) are initialized before the first light emission period, causing the parasitic capacitance of the light-emitting element 32 of the pixels to be empty. Ideally, during the subsequent light emission periods after initialization, the current corresponding to the signal voltage of the video signal flowing to the drive transistor 33 flows through the light-emitting element 32, due to the pixel capacitance 38 (Cs) written after initialization. However, in reality, the parasitic capacitance of the light-emitting element 32 in the pixels is initialized and becomes empty before the first light emission period, so the parasitic capacitance of the light-emitting element 32 is also charged during the first light emission period. In other words, during the first light emission period, a current larger than the current corresponding to the signal voltage of the video signal flows through the light-emitting element 32, due to the charge in the parasitic capacitance of the light-emitting element 32. As a result, the light emission waveform overshoots in the s region during the first light emission period, and the average brightness becomes higher than the target brightness.

[0195] On the other hand, in Figure 28, in the t region spanning from the middle of the first emission period to the third emission period, the emission waveform gradually decreases, and in the u region spanning the fourth and fifth emission periods, the decrease in the emission waveform is minimal. This can be explained using Figure 2 as an example. Ideally, the charge written to the pixel capacitance 38(Cs) after initialization is maintained throughout multiple emission periods after initialization. However, in reality, the charge written to the pixel capacitance 38(Cs) after initialization leaks out gradually, albeit very slowly, and the amount of leakage gradually decreases. As a result, in the t region, the average brightness gradually decreases with the passage of time in the emission period, and in the u region, the average brightness decreases (or is maintained) very gradually with the passage of time in the emission period.

[0196] Therefore, as shown in Figure 29, the duty cycle of each of the multiple subframe periods that make up the frame period is fine-tuned.

[0197] Figure 29 is a diagram illustrating a method for adjusting the duty cycle of multiple subframe periods according to another embodiment. Figure 29(a) shows the actual emission waveform shown in Figure 27B. Figure 29(b) shows a duty cycle waveform with a predetermined duty cycle adjusted to the actual emission waveform shown in Figure 29(a). Figure 29(c) shows the average brightness obtained by the duty cycle waveform with the duty cycle adjusted as shown in Figure 29(b).

[0198] More specifically, as shown in Figures 29(b) and (c), the length of the first and third to fifth emission periods is adjusted by adjusting a predetermined duty cycle so that the resulting average brightness is constant (uniform).

[0199] More specifically, the duty cycle is adjusted so that the length of the first overshoot illumination period is shortened. In other words, the duty cycle is adjusted so that the illumination period following the extinction period in the first subframe period among multiple subframe periods is shorter than the length determined by a predetermined, approximately identical duty cycle. This suppresses the effects of overshoot caused by the illumination characteristics specific to the display panel.

[0200] Furthermore, the duty cycle is adjusted so that the length of the third to fifth emission periods, during which the emission waveform decreases, is longer. Also, the duty cycle is adjusted so that the length of the fourth to fifth emission periods is longer than the length of the third emission period. As a result, the average brightness shown in Figure 29(c) becomes constant.

[0201] Furthermore, the duty cycle of each of the multiple subframe periods should be adjusted according to the frame rate, i.e., the length of the frame period. The degree to which the duty cycle of each of the multiple subframe periods is adjusted depends on the display panel's specific light emission characteristics (actual light emission waveform), and can therefore be determined at the time the display panel is manufactured. For this reason, the degree to which the duty cycle of each of the multiple subframe periods is adjusted can be predetermined for each frame rate.

[0202] Furthermore, the decrease in average brightness due to the degradation (smearing) of the actual emission waveform, as explained in Figure 28, is not very noticeable up to frame rates of around 60 Hz, as illustrated by the frame duration examples given in Figure 12. However, it becomes noticeable at frame rates of 48 Hz and 30 Hz. This is because, at frame rates of around 48 Hz and 30 Hz, the leakage of pixels (charge with pixel capacitance 38) can no longer be ignored due to the length of the emission period.

[0203] As described above, the duty cycle of each of the multiple subframe periods may be further adjusted on a subframe period basis according to the frame rate. This makes it possible to suppress the average brightness of each of the multiple subframe periods constituting one frame period from deviating from the target brightness due to the light emission characteristics specific to the display panel. Thus, it is possible to suppress the flicker phenomenon while suppressing the influence of the light emission characteristics specific to the display panel 10.

[0204] (3) Furthermore, this disclosure is not limited to the configurations described in the embodiments and modifications above, and may be modified as appropriate.

[0205] Although control methods and control devices relating to one or more embodiments of the present disclosure have been described above based on embodiments, the present disclosure is not limited to these embodiments. Without departing from the spirit of the present disclosure, various modifications to these embodiments that a person skilled in the art could conceive of, or forms constructed by combining components from different embodiments, may also be included within the scope of one or more embodiments of the present disclosure. [Industrial applicability]

[0206] This disclosure is particularly useful in technical fields such as television systems, game consoles, and personal computer displays where high-speed and high-resolution display is required. [Explanation of Symbols]

[0207] 1, 9 Display device 10 Display Panel 12 Display section 14 Gate drive circuit 16 Source drive circuit 20 Control device 26 line buffer 28 Synchronization Control Unit 30, 30A, 30B, 30C Pixel Circuits 32 Light-emitting elements 33 drive transistors 34, 36, 37 Switch transistors 35 Selective Transistors 38 pixels capacity 39EL capacity 40 scan lines 42 signal lines 50 Duty Control Unit 52 Light emission control unit 54 Sequencer 541 Sequence Control Unit 542 Line Counter 543 Initialization Period Counter 544 Extinction Period Counter

Claims

1. A control method for when the frame duration, which is the period during which the same image is displayed, fluctuates and the exact frame duration is unknown in advance, Regardless of the input frame duration, each frame of the frame duration is reconstructed using n (where n is an integer greater than or equal to 2) subframe durations, or (n+1) subframe durations, each of which has a predetermined, approximately identical length. Each of the n subframe periods, or (n+1) subframe periods, is a period that is less than or equal to the aforementioned approximately the same length. The (n+1) subframe periods include additional subframe periods which are subframe periods executed after the execution of the first n subframe periods among the (n+1) subframe periods. Each of the n subframe periods has an emission period and an extinction period. The duty cycle, which is the ratio of the light emission period to the extinction period, is controlled to be a predetermined, approximately identical ratio. If a signal indicating the start of the next frame period is detected during the aforementioned additional subframe period, and the detection timing is within a certain threshold time from the start of the additional subframe period, the additional subframe period is terminated midway through the additional subframe period and the next frame period is started. Control method.

2. The signal indicating the start of the aforementioned frame period is either a vertical synchronization signal or a video period signal at the beginning of the frame. The control method according to claim 1.

3. The aforementioned frame period dynamically varies the number of the n subframe periods that constitute the frame period in accordance with the input video signal, in accordance with a standard that allows the rendering start timing to be varied according to the GPU processing time. The control method according to claim 1 or 2.

4. Furthermore, the duty cycle of each of the n subframe periods constituting the frame period is adjusted according to the light emission characteristics of the display panel on which the image is displayed. The control method according to any one of claims 1 to 3.

5. When adjusting the duty cycle of each of the n subframe periods, The duty cycle is adjusted such that the emission period following the extinction period in the first subframe period of the n subframe periods is shorter than the length determined by the substantially same ratio. The control method according to claim 4.

6. The pixels constituting the display panel that displays the aforementioned image consist of light-emitting elements that emit light by current drive, including organic EL elements. The control method according to any one of claims 1 to 5.

7. The extinction period in the first subframe period of the n subframe periods includes an initialization period for initializing a plurality of pixel circuits arranged in a matrix, which are present in the display panel that displays the image. The control method according to claim 6.

8. The pixels constituting the display panel that displays the aforementioned image are made of liquid crystal elements. Each of the n subframe periods has an emission period and an extinction period. The aforementioned light emission period is the period during which the backlight is turned on in the backlight scan. The aforementioned blackout period is the period during which the backlight is turned off. The control method according to any one of claims 1 to 5.

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