Independently addressable high-power surface-emitting laser array with tightly pitched implementation

Abstract

To provide semiconductor lasers, more particularly to provide independently-addressable vertical cavity surface-emitting laser architectures that can produce high power and accommodate tight-pitch packing.SOLUTION: A semiconductor surface-emitting laser array includes a group of independently addressable light-emitting pixels arranged in at least two rows and in a linear array on a common substrate chip and including a common cathode and a dedicated channel associated with an address trace line for each pixel. An aggregate linear pitch can be achieved between pixels of the at least two rows along the linear array in a cross process direction, the aggregate linear pitch being less than the size of a pixel. The semiconductor laser array can include two or more common substrate chips tiled and stitched together in a staggered arrangement to provide an at least 11-inch wide, 1,200 pdi imager with timing delays associated with each of the two or more common substrate chips in the staggered arrangement.SELECTED DRAWING: Figure 10A

Description

[[Technical Field]]

[0001] Embodiments relate to semiconductor lasers. More specifically, embodiments relate to systems and methods for providing independently addressable vertical cavity surface emitting laser (VCSEL) architectures capable of generating high power and accommodating tight pitch packaging. [[Background Art]]

[0002] VCSELs are semiconductor-based lasers capable of emitting light perpendicular to a substrate. When properly designed, technical applications of VCSEL arrays may include data communication systems, light detection and ranging (lidar) systems, printing systems, laser processing systems, zone heating or curing, lighting systems, 3D mapping systems, and face recognition devices (e.g., smartphone face identification).

[0003] High-power surface emitting lasers typically require large apertures because the light emitting region of the device needs to be sufficiently large to maintain the required high optical output. For example, a typical aperture of a vertical cavity surface emitting laser (VCSEL) capable of generating an optical output of 50 mW needs to be about 18 µm or more in diameter. The overall device size will be even larger because the device structure typically includes oxide channels and electrical contacts extending beyond the aperture.

[0004] One of the key advantages of VCSELs is that, if properly positioned, hundreds or thousands of individual emitters can be patterned into a high-density array, each acting as a pixel. This will be important because, depending on the application, it may be necessary to implement high-power surface-emitting lasers in a tightly pitched array where the linear pitch is comparable to or smaller than the normal dimensions of the device. For example, in a 1200 dpi printing application, if each laser pixel in the array is used to address a single dot on the image, the required linear spacing between laser address lines would be approximately 21.2 μm. This linear pitch is tighter than the size of current semiconductor laser devices capable of producing 50 mW of optical output. Today's efficient or high-intensity semiconductor lasers often operate in the wavelength range of 550 nm to 1000 nm. The very close spacing between lasers in such arrays can lead to thermal crosstalk, as heat from each laser can affect the performance of nearby lasers. Also, the total power drop from a large number of high-power lasers operating in a small area can result in a high thermal load density that must be dissipated.

[0005] What is needed is an independently addressable VCSEL architecture that can generate high power at resolutions exceeding 300 dpi, overcome thermally induced drawbacks, and accommodate tightly pitched implementations. [Overview of the Initiative]

[0006] The following summary is provided to facilitate understanding of some of the innovative features specific to the disclosed embodiments and is not intended to be a complete description. A complete understanding of the various aspects of the embodiments disclosed herein can be obtained by looking at the entire specification, claims, drawings, and abstract together.

[0007] According to the embodiments, a semiconductor laser (e.g., VCSEL) architecture is disclosed that can achieve a digital addressability of 300 to at least 1200 DPI. This architecture may have features including improved laser array design, improved laser array geometry, and chip tiling. In the printing embodiment, for example, VCSELs operating as pixels and deployed in array form can deliver laser power up to 50 milliwatts and above with an aperture size that can enable high resolution (e.g., >300 dpi).

[0008] According to one embodiment, the semiconductor laser array can be used, for example, as an individually addressable light source in a DALI (Digital Architecture for Lithographic Inks) printing process, taking advantage of the dramatically reduced size and complexity compared to the laser imager, which is the most sophisticated component in the printing system.

[0009] According to embodiments, large-area, high-power VCSEL arrays such as those presented herein may also be useful for a variety of applications, including facial recognition, laser sintering, non-contact thermochromic printing, zone heating and curing, and lidar applications.

[0010] According to one embodiment, the semiconductor surface-emitting laser array comprises a plurality of independently addressable light-emitting pixels arranged in a linear array in at least two columns on a common substrate chip, each including a common cathode and a dedicated channel associated with the address trace line of each pixel, wherein the dense linear pitch between pixels in at least two columns along the linear array in the cross-process direction is smaller than the size of the pixel.

[0011] According to one embodiment, each independently addressable pixel further includes at least one laser aperture, each of which further includes an asymmetric aperture shape.

[0012] According to the embodiment, the address trace lines associated with each of the multiple independently addressable pixels for each of at least two rows are manufactured to have a dense linear pitch of 22 micrometers or less.

[0013] According to the embodiment, the address trace line is manufactured with low sheet resistance and a width that allows for a trace voltage drop of less than 50% of the voltage drop across the activation pixel at the laser oscillation threshold current.

[0014] According to one embodiment, the electrical contact pads are associated with each address trace line to each independently addressable semiconductor laser, and each electrical contact pad is configured to accept wire bonding.

[0015] According to the embodiment, the semiconductor laser array may include a mounting and cooling architecture that can maintain the laser operating temperature and efficiency.

[0016] According to one feature of the embodiment, the semiconductor laser array may include direct die bonding to a 3D submount having integrated cooling channels.

[0017] According to another feature of the embodiment, the semiconductor laser array may include the movement of a VCSEL epitaxial layer onto a metal host substrate.

[0018] According to another feature of the embodiment, the semiconductor laser array can implement image frame phase delay addressing.

[0019] According to another feature of the embodiment, the semiconductor laser array can use a self-foc lens array.

[0020] According to yet another feature of the embodiment, the semiconductor laser array can be integrated onto a 3D submount.

[0021] According to another feature of the embodiment, the semiconductor laser array can incorporate a multi-row structure interposer design including fan-in for ASIC placement tolerance. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Like reference numerals refer to the same or functionally similar elements throughout the separate drawings, and the accompanying drawings, which are incorporated in and form a part of the present specification, further illustrate the present invention and serve to explain the principles of the embodiment together with the detailed description of the present invention. [Figure 1] 1 shows the architecture of a 1200 dpi pitch independently addressable high power laser array according to an embodiment. [Figure 2] 2 shows an exemplary block diagram of a layout and dimensions according to an embodiment, which can meet the objectives of high-resolution laser oscillation and image formation by staggering the arrangement of bond pads and trace lines. [Figure 3] 3 shows an exemplary block diagram of wire bonding connections of individual lasers to their associated driver chips according to an embodiment. [Figure 4] 4 shows a block diagram of an 11-inch wide VCSEL imager for a 1200 dpi printing system that may be constructed from a plurality of tiled laser array chips according to an embodiment. [Figure 5] 5 shows a block diagram of laser array chips arranged in a staggered arrangement according to an embodiment. [Figure 6] 6 shows an optical micrograph of a portion of a 1200 dpi laser array utilizing an asymmetric laser aperture design according to an embodiment. [Figure 7] 7 shows a chart of light output versus current curves of a device at various substrate temperatures, exhibiting a peak output power of more than 50 mW, according to an embodiment. [Figure 8] 8 shows an optical micrograph of a portion of a 1200 dpi laser array utilizing a common anode multi-aperture pixel design according to an embodiment. [Figure 9]shows a chart of optical output versus current curves for one two-aperture common anode device at various substrate temperatures, exhibiting peak output power exceeding 50 mW, according to an embodiment. [Figure 10A] shows an optical micrograph of a portion of a 1200 dpi laser array utilizing a common anode three-aperture pixel design, according to an embodiment. [Figure 10B] shows an enlarged view of the three-aperture pixel of FIG. 10(a), revealing 6-level staggering in the process direction, according to an embodiment. [Figure 11] shows a back view of a submount, illustrating how a cooling fluid tube may be attached to the submount and also illustrating how integrated mounting holes may be formed in the submount for mounting optical elements, according to an embodiment. [Figure 12A] shows a front view of a lens array that can be used with a semiconductor laser array. [Figure 12B] shows a front view of a lens array that can be used with a semiconductor laser array. [Figure 12C] shows a front view of a lens array that can be used with a semiconductor laser array. [Figure 12D] shows a three-point perspective view of an imaging optical system including a four-row GRIN lens array that can be used with the VCSEL arrays described herein, according to an embodiment. [Figure 13] shows a graph of calculated optical transmittance versus source beam divergence for various laser spatial mode profiles, according to an embodiment. [Figure 14A] shows a photograph of a four-row GRIN lens array (GLA) constructed from two modified two-row SLAs, according to an embodiment. [Figure 14B] shows an optical micrograph of the combined two-row GLA of FIG. 14A, according to an embodiment. [Figure 15A] shows a block diagram of a staggered imaging system for a laser array, according to an embodiment. [Figure 15B]An example of VCSEL scroll timing using a 4-row VCSEL laser array 170 having two apertures, according to an embodiment, is shown. [Figure 16] An embodiment of a feathered imaging system for a laser array is shown. [Figure 17] This example shows an electrical thin-film routing layout for an interposer chip architecture that fans out tightly pitched contact pads on a laser array to wider-pitch contacts on a PCB or driver chip. [Figure 18A] The graph shows the calculated temperature versus substrate thickness at various locations on the laser chip surface according to the embodiment. [Figure 18B] The diagram shows the layout of the laser chip surface according to the embodiment, where the temperature profile is shown across the surface. [Figure 19A] The process steps for transferring the epitaxial layer of a VCSEL array to a metal host substrate according to an embodiment are shown. [Figure 19B] The process steps for transferring the epitaxial layer of a VCSEL array to a metal host substrate according to an embodiment are shown. [Figure 19C] The process steps for transferring the epitaxial layer of a VCSEL array to a metal host substrate according to an embodiment are shown. [Figure 19D] The process steps for transferring the epitaxial layer of a VCSEL array to a metal host substrate according to an embodiment are shown. [Figure 19E] The process steps for transferring the epitaxial layer of a VCSEL array to a metal host substrate according to an embodiment are shown. [Figure 20] Labeled as prior art, the diagram shows components of a printing system incorporating a laser array for inducing the evaporation of dampening solution via laser patterning and associated printing steps, according to an embodiment. [Figure 21A] The diagram shows the components of a completed VCSEL array-based image forming member according to an embodiment. [Figure 21B]Figure 21A shows a side perspective view of the completed VCSEL array-based image forming member. [Figure 22] A block diagram of an electronic module operating as part of a printing system, according to an embodiment, is shown. [Figure 23A] This shows a block diagram of the programming state during printing when using VCSEL for document processing according to the embodiment. [Figure 23B] This shows a block diagram of the programming state during printing when using VCSEL for document processing according to the embodiment. [Figure 24] A block diagram is shown illustrating the possible functions in the main module of a printing system incorporating the use of a VCSEL array, according to the embodiment. [Figure 25] Another block diagram is shown illustrating the possible functions in the main module of a printing system incorporating the use of a VCSEL array, according to the embodiment. [Modes for carrying out the invention]

[0023] The specific values ​​and configurations discussed in these non-limiting embodiments may be modified and are cited merely to illustrate one or more embodiments, and are not intended to limit their scope.

[0024] Herein, the subject matter is described in more detail below with reference to the accompanying drawings, which form part of this specification and illustrate specific exemplary embodiments. However, the subject matter may be embodied in various different forms, and therefore the subject matter covered or claimed is intended to be construed as not being limited to any exemplary embodiments described herein. The exemplary embodiments are provided for illustrative purposes only. Similarly, a fairly broad range is intended for the subject matter claimed or referred to. In particular, for example, the subject matter may be embodied as a method, device, component, or system. Thus, embodiments may take the form of, for example, hardware, software, firmware, or any combination thereof (other than software itself). Accordingly, the embodiments for carrying out the invention described below are not intended to be construed as restrictive.

[0025] Throughout this specification and the claims, terms may have nuances implied or suggested meanings beyond their expressly stated meanings. Similarly, when used herein, phrases such as “in one embodiment” or “in an exemplary embodiment” and variations thereof do not necessarily refer to the same embodiment, and when used herein, phrases such as “in another embodiment” or “in another exemplary embodiment” and variations thereof may or may not refer to a different embodiment. For example, the claimed subject matter is intended to include all or some combinations of exemplary embodiments.

[0026] In general, terms can be understood at least partially from their use in context. For example, terms such as “and,” “or,” or “and / or” as used herein may have various meanings that depend at least partially on the context in which such terms are used. Typically, when “or” is used to relate a list such as A, B, or C, it is intended to mean A, B, and C in an inclusive sense, as well as A, B, or C in an exclusive sense. In addition, when used herein, the term “one or more” may be used at least partially on the context to describe any feature, structure, or characteristic in a singular sense, or to describe a combination of features, structures, or characteristics in a plural sense. Similarly, terms such as “a,” “an,” or “the” can also be understood, at least partially on the context, to convey either a singular or plural use. In addition, the term “based on” is not necessarily intended to convey an exclusive set of factors, but rather, likewise at least partially on the context, may be understood to anticipate the presence of additional factors that are not necessarily explicitly stated.

[0027] Specific terminology is used in the following description for clarity, but these terms are intended to refer only to specific structures of embodiments selected for illustrative purposes in the drawings and are not intended to define or limit the scope of this disclosure. In the following drawings and description, similar numerical notations should be understood to refer to components of similar function.

[0028] Embodiments are not limited in this respect, but as used herein, the terms “plurality” and “a plurality” may include, for example, “multiple” or “two or more.” The terms “plurality” or “a plurality” may be used throughout this specification to describe two or more components, devices, elements, units, parameters, etc. For example, “multiple stations” may include two or more stations. Terms such as “first,” “second,” etc., as used herein do not indicate any order, quantity, or importance, but rather may be used to distinguish one element from another. The terms “a” and “an” as used herein may not indicate a limit on quantity, but rather may indicate the presence of at least one of the items being referenced.

[0029] As used herein, the terms “printing device,” “printing system,” or “digital printing system” may refer to a digital copier or printer, scanner, image printer, digital production press, document processing system, image player, bookbinding machine, facsimile machine, or multifunction device, and may include several marking engines, feeding mechanisms, scanning assemblies, and other printing media processing units such as paper feeders and finishers. A digital printing system can handle sheets, webs, marking materials, etc. A digital printing system is any machine, or any combination of such machines, that can place marks on any surface and read marks on an input sheet.

[0030] As used herein, the term "pitch" may refer to the minimum center-to-center distance between interconnecting lines. Since half-pitch can approximate the minimum line width, it can be used as an indicator of the integration level of an IC.

[0031] As used herein, the term “semiconductor laser” may refer to a surface-emitting semiconductor laser, such as a VCSEL (vertical cavity surface-emitting laser), which can be manufactured on a semiconductor substrate using semiconductor manufacturing techniques.

[0032] When properly designed, current state-of-the-art VCSELs (Vertical Cavity Surface Emitting Lasers) have the capability to generate sufficient optical output power to be deployed in array form and, when properly configured and packaged, can be used for high-resolution evaporation of dampening water in high-speed printing systems. Such systems require each VCSEL in the array to generate tens of milliwatts of optical output power as a standalone device when operating alone, and require that the VCSEL array and its packaging be designed so that the lasers maintain their capability even when adjacent devices are turned on simultaneously. The features of the embodiment provide a unique VCSEL array chip design that can result in, among other things, high-power, small-pitch, individually addressable lasers, methods for mounting, cooling, driving, and image formation, a number of VCSEL array chips that enable wide-width (>100 mm) printing on a chip, and an example of a VCSEL array used for printing in DALI (Digital Architecture for Lithographic Inks) printing processes.

[0033] This specification enables the tightly pitched implementation of independently addressable high-power surface-emitting lasers on a VCSEL array chip. In some embodiments, the VCSELs share a cathode and are individually addressable through individual address lines connecting the individual VCSEL anodes. In some embodiments, a common anode addressing architecture can be used in which each address line in the array can encompass multiple electrically connected apertures. Elongated asymmetric aperture shapes can also be used so as to fit within the pitch of the address lines. In addition, the spacing of the lasers in the process direction can be tolerated, for example by a Dali printing process, to increase the total distance of the lasers while still maintaining an effective cross-process spacing that can be smaller than the size of the lasers themselves.

[0034] A "pixel" can refer to a set of multiple VCSELs or a single VCSEL. For example, in Figure 6, one pixel contains one laser. In Figure 8, one pixel contains two lasers coupled together. In Figure 10, one pixel contains a set of three VCSELs.

[0035] As used herein, “dense linear pitch” refers to the cross-process spacing between adjacent cross-process direction lasers, regardless of their position in the process direction. For example, in Figure 8, this is the cross-process spacing between set B and set C, which is 21.2 μm. The “laser size” in Figure 8 is the “width” of the common anode metal contact of laser set B.

[0036] Optimized thermal management of VCSEL array chips can be achieved using two unique approaches (which can be used together): a) direct die bonding of the slot for the driver chip to a mechanical block incorporating means for cooling, for example, by cooling fluid channels or heat pipes, and means for mounting the optical system; and b) ultrathin laser epitaxy transferred to a thermally conductive metal host substrate.

[0037] The stitching of VCSEL array chips can be enabled so that the effective (stitched) laser array width meets the demands of today's production printing widths. The effective laser array includes means for focusing the laser light originating from the VCSELs during DALI printing operation, driving individual lasers, cooling the lasers, and extracting evaporated dampening water.

[0038] VCSEL array chip design Referring to Figure 1, an architecture of an independently addressable high-power laser array with a 1200 dpi pitch is shown, characterized by the features of the embodiment. Figure 1 shows the arrangement of a linear array 100 of VCSELs 110 with address trace lines 115 having a pitch of 21.2 μm. The electrical contact pads 120 must be large enough to allow wire bonding, and the electrical trace lines 115 must be wide enough to allow low sheet resistance and negligible voltage drop when energized with a signal during operation. In the embodiment shown, the semiconductor lasers 110 can be arranged along two rows, with one set of address lines 115 entering from the top and another set entering from the bottom. These two rows of lasers are offset from each other to form a meshed linear array of optical emitters with a pitch of 21.2 μm. The contact pads 120 on each side can also have a staggered arrangement, and thus they can be large enough for wire bonding and still fit within the available space between the address lines. Figure 1 shows a 21 mm long x 2 mm wide chip that can contain 1000 lasers. Referring to Figure 2, an exemplary layout 105 and dimensions of a bond pad 120 and trace line 115 are further shown, which can further satisfy the achievement of the objectives shown in Figure 1.

[0039] Referring to Figure 3, an exemplary block diagram 130 is shown of wire bonding connections 133 of individual VCSELs 110 of each VCSEL array chip 100 to a dedicated channel of the associated driver chip 135, according to an embodiment. Each wire bonding connection 133 to each driver chip 135 may have the same pitch as the laser pitch, or a slightly different pitch, for example, a smaller pitch. Figure 3 shows how individual laser chips 100 may be connected to their respective driver chips 135 via wire bonding connections 133.

[0040] In an exemplary implementation for printing, many laser array chips 100 may be arranged adjacently along the cross-process (or x) direction of the document 101, as indicated by arrow 103, to form a wide imager 140. Figure 4 shows a 14-chip arrangement forming an 11-inch wide, 1200 dpi imager 140 for processing an image of the document 101 flowing in the process (or y) direction, as indicated by arrow 102. The tiled laser array chips 100 may also have a staggered arrangement 150, as shown in Figure 5, instead of the linear adjacent arrangement shown in Figure 4, for processing an image of the document 101 flowing in the process direction 102 as shown. In a staggered arrangement design, the portion of the print frame corresponding to each chip receives the appropriate timing delay so that the final formed image is correctly stitched. Alignment imperfections can also be addressed by performing calibration to adjust the relative timing delay of each laser chip 100. In other embodiments, the laser array chip may have a dedicated alignment structure to ensure precise alignment of two adjacent laser array chips or precise alignment with respect to a support structure.

[0041] To accommodate large aperture sizes capable of delivering up to 50 mW of optical output per laser, an asymmetric laser aperture design can be used instead of a conventional circular aperture. The aperture shape can be "compressed" along the array direction, resulting in it fitting within the available space for a tightly pitched arrangement. The aperture can be "elongated" proportionally in the direction of the address lines to compensate for the compressed dimensions, so that a sufficiently large emission area can still be achieved.

[0042] Figure 6 shows an optical microscope image of a portion of a 1200 dpi laser array 160 utilizing an oval 8 × 32 μm aperture shape for the VCSEL optical emitter 110. The process direction 102 is indicated by a document icon 101. The optical emitters 110 can be arranged in four interlocking columns 162, with half of the addressing trace lines coming from the top and half from the bottom. The emitter apertures can be positioned at different angles such that the width in the cross-process direction is effectively the same as the emitter pitch (e.g., 21.2 μm). For an 8 × 32 μm aperture shape, for example, an angle of 50.5 degrees would achieve this. Figure 7 shows graphs of the measured optical power versus current curves for each VCSEL device at various substrate temperatures, showing the peak optical power per device above 50 mW.

[0043] Referring to Figure 8, an optical microscope image of a portion of a 1200 dpi laser array 170 utilizing a common anode multi-aperture pixel design according to an embodiment is shown. The process direction 102 is indicated by a document icon 101. In this design, a common anode architecture is used in which each address line 115 in the array encompasses multiple electrically connected apertures 175 to achieve a larger effective overall aperture size. Although the two-aperture “pixels” 175 in this embodiment can fit within a 1200 dpi pitch, each pixel (VCSEL 110) can still emit an optical output of more than 50 mW, as shown in graph 180 provided in Figure 9, where optical output versus current is plotted. The pixels can be arranged in four interlocking columns, addressed from the top and bottom sides.

[0044] The interlocking multi-row arrangement of pixels in Figures 1, 6, and 8 can effectively form a tighter linear pitch in the "cross-process" direction. In printing applications, an image can be formed row by row as the medium traverses the laser array in the "process direction" along the direction of the address lines. Each row of the semiconductor laser 110 can form a portion of the image. Since each row is spatially separated from the others, a time delay can be set between the formation of a portion of the image from one row and other portions from other rows. In Figure 8, for example, pixels from the top row must be positioned adjacent to pixels on the bottom row, and then the second from the top row... The pixels of the bottom row are followed by the pixels immediately above the bottom row. If these rows are labeled as rows A, B, C, and D from top to bottom, and the medium moves from the bottom row to the top along the process direction, the laser for row A must be emitted after the laser for row D by a time delay equal to the distance between row A and row D divided by the speed of movement of the medium. The image frames supplied to rows A-D must be phase-delayed to properly stitch the images together. The print resolution in the process direction can, most conveniently, be the same as the print resolution in the cross-process direction, if the separation between rows is a multiple of the pixel spacing in the cross-process direction.

[0045] Referring to Figure 10A, an optical microscope image of a portion of a 1200 dpi laser array 190 utilizing a common anode 3-aperture pixel design according to an embodiment is shown. Figure 10B shows a closer view of the 3-aperture pixels of Figure 10A, revealing six levels of stacking in the process direction according to an embodiment. The process direction 102 in both figures is again indicated by the flow of document icons 101. In this design, a common anode architecture can be used in which each address line 115 in the array encompasses three electrically connected apertures 195 to achieve a larger effective overall aperture size. A six-level stacking scheme in the process direction can be implemented to accommodate the emitter 110. Timing between activations of horizontally adjacent pixels can be implemented in the driving software. With appropriate timing considering the relative movement of the imaged material and the laser, quasi-one-dimensional positioning of the laser can result in one-dimensional printed lines.

[0046] Mounting, cooling, driving, and image forming VCSEL array chip In such arrays, the close spacing between lasers can lead to thermal crosstalk, as heat from each laser affects the performance of nearby lasers. Furthermore, the total power extracted from numerous high-power lasers operating in a small area results in a high thermal load density that must be dissipated. Failure to dissipate this heat will lead to reduced optical output power due to increased temperature, and potentially damage the lasers.

[0047] These challenging thermal management issues can be addressed by developing a direct die-bonding packaging technique in which the laser array chip is directly die-bonded onto a 3D mechanical block instead of a conventional planar submount. The mechanical block can incorporate embedded cooling fluid channels for flowing a cooling fluid such as cooled water or ethylene glycol, and acts as the cathode electrical contact for the laser chip. The block can be thought of as a 3D submount with an integrated heatsink. The 3D submount also features integrated slots for a driver chip or electrical interposer, and mounting holes for optical system mounting. Alternatively, the submount can include heat pipes.

[0048] Referring to Figure 11, a photograph 230 of the rear view of the mechanical block 220 is shown, illustrating how cooling fluid tubes 233 / 235 may be mounted to the mechanical block 220 according to an embodiment, and also showing how integrated mounting holes may be formed in the mechanical block 220 for mounting optical elements. Cooling fluid channels 236 (dashed line) can be embedded inside the body of the mechanical block 220 and can be fabricated to allow coolant to flow near a heat source for efficient heat removal. Figure 11 also shows an integrated mounting hole 237 that may be provided for mounting optical elements used to image a laser beam.

[0049] Converging optical systems Because the light output from a surface-emitting laser diverges, a focusing optical system is typically required to structure the light beam and form an image. Several commercially available GRIN lens arrays, marketed under the name SELFOC lens array (SLA), can be configured and used for this purpose. SLAs are well suited to this application because they can arrange optical elements in a linear configuration to image a set of laser elements that are also arranged in a linear array, such as in the applications presented herein. The “base cells” of the lens can be arranged in a linear array for this purpose.

[0050] A Surface Laser Angle (SLA) is a device that can be used to project a 1:1 image from a source onto a substrate. These devices are typically quasi-one-dimensional and are used in scanning applications such as photocopiers, scanners, printers, and fax machines. Typically, SLAs are commercially available as two rows of distributed refractive index optical elements coupled together in a predetermined format and can be used in several printing applications, such as LED print bars. Each optical element collects light from a source and projects it onto the substrate. The images from all the optical elements are superimposed to form a projection of the source on the substrate. SLAs are attractive because they can be made relatively large in size to be usable for printing applications that typically require a wide print width. Commercially available SLAs are about 12 inches wide. According to this embodiment, if a considerably wider print width is required, several SLAs can be stitched together along the cross-process direction, or longer custom SLAs can be manufactured, or a complete VCSEL print bar can be staggered for use in wide Dali printing processes.

[0051] Referring to Figure 12A, a diagram of a two-column SLA is shown. One problem with SLA is that the incident light is either captured by the optical elements 240 or absorbed by the binder 241 used to fix the optical elements 240. Ideally, the binder would be transparent to laser light, especially near-infrared light. Approximately 26% of the incident light can be absorbed by the binder 241. Therefore, the optical element packing density is 2pi() / (4+2 * sqrt(5)) = 74%. For many imaging applications, losing 26% of the light is not a problem as they require little power. However, applications such as thermal processes (e.g., patterned sintering or evaporation) require high optical power. In high-power applications, this can lead to two problems: the SLA can become hot, requiring a system and optical design that can withstand the heat, and energy is wasted by the binder 241, thus requiring more power from the source element to achieve the desired thermal response. An overall light utilization rate of over 50% can be considered perfectly usable for many applications, including thermal processes.

[0052] Referring to Figure 12B, a solution that can overcome the absorption problem with currently available SLAs is to provide an SLA design in which the binder can be replaced with a transparent polymer 242. Using this type of binder allows diffuse light to pass through the SLA and be delivered to the substrate. The thermal process is often threshold-dependent. While the entire area can be heated, the desired effect is only seen if there is enough energy to initiate the thermal process. Diffuse light can act as preheating or postheating to provide a thermal offset in the image-forming area. This allows some of the 26% lost light to be used in the thermal process, which can help keep the SLA cool. Scattering elements 243 can also be incorporated into the binder to achieve light diffusion. Referring to Figure 12C, a geometry that can achieve more diffuse light is shown compared to the geometry shown in Figure 12B, which can provide more focused light.

[0053] Referring to Figure 12D, a three-point perspective view 243 is shown of an image-forming optical system including a four-row GRIN lens array that can be used with the VCSEL array described herein, according to an embodiment. Figure 12D shows an exemplary implementation utilizing a four-row GRIN lens array. The optical paths 244 from each laser 110 can traverse several lens elements 245 and converge onto the image plane 247. Figure 13 shows a graph 249 of calculated transmission efficiency versus beam divergence for various laser spatial mode profiles. Optical throughput can be limited by the incomplete packing of the GRIN lens array, as light landing on the material in the gaps between the cylindrical optical elements is lost. Divergent light not captured by the lens array is also lost, so it is beneficial to use enough rows for lenses that ideally capture all the light emanating from the VCSEL array.

[0054] More lens rows can be constructed from commercially available two-row SLAs by removing cladding from one side of the SLA, polishing away the cladding residue, and pressing the two modified SLAs together. Referring to Figure 14A, a photograph 250 of a four-row SLA constructed from two modified two-row SLAs according to an embodiment is shown. Referring to Figure 14B, an optical microscope photograph 255 of the combined two-row SLA 250 shown in Figure 14A is shown.

[0055] Alternative focusing optical system In many cases, the desired print width makes a classical image forming system excessive. Instead of using an SLA to focus the images 110 of the individual VCSEL lasers of the laser array 100 on the blanket cylinder 266, it may also be possible to use different optical elements such as classical focusing lenses 263. Combinations of these types of lenses create an inverted image of the object. Referring to Figure 15A, a block diagram of a staggered image forming system 260 for focusing the output from the VCSEL laser array 100 according to an embodiment is shown. As shown in Figure 15A, it may be necessary to stagger the individual image forming systems 100 in a sawtooth pattern. Each row in the staggered system is operated with appropriate timing delays 265 (e.g., t0, t0+Δt, t0+Δ2t) so that the collective exposures created on the moving image forming member 266 are properly stitched together to form the intended image.

[0056] Referring to Figure 15B, an example of VCSEL scrolling timing is shown using a 2-aperture, 4-row VCSEL laser array 170 (see Figure 8), where document 101 is processed in the process direction 102 at 1 m / s, and the VCSEL column spacing (center-to-center) is 55 μm. As document 101 is processed in the processing direction 102, the pixels in each column are illuminated at different times according to the reference image to adapt to the distance between pixels based on their column assignment. Pixels in column 1 are shown to be illuminated at a timing equal to 0.00 microseconds, pixels in column 2 at 55.00 microseconds, column 3 at 110.00 microseconds, and column 4 at 165.00 microseconds. Thus, considering the described delays may allow for more accurate image stitching during document processing.

[0057] Referring to Figure 16, a feathered imaging system 270 for focusing the output from the laser array 100 is shown according to an embodiment. Output focusing can be achieved by interleaving the individual laser arrays 271 / 272 into at least partially shared imaging paths 275 onto an imaging member 266 (e.g., a drum) by combining the beams using a beam combiner such as a polarizing optical system 274 or a dichroic mirror or both, as shown in Figure 16. A combination of polarizing beam combiners and spectral beam combiners, as well as a cascade of beam combiners, may be used to synthesize the image.

[0058] Referring to Figure 17, a block diagram of an interposer chip architecture 300 is shown, according to an embodiment, which fans out tightly pitched contact pads 315 on a laser array 100 to wider-pitch pads 325 on a PCB or driver chip. For high-resolution printing applications such as 1200 dpi or higher, the required laser array pitch is very tight compared to typical pad and pad spacing dimensions in modern PCBs. In some implementation configurations, an interposer chip 300 can be used to fan out electrical contacts 315 from the laser chip 100 to match a wider-pitch set of contact pads on a PCB or driver chip. Figure 17 shows an example embodiment in which the interposer can be used to fan out 42 μm pitch contact pads 315 to 100 μm pitch pads 325. This interposer design can be used on both sides of a laser chip 210 to address a meshed array of lasers 100 on a 1200 dpi pitch.

[0059] There are alternative interposer designs that allow the contact pitch to be fan-in rather than fan-out. In such designs, the VCSEL array pads can be mapped to corresponding, more closely spaced pads on the output of a driver chip (ASIC), for example. The fan-in arrangement may allow the driver chip to be smaller than the laser array chip, thus providing alignment and placement tolerance for the driver chip when tiling the laser array chips 100 to address them, as shown in Figure 3.

[0060] Thinning of the substrate In certain applications, the ability to directly bond the laser array chip 210 to a large, high-thermal-conductivity block 220 may be essential to prevent thermal overload, as conventional 2D planar submounts add unacceptable thermal resistance between the laser chip 210 and the heatsink. In the presented cooling design described herein with respect to Figure 11, the highly concentrated heat generated within a small area of ​​the laser chip 210 can rapidly enter the copper block 220, spread across a large area of ​​the block 220, and be dissipated from the system via a coolant fluid flowing at high speed through tubes 233 / 235.

[0061] Because semiconductor laser substrates typically have higher thermal resistance compared to metal blocks, the substrate can be a significant bottleneck for heat flow from the heat generated by the laser. Thermal modeling shows that, assuming a coolant flow rate of 4 liters per minute, thinning the substrate from a conventional 150 μm thick layer to 40 μm can reduce the operating laser temperature by 12°C. This can be translated into an improvement of approximately 10% in optical output power. Using an even thinner substrate with a thickness of 20 μm can further reduce the laser temperature.

[0062] Figure 18A shows a graph of calculated temperature versus substrate thickness at various locations on the laser ship surface according to the embodiment. The calculations assume the laser array geometry shown in Figure 1, the 3D submount design shown in Figure 3, an ethylene glycol coolant temperature of -10°C, and a coolant flow rate of 4 L / min. Figure 18B shows the temperature profile across the laser chip surface corresponding to the plotted points shown in Figure 18A. The device under test was in the off state, but the temperature at that location when all lasers in the array were turned on and at full power was calculated. This temperature is a measure of thermal crosstalk and a measure of the influence of adjacent lasers on the performance of the device under test.

[0063] Since a 20 μm thick layer is approximately the thickness of a VCSEL epitaxial layer, the substrate thinning task is equivalent to removing the epitaxial material from its original substrate and transferring it to a host metal substrate. Figures 19A to 19E illustrate the process for achieving this task. The first step involves mounting a laser tip 355 containing the substrate 344 onto a planar handle wafer 350, such as glass or silicon, with the back surface 356 facing upwards and using mounting wax 358, as shown in Figure 19A. The back surface 356 is then chemically and mechanically polished, as shown in Figure 19B, leaving only 20 μm of material. In the case of a GaAs substrate, the polishing step can be performed using sodium hypochlorite in combination with a rotating soft pad. Thickness control can be achieved using a mechanical stop designed to be part of the substrate holder. Alternatively, the GaAs substrate can be selectively removed by using a chemical etching solution that etches the GaAs faster than the etching stop layer in the epitaxial layer stack. For example, a thin layer of AlGaAs can be used as an etching stop for NH4OH / H2O2. Another embodiment utilizes GaInP as an etching stop for HNO3 / H2O2. The handle wafer 350 can then be removed from the polishing jig and placed in a thin film evaporator. In the evaporator, an n-type ohmic contact metal 357, such as AuGe, can be blanket-deposited onto the polished back surface 356 of the thinned substrate 344, as shown in Figure 19C. The back surface metal film can then be used as an electroplating seed for electroforming a layer of electroplating metal 359 to replace the removed substrate, as shown in Figure 19D. The electroplating metal 359 may be, for example, a layer of copper 50 μm thick. The handle wafer 350 can then be removed by dissolving the mounting wax 358 in a solvent such as acetone, as shown in Figure 19E, which allows the handle wafer 350 to be removed from the modified laser tip 355. This step can leave the electroplated metal 359 holding the transferred laser epi 333.Next, the host substrate 356 and the transferred laser array 333 can be annealed to complete the n-side ohmic contact interface. The completed structure can then be die-bonded to the mechanical block 220 as described above.

[0064] Examples of VCSEL array printing applications Without limiting the uses of the embodiments disclosed herein, as mentioned above, for example, the use of a VCSEL array as individually addressable light sources in a digital architecture (DALI) printing system for lithographic inks. DALI printing processes have the advantage of dramatically reducing the size, cost, and complexity of the laser imager, which is the most sophisticated component.

[0065] Figure 20 shows a schematic diagram of a prior art digital printing system 370 including an image forming member 266. The digital printing system 370 can be implemented as a system for variable lithography. The image forming member 266 in the example shown in Figure 1 may be a drum, plate or belt, or another currently known or later developed configuration.

[0066] The image-forming member 266 can be used with a transfer nip 112 to apply an ink image to the image-receiving medium substrate 114. The transfer nip 112 can be formed by an impression roller 118 that applies pressure in the direction of the image-forming member 266 as part of the image transfer mechanism 160. The image-receiving medium substrate 114 should not be considered limited to any particular composition, such as paper, plastic, or composite sheet film. The digital printing system 370 can be used to generate images on a wide variety of image-receiving medium substrates.

[0067] The image forming member 266 may include, for example, a cylindrical core, or a re-imageable surface layer formed on a structural mounting layer which may be one or more structural layers on a cylindrical core.

[0068] The digital printing system 370 may include a dampening system 122 comprising a series of rollers, which may be considered a dampening roller or dampening unit, for uniformly wetting the re-imaging surface of the image-forming member 266 with a dampening solution. The purpose of the dampening system 122 is to deliver a dampening solution layer having a generally uniform and controlled thickness to the re-imaging surface of the image-forming member 266.

[0069] Dampening solutions, such as dampening water, are known to primarily consist of water and, optionally, small amounts of isopropyl alcohol or ethanol added to reduce surface tension and lower the evaporation energy required to assist subsequent laser patterning, as described in more detail below. Small amounts of certain surfactants may also be added to the dampening water. Alternatively, other suitable dampening solutions may be used to improve the performance of ink-based digital lithography systems.

[0070] Once the dampening solution is metered and supplied onto the re-imaging surface of the image-forming member 266, the thickness of the dampening solution can be measured using a sensor 125 that can provide feedback to control the metering and supply of the dampening solution to the re-imaging surface of the image-forming member 266 by the dampening water system 122.

[0071] After a precise and uniform amount of dampening solution is applied to the re-imaging surface of the image-forming member 266 by the dampening solution system 122, a latent image can be selectively formed within a uniform dampening solution layer by using the optical patterning subsystem 130 to pattern the dampening solution layer according to the image, for example, by laser energy. Typically, the dampening solution may not efficiently absorb light energy (IR or visible). The optical patterning subsystem 130 can be implemented as, or may include, a light source 131 (e.g., a vertical cavity surface-emitting diode (VCSEL) array, a light-emitting diode (LED) array, a laser light source that emits a pixelated light beam as a pixelated line laser beam, or a modulated laser source).

[0072] The re-imaging surface of the image-forming member 266 ideally absorbs most of the laser energy (visible or invisible, such as IR) emitted from the optical patterning subsystem 130 adjacent to the surface, minimizing the energy wasted when heating the dampening solution and minimizing lateral heat diffusion to maintain high spatial resolution. Alternatively, appropriate radiosensitive components may be added to the dampening solution to assist in the absorption of incident radiated laser energy. The optical patterning subsystem 130 is described above as a light source such as a laser emitter or containing a light source, but it should be understood that various different systems may be used to deliver optical energy and pattern the dampening solution.

[0073] The mechanism acting on the patterning process carried out by the optical patterning subsystem 130 is known in the art. Briefly, the application of optical patterning energy from the optical patterning subsystem 130 allows for the selective removal of a portion of the dampening solution layer.

[0074] After patterning the dampening layer by the optical patterning subsystem 130, the patterned layer on the re-imaging surface of the image forming member 266 can be presented to the inker subsystem 145. Using the inker subsystem 145, a uniform ink layer can be applied onto the dampening layer and the re-imaging surface layer of the image forming member 266. The inker unit 145 may further include a heated ink bath whose temperature can be adjusted by a temperature control module (not shown in Figure 20). The inker subsystem 145 can meter and supply offset lithographic ink onto one or more ink-forming rollers that can come into contact with the re-imaging surface layer of the image forming member 266, using anilox rollers. Separately, the inker subsystem 145 may include other conventional elements, such as a series of metering and supply rollers, to provide a precise rate of ink supply to the re-imaging surface. The inker subsystem 145 can deposit ink into pockets representing the imaged portions of the re-imaging surface, while ink on the non-formatted portions of the dampening layer will not adhere to those portions.

[0075] The cohesiveness and viscosity of the ink present in the re-imagingable layer of the image-forming member 110 can be modified by several mechanisms. One such mechanism may involve, for example, the use of a rheology (complex viscoelastic coefficient) control subsystem 155. The rheology control system 155 can, for example, form partially cross-linked cores of ink on the re-imagingable surface to increase the ink cohesiveness to the re-imagingable surface layer. Curing mechanisms may include optical curing or photocuring, thermal curing, drying, or various forms of chemical curing. Cooling may be used to modify the rheology via several physical cooling mechanisms and by chemical cooling.

[0076] Next, the ink can be transferred from the re-imaging surface of the image-forming member 266 to the substrate 114 of the image-receiving medium using the transfer subsystem 160. The transfer occurs when the substrate 114 passes through the nip 112 between the image-forming member 266 and the impression roller 118 so that the ink in the voids of the re-imaging surface of the image-forming member 266 comes into physical contact with the substrate 114. If the tackiness of the ink is modified by the rheology control system 155, the modified tackiness of the ink causes the ink to adhere to the substrate 114 and separate from the re-imaging surface of the image-forming member 266. Careful control of the temperature and pressure conditions in the transfer nip 112 can enable the ink transfer efficiency from the re-imaging surface of the image-forming member 266 to the substrate 114 to exceed 95%. Some dampening solution may also wet the substrate 114, but the amount of such dampening solution is minimal and either evaporates rapidly or is absorbed by the substrate 114.

[0077] It should be noted that in certain offset lithography systems, an offset roller (not shown in Figure 20) first receives the ink image pattern, and then the ink image pattern can be transferred to the substrate according to a known indirect transfer method. After the transfer of most of the ink to the substrate 114, residual ink and / or residual dampener must be removed from the re-imaging surface of the image-forming member 266, preferably without scraping or abrading the surface. The residual dampener may be removed using an air knife. However, it is expected that some ink residue may remain. Removal of such remaining ink residue can be achieved through the use of some form of cleaning subsystem 172. The cleaning subsystem 172 may include at least a first cleaning member, such as an adhesive or slightly adhesive member, which physically contacts the re-imaging surface of the image-forming member 266, and the adhesive or slightly adhesive member removes residual ink and any remaining small amount of surfactant compound from the dampener on the re-imaging surface of the image-forming member 266. Next, the adhesive or slightly adhesive member can be brought into contact with a smooth roller from which residual ink can be transferred, and then the ink is peeled off the smooth roller, for example, by a doctor blade.

[0078] Other mechanisms that can facilitate cleaning of the re-imaging surface of the image-forming member 266. However, regardless of this cleaning mechanism, cleaning of residual ink and dampening solution from the re-imaging surface of the image-forming member 266 may be essential to prevent so-called "ghosting." After cleaning, the re-imaging surface of the image-forming member 266 may again be presented to a dampening water system 122 that can supply a fresh layer of dampening solution to the re-imaging surface of the image-forming member 266, and the process may be repeated.

[0079] In the prior art digital printing system 370 shown in Figure 20, a blanket 113 (i.e., an "image-forming cylindrical blanket" or "image-forming blanket") is shown. An image-forming member 266 in the form of a printing plate can surround the cylindrical blanket 113. The blanket 113 having the image-forming member 266 in the form of a printing plate as shown in the example of Figure 20 can be rotated in the direction indicated by the curved arrow 117.

[0080] The ink must be compatible with the materials it comes into contact with, including the image-forming member 266, the dampening solution applied by the dampening solution system 122, and other cured or uncured inks. The ink should also satisfy all functional requirements of the subsystem, including wetting and transfer properties. Transferring the image-formed ink is difficult because the ink must immediately and uniformly wet the blanket material (e.g., the image-forming member 266) and transfer from the blanket 113 to the substrates (112, 114, and 118). Since the cleaning substation can only remove small amounts of residual ink, the transfer of the image layer must be very efficient, reaching at least 90%. Any ink remaining on the blanket after cleaning will result in unacceptable ghost images in subsequent prints. Naturally, the rheology of the ink plays a crucial role in its transfer properties.

[0081] DALI printing systems require the use of high-power lasers in the DALI printing process and the ability to modulate them pixel by pixel to generate latent dampening images that can be used to ink print blankets. DALI systems can enable high-resolution digital printing of high-viscosity inks. Such high-quality printing processes can combine the inherent advantages of inks—high pigment content, low solvent content, and low cost—with the ability to print using these inks in a fully customizable digital style for each pixel of each print.

[0082] In the DALI printing process, a continuous thin layer (e.g., several tens of nanometers) of dampening solution, which can be deposited on the surface of the printing blanket, can prevent the transfer of ink to the blanket 113 (particularly the image-forming member 266). A high-power laser is used to heat the surface area of ​​the light-absorbing blanket, thereby allowing the dampening solution to evaporate in an image-like pattern. However, the laser must heat the blanket sufficiently to supply the latent heat of evaporation, as well as the sensible heat to raise the fluid to its evaporation temperature (e.g., about 175°C). The evaporated area can then be inked, and the ink can be transferred to the receiving medium.

[0083] While existing DALI printing systems can enable high-resolution digital printing of high-viscosity inks, current DALI printing processes can be relatively expensive due to the cost of high-power lasers and their modulation devices. Therefore, solutions such as those described with respect to the embodiments described herein are needed to significantly reduce the cost of DALI printing systems.

[0084] The design drawings of the completed VCSEL array-based image forming member 380 are depicted from the viewpoint shown in Figures 21A and 21B. The macro interposer PCB 225 is shown mounted on the VCSEL cooling block 220. The VCSEL array 210 is shown mounted on the VCSEL cooling block 220, and the GRIN lens array 240 is shown aligned with the VCSEL array 210 and positioned on the opposite side from the VCSEL cooling block 220. In addition to the elements described, Figures 21A / 21B may also include a vapor extraction unit 388 mounted on a vapor extraction mount 387 and positioned close to the focusing region (output) of the GRIN lens array 240. In some embodiments, the vapor extraction unit 388 may include a vacuum blade 389 or a physical blade or both. The vapor extraction unit 388 can extract vapor from dampening water generated by selective laser heating during the process of digitally structuring the dampening water. Figure 21B shows the approximate locations of the wire bond 382 and the VCSEL interposers 381 / 384, as well as a collection plane 360 ​​which can be adjusted to typically be located on the blanket shell 375. Figure 21A shows where the vapor extraction adjustment 383 may occur. Furthermore, as shown in Figure 11, cooling fluid tubes 233 that can supply coolant to the VCSEL cooling block 220 may be attached to the block.

[0085] Referring to Figure 22, a block diagram 400 of an electronic module operating as part of a printing system according to an embodiment is shown. The electronic module shown can provide the system functionality of the application-specific integrated circuit (ASIC) driver chip 135 described with respect to Figure 3 and in subsequent discussion. The electronic module shown can work together to enable a system for controlling and driving independently addressable semiconductor lasers. A computer 405 can be provided that converts images into raw data and provides it to a control interface 410. The control interface 410 can then transmit the raw data and timing to the driver electronics 415. The current driver 415 can convert the raw data and timing information provided by the control interface 410 into a coordinated current signal. The VCSEL array 420 can then convert the current signal into light used to illuminate the image forming member 266 (see Figure 15A).

[0086] Referring to Figures 23A and 23B, a block diagram 450 is shown, which is merely an example of the functional states that can be implemented in the control interface circuit. The control interface circuit can take a stream of image data for each column of the VCSEL device from the computer and convert it into timing signals and appropriately timed data for the current driver circuit to power the VCSEL device to produce the desired print output. The interface circuit requires the stream of image data, as well as system information including, but not limited to, inter-device variations in print medium speed, print medium acceleration, deceleration, and VCSEL power. In the idle state 460, the control interface typically waits for image data from the computer. In the print setup state 470, the control interface circuit receives and buffers a pre-formatted image data stream from the computer for each VCSEL column in preparation for producing the desired print output. In the line print states 451-454, the data for each column of the four-column VCSEL array responds to subframe delay 458 data for appropriately stitched and timed images to be produced on the drum. Each line print can process data and timing information using the line display module, next line transmission module, and memory access module based on image processing data received from the modules of the print setup 470. After document processing, the system can return to idle state 460 (459) and await additional / new processing requirements.

[0087] Referring to Figure 24, block diagram 500 is shown, illustrating possible functions in the main module of a printing system incorporating the use of a VCSEL array according to an embodiment. As shown in block 503, the image can be converted into four data streams (e.g., A, B, C, and D) corresponding to each of the four columns of the VCSEL array. Simultaneously, timing information is converted into clock pulse values, as shown in block 505, and sent to FPGA memory where the current setpoint is set. Image data can be buffered in FPGA memory using DMA functionality, as shown in block 510, while timing information can be retrieved from FPGA memory and stored in FPGA registers, as shown in block 513. Then, as shown in block 515, the current setpoint information can be stored in a dot correction register in the printing module in preparation for further document processing / rendering using the VCSELs.

[0088] Referring to Figure 25, another block diagram 550 is shown illustrating possible functions in the electronic module of a printing system incorporating the use of a VCSEL array according to an embodiment. As shown in block 555, print start and stop operations can be initiated by a computer after the steps described herein with respect to Figure 24. As shown in block 560, image data can be retrieved from FPGA memory for each line print, formatted, and shifted from the FPGA to the module. Simultaneously, as shown in block 563, a control (CNTRL) signal can be raised and lowered for each group (ABCD) based on timing values ​​stored in a register. Then, as shown in block 565, a current output can be activated according to the value of a grayscale register at the start of each line print cycle. Furthermore, while the current is being output, the next line data can be shifted to the grayscale register.

[0089] In summary, structures and methods for realizing a tightly pitched, independently addressable, high-power surface-emitting laser array are disclosed herein. Related components and methods that can enable the use of such laser arrays in printing applications are also described herein.

[0090] It will be understood that the features and functions disclosed above, as well as other features and functions, or variations thereof, may preferably be combined into many other different systems or applications. Various alternatives, modifications, variations, or improvements not currently anticipated or expected may be made later by those skilled in the art and are intended to be covered by the following claims.

Claims

1. A semiconductor surface-emitting laser array comprising a plurality of independently addressable surface-emitting lasers arranged in a linear array in at least two rows on a common substrate chip, each including a common cathode and a dedicated channel associated with an address trace line for each surface-emitting laser, wherein the dense linear pitch between the surface-emitting lasers of the at least two rows along the linear array in the cross-process direction is smaller than the size of a pixel, which is the aperture size of the surface-emitting lasers in the cross-process direction.

2. The semiconductor laser array according to claim 1, wherein each independently addressable surface-emitting laser further includes at least one laser aperture, each of the at least one laser aperture further includes an asymmetric aperture shape.

3. The semiconductor laser array according to claim 1, wherein the address trace lines associated with each of the plurality of independently addressable surface-emitting lasers for each of the at least two rows are manufactured to have a dense linear pitch of 22 micrometers or less.

4. The semiconductor laser array according to claim 1, wherein the address trace lines are manufactured with a width that allows for a reduction in sheet resistance and a trace voltage drop of less than 50% of the voltage drop across the activated surface-emitting laser at the laser oscillation threshold current.

5. The semiconductor laser array according to claim 1, further comprising an electrical contact pad associated with each address trace line for each independently addressable surface-emitting laser, wherein each electrical contact pad is configured to accept wire bonding.

6. The semiconductor laser array according to claim 1, wherein the plurality of independently addressable surface-emitting lasers are arranged along at least two rows, with one set of address lines entering from the top of the common substrate chip and connecting to a first row of independently addressable surface-emitting lasers, and another set of address lines entering from the bottom of the common substrate chip and connecting to a second row of independently addressable surface-emitting lasers.

7. The semiconductor laser array according to claim 6, further comprising driver circuits attached to each of the first and second rows of independently addressable surface-emitting lasers by wire bonding to electrical contact pads associated with each of the first and second rows of independently addressable surface-emitting lasers.

8. The semiconductor laser array according to claim 6, wherein the first and second rows of independently addressable surface-emitting lasers are offset from each other to form a meshed linear array of optical emitters.

9. The semiconductor laser array according to claim 5, wherein the electrical contact pads are manufactured in a staggered arrangement to enable wire bonding, and the contact pads are also made to fit within the space between the address trace lines.

10. The semiconductor laser array according to claim 1, wherein the common substrate chip includes at least 1,000 independently addressable surface-emitting lasers.

11. The semiconductor laser array according to claim 10, further comprising two or more common substrate chips that are tiled side-by-side and joined together to provide a 1200 dpi imager with a width of at least 11 inches.

12. The semiconductor laser array according to claim 10, further comprising two or more common substrate chips tiled in a staggered arrangement and joined to one another to provide a 1200 dpi imager with a width of at least 11 inches, wherein a timing delay is associated with each of the two or more common substrate chips in the staggered arrangement.

13. The semiconductor laser array according to claim 1, wherein each address trace line associated with each channel for each of the plurality of independently addressable surface-emitting lasers further comprises two or more apertures that can operate together.

14. The semiconductor laser array according to claim 13, wherein the two or more apertures capable of operating together are two-aperture surface-emitting lasers.

15. The semiconductor laser array according to claim 1, wherein the plurality of independently addressable surface-emitting lasers are arranged along at least four interlocking rows from top to bottom, one set of address lines enters from the top of the common substrate chip and connects to the first and second rows of independently addressable surface-emitting lasers, and another set of address lines enters from the bottom of the common substrate chip and connects to the third and fourth rows of independently addressable surface-emitting lasers.

16. The semiconductor laser array according to claim 15, further comprising driver circuits attached to each of the first, second, third, and fourth rows of independently addressable surface-emitting lasers by wire bonding to electrical contact pads associated with each of the first, second, third, and fourth rows of independently addressable surface-emitting lasers.

17. The semiconductor laser array according to claim 16, wherein each of the second, third, and fourth columns is operable with a different time delay than the first column by the operation of the driver circuit attached to each of the columns.

18. The semiconductor laser array according to claim 17, wherein the time delay of each column is based on the distance from the first column to the second column, from the second column to the third column, and from the third column to the fourth column.

19. The semiconductor laser array according to claim 1, further comprising a 3D mechanical block having at least a liquid cooling channel inside, on which a common substrate chip having the plurality of independently addressable surface-emitting lasers arranged in a linear array is mounted, and configured to operate to control the temperature of the independently addressable surface-emitting lasers during their operation.

20. The semiconductor laser array according to claim 1, wherein the plurality of independently addressable surface-emitting lasers are arranged along at least six interlocking rows from top to bottom along the process direction, one set of address lines enters from the top of the common substrate chip and connects to the first to third rows of independently addressable surface-emitting lasers, and another set of address lines enters from the bottom of the common substrate chip and connects to the fourth to sixth rows of independently addressable surface-emitting lasers.

21. The semiconductor laser array according to claim 20, wherein the electrical contact pads associated with each laser of the surface-emitting laser are manufactured in a staggered arrangement to enable wire bonding, and also to allow the contact pads to be located within the space between the address trace lines.

22. The semiconductor laser array according to claim 20, further comprising each column which is operated with a timing delay to correspond to the position of each column relative to the first column.

23. The semiconductor laser array according to claim 20, wherein each address trace line associated with each channel for each of the plurality of independently addressable surface-emitting lasers further comprises two or more apertures that can operate together.

24. The semiconductor laser array according to claim 23, wherein each address trace line associated with each channel for each of the plurality of independently addressable surface-emitting lasers is formed around adjacent surface-emitting lasers.

25. The semiconductor laser array according to claim 13, wherein the two or more apertures that can operate together are multi-aperture surface-emitting lasers.

26. Multiple independently addressable surface-emitting lasers are arranged in a linear array on a common substrate chip, each including a dedicated channel associated with the address trace line of the surface-emitting laser, At least one laser aperture associated with each independently addressable surface-emitting laser, each of the at least one aperture further includes an asymmetric aperture shape configured to fit within the pitch of each address trace line associated with each channel for each of the plurality of independently addressable surface-emitting lasers, An electrical contact pad associated with each address trace line for each independently addressable surface-emitting laser, wherein each electrical contact pad is configured to accept wire bonding, comprising: A semiconductor surface-emitting laser array in which the plurality of independently addressable surface-emitting lasers are arranged along at least two rows, with one set of address lines entering from the top of the common substrate chip and connecting to a first row of independently addressable surface-emitting lasers, and another set of address lines entering from the bottom of the common substrate chip and connecting to a second row of independently addressable surface-emitting lasers.

27. ​​The semiconductor laser array according to claim 26, further comprising driver circuits attached to each of the first and second rows by wire bonding to electrical contact pads associated with each of the first and second rows of independently addressable surface-emitting lasers.

28. The semiconductor laser array according to claim 26, wherein the first row and the second row are offset from each other to form a meshing linear array of surface-emitting lasers.

29. The semiconductor laser array according to claim 26, wherein the electrical contact pads are manufactured in a staggered arrangement to enable wire bonding, and the contact pads are also made to fit within the space between the address trace lines.

30. The semiconductor laser array according to claim 26, wherein the common substrate chip includes at least 1,000 independently addressable surface-emitting lasers thereon.

31. The semiconductor laser array according to claim 30, further comprising two or more common substrate chips that are tiled side-by-side and joined together to provide a 1200 dpi imager with a width of at least 11 inches.

32. The semiconductor laser array according to claim 30, further comprising two or more common substrate chips tiled in a staggered arrangement and joined to one another to provide a 1200 dpi imager with a width of at least 11 inches, wherein a timing delay is associated with each of the two or more common substrate chips in the staggered arrangement.

33. The semiconductor laser array according to claim 26, wherein the plurality of independently addressable surface-emitting lasers are arranged along four interlocking rows from top to bottom, one set of address lines enters from the top of the common substrate chip and connects to the first and second rows of independently addressable surface-emitting lasers, and another set of address lines enters from the bottom of the common substrate chip and connects to the third and fourth rows of independently addressable surface-emitting lasers.

34. The semiconductor laser array according to claim 33, further comprising driver circuits attached to each of the first, second, third, and fourth rows of independently addressable surface-emitting lasers by wire bonding to electrical contact pads associated with each of the first, second, third, and fourth rows of independently addressable surface-emitting lasers.

35. The semiconductor laser array according to claim 34, wherein each of the second, third, and fourth columns is operable with a different time delay than the first column by the operation of the driver circuit attached to each of the columns.

36. The semiconductor laser array according to claim 35, wherein the time delay of each column is based on the distance from the first column to the second column, from the second column to the third column, and from the third column to the fourth column.

Images