Semiconductor device and method for manufacturing a semiconductor device

Abstract

To provide a technique of increasing decoupling capacitance between a power source line and a ground line in a semiconductor device.SOLUTION: A semiconductor device according to the present disclosure includes: a substrate having a first main surface and a second main surface; a plurality of elements formed on or over the first main surface of the substrate; at least one first power source line electrically connected to at least one of the elements, in which the at least one first power source line is disposed in a first layer disposed over the first main surface of the substrate and has an upper surface, a first side surface continuing from the upper surface, and a second side surface facing the first side surface and continuing from the upper surface; and at least one second power source line disposed in a second layer disposed on or over the first layer, in which the at least one second power source line is disposed ranging from the second layer to the first layer so as to cover the upper surface, the first side surface, and the second side surface in a part of the at least one first power source line.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] Exemplary embodiments of the present disclosure relate to a semiconductor device and a method for manufacturing a semiconductor device.

Background Art

[0002] As a semiconductor device having an interconnect level structure, there is the semiconductor device described in Patent Document 1.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problem to be Solved by the Invention

[0004] The present disclosure provides a technique for increasing the decoupling capacitance between a power supply line and a ground line in a semiconductor device.

Means for Solving the Problem

[0005] In one exemplary embodiment of the present disclosure, a semiconductor device is provided. The semiconductor device includes: a substrate having a first main surface and a second main surface; a plurality of elements formed at or above the first main surface of the substrate; at least one first power supply line electrically connected to at least one of the plurality of elements, wherein the at least one first power supply line is arranged in a first layer provided above the first main surface of the substrate, and the at least one first power supply line has an upper surface, a first side surface continuous from the upper surface, and a second side surface facing the first side surface and continuous from the upper surface; and at least one second power supply line arranged in the first layer and a second layer located above the first layer, wherein the at least one second power supply line is arranged extending from the second layer to the first layer so as to cover the upper surface, the first side surface, and the second side surface at a portion of the at least one first power supply line. [Effects of the Invention]

[0006] According to one exemplary embodiment of the present disclosure, a technique can be provided to increase the decoupling capacitance between a power line and a ground line in a semiconductor device. [Brief explanation of the drawing]

[0007] [Figure 1] This is a schematic cross-sectional view showing an example of the structure of a semiconductor device 100. [Figure 2A] This figure shows an example of the manufacturing process for semiconductor device 100. [Figure 2B] This figure shows an example of the manufacturing process for semiconductor device 100. [Figure 2C] This figure shows an example of the manufacturing process for semiconductor device 100. [Figure 2D] This figure shows an example of the manufacturing process for semiconductor device 100. [Figure 2E] This figure shows an example of the manufacturing process for semiconductor device 100. [Figure 2F] This figure shows an example of the manufacturing process for semiconductor device 100. [Figure 2G] This figure shows an example of the manufacturing process for semiconductor device 100. [Figure 2H] This figure shows an example of the manufacturing process for semiconductor device 100. [Figure 3] This is a schematic cross-sectional view showing another example of the structure of the semiconductor device 100. [Figure 4] This is a schematic cross-sectional view showing another example of the structure of the semiconductor device 100. [Modes for carrying out the invention]

[0008] The embodiments of this disclosure are described below.

[0009] In one exemplary embodiment, a semiconductor device is provided. The semiconductor device comprises a substrate having a first main surface and a second main surface; a plurality of elements formed on the first main surface of the substrate or above the first main surface; and at least one first power line electrically connected to at least one of the plurality of elements, wherein the at least one first power line is located in a first layer located above the first main surface of the substrate, and the at least one first power line has a top surface, a first side surface continuous with the top surface, and a second side surface facing the first side surface and continuous with the top surface; and at least one second power line located in a first layer and a second layer located above the first layer, wherein the at least one second power line is located across the second layer and the first layer such that it covers the top surface, the first side surface, and the second side surface of the at least one first power line in part.

[0010] In one exemplary embodiment, the system further comprises at least two signal lines electrically connected to at least one of a plurality of elements, the at least two signal lines being located in at least a first layer. In one exemplary embodiment, at least two signal lines are arranged across the second layer and the first layer.

[0011] In one exemplary embodiment, the system further comprises a first dielectric film disposed between at least two signal lines in a first layer, the first dielectric film having a first dielectric constant, and a second dielectric film disposed between at least one first power line and at least one second power line in the first layer, the second dielectric film having a second dielectric constant higher than the first dielectric constant.

[0012] In one exemplary embodiment, in the first layer, the spacing between at least two signal lines is greater than the spacing between at least one first power line and at least one second power line.

[0013] In one exemplary embodiment, in a first layer, each of at least two signal lines includes a wiring portion and a plug portion, and in the first layer, at least one first power supply line includes a wiring portion and a plug portion, and a length of the plug portion of each of the at least two signal lines is longer than a length of the plug portion of the at least one first power supply line.

[0014] In one exemplary embodiment, in a plan view of a first main surface, the at least one first power supply line and the at least one second power supply line are arranged so as to intersect each other.

[0015] In one exemplary embodiment, a cross-sectional area of the at least one first power supply line is larger than a cross-sectional area of each of the at least two signal lines.

[0016] In one exemplary embodiment, the second power supply line is a ground line.

[0017] In one exemplary embodiment, the device comprises: a substrate having a first main surface and a second main surface; a plurality of elements formed on the first main surface of the substrate or above the first main surface; at least one first power supply line electrically connected to at least one of the plurality of elements, wherein the at least one first power supply line is arranged in a first layer provided below the second main surface of the substrate, and the at least one first power supply line has a lower surface, a first side surface continuous from the lower surface, and a second side surface opposite the first side surface and continuous from the lower surface; and at least one second power supply line arranged in the first layer and a second layer located below the first layer, wherein the at least one second power supply line is arranged from the second layer to the first layer so as to cover the lower surface, the first side surface and the second side surface in a part of the at least one first power supply line.

[0018] In one exemplary embodiment, the device further comprises at least two signal lines electrically connected to at least one of the plurality of elements, wherein the at least two signal lines are arranged in a third layer provided above the first main surface.

[0019] In one exemplary embodiment, the present invention provides a substrate having a first main surface and a second main surface, a plurality of elements formed on or above the first main surface of the substrate, and at least one first power line electrically connected to at least one of the plurality of elements, wherein the at least one first power line is located in a first layer located above the first main surface of the substrate, and the at least one first power line has a bottom surface, a first side surface continuous with the bottom surface, and a second side surface facing the first side surface and continuous with the bottom surface, and the present invention provides at least one second power line located in a second layer located above the first layer, wherein the at least one second power line is located from the second layer to the first layer so as to cover the bottom surface, the first side surface, and the second side surface in part with respect to at least two power lines.

[0020] Hereinafter, each embodiment of this disclosure will be described in detail with reference to the drawings. In each drawing, the same or similar elements are denoted by the same reference numeral, and redundant explanations are omitted. Unless otherwise specified, positional relationships such as top, bottom, left, and right will be described based on the positional relationships shown in the drawings. The dimensional ratios in the drawings do not represent actual ratios, and actual ratios are not limited to those shown.

[0021] Figure 1 is a schematic cross-sectional view showing an example of the structure of the semiconductor device 100 of this disclosure. The semiconductor device 100 comprises a substrate 10, an element layer 20, and wiring layers 30 to 80. The semiconductor device 100 may be, for example, a logic device, a memory device, or an analog device.

[0022] The substrate 10 may be a semiconductor substrate. For example, the substrate 10 may be a semiconductor wafer composed of semiconductor materials such as silicon (Si), germanium, or gallium arsenide. The substrate 10 includes a first main surface 12 on which the element 22 is formed, and a second main surface 14 on the opposite side of the first main surface 12. At least a part of the structure of the element 22 may be formed inside the substrate 10.

[0023] The element layer 20 is a layer on which a plurality of elements 22 are arranged. In this embodiment, the element layer 20 is composed of at least a part of the structure of the plurality of elements 22, a dielectric film 24, and a plurality of plugs 26. A part of the structure of the plurality of elements 22 may be arranged or formed on the substrate 10. The elements 22 may be active elements such as MOS transistors, or passive elements such as resistors and capacitors. The dielectric film 24 may function as an interlayer insulating film. The dielectric film 24 may be composed of a dielectric material or an insulating material. A plurality of plugs 26 are arranged on the element layer 20. The plurality of plugs 26 electrically connect the plurality of elements 22 and the plurality of wirings 36. One end of the plurality of plugs 26 may be connected to the plurality of elements 22 on the substrate 10. Alternatively, one end of the plurality of plugs 26 may be connected to the plurality of elements 22 on the semiconductor layer 20. The plurality of plugs 26 may be composed of a conductive material. The conductive material may be a metallic material or a semiconductor material.

[0024] The wiring layer 30 may consist of dielectric films 32 and 34, and a plurality of wirings 36. The dielectric films 32 and 34 may function as interlayer insulating films. The dielectric films 32 and 34 may consist of dielectric materials or insulating materials. Furthermore, the dielectric film 32 may function as a so-called stopper in the etching of the dielectric film 34. That is, the dielectric film 32 may consist of a material having a lower etching rate than the dielectric film 34 in the etching of the dielectric film 34. The etching may be an etching that forms grooves in the dielectric film 34 for forming the plurality of wirings 36. Each of the plurality of wirings 36 may consist of a wiring portion 36a and a plug portion 36b. The plurality of wirings 36 electrically connect the plurality of plugs 26 and the plurality of wirings 46. The plurality of wirings 36 are connected to the plurality of plugs 26 at the plug portion 36b.

[0025] The wiring layer 40 may consist of dielectric films 42 and 44, and a plurality of wirings 46. The dielectric films 42 and 44 may function as interlayer insulating films. The dielectric films 42 and 44 may consist of dielectric materials or insulating materials. Furthermore, the dielectric film 42 may function as a so-called stopper in the etching of the dielectric film 44. That is, the dielectric film 42 may consist of a material having a lower etching rate than the dielectric film 44 in the etching of the dielectric film 44. The etching may be an etching that forms grooves in the dielectric film 44 for forming the plurality of wirings 46. Each of the plurality of wirings 46 may consist of a wiring portion 46a and a plug portion 46b. The plurality of wirings 46 electrically connect the plurality of wirings 36 and the plurality of wirings 56. The plurality of wirings 46 are connected to the wiring portion 36a of the plurality of wirings 36 at the plug portion 46b.

[0026] The wiring layer 50 may consist of dielectric films 52 and 54, and a plurality of wirings 56. The dielectric films 52 and 54 may function as interlayer insulating films. The dielectric films 52 and 54 may consist of dielectric materials or insulating materials. Furthermore, the dielectric film 52 may function as a so-called stopper in the etching of the dielectric film 54. That is, the dielectric film 52 may consist of a material having a lower etching rate than the dielectric film 54 in the etching of the dielectric film 44. The etching may be an etching that forms grooves in the dielectric film 54 for forming the plurality of wirings 56. Each of the plurality of wirings 56 may consist of a wiring portion 56a and a plug portion 56b. The plurality of wirings 56 electrically connect the plurality of wirings 56 and the plurality of wirings 66. The plurality of wirings 56 are connected to the wiring portion 46a of the plurality of wirings 46 at the plug portion 46b.

[0027] The wiring arranged in wiring layers 30 to 50 can be electrically connected to at least one of the element 22, power line 76, power line 86, and signal line 88. For example, the wiring arranged in wiring layers 30 to 50 can electrically connect element 22 to power line 76 or 86. Also, the wiring arranged in wiring layers 30 to 50 can electrically connect element 22 to signal line 88. Furthermore, the wiring arranged in wiring layers 30 to 50 can electrically connect between power lines 76, between power lines 86, or between signal lines 88. Note that power line 76 is an example of a first power line. Also, ground line 86 is an example of a second power line.

[0028] The wiring layer 60 may be composed of dielectric films 62 and 64 and wiring 66 and 68. Dielectric films 62 and 64 may function as interlayer insulating films. Dielectric films 62 and 64 may be composed of dielectric materials or insulating materials. Furthermore, dielectric film 62 may function as a so-called stopper in the etching of dielectric film 64. That is, dielectric film 62 may be composed of a material that has a lower etching rate than dielectric film 64 in the etching of dielectric film 44. The etching may be an etching that forms grooves in the dielectric film 64 that form a plurality of wiring 66 and / or 68.

[0029] Each of the multiple wirings 66 may consist of a wiring portion 66a and a plug portion 66b. The multiple wirings 66 electrically connect to at least one of the multiple power lines 76. The multiple wirings 66 are connected to the wiring portion 56a of the multiple wirings 56 at the plug portion 46b. The wiring portion 66a of the wiring 66 may be formed in the thickness direction of the wiring layer 60, extending from the dielectric film 62 to the dielectric film 72. That is, the thickness of the wiring portion 66a may be approximately the same as the thickness of the dielectric film 64. Also, the thickness of the plug portion 66b may be approximately the same as the thickness of the dielectric film 62.

[0030] Multiple wires 68 can function as signal lines. That is, multiple wires 68 are electrically connected to multiple signal lines 88. Multiple wires 68 can also be electrically connected to multiple elements 22 via other wiring layers arranged in wiring layers 30 to 50. Multiple wires 68, like wires 36, 46 and 56, may include a wiring portion and a plug portion. In this case, multiple wires 68 can be connected to multiple signal lines 88 in the wiring portion. The thickness of the wiring portion of multiple wires 68 may be approximately the same as the thickness of the dielectric film 64, as shown in Figure 1. Multiple wires 68 can be connected to other wires arranged in wiring layer 50 in the plug portion. The thickness of the plug portion of multiple wires 68 may be approximately the same as the thickness of the dielectric film 62.

[0031] The wiring layer 70 may consist of dielectric films 72 and 74, a plurality of power lines 76, a plurality of signal lines 88 (wiring portion 88b and plug portion 88c), and a high dielectric film 90. Dielectric films 72 and 74 can function as interlayer insulating films. Dielectric films 72 and 74 may consist of dielectric material or insulating material. Furthermore, dielectric film 72 may function as a so-called stopper in etching of dielectric film 74. That is, dielectric film 72 may consist of a material having a lower etching rate than dielectric film 74 in etching of dielectric film 74. Such etching may be an etching that forms grooves in dielectric film 74 that form a plurality of power lines 76, a plurality of signal lines 88 (wiring portion 88b), and part of the grounding line 86. Furthermore, the wiring layer 80 may consist of dielectric films 82 and 84, a plurality of grounding lines 86, and a plurality of signal lines 88 (wiring portion 88a). Dielectric films 82 and 84 can function as interlayer insulating films. The dielectric films 82 and 84 may be composed of a dielectric material or an insulating material.

[0032] The power line 76 is composed of a wiring portion 76a and a plug portion 76b. The thickness of the wiring portion 76a may be approximately the same as the thickness of the dielectric film 74 in the thickness direction of the wiring layer 70. The wiring portion 76a also has a top surface and side surfaces. Furthermore, the thickness of the wiring portion 76a may be thicker than the thickness of the wiring portion 88b of the signal line 88.

[0033] The grounding wire 86 is composed of a wiring portion 86b, a wiring portion 86b, and a plug portion 86c. The wiring portion 86a may be approximately the same thickness as the wiring layer 80 or the dielectric film 84 in the thickness direction of the wiring layer 80. The wiring portion 86b may be approximately the same thickness as the dielectric film 74 and the high-dielectric film 90 in the thickness direction of the wiring layer 70. The wiring portion 86b may also be approximately the same thickness as the wiring layer 70 or the dielectric film 74. Furthermore, the cross-sectional area of ​​the power line 76 and / or the grounding wire 86 may be larger than the cross-sectional area of ​​the signal line 88.

[0034] For example, the power line 76 and signal line 88 may be wiring arranged mainly in the Y-axis direction as shown in Figure 1. The ground line 86 may also be wiring arranged mainly in the X-axis direction as shown in Figure 1. That is, the power line 76 and the ground line 86 may be arranged so as to intersect each other in a plan view of the first main surface 12 of the substrate 10. The power line 76 and the ground line 86 may be substantially perpendicular in a plan view of the first main surface 12 of the substrate 10. Furthermore, the ground line 86 includes a portion formed from wiring layer 80 to wiring layer 70 at the point where it intersects with the power line 76. Specifically, the ground line 86 is composed of a wiring portion 86a present in wiring layer 80, a wiring portion 86b present in wiring layer 70, and a plug portion 86c. The wiring portion 86b is a portion that protrudes from the wiring portion 86a in the direction from wiring layer 80 toward wiring layer 70. The direction from wiring layer 80 toward wiring layer 70 is the Z-axis direction as shown in Figure 1.

[0035] As an example, in one cross-section of the semiconductor device 100, a plurality of power lines 76 and a plurality of wiring portions 86b may be arranged alternately in the X-axis direction in the wiring layer 70. Furthermore, the plurality of power lines 76 and the plurality of wiring portions 86b may be arranged adjacent to each other. That is, at least one of the wiring portions 86b of the ground line 86 may be arranged between a plurality of wiring portions 76a in the wiring layer 70. Also, at least one of the wiring portions 76a of the power line 76 may be arranged between a plurality of wiring portions 86b in the wiring layer 70.

[0036] The signal line 88 is composed of a wiring portion 88a, a wiring portion 88b, and a plug portion 88c. The thickness of the wiring portion 88b may be thinner than the thickness of the wiring portion 76a of the power line 76. The length of the plug portion 88c may be longer than the plug portion 76b of the power line 76. Multiple adjacent signal lines 88 (wiring portions 88b) may be separated by the dielectric film 74. In addition, a signal line 88 (wiring portion 88a) and an adjacent ground line 86 may be separated by the dielectric film 74 and the high-dielectric film 90.

[0037] The high dielectric film 90 is composed of a dielectric material having a high dielectric constant. The dielectric constant of the dielectric material contained in the high dielectric film 90 is higher than that of the dielectric material contained in the dielectric film 74. For example, the dielectric material contained in the high dielectric film 90 may be a metal oxide or a metal nitride. The dielectric material may be a mixture of multiple metal oxides, a mixture of multiple metal nitrides, or a mixture of one or more metal oxides and one or more metal nitrides. For example, the metal oxide may include hafnia (HfO2), zirconia (ZrO2), or alumina (Al2O3). For example, the metal nitride may include hafnium nitride (HfN), zirconium nitride (ZrN), or aluminum nitride (AlN). As an example, the high dielectric film 90 may be placed between wiring portion 76a and wiring portion 86a, between wiring portion 76a and wiring portion 86b (on the sides of wiring portion 76a and wiring portion 86b), between dielectric film 74 and wiring portion 86b (on the sides of wiring portion 86b), between dielectric film 74 and wiring portion 86a (on the sides of wiring portion 86b), and between dielectric film 64 and / or dielectric film 72 and wiring portion 86b (on the lower surface of wiring portion 86b). That is, the high dielectric film 90 may be placed so as to cover the upper and side surfaces of wiring portion 76a, the lower surface of wiring portion 86a, and the lower and side surfaces of wiring portion 86b. In addition, the high dielectric film 90 may be placed between dielectric film 74 and dielectric film 82 and / or dielectric film 84, and between wiring portion 88b of signal line 88 and dielectric film 82 and / or dielectric film 84.

[0038] The semiconductor device 100 may further include one or more layers similar to the wiring layers 30 to 80 above the wiring layer 80. The semiconductor device 100 may also include any number of additional wiring layers / element layers below the wiring layer 80. Furthermore, the wiring layers 30 to 50 may include wiring electrically connected to the signal line 88. The semiconductor device 100 may also include elements, wiring, and / or dielectric films not shown in Figure 1 in other cross-sections of the semiconductor device 100.

[0039] Furthermore, the wiring, signal lines, power lines, and ground lines (hereinafter also referred to as "wiring, etc.") included in wiring layers 30 to 80 are composed of a metallic material. For example, the metallic material may be copper (Cu). Also, the wiring, etc. may be laminated wiring in which multiple materials are stacked. For example, the laminated wiring may include a barrier film. For example, the barrier film may include tantalum nitride (TaN) and / or cobalt (Co).

[0040] Furthermore, as an example, the dielectric film included in the wiring layers 30-80 may be composed of silicon oxide. For example, the dielectric film may be composed of SOG (Spin On Glass). Also, the dielectric film included in the wiring layers 30-80 may be a laminated film in which films composed of dielectric materials are stacked.

[0041] Figures 2A to 2I show an example of the manufacturing process of the semiconductor device 100. For ease of explanation, Figures 2A to 2I show wiring layers 60 to 80 of the semiconductor device 100.

[0042] As shown in Figures 2A and 2B, after the wiring layer 60 is formed, dielectric films 72 and 74 are formed on the wiring layer 60. Next, recesses for forming power lines 76 are formed in the dielectric films 72 and 74. For example, these recesses include a recess for forming a plug portion 76b and a recess for forming a wiring portion 76a. For example, the recess for forming the plug portion 76b may be formed in the dielectric film 72 (and dielectric film 74) first, and then the recess for forming the wiring portion 76a may be formed in the dielectric film 74. Next, metal films are formed on the dielectric films 72 and 74 to fill these recesses. Next, when a portion of the metal film is removed by CMP or etching, power lines 76 are formed on the wiring layer 70, as shown in Figure 2C.

[0043] Next, as shown in Figure 2D, recesses RC1 and RC2, a high-dielectric film 90, and a dielectric film 82 are formed in the wiring layer 70 (dielectric film 74). Recess RC1 may include a recess in which a ground wire 86 is formed. Recess RC2 may include a recess in which a signal wire 88 is formed. As an example, recesses RC1 and RC2 can be formed in the dielectric film 74 by photolithography patterning and plasma etching. Recesses RC1 and RC2 are formed such that a portion of the dielectric film 72 is exposed at their bottoms.

[0044] Then, as shown in Figure 2D, a high-dielectric film 90 and a dielectric film 82 are formed. The high-dielectric film 90 is formed on the dielectric film 72 and the dielectric film 74. The high-dielectric film 90 may be formed on the upper surface of the dielectric film 74, the side surface of the dielectric film 74, and a part of the upper surface of the dielectric film 72. The recesses RC1 and RC2 may be defined by the side surface of the dielectric film 72 and the upper surface of the dielectric film 72. Also, as shown in Figure 2D, the dielectric film 82 is formed on the high-dielectric film 90.

[0045] Next, a dielectric film 84 is formed as shown in Figure 2E. The dielectric film 84 may be formed on the dielectric film 82 so as to fill the recesses RC1 and RC2 shown in Figure 2D. The surface of the dielectric film 84 may be planarized by CMP or etching.

[0046] Next, as shown in Figure 2F, recesses RC3 and RC4 are formed in the wiring layers 70 and 80. Recess RC3 may include a recess in which a ground wire 86 is formed. Recess RC4 may include a recess in which a signal wire 88 is formed. For example, recesses RC3 and RC4 can be formed in the wiring layers 70 and 80 by photolithography patterning and plasma etching. For example, recesses RC3 and RC4 may be formed by selectively etching dielectric films 74, 82 and 84 relative to the high dielectric film 90.

[0047] Next, recesses RC5 and RC6 are formed as shown in Figure 2G. Recesses RC5 and RC6 can be formed by removing a portion of the high dielectric film 90 and a portion of the dielectric film 72 at the bottom of recesses RC3 and RC4. For example, recesses RC5 and RC6 can be formed by patterning by photolithography and etching by plasma. Recess RC5 can be formed by selective etching of a portion of the high dielectric film 90 and a portion of the dielectric film 72 with respect to the wiring 66. Recess RC6 can also be formed by selective etching of a portion of the high dielectric film 90 and a portion of the dielectric film 72 with respect to the wiring 68. Recess RC5 includes a recess in which the plug portion 86c of the ground wire 86 is formed. Recess RC6 also includes a recess in which the plug portion 88c of the signal wire 88 is formed.

[0048] Furthermore, recesses RC3 and RC4 may be formed after recesses RC5 and RC6 are formed. That is, first, after the dielectric film 84 is formed in Figure 2E, the dielectric films 84 and 82, the high-dielectric film 90, and the dielectric film 72 may be etched to form recesses RC5 and RC6. Then, the dielectric films 84 and 82 may be etched to form recesses RC3 and RC4.

[0049] Next, as shown in Figure 2H, a ground wire 86 and a signal wire 88 are formed. That is, first, a metal film is formed to fill the recesses RC3 to RC6. Then, by removing the metal film by CMP or etching until the upper surface of the dielectric film 84 is exposed, the ground wire 86 and the signal wire 88 can be formed.

[0050] Figure 3 is a schematic cross-sectional view showing another example of the structure of the semiconductor device 100. In the example shown in Figure 3, wiring layers 30 to 50 are arranged above the main surface 12 of the substrate 10. Also, wiring layers 130 to 180 are arranged below the second main surface 14 of the substrate 10. Wiring layers 130 to 180 may have the same configuration and / or function as wiring layers 30 to 80 shown in Figure 1. Wirings 136 to 166 may have the same configuration and / or function as wirings 36 to 66 shown in Figure 1. In addition, power lines 176 and ground lines 186 may have the same configuration and / or function as power line 76 and ground line 86 shown in Figure 1, respectively.

[0051] In the example shown in Figure 3, the wires 36-56 may be signal lines or wires electrically connected to signal lines. Also, the wires 136-166 may be wires electrically connected to power lines 176 or ground lines 186. The multiple plugs 116 electrically connect the multiple elements 22 and the multiple wires 136. One end of the multiple plugs 116 may be connected to the wires 136 on the main surface 14 of the substrate 10. The other end of the multiple plugs 116 may be connected to the multiple elements 22 inside the substrate 10. That is, the multiple plugs 116 may be formed inside the substrate 10, extending from the main surface 14 to the multiple elements 22.

[0052] Figure 4 is a schematic cross-sectional view showing another example of the structure of the semiconductor device 100. In the example shown in Figure 4, wiring layers 30 to 50 are arranged above the main surface 12 of the substrate 10. Also, wiring layers 170 and 180 are arranged below the second main surface 14 of the substrate 10. That is, the semiconductor device 100 shown in Figure 4 differs from the semiconductor device 100 shown in Figure 3 in that it does not have the wiring layers 130 to 150 shown in Figure 3. In the example shown in Figure 4, one end of each of the plugs 116 can be connected to a power line 176 and a ground line 186 on the main surface 14 of the substrate 10. The other end of each of the plugs 116 can be connected to a plurality of elements 22 inside the substrate 10.

[0053] Furthermore, in the example shown in Figure 4, wiring layers 270 and 280 may be further arranged below wiring layers 170 and 180. Wiring layers 270 and 280 may have the same configuration and / or function as wiring layers 170 and 180. Power line 276 may be connected to power line 176. Grounding line 286 may be connected to grounding line 186. Note that dielectric film 272 may be formed from a material with a higher dielectric constant than dielectric film 274. For example, dielectric film 272 may be formed from the same material as high dielectric film 290.

[0054] According to one embodiment of the present disclosure, in a semiconductor device, it is possible to improve the decoupling capacitance between the power line and the ground line while suppressing parasitic capacitance between signal lines. Furthermore, according to one embodiment of the present disclosure, it is possible to reduce the resistance values ​​of the power line and the ground line in a semiconductor device. Furthermore, according to one embodiment of the present disclosure, it is possible to improve the heat dissipation efficiency of the power line and the ground line in a semiconductor device.

[0055] This disclosure may include, for example, the following configurations:

[0056] (Note 1) A substrate having a first main surface and a second main surface, A plurality of elements formed on the first main surface of the substrate or above the first main surface, At least one first power line electrically connected to at least one of the plurality of elements, wherein the at least one first power line is arranged in a first layer provided above the first main surface of the substrate, and the at least one first power line has a top surface, a first side surface continuous with the top surface, and a second side surface facing the first side surface and continuous with the top surface, At least one second power line is arranged in the first layer and the second layer above the first layer, wherein the at least one second power line is arranged from the second layer to the first layer such that a portion of the at least one first power line covers the top surface, the first side surface and the second side surface, and A semiconductor device equipped with the following features.

[0057] (Note 2) The semiconductor device according to Appendix 1, further comprising at least two signal lines electrically connected to at least one of the plurality of elements, wherein the at least two signal lines are arranged in at least the first layer.

[0058] (Note 3) The semiconductor device according to Appendix 2, wherein the at least two signal lines are arranged from the second layer to the first layer.

[0059] (Note 4) A first dielectric film disposed between the at least two signal lines in the first layer, wherein the first dielectric film has a first dielectric constant, A second dielectric film disposed between the at least one first power line and the at least one second power line in the first layer, wherein the second dielectric film has a second dielectric constant higher than the dielectric constant of the first dielectric film and A semiconductor device as described in Appendix 2 or 3, further comprising the above.

[0060] (Note 5) The semiconductor device according to any one of appendices 2 to 4, wherein in the first layer, the spacing between the at least two signal lines is wider than the spacing between the at least one first power line and the at least one second power line.

[0061] (Note 6) In the first layer, each of the at least two signal lines includes a wiring portion and a plug portion. In the first layer, the at least one first power line includes a wiring portion and a plug portion. The semiconductor device according to any one of the appendices 2 to 4, wherein the length of the plug portion of at least two signal lines is longer than the length of the plug portion of at least one first power line.

[0062] (Note 7) A semiconductor device according to any one of the appendices 1 to 6, wherein, in a plan view of the first main surface, the at least one first power line and the at least one second power line are arranged to intersect.

[0063] (Note 8) The semiconductor device according to any one of the appendices 2 to 7, wherein the cross-sectional area of ​​at least one first power line is larger than the cross-sectional area of ​​each of the at least two signal lines.

[0064] (Note 9) The semiconductor device described in any one of the appendices 1 to 8, wherein the second power line is a ground line.

[0065] (Note 10) A substrate having a first main surface and a second main surface, A plurality of elements formed on the first main surface of the substrate or above the first main surface, At least one first power line electrically connected to at least one of the plurality of elements, wherein the at least one first power line is arranged in a first layer provided below the second main surface of the substrate, and the at least one first power line has a bottom surface, a first side surface continuous with the bottom surface, and a second side surface facing the first side surface and continuous with the bottom surface, At least one second power line is arranged in the first layer and the second layer located below the first layer, wherein the at least one second power line is arranged from the second layer to the first layer such that a portion of the at least one first power line covers the bottom surface, the first side surface and the second side surface, and A semiconductor device equipped with the following features.

[0066] (Note 11) The semiconductor device according to Appendix 10, further comprising at least two signal lines electrically connected to at least one of the plurality of elements, wherein the at least two signal lines are arranged in a third layer which is also placed above the first main surface.

[0067] (Note 12) The semiconductor device described in Appendix 10 or 11, wherein the second power supply line is a ground line.

[0068] (Note 13) A substrate having a first main surface and a second main surface is prepared, Forming a plurality of elements on the first main surface of the substrate or above the first main surface, The present invention provides for the formation of at least one first power line electrically connected to at least one of the plurality of elements, wherein the at least one first power line is arranged in a first layer provided above the first main surface of the substrate, and the at least one first power line has a bottom surface, a first side surface continuous with the bottom surface, and a second side surface facing the first side surface and continuous with the bottom surface. To form at least one second power line arranged in a second layer above the first layer, wherein the at least one second power line is arranged from the second layer to the first layer so as to cover the bottom surface, the first side surface and the second side surface of at least two power lines. A method for manufacturing a semiconductor device, including the method described above.

[0069] In the exemplary embodiments described above, the semiconductor device and the method for manufacturing the semiconductor device can be modified in various ways without departing from the scope and spirit of the disclosure. For example, some components of one embodiment can be added to other embodiments within the ordinary creative ability of a person skilled in the art. Also, some components of one embodiment can be replaced with corresponding components of other embodiments. [Explanation of Symbols]

[0070] 10...Substrate, 12...First main surface, 14...Second main surface, 22...Element, 24...Dielectric film, 24, 26...Plug, 32, 34, 42, 44, 52, 54, 62, 64, 72, 74, 82, 84...Dielectric film, 46, 56...Wiring, 36, 46, 56, 66...Wiring, 36a, 46a, 56a, 66a, 76a, 78a, 86a, 86b...Wiring section, 36b, 46b, 56b, 66b, 76b, 78b, 86c...Plug section, 76...Power line, 76a...Wiring section, 76b...Plug section, 78...Signal line, 86...Ground line, 88...Signal line, 100...Semiconductor device

Claims

1. A substrate having a first main surface and a second main surface, A plurality of elements formed on the first main surface of the substrate or above the first main surface, At least one first power line electrically connected to at least one of the plurality of elements, wherein the at least one first power line is arranged in a first layer provided above the first main surface of the substrate, and the at least one first power line has a top surface, a first side surface continuous with the top surface, and a second side surface facing the first side surface and continuous with the top surface, and in the first layer, the at least one first power line includes a wiring portion and a plug portion, At least one second power line is arranged in the first layer and the second layer above the first layer, wherein the at least one second power line is arranged from the second layer to the first layer so as to cover the top surface, the first side surface and the second side surface of a portion of the at least one first power line, At least two signal lines electrically connected to at least one of the plurality of elements, wherein the at least two signal lines are arranged in at least the first layer, and in the first layer, each of the at least two signal lines includes a wiring portion and a plug portion, and the length of the plug portion of the at least two signal lines is longer than the length of the plug portion of the at least one first power line, and A semiconductor device equipped with the following features.

2. The semiconductor device according to claim 1, wherein the at least two signal lines are arranged from the second layer to the first layer.

3. A first dielectric film disposed between the at least two signal lines in the first layer, wherein the first dielectric film has a first dielectric constant, A second dielectric film disposed between the at least one first power line and the at least one second power line in the first layer, wherein the second dielectric film has a second dielectric constant higher than the dielectric constant of the first dielectric film and The semiconductor device according to claim 1, further comprising the above.

4. The semiconductor device according to claim 1, wherein in the first layer, the spacing between the at least two signal lines is wider than the spacing between the at least one first power line and the at least one second power line.

5. The semiconductor device according to claim 1, wherein, in a plan view of the first main surface, the at least one first power line and the at least one second power line are arranged to intersect.

6. The semiconductor device according to claim 1, wherein the cross-sectional area of ​​at least one first power line is larger than the cross-sectional area of ​​each of the at least two signal lines.

7. The semiconductor device according to any one of claims 1 to 6, wherein the second power line is a ground line.

8. A substrate having a first main surface and a second main surface, A plurality of elements formed on the first main surface of the substrate or above the first main surface, At least one first power line electrically connected to at least one of the plurality of elements, wherein the at least one first power line is arranged in a first layer provided below the second main surface of the substrate, and the at least one first power line has a bottom surface, a first side surface continuous with the bottom surface, and a second side surface facing the first side surface and continuous with the bottom surface, and in the first layer, the at least one first power line includes a wiring portion and a plug portion, At least one second power line is arranged in the first layer and the second layer located below the first layer, wherein the at least one second power line is arranged from the second layer to the first layer so as to cover the bottom surface, the first side surface and the second side surface of a portion of the at least one first power line, At least two signal lines electrically connected to at least one of the plurality of elements, wherein the at least two signal lines are arranged in at least the first layer, and in the first layer, each of the at least two signal lines includes a wiring portion and a plug portion, and the length of the plug portion of the at least two signal lines is longer than the length of the plug portion of the at least one first power line, and A semiconductor device equipped with the following features.

9. The semiconductor device according to claim 8, wherein the at least two signal lines are arranged in a third layer provided above the first main surface.

10. The semiconductor device according to claim 8 or 9, wherein the second power line is a ground line.

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