Method for controlling quantum computing systems and qubit arrays

Abstract

To provide a quantum computing system and a control method for a quantum bit array that efficiently and collectively control with a small amount of higher-order control information, a control sequence required for realizing a target operation in a quantum computing system.SOLUTION: A quantum computing system comprises: a quantum bit array where a plurality of quantum bits with characteristics changeable by a bias voltage are arranged one or two dimensionally; a bias voltage changeover switch matrix that selects the bias voltage applied to the quantum bit array; a bias voltage control register that controls operation of the bias voltage changeover switch matrix; and an instruction conversion unit including a bias voltage waveform pattern generation unit that generates a setting pattern for a bias voltage control register. The bias voltage waveform pattern generating unit generates one or more bias voltage waveform patterns required for executing quantum operation, on the basis of instruction values that specify a type of a quantum operation to be executed by the quantum bits and coordinates of the quantum bits being targets of the operation.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a gated quantum computer system, and particularly relates to a quantum dot array control device and a control method that, when combined with a quantum arithmetic device in which single-electron spin qubits are arranged in an array, achieve efficient operation with a small number of control signals for each quantum dot in the quantum device, that is, generation of bias voltage application sequences. Background Art

[0002] Performance improvement through miniaturization of semiconductor elements, which has supported the development of computers for more than half a century, is widely expected to reach its limit in the near future when comparing process rules with the interatomic distance of silicon. Quantum computers are an attempt to break through this limit using new computing principles and devices, and quantum arithmetic devices and arithmetic methods using superconducting circuits, ion traps, photons, silicon quantum dots, and the like have been proposed. In addition, as a preliminary step toward the future vision of executing large-scale practical applications on an error-tolerant general-purpose quantum computer system, at present, principle verification and algorithm exploration are underway for a system called NISQ (Noisy Intermediate-Scale Quantum device), which is based on the premise that the number of qubits is as small as about 100 and error correction is not possible.

[0003] To realize a quantum computer system applying a quantum arithmetic device that uses quantum effects exhibited at extremely low temperatures as the arithmetic principle, such as a single electron spin in a silicon quantum dot, it is customary to select a dilution refrigerator as the device to be incorporated. In this case, the quantum arithmetic device is fixed to the mixing chamber where the temperature is the lowest in the dilution refrigerator, signals required for operation control of the quantum arithmetic device are applied from a signal generator arranged outside the dilution refrigerator, and the operation result is read out by a measuring instrument outside the dilution refrigerator, so a configuration similar to that of an experimental apparatus is often adopted. Prior Art Documents Patent Documents

[0004] [Patent Document 1] U.S. Patent No. 10635990 [Overview of the Initiative] [Problems that the invention aims to solve]

[0005] Patent Document 1 discloses a technique for utilizing analog memory when applying voltage to bias voltage control lines that control qubits. One or more capacitors in each cell of the analog memory are charged to a predetermined voltage value, and in cooperation with an external switch matrix, the voltage is switched to output to each bias voltage control line, thereby realizing bias voltage control including sequences. When the number of qubits is small and the number of bias control lines to be controlled is also small, direct control at the bias control line level is sufficiently efficient, but in large-scale systems containing many qubits, a control method based on control units with a higher level of abstraction than bias control lines is desired.

[0006] The wiring connecting the inside and outside of a dilution refrigerator not only transmits power and signals but also acts as a medium for heat conduction. Therefore, there is a constraint unique to quantum computers: only the minimum necessary number of wires can be laid, determined by the balance between the target temperature of the mixing chamber and the cooling capacity of the dilution refrigerator. This constraint becomes even more severe when aiming to scale up from current NISQ-type systems to future general-purpose quantum computers. Even for quantum computing devices that integrate a large number of qubits in an array, as a means of ensuring the scalability of quantum operations, it is desirable to be able to perform flexible control with a small number of control signals.

[0007] The present invention has been made in view of the above problems, and aims to provide a quantum dot array control device, a control method, and a quantum computer system including a quantum dot array control device that enable collectively control of a quantum computing device for realizing a target computation sequence by replacing the primitive control information required by each qubit with a small amount of higher-order control information abstracted based on the array structure of the quantum computing device, rather than directly supplying the primitive control information required by each qubit to each qubit using a large number of control signal lines connected to the outside of the device. [Means for solving the problem]

[0008] One aspect of the present invention is a quantum computing system comprising: a qubit array in which a plurality of qubits whose characteristics are variable by a bias voltage are arranged in one or two dimensions; a bias voltage selection circuit for selecting a bias voltage to be supplied to the qubit array; a bias voltage control register for controlling the operation of the bias voltage selection circuit; and a bias voltage waveform pattern generation circuit for generating setting patterns for the bias voltage control register, wherein the bias voltage waveform pattern generation circuit generates one or more bias voltage waveform patterns necessary for executing the quantum operation based on the type of quantum operation to be performed on the qubits and an instruction value that identifies the coordinates of the qubits to be operated on.

[0009] Another aspect of the present invention is a method for controlling a qubit array, which is arranged in a first temperature environment and has multiple qubits whose characteristics are variable by a bias voltage. The method involves supplying a bias voltage to the qubit array, which is arranged in a first temperature environment and has multiple qubits whose characteristics are variable by a bias voltage. The method includes: a first step in which an information processing device, located in a second temperature environment at a higher temperature than the first temperature environment, outputs position information to identify the qubits and command information indicating the processing that the qubits should perform; a second step in which a bias voltage waveform pattern generation unit, located in a third temperature environment at a lower temperature than the second temperature environment, outputs bias control address information to identify a bias control switch to be controlled and bias control data information to identify a bias voltage value that the bias control switch should select, based on the position information and the command information; and a third step in which the bias voltage is applied to the qubits based on the bias control address information and the bias control data information, and the processing to be performed on the qubits identified in the first step. [Effects of the Invention]

[0010] According to the quantum computing system and qubit control method equipped with a bias voltage waveform pattern generation circuit according to the present invention, for quantum computing devices in which a large number of qubits are arranged in an array, a more abstract and flexible control can be scalably realized with a small number of control signals, instead of primitive control that requires a large number of control signals. [Brief explanation of the drawing]

[0011] [Figure 1] This is a block diagram showing the configuration of the quantum computing system 1 according to the first embodiment. [Figure 2] This is a block diagram showing part of the configuration of the quantum dot array 340. [Figure 3] This diagram shows the ID (SID) assigned to the bias control switch. [Figure 4] This is a diagram illustrating the definition of the bias voltage code. [Figure 5] This is a block diagram showing part of the configuration of the bias voltage switching switch matrix 330. [Figure 6] It is a drawing showing an example of a voltage waveform applied to a bias control line. [Figure 7] It is a block diagram showing a configuration of an instruction conversion unit 210. [Figure 8] It is a block diagram showing a configuration of a bias voltage waveform pattern generation unit 2130. [Figure 9] It is a drawing showing an example of the content of a coordinate-switch ID conversion table 2131. [Figure 10] It is a drawing showing an example of the content of a bias voltage waveform template 2133. [Figure 11] It is a timing chart showing an example of an instruction execution control sequence. [Figure 12] It is a block diagram showing a configuration of a first modified example 2130A of the bias voltage waveform pattern generation unit. [Figure 13] It is a drawing showing an example of the content of a bias voltage waveform template 2133A. [Figure 14] It is a block diagram showing a configuration of a second modified example 2130B of the bias voltage waveform pattern generation unit. [Figure 15] It is a drawing showing an example of the content of a coordinate-switch ID conversion table 2131B. [Figure 16] It is a drawing showing an example of the content of a bias voltage waveform template 2133B. [Figure 17] It is a block diagram showing a configuration of a third modified example 2130C of the bias voltage waveform pattern generation unit. [Figure 18] It is a drawing showing an example of the content of a bias voltage waveform template 2133C. [Figure 19] It is a block diagram showing a configuration of a quantum operation system 1A according to a second embodiment. [Figure 20] It is a block diagram showing a configuration of a quantum operation system 1B according to a third embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0012] This embodiment will be described below with reference to the attached drawings. In the attached drawings, functionally identical elements may be indicated by the same or corresponding numbers. The attached drawings show embodiments and examples in accordance with the principles of this disclosure, but they are for the purpose of understanding this disclosure and are not to be used in any way to restrict the interpretation of this disclosure. The descriptions in this specification are typical examples and do not limit the claims or applications of this disclosure in any way.

[0013] While this embodiment is described in sufficient detail for those skilled in the art to implement the disclosure, other implementations and forms are possible, and it is important to understand that the configuration and structure can be changed and various elements replaced without departing from the scope and spirit of the technical idea of ​​this disclosure. Therefore, the following description should not be interpreted as limiting it to this embodiment.

[0014] To solve the aforementioned problems, the quantum computing system according to this embodiment comprises a qubit array in which a plurality of qubits whose characteristics are variable by a bias voltage are arranged in one or two dimensions, a bias voltage selection circuit for selecting a bias voltage to be supplied to the qubit array, a bias voltage control signal register for controlling the operation of the bias voltage selection circuit, and a bias voltage waveform pattern generation circuit for generating setting patterns for the bias voltage control register.

[0015] Furthermore, the bias voltage waveform pattern generation circuit is characterized by realizing a qubit control method that generates one or more bias voltage waveform patterns necessary for executing the quantum operation, based on the type of quantum operation to be performed by the qubit and an instruction value that identifies the coordinates of the qubit to be operated on. [Examples]

[0016] Figure 1 shows the configuration of a quantum computing system 1 according to the first embodiment of the present invention. This embodiment is a system that combines a quantum device 300 that performs quantum operations with a host PC 100 that oversees the entire quantum operation sequence and a control device 200 that converts high-level control signals from the host PC 100 into primitive control signals required by the quantum device 300.

[0017] The host PC 100 is typically installed in a room temperature environment (e.g., 20°C). On the other hand, the quantum dot array 340 of the quantum device 300 is placed in the mixing chamber (a cryogenic environment, e.g., minus 272°C) where the temperature is lowest within the dilution refrigerator, enabling the operation of the qubits. The other components are placed between the room temperature environment and the cryogenic environment. In this case, the temperature gradient changes from high temperature to low temperature along the signal flow from the host PC 100 to the quantum dot array 340. For example, the semiconductor chips constituting the quantum device 300 are placed in a dilution refrigerator to create a cryogenic environment, while the semiconductor chips constituting the control device 200 are placed in an environment lower than room temperature (but not the cryogenic environment in which the qubits operate). However, for example, the control device 200 and the quantum device 300 may be composed of the same semiconductor chip, and the entire system may be placed in a dilution refrigerator to create a cryogenic environment.

[0018] The host PC 100 is a general-purpose personal computer equipped with a microprocessor (not shown), memory, storage device, input device, output device, etc., and is running a system control application that manages the overall control of the quantum computation sequence to be executed by the quantum computing system 1.

[0019] The system control application interprets the specified quantum operation sequence and outputs control information necessary for quantum operations via the interface unit 110, namely X-coordinate information 120 and Y-coordinate information 121 indicating the position of the quantum dot to be subjected to quantum operation within the quantum dot array 340, instruction information 122 indicating the process (instruction) that the quantum dot should execute, instruction conversion control signal 130 controlling the start of instruction conversion processing based on the control information, and bias voltage setting signal 140 which sets the bias voltage to be supplied from the control device 200 to the quantum device 300.

[0020] Here, some or all of the X-coordinate information 120, Y-coordinate information 121, instruction information 122, instruction conversion control signal 130, and bias voltage setting signal 140 may share a single physical communication interface connecting the host PC 100 and the control device 200. Furthermore, the communication interface may be an interface based on standard communication specifications such as USB(trademark), SPI(trademark), I2C(trademark), RS-232C, PCI Express(trademark), or Ethernet(trademark), or it may be a proprietary specification based on general-purpose I / O.

[0021] The control device 200 includes an instruction conversion unit 210, a sequence control unit 230, a bias voltage generation unit 250, and an RF signal generation unit 260.

[0022] When the sequence control unit 230 receives an instruction execution request from the instruction conversion control signal 130, it instructs the instruction conversion unit 210 to perform the instruction conversion process via the instruction conversion control information 241 and waits for the instruction conversion process to be completed. When the completion of the instruction conversion process is notified by the instruction conversion response information 242, the sequence control unit 230 instructs the quantum device 300 to switch the bias voltage applied to the quantum dot array 340 via the bias voltage switching strobe 240, and at the same time instructs the RF signal generation unit 260 to output the RF signal 261 via the RF signal output strobe 243.

[0023] The instruction conversion unit 210, having received instructions to perform instruction conversion processing from the instruction conversion control information 241, outputs one or more sets of bias control information 220 necessary for identifying the bias voltage to be applied to the quantum dot array 340, and a bias control information strobe 223 indicating the timing at which the quantum device 300 should acquire the bias control information 220, based on the X coordinate information 120, the Y coordinate information 121, and the instruction information 122.

[0024] The bias control information 220 consists of bias control address information 221 that specifies an ID associated with the bias control switch to be controlled, and bias control data information 222 associated with the bias voltage value that the switch should select. Furthermore, the bias control information 220 and the bias control information strobe 223 may be completed in one step for a single instruction, or they may include two or more steps. In any case, once the conversion process for the specified instruction is completed, the sequence control unit 230 is notified of the completion of the conversion process by the instruction conversion response information 242.

[0025] The bias voltage generation unit 250 includes multiple D / A conversion circuits, each with a programmable output voltage. Each channel independently outputs a specified voltage to the bias voltage supply line 251 based on a setting request from the bias voltage setting signal 140. While not particularly limited, the number of channels, i.e., the number of bias voltage supply lines 251, is implemented at a rate equal to or greater than the number required for quantum operations in the quantum dot array 340, and the voltage is not changed during instruction execution.

[0026] The quantum device 300 comprises a control register write control unit 310, a bias voltage control register 320, a bias voltage switching switch matrix 330, and the quantum dot array 340.

[0027] When the control register write control unit 310 detects, via the bias control information strobe 223, that it is time to retrieve the contents of the bias control information 220, it instructs the bias voltage control register 320 via the control register write control signal 311 to write the setting value specified in the bias control data information 222 to the register that controls the bias control switch identified by the bias control address information 221, which is one of the registers constituting the bias voltage control register 320.

[0028] The bias voltage control register 320 holds a setting value for each bias control switch that constitutes the bias voltage switching switch matrix 330, which is referenced when switching the bias voltage applied to the quantum dot array 340. The setting value of the control register is output to the bias voltage switching switch matrix 330 as the bias voltage control register setting value 321.

[0029] When the bias voltage switching switch matrix 330 detects that it is the bias voltage switching timing instructed by the sequence control unit 230 via the bias voltage switching strobe 240, it first latches the bias voltage control register setting value 321 using an internal latch circuit (not shown). Subsequently, it selects the bias voltage to be applied to the bias voltage control line by connecting it to one of the bias voltage supply lines 251 specified by the latched setting value using a bias control switch provided for each bias voltage control line that controls the quantum dots. The bias voltage selected by all bias control switches is output to the quantum dot array 340 as the quantum dot array applied bias voltage control line 331.

[0030] Figure 2 shows an example of the circuit configuration of the quantum dot array (qubit array) 340. The qubits are realized by confining a single electron within a potential barrier formed in a silicon channel with a MOS (Metal-Oxide Semiconductor) structure. Multiple quantum dots are arranged in a two-dimensional lattice array structure via transfer gates that control the movement and interaction of electrons between quantum dots. Each quantum dot is assigned coordinates that specify its position in the X (horizontal) and Y (vertical) directions within the array.

[0031] The quantum dot array applied bias voltage control lines 331 include bias control line XQ for gate control of quantum dot control gate MOS arranged in the X direction, bias control lines YQW-YQE for gate control of quantum dot control gate MOS arranged in the Y direction, bias control lines XJN-XJS for gate control of transfer gate MOS connecting quantum dots in the X direction, and bias control lines YJW-YJE for gate control of transfer gate MOS connecting quantum dots in the Y direction.

[0032] By applying a magnetic field to a quantum dot containing a single electron, and further irradiating it with a high-frequency signal that matches (resonates with) the electron spin precession determined by the strength of the magnetic field, the electron spin rotates and quantum computation can be performed. However, in a quantum dot array containing multiple quantum dots, a means is needed to select or deselect the quantum dots to which quantum computation is to be performed. Specifically, for example, one method is envisioned in which a local magnetic field is generated by the current flowing through appropriately controlling the bias voltage of the bias voltage control line, thereby locally modulating the strength of the magnetic field at each quantum dot position and slightly shifting the resonance frequency of the electron spin precession. In that case, by inputting a high-frequency signal from the RF signal 261 that matches the resonance frequency of the selected quantum dots, only the selected quantum dots will selectively perform quantum computation.

[0033] Figure 3 shows an example of a switch ID (SID) defined in the bias voltage switching switch matrix 330 to identify each of the quantum dot array applied bias voltage control lines 331, that is, each of the bias control switches that select and output the bias voltage to be applied to the bias voltage control line. Although not particularly limited, this definition shall also be used as part of the bias control address information 221 and the control register write control signal 311.

[0034] Figure 4 shows an example of a definition of a bias voltage code for identifying the bias voltage supplied to the bias voltage switching switch matrix 330 by the bias voltage supply line 251. While not particularly limited, the bias voltage supply line 251 includes a total of 55 different bias voltages required for performing specific operations on a single electron confined within a quantum dot, and the specific voltage values ​​corresponding to each voltage code are assumed to have been experimentally determined in advance.

[0035] Figure 5 shows a detailed example of a typical bias control switch configuration included in the bias voltage switching switch matrix 330. The quantum dot array applied bias voltage control line 331 is connected to independent bias control switches SXJN[i], SXJS[i], SYJW[k], and SYJE[k] for each controlled object. When each bias control switch detects the bias voltage switching timing indicated by the bias voltage switching strobe 240, it internally latches the setting value (binary, or a bitmap decoded from binary) for its own switch from the bias voltage control register setting value 321. Subsequently, it selects one of the supply lines of the bias voltage supply line 251 specified by the latched setting value, thereby outputting a bias voltage with a voltage value reflecting the setting value.

[0036] While not particularly limited, it is desirable that each bias control switch be configured such that it selects only the bias voltage supply lines from the bias voltage supply line 251 that have the potential to output to the corresponding control line within the quantum dot array applied bias voltage control line 331, which is the target of control of the bias control switch. This reduces the circuit size of the bias control switch.

[0037] Figure 6 shows an example of the bias voltage to be applied from the quantum dot array bias voltage control line 331 and the period during which a high frequency should be input from the RF signal 261 when executing a predetermined quantum operation (instruction) targeting one quantum dot in the quantum dot array 340. Here, the state in which a specific bias voltage is continuously applied to the quantum dot array 340 from the quantum dot array bias voltage control line 331 is called a bias voltage waveform block. In the case of the instruction shown in this figure, it consists of two bias voltage waveform blocks.

[0038] Here, symbols such as VL, VL1s, VL1n, VL3w, and VL4e are bias voltage codes defined in Figure 4, indicating that the bias voltage identified by the code is applied to the bias voltage control line. Note that while RF signals are shown simply for the period when high-frequency signals are input, they should normally have a waveform with an envelope designed to minimize the loss of fidelity that occurs during command execution.

[0039] Figure 7 shows an example of the detailed configuration of the instruction conversion unit 210. The instruction conversion unit 210 includes an X-coordinate register 2100, a Y-coordinate register 2110, an instruction register decoder 2120, a bias voltage waveform pattern generation unit 2130, and a transfer control unit 2140. Of these, the details of the bias voltage waveform pattern generation unit 2130 will be described later with reference to Figure 8.

[0040] When the X-coordinate register 2100 receives an instruction to start the conversion process from the transfer control unit 2140 via the instruction conversion start strobe 2141, it latches the contents of the X-coordinate information 120 and outputs the latched contents as the latched X-coordinate information 2101.

[0041] When the Y-coordinate register 2110 receives an instruction from the transfer control unit 2140 to start the conversion process via the instruction conversion start strobe 2141, it latches the contents of the Y-coordinate information 121 and outputs the latched contents as the latched Y-coordinate information 2111.

[0042] When the instruction register decoder 2120 receives an instruction to start the conversion process from the transfer control unit 2140 via the instruction conversion start strobe 2141, it latches the contents of the instruction information 122, decodes the latched instruction information, and outputs the decoded result as decoded instruction information 2121. The decoded result may include, but is not particularly limited, a bias voltage waveform block ID that identifies the entry point of the bias voltage waveform template (described later) necessary for the execution of the instruction, and / or the number of bias voltage waveform blocks for the instruction.

[0043] When the transfer control unit 2140 receives an instruction to perform instruction conversion processing from the sequence control unit 230 via the instruction conversion control information 241, it first notifies the X coordinate register 2100, the Y coordinate register 2110, and the instruction register decoder 2120 of the start of conversion processing using the instruction conversion start strobe 2141.

[0044] Next, the transfer control unit 2140 obtains the instruction decoding result from the decoded instruction information 2121 relating to the latched instruction, and instructs the bias voltage waveform pattern generation unit 2130, via the bias voltage waveform template control information 2142, to perform instruction conversion processing, i.e., conversion to the bias control information 220 necessary to execute the specified instruction for the quantum dot at the specified coordinates, on a bias voltage waveform block-by-block basis. In addition, the transfer control unit 2140 notifies the control register write control unit 310 via the bias control information strobe 223 that the contents of the bias control information 220 are valid and that the bias control information can be latched on the quantum device 300 side.

[0045] When processing for the first bias voltage waveform block constituting the instruction is completed, the transfer control unit 2140 updates the contents of the bias voltage waveform template control information 2142 and sequentially processes subsequent bias voltage waveform blocks on a bias voltage waveform block basis. When the transfer of the last bias control information 220 for the last bias voltage waveform block constituting the instruction is completed, the transfer control unit 2140 notifies the sequence control unit 230 of the completion of the instruction conversion process via the instruction conversion response information 242. Although not particularly limited, in an instruction composed of multiple bias voltage waveform blocks, the bias voltage waveform block IDs that identify each block are assigned in ascending order from the first block. Furthermore, the same bias voltage waveform block ID may be assigned to bias voltage waveform blocks that are common to multiple instructions.

[0046] Figure 8 shows an example of the detailed configuration of the bias voltage waveform pattern generation unit 2130. The bias voltage waveform pattern generation unit 2130 includes a coordinate-switch ID conversion table 2131, a bias voltage waveform template 2133, and a transfer arbitration unit 2139. In general terms, the bias voltage waveform template 2133 generates a bias voltage waveform pattern linked to a bias voltage waveform block that constitutes the instruction to be executed, and the coordinate-switch ID conversion table 2131 identifies the bias control switch to which the bias voltage waveform pattern should be applied, both independently and simultaneously.

[0047] The coordinate-switch ID conversion table 2131 converts the latched X coordinate information 2101 and the latched Y coordinate information 2111, which indicate the coordinates of the quantum dot targeted for instruction execution, into switch IDs (see Figure 3 for definitions) that identify, for example, eight bias control switches in the bias voltage switching switch matrix 330 that should be controlled for instruction execution at the quantum dot. The conversion results are simultaneously output as bias control address information 2132-1, 2132-2, 2132-3, 2132-4, 2132-5, 2132-6, 2132-7, and 2132-8. The number of outputs and the number of bias control switches to be controlled depend on the control method of the quantum dot array.

[0048] Specific examples of each bias control address information are as follows. To explain in more detail, an example is given in Figure 2 where the quantum dot indicated by symbol A is the quantum dot targeted for instruction execution.

[0049] Bias control address information 2132-1: The SID (XJ_UL) of the bias control switch XJN located at the upper end of the bias control line XJN-XJS, which controls the transfer gate connected to the left side of the quantum dot targeted for instruction execution. In the example in Figure 2, this is the switch ID of the switch connected to XJN[0].

[0050] Bias control address information 2132-2: The SID (XJ_UR) of the bias control switch XJN located at the upper end of the bias control line XJN-XJS, which controls the transfer gate connected to the right side of the quantum dot targeted for instruction execution. In the example in Figure 2, this is the switch ID of the switch connected to XJN[1].

[0051] Bias control address information 2132-3: The SID (XJ_LL) of the bias control switch XJS located at the lower end of the bias control line XJN-XJS, which controls the transfer gate connected to the left side of the quantum dot targeted for instruction execution. In the example in Figure 2, this is the switch ID of the switch connected to XJS[0].

[0052] Bias control address information 2132-4: The SID (XJ_LR) of the bias control switch XJS located at the lower end of the bias control line XJN-XJS, which controls the transfer gate connected to the right side of the quantum dot targeted for instruction execution. In the example in Figure 2, this is the switch ID of the switch connected to XJS[1].

[0053] Bias control address information 2132-5: The SID (YJ_UL) of bias control switch YJW, located at the left end of the bias control line YJW-YJE, which controls the transfer gate connected to the upper side of the quantum dot targeted for instruction execution. In the example in Figure 2, this is the switch ID of the switch connected to YJW[0].

[0054] Bias control address information 2132-6: The SID (YJ_UR) of bias control switch YJE, located at the right end of the bias control line YJW-YJE, which controls the transfer gate connected to the upper side of the quantum dot targeted for instruction execution. In the example in Figure 2, this is the switch ID of the switch connected to YJE[0].

[0055] Bias control address information 2132-7: The SID (YJ_LL) of bias control switch YJW, located at the left end of the bias control line YJW-YJE, which controls the transfer gate connected to the lower side of the quantum dot targeted for instruction execution. In the example in Figure 2, this is the switch ID of the switch connected to YJW[1].

[0056] Bias control address information 2132-8: The SID (YJ_LR) of bias control switch YJE, located at the right end of the bias control line YJW-YJE, which controls the transfer gate connected to the lower side of the quantum dot targeted for instruction execution. In the example in Figure 2, this is the switch ID of the switch connected to YJE[1].

[0057] The conversion from quantum dot coordinates to switch IDs has the advantage of being uniquely determined from the layout of quantum dots and bias control lines within the quantum dot array. Therefore, in implementation, it is possible to simply use read-only memory or a hardwired logic circuit. Depending on the encoding definition of the switch IDs, it may also be implemented as an arithmetic circuit combining adder and shift circuits.

[0058] The bias voltage waveform template 2133 converts the bias voltage waveform block ID included in the bias voltage waveform template control information 2142 into setting values ​​to be set for each bias control switch specified by the bias control address information 2132-1 to 2132-8 in the bias voltage waveform block that constitutes the currently executing instruction, and simultaneously outputs the conversion results as bias control data information 2135-1, 2135-2, 2135-3, 2135-4, 2135-5, 2135-6, 2135-7, and 2135-8, corresponding to each of the bias control address information 2132-1 to 2132-8. The setting values ​​that can be set for the bias control switches, and the bias voltage values ​​corresponding to each setting value, depend on the detailed configuration of the bias voltage switching switch matrix 330.

[0059] Specific examples of bias control data information are as follows:

[0060] Bias control data information 2135-1: Control value SWNO(XJ_UL) for bias control switch XJN located at the upper end of bias control line XJN-XJS, which controls the transfer gate connected to the left side of the quantum dot targeted for instruction execution. Bias control data information 2135-2: Control value SWNO(XJ_UR) for bias control switch XJN located at the upper end of bias control line XJN-XJS, which controls the transfer gate connected to the right side of the quantum dot targeted for instruction execution. Bias control data information 2135-3: Control value SWNO(XJ_LL) for bias control switch XJS located at the lower end of bias control line XJN-XJS, which controls the transfer gate connected to the left side of the quantum dot targeted for instruction execution. Bias control data information 2135-4: Control value SWNO(XJ_LR) for bias control switch XJS located below bias control line XJN-XJS, which controls the transfer gate connected to the right side of the quantum dot targeted for instruction execution. Bias control data information 2135-5: Control value SWNO(YJ_UL) for bias control switch YJW, located at the left end of bias control line YJW-YJE, which controls the transfer gate connected to the upper side of the quantum dot targeted for instruction execution. Bias control data information 2135-6: Control value SWNO(YJ_UR) for bias control switch YJE, located at the right end of bias control line YJW-YJE, which controls the transfer gate connected to the upper side of the quantum dot targeted for instruction execution. Bias control data information 2135-7: Control value SWNO(YJ_LL) for bias control switch YJW, located at the left end of bias control line YJW-YJE, which controls the transfer gate connected to the lower side of the quantum dot targeted for instruction execution. Bias control data information 2135-8: Control value SWNO(YJ_LR) for bias control switch YJE, located at the right end of bias control line YJW-YJE, which controls the transfer gate connected to the lower side of the quantum dot targeted for instruction execution. The conversion from bias voltage waveform block ID to bias control address information / bias control data information differs for each quantum phenomenon induced by that bias voltage waveform block on electron spins within the quantum dot. Therefore, once the combination and variations of quantum phenomena, i.e., the instruction set, are defined, the contents of the bias voltage waveform template 2133 are also determined based on that.

[0061] By adding means for rewriting the contents of the bias voltage waveform template 2133 via the instruction conversion control signal 130, the instruction conversion control information 241, and the bias voltage waveform template control information 2142, or by adding means for directly connecting the interface unit 110 and the bias voltage waveform template 2133, the instruction set can be replaced with one optimized for the application that the quantum computing system 1 wants to execute, without changing the design of the quantum dot array 340, thereby improving the practicality of the quantum computing system 1.

[0062] To reiterate, note that the coordinate-switch ID conversion table 2131 is uniquely determined from the quantum dot array layout and is therefore unaffected by instruction set swapping. However, if the number of instruction bias voltage waveform blocks changes due to instruction set swapping, it would be beneficial to extend the functionality of the instruction register decoder 2120 so that its decoding operation can also be programmed to correspond to the instruction set.

[0063] The transfer arbitration unit 2139 temporarily buffers the bias control address information 2132-1 to 2132-8 and the bias control data information 2135-1 to 2135-8, combines the information having the same auxiliary code (-1 to -8), and outputs it as bias control information 220 in a predetermined order. This is essential when the number of sets of bias control information that can be transferred simultaneously as bias control information 220 is less than the number of sets of bias control information to be transferred, and simple control such as fixing the auxiliary code in ascending order is sufficient for the transfer order. The bias control address information 2132-1 to 2132-8 is output from the bias control address information 221, and the bias control data information 2135-1 to 2135-8 is output from the bias control data information 222.

[0064] Figure 9 shows an example of the contents of the coordinate-switch ID conversion table 2131. This conversion table takes the post-latch X coordinate information 2101 and the post-latch Y coordinate information 2111 as inputs and outputs the bias control address information 2132-1 to 2132-8 that identify the switch ID. The quantum dot array 340 contains enough entries to cover at least the quantum dots that are the target of instruction execution.

[0065] Figure 10 shows an example of the contents of the bias voltage waveform template 2133. This template takes the bias voltage waveform block ID 1001, which is included in the bias voltage waveform template control information 2142, as input and outputs the bias control data information 2135-1 to 2135-8 corresponding to the switch ID. There are enough entries to identify all bias voltage waveform blocks 1001 included in all instructions that can be executed on the quantum dot.

[0066] Figure 11 is an example of a control sequence diagram that provides an overview of the entire instruction execution control sequence in the control device 200, starting from an instruction execution request from a system control application running on the host PC 100. While not particularly limited, the control device 200 operates in synchronization with a predetermined clock signal input to it, and the quantum device 300 operates either in synchronization with the control device 200 or asynchronously with respect to the edge of the interface signal.

[0067] In this example sequence, the bias control information 220 is composed of two sets of bias control information, 220-1 and 220-2, and is capable of outputting two sets of control information simultaneously. The bias control information 220-1 is expressed as a combination of bias control address information 221-1 and bias control data information 222-1, and the bias control information 220-2 is expressed as a combination of bias control address information 221-2 and bias control data information 222-2.

[0068] In cycle 1, the host PC 100 outputs the X coordinate information 120, the Y coordinate information 121, the instruction information 122, and the instruction conversion control signal 130, which includes an instruction execution request, to the control device 200.

[0069] When the sequence control unit 230, which constitutes the control device 200, receives an instruction execution request from the instruction conversion control signal 130, in cycle 2, it outputs information to the instruction conversion control information 241 instructing the start of the conversion process for the specified instruction, and instructs the instruction conversion unit 210 to perform an instruction conversion process targeting the bias voltage waveform block at the beginning of the instruction. After that, the sequence control unit 230 waits for notification of the completion of the conversion process from the instruction conversion response information 242.

[0070] In cycle 2, when the transfer control unit 2140, which constitutes the instruction conversion unit 210, receives an instruction to perform instruction conversion processing from the instruction conversion control information 241, it first asserts the instruction conversion start strobe 2141 within the same cycle and instructs the X coordinate register 2100, the Y coordinate register 2110, and the instruction register decoder 2120 to latch the input information.

[0071] The X-coordinate register 2100 and the Y-coordinate register 2110, upon receiving the instruction, latch the contents of the X-coordinate information 120 and the Y-coordinate information 121, respectively, at the beginning of cycle 3, and output the results as the latched X-coordinate information 2101 and the latched Y-coordinate information 2111, respectively. Similarly, the instruction register / decoder 2120, upon receiving the instruction, latches the contents of the instruction information 122 at the beginning of cycle 3, and decodes from the latched instruction information the bias voltage waveform block ID that identifies the leading bias voltage waveform block constituting the instruction, and the number of bias voltage waveform blocks included in the instruction, and outputs information including some or all of the decoding results as the decoded instruction information 2121.

[0072] In cycle 3, the coordinate-switch ID conversion table 2131 converts the latched X coordinate information 2101 and the latched Y coordinate information 2111, which identify the coordinates of the quantum dot to be processed, into IDs (SIDs) of the eight bias control switches included in the bias voltage switching switch matrix 330 that are controlled during the execution of the instruction, and outputs them as bias control address information 2132-1 to 2132-8, respectively. These eight switch IDs identify a total of eight bias control switches located at both ends of the four bias control lines surrounding the quantum dot to be processed on all sides (top, bottom, left, and right).

[0073] Furthermore, in cycle 3, the bias voltage waveform template 2133 converts the bias voltage waveform template control information 2142, which includes a bias voltage waveform block ID that identifies the first bias voltage waveform block of the initially specified instruction, into eight setting values ​​to be set on the bias control switches identified by the eight bias control address information 2132-1 to 2132-8 in that bias voltage waveform block, and outputs them as bias control data information 2135-1 to 2135-8.

[0074] The transfer arbitration unit 2139 spends a total of four cycles, from cycle 4 to 7, and outputs eight sets of bias control address information 2132-1 to 2132-8 and bias control data information 2135-1 to 2135-8 in pairs, starting from the smallest auxiliary code (-1 to -8), as bias control information 220-1 and 220-2. It also outputs information to the bias control information strobe 223 indicating that the contents of bias control information 220-1 and 220-2 are valid. When the control register write control unit 310 detects that the bias control information strobe 223 is valid, it instructs the bias voltage control register 320 via the control register write control signal 311 to write the setting value specified in the bias control data information 222-1 (or 222-2) to the register that controls the bias control switch identified by the bias control address information 221-1 (or 221-2), based on the instructions in the bias control information 220-1 (or 220-2).

[0075] In cycle 7, which is the final transfer cycle of the bias control information 220-1 and 220-2, the transfer control unit 2140 checks whether the bias voltage waveform block currently undergoing instruction conversion processing is the final bias voltage waveform block constituting the instruction. If it is not the final waveform block, it outputs information indicating the completion of the conversion process for the non-final bias voltage waveform block to the instruction conversion response information 242, and if it is the final waveform block, it outputs information indicating the completion of the conversion process for the final bias voltage waveform block, notifying the sequence control unit 230 that the conversion process is complete.

[0076] Upon receiving notification of the completion of the conversion process from the instruction conversion response information 242, the sequence control unit 230 instructs the bias voltage switching switch matrix 330 to switch the bias voltage using the bias voltage switching strobe 240 in cycle 8. In addition, if the sequence control unit 230 requires the output of the RF signal 261 for the purpose of performing a predetermined calculation operation in the quantum dot array 340 after the bias voltage switching, it instructs the RF signal generator 260 to output the RF signal 261 via the RF signal output strobe 243. Upon receiving the instruction, the RF signal generator 260 outputs a high frequency with a waveform envelope suitable for the calculation operation from the RF signal 261. Here, one or more parameters representing the waveform envelope, and / or the delay time from the RF signal output strobe 243 to the rising edge of the RF signal 261 output, may be set in advance in the RF signal generator 260, or they may be included as information in the RF signal output strobe 243 and provided by the sequence control unit 230 simultaneously with the strobe.

[0077] If the instruction consists of multiple bias voltage waveform blocks, the above process is repeated for the number of waveform blocks. In cycle 10, when the transfer control unit 2140 updates the contents of the bias voltage waveform template control information 2142 to information including a bias voltage waveform block ID that identifies the subsequent bias voltage waveform block, the bias control address information 2132-1 to 2132-8 output by the coordinate-switch ID conversion table 2131 remains unchanged, and only the bias control data information 2135-1 to 2135-8 output by the bias voltage waveform template 2133 switches to the contents corresponding to the bias voltage waveform block. In cycles 11 to 14, the transfer arbitration unit 2139 outputs two sets each of the bias control address information 2132-1 to 2132-8 and the bias control data information 2135-1 to 2135-8 as bias control information 220-1 and 220-2, similar to the case of the leading bias voltage waveform block, and also outputs information to the bias control information strobe 223 indicating that the output content is valid.

[0078] In cycle 14, which is the final transfer cycle of the bias control information 220-1 and 220-2, the transfer control unit 2140 checks whether the bias voltage waveform block is the final waveform block that constitutes the instruction, and depending on the result, outputs either information indicating the completion of the conversion process for the non-final bias voltage waveform block or information indicating the completion of the conversion process for the final bias voltage waveform block to the instruction conversion response information 242, notifying the sequence control unit 230 that the conversion process is complete.

[0079] In the example shown in Figure 11, eight bias voltages are controlled to operate a single qubit. As qubit arrays become more integrated and parallelized, and instructions become more complex, it is expected that the number of signal lines after the instruction conversion unit 210 will increase rapidly. In this embodiment, the number of signal lines can be reduced by adopting a configuration that converts abstract control signals into concrete control signals.

[0080] As described in detail above using the drawings, with respect to the control of a quantum device including a qubit array that performs quantum operations, by combining a control device equipped with the function of generating a waveform pattern of bias voltage applied to each qubit from instruction information specifying the operation to be performed and coordinate information specifying the qubit to be performed, the capacity of the control data and the number of wires required for control data transfer can be significantly reduced compared to directly controlling each qubit, enabling efficient computation control.

[0081] In this embodiment, conversion control is performed on an instruction-by-instruction basis from the host PC 100 through the sequence control unit 230 to the transfer control unit 2140, and conversion control is performed on a bias voltage waveform block basis between the transfer control unit 2140 and the bias voltage waveform pattern generation unit 2130. However, modifications may be considered depending on the purpose of the control.

[0082] By adding setting items in the bias voltage waveform template 2133 and / or by extending the functionality of the sequence control unit 230, it may be possible to set the time from one bias voltage switching strobe to the next bias voltage switching strobe, i.e., the duration of the bias voltage waveform block.

[0083] Furthermore, by unifying the conversion control from the host PC 100 to the transfer control unit 2140 using bias voltage waveform blocks as the unit, the control information between the host PC 100 and the sequence control unit 230 increases slightly, but the decoding function of the instruction register decoder 2120 becomes unnecessary, and the conversion control by the transfer control unit 2140 is simplified.

[0084] Alternatively, a hybrid control system may be used, in which control is maintained on an instruction basis between the host PC 100 and the sequence control unit 230, the sequence control unit 230 performs a conversion from instructions to sequence definitions on a bias voltage waveform block basis, and control is performed on a bias voltage waveform block basis between the sequence control unit 230 and the bias voltage waveform pattern generation unit 2130 via the transfer control unit 2140 based on the converted sequence definition. This significantly improves the degree of freedom of calculation control without increasing the control information between the host PC 100 and the sequence control unit 230.

[0085] Figure 12 shows an example of a detailed configuration of a modified example 2130A of the bias voltage waveform pattern generation unit 2130. In this embodiment, the bias voltage waveform pattern generation unit 2130 includes a circuit that overrides an instruction value that specifies the coordinates of a qubit when the setting pattern to the bias voltage control register 320 cannot be categorized by an instruction value that specifies the type of quantum operation, the coordinates of a qubit, or both.

[0086] The bias voltage waveform pattern generation unit 2130A comprises the coordinate-switch ID conversion table 2131, a bias voltage waveform template 2133A which is a modified example of the bias voltage waveform template 2133, bias control address information selectors 2136-1, 2136-2, 2136-3, 2136-4, 2136-5, 2136-6, 2136-7, and 2136-8, and the transfer arbitration unit 2139. It is useful when overriding the contents of the bias control address information 2132-1 to 2132-8 for the purpose of realizing conversion control for special instructions that differ from normal instructions in which the execution target is fixed to one quantum dot, such as initializing some or all of the quantum dots constituting the quantum dot array 340.

[0087] The aforementioned coordinate-switch ID conversion table 2131 is the same as the one shown in Figure 8, and a detailed explanation is omitted.

[0088] The bias voltage waveform template 2133A outputs override bias control address information 2134-1, 2134-2, 2134-3, 2134-4, 2134-5, 2134-6, 2134-7, and 2134-8, which identify the bias control switches to which each of the values ​​indicated by the bias control data information 2135-1 to 2135-8 should be set, in addition to the bias control data information 2135-1 to 2135-8. The override bias control address information 2134-1 to 2134-8 can specify IDs that identify any of the bias control switches included in the bias voltage switching switch matrix 330, in any order.

[0089] When the override function is used, it is sufficient that there is a correspondence between the override bias control address information 2134-1 to 2134-8 and the bias control data information 2135-1 to 2135-8. When the override function is not used, it is sufficient that there is a correspondence between the bias control address information 2132-1 to 2132-8 and the bias control data information 2135-1 to 2135-8.

[0090] The bias control address information selectors 2136-1 to 2136-8 select the override bias control address information 2134-1 to 2134-8 when the override function is enabled (Y) by the override control signal 2137, and select the bias control address information 2132-1 to 2132-8 when the override is disabled (N), and output the override-post-bias control address information 2138-1, 2138-2, 2138-3, 2138-4, 2138-5, 2138-6, 2138-7, and 2138-8, respectively.

[0091] The transfer arbitration unit 2139 is the same as that shown in Figure 8, except that the input bias control address information is changed from the bias control address information 2132-1 to 2132-8 to the overridden bias control address information 2138-1 to 2138-8, and a detailed explanation is omitted.

[0092] Figure 13 shows an example of the contents of the bias voltage waveform template 2133A. This template takes the bias voltage waveform block ID 1001, which is included in the bias voltage waveform template control information 2142, as input and outputs the override control signal 2137, the bias control data information 2135-1 to 2135-8, and the override bias control address information 2134-1 to 2134-8. There are enough entries to identify all bias voltage waveform blocks 1001 included in all instructions that can be executed by a quantum dot, including special instructions such as quantum dot initialization.

[0093] Figure 14 shows an example of a detailed configuration of a modified example 2130B of the bias voltage waveform pattern generation unit 2130. The bias voltage waveform pattern generation unit 2130B includes a coordinate-switch ID conversion table 2131B, which is a modified example of the coordinate-switch ID conversion table 2131, and a bias voltage waveform template 2133B, which is a modified example of the bias voltage waveform template 2133. Here, the bias control information 220 is capable of outputting two sets of control information simultaneously. By matching the number of sets of bias control information 220 that can be output simultaneously with the number of bias control address information 2132-1 to 2132-2 output by the coordinate-switch ID conversion table 2131B and the number of bias control data information 2135-1 to 2135-2 output by the bias voltage waveform template 2133B, the transfer arbitration unit 2139 can be omitted, and the configuration of the bias voltage waveform pattern generation unit 2130B is simplified.

[0094] To achieve the above simplification, the transfer order management function of the transfer arbitration unit 2139 is integrated as a function of the transfer control unit 2140. More specifically, the bias voltage waveform template control information 2142 includes a bias voltage waveform block ID that identifies the bias voltage waveform block being processed, as well as a sequence number that identifies which cycle of the bias control information 220, which was time-divided output in four cycles, it corresponds to. Furthermore, in order to enable the transfer control unit 2140 to control the output of the bias control information 220, a function is incorporated into the transfer control unit 2140 that sequentially outputs values ​​obtained by incrementing the sequence number from 0 to 3 as the bias voltage waveform template control information 2142 while keeping the bias voltage waveform block ID constant. Note that the sequence number in the bias voltage waveform template control information 2142 also needs to be referenced in the coordinate-switch ID conversion table 2131B, so the configuration is changed.

[0095] Figure 15 shows an example of the contents of the coordinate-switch ID conversion table 2131B. This conversion table takes the sequence number 1501 included in the bias voltage waveform template control information 2142 as input, in addition to the latched X coordinate information 2101 and the latched Y coordinate information 2111, and outputs two bias control address information sets 2132-1 to 2132-2, which are equal to the number of sets of bias control information 220. Among the quantum dots included in the quantum dot array 340, there are at least the number of quantum dots that are the target of instruction execution multiplied by the number of types of sequence number 1501.

[0096] Figure 16 shows an example of the contents of the bias voltage waveform template 2133B. This template takes bias voltage waveform block ID 1001 and sequence number 1501, which are included in the bias voltage waveform template control information 2142, as input and outputs two bias control data information sets 2135-1 to 2135-2, which are equal to the number of sets of bias control information 220. There are a number of entries equal to the number of waveform block types that identify all bias voltage waveform blocks included in all instructions that can be executed by the quantum dot, multiplied by the number of sequence number 1501 types.

[0097] Figure 17 shows an example of the detailed configuration of a modified example 2130C of the bias voltage waveform pattern generation unit 2130. Conceptually, the bias voltage waveform pattern generation unit 2130C is based on the bias voltage waveform pattern generation unit 2130A, combined with the configuration simplification method described for the bias voltage waveform pattern generation unit 2130B. The only differences in configuration are the reduction in the number of bias control address information, override bias control address information, and bias control data information, as well as the number of bias control address information selectors, so a detailed explanation is omitted.

[0098] Figure 18 shows an example of the contents of the bias voltage waveform template 2133C. This template takes the bias voltage waveform block ID 1001 and sequence number 1501 included in the bias voltage waveform template control information 2142 as input and outputs the override control signal 2137, two bias control data information entries 2135-1 to 2135-2, and override bias control address information entries 2134-1 to 2134-2, each equal to the number of sets of bias control information 220. There are a number of entries equal to the number of waveform block types that identify all bias voltage waveform blocks included in all instructions that can be executed by a quantum dot, taking into account special instructions such as quantum dot initialization, multiplied by the number of sequence number 1501 types. [Examples]

[0099] Referring to Figure 19, a quantum computing system 1A according to a second embodiment of the present invention will be described. Since the system configuration of the second embodiment is substantially the same as that of the first embodiment, redundant explanations will be omitted.

[0100] In the second embodiment, if there is sufficient margin in the allowable logic scale and power consumption of the quantum device 300, the instruction conversion unit 210 is moved from the control device 200 to the quantum device 300. By completing and concealing the transmission of the bias control information 220 and the bias control information strobe 223 within the quantum device 300, the number of wires between devices is reduced, and even when the array size of the quantum device 300 is increased, the increase in the number of wires connected to the outside of the quantum device 300 can be suppressed. The above features are particularly advantageous for devices that must operate in an extremely low-temperature environment using a dilution refrigerator where the number of wires is severely constrained, such as silicon quantum dots on which this embodiment is based. [Examples]

[0101] Referring to Figure 20, a quantum computing system 1B according to a third embodiment of the present invention will be described. Since the system configuration of the third embodiment is substantially the same as that of the first embodiment, redundant explanations will be omitted.

[0102] In the third embodiment, although there is no margin in the allowable logic scale and power consumption of the quantum device 300, if a chamber with sufficient cooling capacity exists between the control device 200 and the quantum device 300, the instruction conversion unit 210 is moved to an intermediate device 400 that is independent of both the control device 200 and the quantum device 300. Although the number of lines required for the transmission of the bias control information 220 and the bias control information strobe 223 is not reduced, the shortened distance has the effect of mitigating the electrical characteristics required for the wiring.

[0103] Although embodiments of the present invention have been described above, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. The components described in the embodiments may be implemented by hardware or by software.

[0104] According to the above embodiment, a practical quantum computer can be realized, resulting in low energy consumption, reduced carbon emissions, prevention of global warming, and contribution to the realization of a sustainable society. [Explanation of Symbols]

[0105] 1, 1A, 1B: Quantum computing systems 100: Host PC 110: Interface section 120: X coordinate information 121: Y coordinate information 122: Instruction information 130: Instruction conversion control signal 140: Bias voltage setting signal 200: Control devices 210: Instruction conversion unit

Claims

1. A qubit array in which multiple qubits, whose characteristics are variable by a bias voltage, are arranged in one or two dimensions, A bias voltage selection circuit for selecting the bias voltage to be supplied to the qubit array, A bias voltage control register that controls the operation of the bias voltage selection circuit, The system includes a bias voltage waveform pattern generation circuit that generates a setting pattern for the bias voltage control register, The bias voltage waveform pattern generation circuit is characterized by generating one or more bias voltage waveform patterns necessary for executing the quantum operation, based on the type of quantum operation to be performed on the qubit and an instruction value that identifies the coordinates of the qubit to be operated on. Quantum computing system.

2. The bias voltage waveform pattern generation circuit is characterized in that, if the setting pattern for the bias voltage control register cannot be categorized by at least one of the type of quantum operation and the instruction value that specifies the coordinates of the qubit, it includes a circuit that overrides the instruction value that specifies the coordinates of the qubit. The quantum computing system according to claim 1.

3. The bias voltage waveform pattern generation circuit allows the generation rules for the bias voltage waveform pattern to be changed from outside the bias voltage waveform pattern generation circuit. The quantum computing system according to claim 1.

4. The bias voltage waveform pattern generation rule is characterized by being optimized based on the application executed by the quantum computing system. The quantum computing system according to claim 3.

5. The qubit array and the bias voltage waveform pattern generation circuit are characterized in that they are mounted on the same semiconductor chip. The quantum computing system according to claim 1.

6. The qubit array and the bias voltage waveform pattern generation circuit are characterized in that they are mounted on different semiconductor chips. The quantum computing system according to claim 1.

7. A qubit array in which a plurality of qubits whose characteristics are variable by a bias voltage are arranged in one or two dimensions, A bias voltage selection circuit for selecting the bias voltage to be supplied to the qubit array, A bias voltage control register that controls the operation of the bias voltage selection circuit, The system includes a bias voltage waveform pattern generation circuit that generates a setting pattern for the bias voltage control register, The bias voltage waveform pattern generation circuit is characterized by generating one or more bias voltage waveform patterns necessary for executing the quantum operation, based on the type of quantum operation to be performed on the qubit and an instruction value that identifies the coordinates of the qubit to be operated on. Using a quantum computing system, When supplying the bias voltage to the qubit array placed in the first temperature environment, A first step involves an information processing device, placed in a second temperature environment that is hotter than the first temperature environment, outputting an instruction value that includes positional information to identify the qubit and instruction information indicating the process that the qubit should perform. A second step in which the bias voltage waveform pattern generation circuit, which is located in a third temperature environment that is lower than the second temperature environment, outputs the bias voltage waveform pattern, which includes bias control address information that identifies the bias control switch to be controlled, and bias control data information that identifies the bias voltage value that the bias control switch should select, based on the position information and the command information. Based on the bias control address information and the bias control data information, the bias voltage control register and the bias voltage selection circuit apply the bias voltage to the qubit, and the third step involves performing the processing to be executed on the qubit identified in the first step. A method for controlling a qubit array that performs the following.

8. In the first step, the number of signal lines that output the position information and the command information is less than the number of signal lines that output the bias control address information and bias control data information in the second step. A method for controlling a qubit array according to claim 7.

9. The first temperature environment is an extremely low temperature environment in which the qubit can operate, and the second temperature environment is a room temperature environment. A method for controlling a qubit array according to claim 7.

10. The third temperature environment is an extremely low temperature environment in which the qubit can operate. A method for controlling a qubit array according to claim 9.

11. In the second step described above, a coordinate-switch ID conversion table is used, which associates the coordinates based on the position information with the bias control address information. A method for controlling a qubit array according to claim 7.

12. In the second step described above, a bias voltage waveform template is used, which associates a waveform block ID based on the instruction information with bias control data information corresponding to the bias control switch. A method for controlling a qubit array according to claim 11.

13. In the second step described above, the waveform block ID based on the instruction information and the bias control data information corresponding to the bias control switch are identified, and a bias voltage waveform template that associates the waveform block ID with the bias control address information is used. Based on the override signal, select which bias control address information to use: the coordinate-switch ID conversion table or the bias voltage waveform template. A method for controlling a qubit array according to claim 11.

14. In the second step described above, a coordinate-switch ID conversion table is used, which associates the bias control address information with the coordinate-sequence number pair based on the position information. A method for controlling a qubit array according to claim 7.

15. In the second step described above, a bias voltage waveform template is used, which associates bias control data information corresponding to the bias control switch with a set of waveform block ID and sequence number based on the instruction information. A method for controlling a qubit array according to claim 14.

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