Exposure apparatus, exposure method, and method for manufacturing a semiconductor device

Abstract

To improve yield of semiconductor devices.SOLUTION: An exposure device of the embodiment exposes a substrate. The exposure device includes a control device configured to correct an exposure amount based on the measurement results of three or more alignment marks placed on the substrate. Based on the measurement result, the control device executes an alignment in which the magnification components of the first and second directions intersecting each other and parallel to the plane of the substrate are corrected is performed. The control device corrects an exposure amount based on the value of the difference between the magnification component in the first direction and the magnification component in the second direction.SELECTED DRAWING: Figure 22

Description

[Technical Field]

[0001] Embodiments relate to an exposure apparatus, an exposure method, and a method for manufacturing a semiconductor device. [Background Art]

[0002] A three-dimensional stacking technique for three-dimensionally stacking semiconductor circuit boards is known. [Prior Art Literature] [Patent Literature]

[0003] [Patent Literature 1] Japanese Unexamined Patent Publication No. 2012-216260 [Summary of the Invention] [Problem to be Solved by the Invention]

[0004] An object of the present invention is to improve the yield of semiconductor devices. [Means for Solving the Problem]

[0005] The exposure apparatus of an embodiment exposes a substrate. The exposure apparatus includes a control device configured to correct an exposure amount based on measurement results of three or more alignment marks arranged on the substrate. The control device executes alignment in which magnification components in a first direction and a second direction that intersect each other and are parallel to an in-plane direction of the substrate are corrected, based on the measurement results. The control device corrects the exposure amount based on a difference value between the magnification component in the first direction and the magnification component in the second direction. [Brief Description of the Drawings]

[0006] [Figure 1] FIG. 1 is a block diagram showing an example of an overall configuration of a memory device according to an embodiment. [Figure 2] FIG. 2 is a circuit diagram showing an example of a circuit configuration of a memory cell array included in the memory device according to the embodiment. [Figure 3] FIG. 3 is a perspective view showing an example of a structure of the memory device according to the embodiment. [Figure 4] A plan view showing an example of a planar layout of a memory cell array in a memory device according to the embodiment. [Figure 5] A cross-sectional view showing an example of the cross-sectional structure of a memory cell array provided in a memory device according to the embodiment. [Figure 6] A cross-sectional view along the line VI-VI in Figure 5, showing an example of the cross-sectional structure of a memory pillar in a memory device according to the embodiment. [Figure 7] A cross-sectional view showing an example of the cross-sectional structure of a memory device according to the embodiment. [Figure 8] A plan view showing an example of the planar layout of the film stress adjustment layer provided in the memory device according to this embodiment. [Figure 9] A cross-sectional view along the line IX-IX in Figure 8, showing an example of the cross-sectional structure of the film stress adjustment layer provided in the memory device according to the embodiment. [Figure 10] A block diagram showing an example of the configuration of a semiconductor manufacturing system according to the embodiment. [Figure 11] A block diagram showing an example of the configuration of an exposure apparatus according to the embodiment. [Figure 12] A block diagram showing an example of the configuration of a bonding device according to the embodiment. [Figure 13] A block diagram showing an example of the server configuration according to the embodiment. [Figure 14] A schematic diagram showing an overview of the manufacturing method for a semiconductor device according to the embodiment. [Figure 15] A schematic diagram showing an example of the arrangement of alignment marks used in the manufacturing process of a semiconductor device according to the embodiment. [Figure 16] A table showing an example of the correction performance of the overlap misalignment component within the wafer surface in an exposure apparatus and bonding apparatus used in the manufacturing process of a semiconductor device according to the embodiment. [Figure 17] A graph showing an example of the relationship between wafer warpage XY difference and wafer magnification XY difference. [Figure 18] A flowchart showing an example of the process for forming a film stress adjustment layer included in the manufacturing process of a semiconductor device according to the embodiment. [Figure 19] Schematic diagram illustrating an example of a structure when forming a film stress adjustment layer of a semiconductor device according to an embodiment. [Figure 20] Schematic diagram illustrating an example of a structure when forming a film stress adjustment layer of a semiconductor device according to an embodiment. [Figure 21] Schematic diagram illustrating an example of a structure when forming a film stress adjustment layer of a semiconductor device according to an embodiment. [Figure 22] Flowchart illustrating an example of an exposure method of an exposure apparatus according to an embodiment. [Figure 23] Graph illustrating an example of a correction formula used in an exposure apparatus according to an embodiment. [Figure 24] Flowchart illustrating an example of a method of creating a correction formula used in an exposure apparatus according to an embodiment. [Figure 25] Schematic diagram illustrating a specific example of a method of creating a correction formula used in an exposure apparatus according to an embodiment. [Figure 26] Schematic diagram illustrating an example of a change in wafer magnification when a shrinkage film is used in a film stress adjustment layer of a semiconductor device according to an embodiment. [Figure 27] Schematic diagram illustrating an example of a change in wafer magnification when an expansion film is used in a film stress adjustment layer of a semiconductor device according to an embodiment. [Figure 28] Schematic diagram illustrating an example of adjusting wafer magnification in a method of manufacturing a semiconductor device according to an embodiment. Mode for Carrying Out the Invention

[0007] Embodiments are described below with reference to the drawings. The embodiments exemplify apparatuses and methods for embodying the technical idea of the invention. The drawings are schematic or conceptual. Dimensions and ratios in the drawings do not necessarily match those in actual products. Illustrations of components are omitted as appropriate. Hatching added to the drawings is not necessarily related to the material or characteristics of components. Components having substantially the same function and configuration are denoted by the same reference signs. Numbers and the like added to reference signs are used to distinguish between similar elements that are referred to by the same reference sign.

[0008] <1> Specific examples of semiconductor devices The semiconductor device described herein is formed by joining two semiconductor circuit boards (wafers), each having a semiconductor circuit formed on it, and then separating the joined semiconductor circuit boards into individual chips. An example of a semiconductor device having such a joined structure is a memory device capable of storing data non-volatilely. Below, as a specific example of a semiconductor device, an example of the configuration of a memory device having a joined structure will be described.

[0009] <1-1> Overall configuration of memory device 10 Figure 1 is a block diagram showing an example of the overall configuration of a memory device 10 according to an embodiment. As shown in Figure 1, the memory device 10 includes, for example, a memory interface (memory I / F) 11, a sequencer 12, a memory cell array 13, a driver module 14, a row decoder module 15, and a sense amplifier module 16.

[0010] The memory interface 11 is a hardware interface connected to an external memory controller via a channel CH. The memory interface 11 communicates with the memory device 10 and the memory controller according to the interface standard. The memory interface 11 supports, for example, the NAND interface standard.

[0011] The sequencer 12 is a control circuit that controls the overall operation of the memory device 10. Based on commands received via the memory interface 11, the sequencer 12 controls the driver module 14, the row decoder module 15, the sense amplifier module 16, etc., to perform read operations, write operations, erase operations, etc.

[0012] The memory cell array 13 is a memory circuit that includes a collection of multiple memory cells. The memory cell array 13 includes multiple blocks BLK0 to BLKn (where n is an integer greater than or equal to 1). Block BLK is used, for example, as a data erasure unit. The memory cell array 13 is also provided with multiple bit lines and multiple word lines. Each memory cell is associated with, for example, one bit line BL and one word line WL. Each memory cell is identified based on an address that identifies the word line WL and an address that identifies the bit line BL.

[0013] The driver module 14 is a driver circuit that generates voltages used in read, write, and erase operations. The driver module 14 is connected to the row decoder module 15 via multiple signal lines. The driver module 14 can change the voltage applied to each of the multiple signal lines based on the page address received via the memory interface 11.

[0014] The row decoder module 15 is a decoder that decodes the row address received via the memory interface 11. Based on the decoding result, the row decoder module 15 selects one block BLK. The row decoder module 15 then transfers the voltages applied to multiple signal lines to multiple wirings (such as word lines WL) provided in the selected block BLK.

[0015] The sense amplifier module 16 is a sense circuit that senses data read from a selected block BLK based on the voltage of the bit line BL during read operations. The sense amplifier module 16 transmits the read data to the memory controller via the memory I / F 11. In addition, during write operations, the sense amplifier module 16 can apply a voltage to each bit line BL corresponding to the data to be written to the memory cell.

[0016] <1-2> Circuit configuration of the memory cell array 13 Figure 2 is a circuit diagram showing an example of the circuit configuration of a memory cell array 13 provided in the memory device 10 according to the embodiment. Figure 2 shows one of several block BLKs included in the memory cell array 13. As shown in Figure 2, the block BLK includes, for example, four string units SU0 to SU3.

[0017] Each string unit SU contains multiple NAND strings NS. Each NAND string NS is associated with a bit line BL0 to BLm (where m is an integer greater than or equal to 1). Each bit line BL0 to BLm is assigned a different column address. Each bit line BL is shared among multiple blocks BLK by NAND strings NS that are assigned the same column address. Each NAND string NS includes, for example, memory cell transistors MT0 to MT7, as well as selection transistors STD and STS.

[0018] Each memory cell transistor MT includes a control gate and a charge storage layer, and stores data nonvolatilically. The memory cell transistors MT0 to MT7 of each NAND string NS are connected in series. The control gates of the memory cell transistors MT0 to MT7 are connected to word lines WL0 to WL7, respectively. Each of the word lines WL0 to WL7 is provided for each block BLK. A collection of multiple memory cell transistors MT connected to a common word line WL in the same string unit SU is called, for example, a "cell unit CU". When each memory cell transistor MT stores 1 bit of data, the cell unit CU stores "1 page of data". Depending on the number of bits of data stored by the memory cell transistors MT, the cell unit CU may have a storage capacity of 2 pages or more.

[0019] The selection transistors STD and STS are used for selecting string unit SU, respectively. The drain of selection transistor STD is connected to the associated bit line BL. The source of selection transistor STD is connected to one end of the series-connected memory cell transistors MT0 to MT7. The gates of the selection transistor STDs included in string units SU0 to SU3 are connected to the selection gate lines SGD0 to SGD3, respectively. The drain of selection transistor STS is connected to the other end of the series-connected memory cell transistors MT0 to MT7. The source of selection transistor STS is connected to the source line SL. The gate of selection transistor STS is connected to the selection gate line SGS. The source line SL is shared, for example, by multiple blocks BLK.

[0020] <1-3> Structure of memory device 10 An example of the structure of the memory device 10 according to the embodiment is described below. In this specification, the X and Y directions are directions that intersect each other and are parallel to the surface of the semiconductor substrate. The Z direction is a direction that intersects each of the X and Y directions and corresponds to the direction perpendicular to the surface of the semiconductor substrate used to form the memory device 10. For example, the X direction corresponds to the extension direction of the word line WL, and the Y direction corresponds to the extension direction of the bit line BL. In this specification, "up and down" is defined based on the direction along the Z direction. Hereafter, the upper and lower sides of the drawings will be described in relation to "up" and "down," respectively.

[0021] Figure 3 is a perspective view showing an example of the structure of a memory device 10 according to an embodiment. As shown in Figure 3, the memory device 10 includes a memory chip MC and a CMOS chip CC. The memory chip MC includes, for example, a memory area MR, draw-out areas HR1 and HR2, and a pad area PR1. The CMOS chip CC includes, for example, a sense amplifier area SR, a peripheral circuit area PERI, transfer areas XR1 and XR2, and a pad area PR2.

[0022] The memory area MR includes the memory cell array 13. The lead-out areas HR1 and HR2 include wiring used for connecting the stacked wiring provided on the memory chip MC and the low decoder module 15 provided on the CMOS chip CC. The pad area PR1 includes pads used for connecting the memory device 10 and the memory controller. The lead-out areas HR1 and HR2 sandwich the memory area MR in the X direction. The pad area PR1 is adjacent to the memory area MR and the lead-out areas HR1 and HR2 in the Y direction.

[0023] The sense amplifier area SR includes the sense amplifier module 16. The peripheral circuit area PERI includes the sequencer 12 and the driver module 14, etc. The transfer areas XR1 and XR2 include the row decoder module 15. The pad area PR2 includes the memory I / F 11. The sense amplifier area SR and the peripheral circuit area PERI are located adjacent to each other in the Y direction and overlap with the memory area MR. The transfer areas XR1 and XR2 sandwich the sense amplifier area SR and peripheral circuit area PERI in the X direction and overlap with the extraction areas HR1 and HR2, respectively. The pad area PR2 overlaps with the pad area PR1 of the memory chip MC.

[0024] The memory chip MC has multiple bonding pads BP at the bottom of each of the following areas: the memory area MR, the lead areas HR1 and HR2, and the pad area PR1. The bonding pads BP of the memory area MR are connected to the associated bit lines BL. The bonding pads BP of the lead area HR are connected to the associated wiring (e.g., word lines WL) among the stacked wiring provided in the memory area MR. The bonding pads BP of the pad area PR1 are connected to pads (not shown) provided on the top surface of the memory chip MC. The pads provided on the top surface of the memory chip MC are used, for example, for connections between the memory device 10 and the memory controller.

[0025] The CMOS chip CC has multiple junction pads BP above the sense amplifier area SR, the peripheral circuit area PERI, the transfer areas XR1 and XR2, and the pad area PR2. The junction pad BP of the sense amplifier area SR overlaps with the junction pad BP of the memory area MR. The junction pads BP of the transfer areas XR1 and XR2 overlap with the junction pads BP of the lead areas HR1 and HR2, respectively. The junction pad BP of the pad area PR1 overlaps with the junction pad BP of the pad area PR2.

[0026] The memory device 10 has a structure in which the lower surface of the memory chip MC (the front surface of the semiconductor substrate on which the memory chip MC is formed) and the upper surface of the CMOS chip CC (the front surface of the semiconductor substrate on which the CMOS chip CC is formed) are joined together. Of the multiple bonding pads BP provided on the memory device 10, two bonding pads BP facing each other between the memory chip MC and the CMOS chip CC are electrically connected by bonding. As a result, the circuits within the memory chip MC and the circuits within the CMOS chip CC are electrically connected via the bonding pads BP. The pair of bonding pads BP facing each other between the memory chip MC and the CMOS chip CC may have a boundary or may be integrated.

[0027] <1-3-1> Structure of the memory cell array 13 The structure of the memory cell array 13 is described below.

[0028] (Planar layout of memory cell array 13) Figure 4 is a plan view showing an example of the planar layout of a memory cell array 13 provided in a memory device 10 according to an embodiment. Figure 4 shows a region containing one block BLK of the memory region MR. As shown in Figure 4, the memory device 10 includes, for example, a plurality of slits SLT, a plurality of slits SHE, a plurality of memory pillars MP, a plurality of bit lines BL, and a plurality of contacts CV. In the memory region MR, the planar layout described below is repeatedly arranged in the Y direction.

[0029] Each slit SLT has a structure in which, for example, an insulating material is embedded. Each slit SLT insulates adjacent wiring (e.g., word lines WL0 to WL7, and selection gate lines SGD and SGS) through it. Each slit SLT has a portion that extends along the X direction and crosses the memory area MR and the lead areas HR1 and HR2 along the X direction. Multiple slit SLTs are arranged in the Y direction. The areas separated by the slit SLTs correspond to blocks BLK.

[0030] Each slit SHE has a structure in which, for example, an insulating material is embedded. Each slit SHE insulates adjacent wiring (at least the selected gate line SGD) through the slit SLT. Each slit SHE has a portion that extends along the X direction and crosses the memory area MR. Multiple slit SHEs are aligned in the Y direction. In this example, three slit SHEs are positioned between adjacent slit SLTs. Multiple regions separated by slit SLTs and SHEs correspond to string units SU0 to SU3, respectively.

[0031] Each memory pillar MP functions, for example, as a single NAND string NS. Multiple memory pillar MPs are arranged in a staggered pattern, for example, 19 rows, in the region between two adjacent slits SLT. Then, counting from the top of the paper, one slit SHE overlaps each of the 5th, 10th, and 15th memory pillar MPs.

[0032] Each bit line BL has a portion that extends along the Y direction and traverses the region where multiple block BLKs are provided along the Y direction. Multiple bit lines BLs are aligned in the X direction. Each bit line BL is positioned to overlap with at least one memory pillar MP for each string unit SU. In this example, two bit lines BL overlap with each memory pillar MP.

[0033] Each contact CV is placed between one of the multiple bit lines BL that overlap the memory pillar MP and the memory pillar MP in question. The contact CV electrically connects the memory pillar MP and the bit line BL. Note that the contact CV between the memory pillar MP that overlaps with the slit SHE and the bit line BL is omitted.

[0034] (Cross-sectional structure of memory cell array 13) Figure 5 is a cross-sectional view showing an example of the cross-sectional structure of a memory cell array 13 provided in a memory device 10 according to an embodiment. Figure 5 shows a cross-section along the Y direction, including a memory pillar MP and a slit SLT within the memory region MR. As shown in Figure 5, the memory device 10 includes, for example, insulating layers 110-118, conductive layers 120-126, and contacts V1 and V2.

[0035] The insulating layer 110 is provided, for example, at the bottom layer of the memory chip MC. Wiring used for connecting the conductive layer 120 and the pad PD may be provided on the layer on which the insulating layer 110 is formed. The conductive layer 120 is provided on the insulating layer 110. The insulating layer 111 is provided on the conductive layer 120. Conductive layers 121 and insulating layers 112 are provided alternately on the insulating layer 111. The insulating layer 113 is provided on the uppermost conductive layer 121. Conductive layers 122 and insulating layers 114 are provided alternately on the insulating layer 113. The insulating layer 115 is provided on the uppermost conductive layer 122. Conductive layers 123 and insulating layers 116 are provided alternately on the insulating layer 115. The insulating layer 117 is provided on the uppermost conductive layer 123. A conductive layer 124 is provided on the insulating layer 117. An insulating layer 118 is provided on the conductive layer 124. The layer on which the insulating layer 118 is formed includes contacts V1 and V2, and conductive layers 125 and 126. Contact V1 is provided on the conductive layer 124. A conductive layer 125 is provided on contact V1. Contact V2 is provided on the conductive layer 125. A conductive layer 126 is provided on contact V2.

[0036] Each of the conductive layers 120, 121, 122, and 123 is formed, for example, as a plate extending along the XY plane. Conductive layer 124 is formed, for example, as a line extending in the Y direction. Conductive layers 120, 121, and 123 are used as source line SL, selection gate line SGS, and selection gate line SGD, respectively. Multiple conductive layers 123 are used, from bottom to top, as word lines WL0 to WL7, respectively. Conductive layer 124 is used as bit line BL. Conductive layers 124 and 125 are connected via contact V1. Conductive layer 125 and conductive layer 126 are connected via contact V2. Conductive layer 126 is in contact with the interface of the memory chip MC and is used as a bonding pad BP. Conductive layer 126 contains, for example, copper.

[0037] The slit SLT has a plate-like portion that extends along the XZ plane, dividing the insulating layers 111-116 and the conductive layers 121-123. Each memory pillar MP is provided extending along the Z direction and penetrates the insulating layers 111-116 and the conductive layers 121-123. Each memory pillar MP includes, for example, a core member 130, a semiconductor layer 131, and a laminated film 132. The core member 130 is an insulator provided extending along the Z direction. The semiconductor layer 131 covers the core member 130. The lower part of the semiconductor layer 131 is in contact with the conductive layer 120. The laminated film 132 covers the side surface of the semiconductor layer 131. A contact CV is provided on the semiconductor layer 131. The semiconductor layer 131 is electrically connected to the conductive layer 124 via the contact CV.

[0038] The illustrated region shows the contact CV corresponding to one of the two memory pillar MPs. For memory pillar MPs that do not have a contact CV connected in this region, a contact CV is connected in a region not shown. The portion where the memory pillar MP intersects with multiple conductive layers 121 functions as a selection transistor STS. The portion where the memory pillar MP intersects with conductive layer 122 functions as a memory cell transistor MT. The portion where the memory pillar MP intersects with multiple conductive layers 123 functions as a selection transistor STD. Hereinafter, the wiring layers including conductive layers 124, 125, and 126 will be referred to as "M0", "M1", and "M2", respectively.

[0039] (Cross-sectional structure of memory pillar MP) Figure 6 is a cross-sectional view along line VI-VI in Figure 5, showing an example of the cross-sectional structure of a memory pillar MP in the memory device 10 according to the embodiment. Figure 6 shows a cross-section including the memory pillar MP and the conductive layer 122, and parallel to the X and Y directions, respectively. As shown in Figure 5, the laminated film 132 includes, for example, a tunnel insulating film 133, an insulating film 134, and a block insulating film 135.

[0040] The core member 130 is provided, for example, in the center of the memory pillar MP. The semiconductor layer 131 surrounds the sides of the core member 130. The tunnel insulating film 133 surrounds the sides of the semiconductor layer 131. The insulating film 134 surrounds the sides of the tunnel insulating film 133. The block insulating film 135 surrounds the sides of the insulating film 134. The conductive layer 122 surrounds the sides of the block insulating film 135. The semiconductor layer 131 is used as the channel (current path) for the memory cell transistors MT0 to MT7 and the selection transistors STD and STS. The tunnel insulating film 133 and the block insulating film 135 each contain, for example, silicon dioxide (SiO2). The insulating film 134 is used as the charge storage layer for the memory cell transistor MT and contains, for example, silicon nitride (SiN). Thus, each of the memory pillar MP functions as one NAND string NS.

[0041] <1-3-2> Cross-sectional structure of memory device 10 Figure 7 is a cross-sectional view showing an example of the cross-sectional structure of a memory device 10 according to an embodiment. Figure 7 shows a cross-section including the memory region MR and the sense amplifier region SR, that is, a cross-section including the memory chip MC and the CMOS chip CC. As shown in Figure 7, the memory device 10 includes, for example, a semiconductor substrate 140, conductive layers GC and 141-144, and contacts CS and C0-C3 in the sense amplifier region SR.

[0042] The semiconductor substrate 140 is a substrate used for forming a CMOS chip CC. The semiconductor substrate 140 includes a plurality of well regions (not shown). A transistor TR is formed in each of the plurality of well regions. The plurality of well regions are separated by, for example, STI (Shallow Trench Isolation). A conductive layer GC is provided on the semiconductor substrate 140 via a gate insulating film. The conductive layer GC in the sense amplifier region SR is used as the gate electrode of the transistor TR included in the sense amplifier module 16. A contact C0 is provided on the conductive layer GC. Two contacts CS are provided on the semiconductor substrate 140 corresponding to the source and drain of the transistor TR.

[0043] A conductive layer 141 is provided above contact CS and above contact C0. A contact C1 is provided above conductive layer 141. A conductive layer 142 is provided above contact C1. Conductive layers 141 and 142 are electrically connected via contact C1. A contact C2 is provided above conductive layer 142. A conductive layer 143 is provided above contact C2. Conductive layers 142 and 143 are electrically connected via contact C2. A contact C3 is provided above conductive layer 143. A conductive layer 144 is provided above contact C3. Conductive layers 143 and 144 are electrically connected via contact C3. Hereinafter, the wiring layers on which conductive layers 141 to 144 are provided will be referred to as "D0", "D1", "D2", and "D3", respectively.

[0044] The conductive layer 144 is in contact with the interface of the CMOS chip CC and is used as a bonding pad BP. The conductive layer 144 in the sense amplifier region SR is bonded to the conductive layer 126 in the memory region MR (i.e., the bonding pad BP of the memory chip MC) which is located opposite it. Each conductive layer 144 in the sense amplifier region SR is electrically connected to a single bit line BL. The conductive layer 144 contains, for example, copper. In the memory device 10, the wiring layer D3 of the CMOS chip CC and the wiring layer M2 of the memory chip MC are adjacent to each other because the memory chip MC and the CMOS chip CC are bonded together.

[0045] In this example, the semiconductor substrate used to form the memory chip MC is removed during processes such as the formation of pads after bonding. The semiconductor substrate used to form the memory chip MC may remain. The number of wiring layers of the memory chip MC and CMOS chip CC is not limited to the numbers described above. The number of wiring layers of the memory chip MC and CMOS chip CC can be appropriately changed depending on the configuration of the memory device 10.

[0046] <1-3-3> Structure of the film stress adjustment layer AL The memory device 10 according to this embodiment includes a film stress adjustment layer AL. The film stress adjustment layer AL is a structure provided to suppress warping of the semiconductor substrate. The film stress adjustment layer AL is formed by a semiconductor device manufacturing method described later and is appropriately placed in the memory device 10 at a location where no wiring or elements connected to a circuit are arranged. The film stress adjustment layer AL may be included in a wiring layer. For example, the film stress adjustment layer AL is included in the wiring layer M1 in the Z direction. However, it is not limited to this. The film stress adjustment layer AL may be provided at other heights, or may be provided in either the memory chip MC or the CMOS chip CC. An example of the structure of the film stress adjustment layer AL is described below.

[0047] (Planar layout of the film stress adjustment layer AL) Figure 8 is a plan view showing an example of the planar layout of the film stress adjustment layer AL provided in the memory device 10 according to the embodiment. As shown in Figure 8, the film stress adjustment layer AL includes, for example, a plurality of insulating layers 150 and a plurality of stress adjustment members 160.

[0048] The insulating layer 150 is an insulator used in the formation of the film stress adjustment layer AL. The stress adjustment member 160 is a member provided on the processed portion of the insulating layer 150. The stress adjustment member 160 is either a shrinkable film or an expandable film. Examples of materials used for the shrinkable film stress adjustment member 160 include tungsten (W) and silicon nitride (SiN). Examples of materials used for the expandable film stress adjustment member 160 include silicon dioxide (SiO2). Hereinafter, the shrinkable film stress adjustment member 160 will also be referred to as "stress adjustment member 160a". The expandable film stress adjustment member 160 will also be referred to as "stress adjustment member 160b". The stress adjustment member 160 may also simply be called "the member".

[0049] Each of the multiple insulating layers 150 has a portion that extends in the Y direction. The portions of each of the multiple insulating layers 150 that extend in the Y direction are arranged at approximately equal intervals along the X direction. Each of the multiple stress adjustment members 160 has a portion that extends in the Y direction. The portions of each of the multiple stress adjustment members 160 that extend in the Y direction are arranged at approximately equal intervals along the X direction. The portions of the multiple insulating layers 150 that extend in the Y direction and the portions of the multiple stress adjustment members 160 that extend in the Y direction are arranged alternately along the X direction and are in contact with each other.

[0050] The portions of each of the multiple insulating layers 150 that extend in the Y direction are provided with approximately the same width. The portions of each of the multiple stress adjustment members 160 that extend in the Y direction are provided with approximately the same width. Hereinafter, the dimension (width) of the portion of the stress adjustment member 160 that extends in the Y direction will be referred to as "L1". The dimension (width) of the portion of the insulating layer 150 that extends in the Y direction will be referred to as "L2". The dimensions of L1 and L2 can be appropriately changed by the exposure process of the exposure apparatus 20 according to the embodiment described later.

[0051] (Cross-sectional structure of the membrane stress adjustment layer AL) Figure 9 is a cross-sectional view along line IX-IX in Figure 8, showing an example of the cross-sectional structure of the film stress adjustment layer AL provided in the memory device 10 according to the embodiment. As shown in Figure 9, the film stress adjustment layer AL further includes, for example, an insulating layer 170. In this example, the insulating layers 150 and 170 are included in the insulating layer 118 shown in Figure 5.

[0052] The insulating layer 150 is provided continuously beneath the wiring layer M1. That is, in the film stress adjustment layer AL, multiple trenches are provided on the upper part of the insulating layer 150. A stress adjustment member 160 is embedded in each of the multiple trenches of the insulating layer 150. Then, the insulating layer 170 is provided so as to cover the insulating layer 150 and the stress adjustment member 160. When such a structure is provided in the film stress adjustment layer AL, the upper surface of the insulating layer 150 and the upper surface of the stress adjustment member 160 are aligned.

[0053] Furthermore, the insulating layer 150 does not necessarily have a portion that is continuously provided below the wiring layer M1. The stress adjustment member 160 and the insulating layer 170 may be provided as a single unit. The film stress adjustment layer AL may have a plurality of stress adjustment members 160 arranged at equal intervals. The height of the bottom of the plurality of stress adjustment members 160 is the same based on the fact that they are formed in one piece. If it is possible to adjust the film stress as described later, parts of adjacent stress adjustment members 160 in a layer of the same height may be in contact.

[0054] The above description illustrates the case where the portions of the multiple stress adjustment members 160 that extend in the Y direction are aligned in the X direction, but is not limited to this. The memory device 10 may have a structure in which the structure of the membrane stress adjustment layer AL shown in Figures 8 and 9 is rotated by 90 degrees in a plan view. The membrane stress adjustment layer AL only needs to have at least one of the following: a plurality of stress adjustment members 160 in which the portions that extend in the Y direction are aligned at equal intervals along the X direction, and a plurality of stress adjustment members 160 in which the portions that extend in the X direction are aligned at equal intervals along the Y direction.

[0055] <2> Configuration of a semiconductor manufacturing system PS Next, a semiconductor manufacturing system PS used for forming a semiconductor device (e.g., a memory device 10) equipped with a film stress adjustment layer AL will be described. Figure 10 is a block diagram showing an example of the configuration of the semiconductor manufacturing system PS according to an embodiment. As shown in Figure 10, the semiconductor manufacturing system PS includes, for example, an exposure apparatus 20, a bonding apparatus 30, and a server 40.

[0056] The exposure apparatus 20, bonding apparatus 30, and server 40 are configured to communicate via a network NW. The network NW may be wired or wireless. The exposure apparatus 20 has the function of transferring (exposing) a pattern formed on a mask (reticle) onto a resist material formed on a wafer. The bonding apparatus 30 has the function of bonding two corresponding wafers. The server 40 is, for example, a computer that controls the entire semiconductor device manufacturing process. The server 40 manages lot processing steps and correction values ​​used in each manufacturing step. The semiconductor manufacturing system PS may also include superposition measurement devices.

[0057] Hereafter, the process by which the exposure apparatus 20 transfers the mask pattern onto the resist material will be referred to as the "exposure process." The process of joining two wafers will be referred to as the "joining process." The wafer placed on top during the joining process will be referred to as the "upper wafer UW." The wafer placed on the bottom during the joining process will be referred to as the "lower wafer LW." The pair of joined wafers, namely the upper wafer UW and the lower wafer LW, will be referred to as the "joined wafer BW." The "front side of the wafer" corresponds to the side on which the semiconductor circuit is formed. The "back side of the wafer" corresponds to the side of the wafer opposite to the front side.

[0058] <2-1> Configuration of the exposure apparatus 20 Figure 11 is a block diagram showing an example of the configuration of an exposure apparatus 20 according to an embodiment. As shown in Figure 11, the exposure apparatus 20 includes, for example, a control device 21, a storage device 22, a transport device 23, a communication device 24, and an exposure unit 25.

[0059] The control device 21 is a computer or similar device that controls the overall operation of the exposure apparatus 20. The control device 21 controls the storage device 22, the transport device 23, the communication device 24, and the exposure unit 25. Although not shown in the diagram, the control device 21 includes a CPU (Central Processing Unit), ROM (Read Only Memory), RAM (Random Access Memory), etc. The CPU is a processor that executes various programs related to the control of the apparatus. ROM is a non-volatile storage medium that stores the control programs of the apparatus. RAM is a volatile storage medium used as the CPU's workspace.

[0060] The storage device 22 is a storage medium used to store data, programs, and the like. The storage device 22 stores, for example, an exposure recipe 220, correction value information 221, and a correction formula 222. The exposure recipe 220 is a table recording the settings for the exposure process. The exposure recipe 220 includes information such as the shape and layout of the shot, the exposure dose, the focus setting, and the alignment setting. The correction value information 221 is a log recording the alignment correction values ​​(i.e., the alignment result) used when the exposure process was performed. The correction value information 221 may also record information about other correction values ​​associated with the wafer being exposed. The correction formula 222 is a mathematical formula for adjusting the exposure dose based on the alignment result. Details of the correction formula 222 will be described later.

[0061] The transport device 23 is equipped with a transport arm capable of transporting wafers (WF) and a transition for temporarily placing multiple wafers. For example, the transport device 23 transports wafers (WF) received from an external coating and developing device to the exposure unit 25. After the exposure process, the transport device 23 transports the wafers (WF) received from the exposure unit 25 to the outside of the exposure device 20.

[0062] The communication device 24 is a communication interface that can be connected to a network NW. The exposure device 20 may operate based on operations performed by a terminal on the network NW, or the server 40 may store the exposure recipe 220, correction value information 221, and correction formula 222.

[0063] The exposure unit 25 is a set of components used in the exposure process. The exposure unit 25 includes, for example, a wafer stage 250, a reticle stage 251, a light source 252, a projection optical system 253, and a camera 254. The wafer stage 250 has the function of holding the wafer WF. The reticle stage 251 has the function of holding the reticle RT (mask). The respective stage positions of the wafer stage 250 and the reticle stage 251 can be controlled by the control device 21. The light source 252 irradiates the reticle RT with the light it generates. The projection optical system 253 focuses the light that has passed through the reticle RT onto the surface of the wafer WF. The camera 254 is an imaging mechanism used to measure alignment marks AM.

[0064] The "coating and developing apparatus" is an apparatus that performs pre-treatment and post-treatment of the exposure process. The pre-treatment of the exposure process includes the process of coating a resist material (photosensitive material) onto the wafer. The post-treatment of the exposure process includes the process of developing the pattern exposed on the wafer. Multiple semiconductor manufacturing apparatuses may be used as the apparatus for the pre-treatment and post-treatment of the exposure process.

[0065] <2-2> Configuration of the joining device 30 Figure 12 is a block diagram showing an example of the configuration of a joining device 30 according to an embodiment. As shown in Figure 12, the joining device 30 includes, for example, a control device 31, a transport device 32, a communication device 33, and a joining unit 34.

[0066] The control device 31 is a computer that controls the overall operation of the bonding apparatus 30. The control device 31 controls the transport apparatus 32, the communication apparatus 33, and the bonding unit 34. Although not shown in the figure, the control device 31 includes a CPU, ROM, RAM, etc., similar to the exposure apparatus 20.

[0067] The transport device 32 is a device equipped with a transport arm capable of transporting wafers and a transition for temporarily placing multiple wafers. For example, the transport device 32 transports the upper wafer UW and lower wafer LW received from the pre-processing device for bonding to the bonding unit 34. After the bonding process, the transport device 32 transports the bonded wafer BW received from the bonding unit 34 to the outside of the bonding device 30. The transport device 32 may also be equipped with a mechanism for inverting the wafers.

[0068] The communication device 33 is a communication interface that can be connected to a network NW. The connecting device 30 may operate based on the control of a terminal on the network NW, or it may store an operation log in the server 40.

[0069] The bonding unit 34 is a set of components used in the bonding process. The bonding unit 34 includes, for example, a lower stage 340, a stress device 341, a camera 342, an upper stage 343, a pressing pin 344, and a camera 345. The lower stage 340 has the function of holding the lower wafer LW. The lower stage 340 includes, for example, a wafer chuck that holds the wafer by vacuum suction. The stress device 341 has the function of applying stress to the lower stage 340 and deforming the lower wafer LW through the lower stage 340. Depending on the amount of deformation of the lower stage 340 by the stress device 341, the amount of expansion (scaling) of the lower wafer LW held in the lower stage 340 may change. The camera 342 is located on the lower stage 340 side and is an imaging mechanism used to measure the alignment mark AM of the upper wafer UW. The upper stage 343 has the function of holding the upper wafer UW. The upper stage 343 includes, for example, a wafer chuck that holds the wafer by vacuum suction. The pressing pin 344 is a pin that is driven vertically based on the control of the control device 31 and can press the upper surface of the center of the upper wafer UW held on the upper stage 343. The camera 345 is an imaging mechanism located on the upper stage 343 side and used to measure the alignment mark AM of the lower wafer LW. The bonding apparatus 30 may have a vacuum pump used for vacuum adsorption of the lower stage 340 and the upper stage 343.

[0070] The lower stage 340 and the upper stage 343 are configured to allow the lower wafer LW held in the lower stage 340 and the upper wafer UW held in the upper stage 343 to be positioned opposite each other. That is, the upper stage 343 can be positioned above the lower stage 340. In the bonding process, the upper surface of the upper wafer UW corresponds to the back surface of the upper wafer UW and is held in the upper stage 343. In the bonding process, the lower surface of the upper wafer UW corresponds to the front surface of the upper wafer UW, i.e., the bonding surface. The upper surface of the lower wafer LW corresponds to the front surface of the lower wafer LW, i.e., the bonding surface. The lower surface of the lower wafer LW corresponds to the back surface of the lower wafer LW and is held in the lower stage 340. The bonding apparatus 30 can adjust the shift component and rotation component of the overlapping misalignment by adjusting the relative positions of the lower stage 340 and the upper stage 343. Furthermore, the bonding apparatus 30 can adjust the XY common wafer magnification of the lower wafer LW held on the deformed lower stage 340 by deforming the lower stage 340 with the stress device 341.

[0071] The “pre-treatment device for bonding” is a device that modifies and hydrophilizes the bonding surfaces of the upper wafer UW and lower wafer LW before the bonding process of the bonding device 30. The pre-treatment device first performs plasma treatment on the surfaces of the upper wafer UW and lower wafer LW to modify their surfaces. In the plasma treatment, oxygen ions or nitrogen ions are generated from oxygen gas or nitrogen gas, which are the processing gases, under a predetermined reduced-pressure atmosphere, and the generated oxygen ions or nitrogen ions are irradiated onto the bonding surfaces of each wafer. After that, the pre-treatment device supplies pure water to the surfaces of the upper wafer UW and lower wafer LW. As a result, hydroxyl groups adhere to the surfaces of the upper wafer UW and lower wafer LW, making the surfaces hydrophilic. In the bonding process, the upper wafer UW and lower wafer LW, whose bonding surfaces have been modified and hydrophilized in this way, are used. The bonding device 30 may be combined with the pre-treatment device and the like to form a bonding system.

[0072] <2-3> Server 40 Configuration Figure 13 is a block diagram showing an example configuration of a server 40 according to an embodiment. As shown in Figure 13, the server 40 includes, for example, a CPU 41, ROM 42, RAM 43, storage device 44, and communication device 45. The CPU 41 is a processor that executes various programs related to the control of the server 40. The ROM 42 is a non-volatile storage device that stores the control programs of the server 40. The RAM 43 is a volatile storage device used as a workspace for the CPU 41. The storage device 44 is a non-volatile storage medium capable of storing information received from an exposure apparatus 20, a bonding apparatus 30, etc. The communication device 45 is a communication interface that can be connected to a network NW.

[0073] <3> Manufacturing method for semiconductor devices Next, a method for manufacturing a semiconductor device according to the embodiment will be described. Figure 14 is a schematic diagram showing an overview of the method for manufacturing a semiconductor device according to the embodiment. Below, with reference to Figure 14, the general flow of the process in the method for manufacturing a semiconductor device according to the embodiment will be described.

[0074] First, wafers are assigned to lots ("lot assignment"). A lot may contain multiple wafers. For example, lots can be classified into lots containing upper wafers (UW) and lots containing lower wafers (LW). Then, front-end processes are carried out on each of the lots containing upper wafers (UW) and lower wafers (LW), and semiconductor circuits are formed on each of them. Front-end processes include a combination of "exposure processing," "exposure OL (overlay) measurement," and "processing."

[0075] The exposure process transfers the mask pattern onto the resist material on the wafer in shot units. A "shot" corresponds to the exposure area in the exposure process. In the exposure process, one exposure shot is repeatedly performed with a shifted position. That is, the exposure apparatus 20 performs the exposure process using a step-and-repeat method. In the exposure process, the arrangement and shape of each shot are corrected based on the measurement results of the alignment marks described later and various correction values, and the overlapping position with the underlying pattern formed on the wafer is adjusted (aligned). The arrangement of multiple shots on the upper wafer UW and the arrangement of multiple shots on the lower wafer LW are set to be the same. Hereinafter, the correction value used for the alignment of the overlapping position, that is, the control parameter of the exposure apparatus to suppress overlapping misalignment, will be called the "alignment correction value". When a polynomial is used for alignment correction, the coefficient of each term will be called the "alignment correction coefficient". The alignment correction value can be calculated based on the alignment correction coefficient of each term and the exposure position.

[0076] Exposure OL measurement is a process that measures the amount of overlap misalignment between the pattern formed by the exposure process and the underlying pattern for the exposure process. The measurement results of the overlap misalignment obtained from exposure OL measurement are used for determining whether the exposure process requires rework and for calculating alignment correction values ​​to be applied to subsequent lots. The processing process is a process of etching the wafer using the mask formed by the exposure process. Once the processing process is complete, the used mask is removed and the next process is executed. The preceding processes may include heating, cleaning, and film formation processes in addition to the exposure process, exposure OL measurement, and processing process.

[0077] Once the preceding processes for the corresponding upper wafer UW and lower wafer LW are completed, the bonding process is performed. In the bonding process, the bonding apparatus 30 positions the front surface of the upper wafer UW and the front surface of the lower wafer LW facing each other. The bonding apparatus 30 then adjusts (aligns) the overlapping position of the pattern formed on the front surface of the upper wafer UW and the pattern formed on the front surface of the lower wafer LW. Then, the bonding apparatus bonds the front surfaces of the upper wafer UW and the lower wafer LW together to form a bonded wafer BW.

[0078] Bonded wafers BW formed by the bonding process are subjected to bonded OL (overlay) measurement. Bonded OL measurement is a process that measures the amount of overlap misalignment between the pattern formed on the front surface of the upper wafer UW and the pattern formed on the front surface of the lower wafer LW. The measurement results of the overlap misalignment obtained by bonded OL measurement can be used to calculate alignment correction values ​​applied to the exposure process of subsequent lots.

[0079] The amount of overlap misalignment that occurs during exposure and bonding processes can be expressed by a combination of various components. The overlap misalignment components include an offset (shift) component, a magnification component, and an orthogonality component. The formulas corresponding to each component are listed below. In the following formulas, "x" and "y" correspond to the coordinates in the X direction (X coordinate) and the Y direction (Y coordinate), respectively. "dx" and "dy" are the amount of overlap misalignment in the X and Y directions, respectively. "K1" to "K6" each correspond to an alignment correction coefficient (polynomial regression coefficient).

[0080] X-direction offset (shift) component: dx = K1 Y-direction offset (shift) component: dy = K² Magnification component in the X direction: dx = K3 * x Y-axis magnification component: dy = K4*y Orthogonality component in the X direction: dx = K5 * y Orthogonality component in the Y direction: dy = K6 * x

[0081] In this example, the overlap misalignment amount Ex in the X direction is calculated by "Ex = K1 + K3*x + dy + K5*y". The overlap misalignment amount Ey in the Y direction is calculated by "Ey = K2 + K4*y + K6*x". When the overlap misalignment component is expressed by polynomial regression, coefficients assigned to higher-order overlap components, not just K1 to K6, may be used as polynomial regression coefficients. The measurement results of the overlap (alignment) can be decomposed for each K value by polynomial regression. Alignment corresponds to the wafer shape relative to the exposure apparatus. The overlap misalignment amount corresponds to the positional misalignment of the pattern between the target and source of the wafer WF. In other words, the component that cannot be corrected by exposure processing based on the alignment measurement results becomes the overlap misalignment amount. Hereafter, the overlap misalignment component of the magnification component that occurs in the plane of the wafer will also be called the "wafer magnification".

[0082] Figure 15 is a schematic diagram showing an example of the arrangement of alignment marks AM used in the manufacturing process of a semiconductor device according to the embodiment. Figure 15(A) illustrates the position of alignment marks AM on a wafer WF measured during exposure processing. Figure 15(B) illustrates the position of alignment marks AM on a wafer WF measured during bonding processing.

[0083] As shown in Figure 15(A), the exposure apparatus 20 can measure multiple alignment marks AM (at least three or more) placed on the wafer WF during the exposure process. The exposure apparatus 20 can then calculate correction values ​​for overlap misalignment components such as shift components, magnification components, and orthogonality components in the X and Y directions by approximating the measurement results of the multiple alignment marks AM using a function in a Cartesian coordinate system. The exposure apparatus 20 can then correct both the overlap misalignment component on a shot-by-shot basis and the overlap misalignment component within the wafer plane during the exposure process. In other words, when the exposure apparatus 20 calculates the wafer magnification in the X direction and the wafer magnification in the Y direction based on the alignment during the exposure process, it utilizes the measurement results of three or more alignment marks AM placed on the substrate.

[0084] As shown in Figure 15(B), the bonding apparatus 30 measures, for example, three alignment marks AM_C, AM_L, and AM_R placed on the wafer WF (upper wafer UW and lower wafer LW) during the bonding process. Alignment mark AM_C is placed near the center of the wafer. The bonding apparatus 30 aligns the shift component based on the measurement results of the respective alignment marks AM_C on the upper wafer UW and lower wafer LW. Alignment marks AM_L and AM_R are placed on one side and the other side of the outer circumference of the wafer WF, respectively. The bonding apparatus 30 aligns the rotation component based on the measurement results of the alignment marks AM_L and AM_R on the upper wafer UW and lower wafer LW. As a result, the bonding apparatus 30 can calculate correction values ​​for the shift component and rotation component and correct simple overlap misalignment components within the wafer surface. The bonding apparatus 30 can also correct a common wafer magnification in the X and Y directions by deforming the stage that holds the lower wafer LW.

[0085] Figure 16 is a table showing an example of the correction performance of the overlap misalignment component within the wafer surface in the exposure apparatus 20 and bonding apparatus 30 used in the manufacturing process of a semiconductor device according to the embodiment. As shown in Figure 16, the shift component can be corrected in both the exposure apparatus 20 and the bonding apparatus 30. The wafer magnification that is common in the X and Y directions (XY common magnification component) can be corrected in both the exposure apparatus 20 and the bonding apparatus 30. The wafer magnification that differs in the X and Y directions (XY difference magnification component) can be corrected in the exposure apparatus 20. On the other hand, the XY difference magnification component is difficult to correct in the bonding apparatus 30. The rotation component (i.e., the orthogonality component common in the X and Y directions) can be corrected in both the exposure apparatus 20 and the bonding apparatus 30. The orthogonality component can be corrected in the exposure apparatus 20. On the other hand, the orthogonality component is difficult to correct in the bonding apparatus 30.

[0086] Figure 17 is a graph showing an example of the relationship between the XY difference in wafer warpage and the XY difference in wafer magnification. The XY difference in wafer warpage corresponds to the difference between the amount of warpage of the wafer WF in the X direction and the amount of warpage of the wafer WF in the Y direction. The warpage of the wafer WF can be caused by the stress of the film formed on the wafer WF (film stress). The XY difference in wafer magnification corresponds to the difference (MagX-MagY) between the wafer magnification in the X direction (MagX) and the wafer magnification in the Y direction. Hereafter, the difference between the wafer magnification in the X direction and the wafer magnification in the Y direction will also be referred to as "D_MagXY".

[0087] As shown in Figure 17, the wafer magnification XY difference tends to change depending on the wafer warp XY difference. For example, when the wafer magnification XY difference is negative, the wafer magnification in the Y direction is greater than that in the X direction, and the wafer WF is deformed into an elongated shape (an ellipse where the Y direction corresponds to the major axis and the X direction corresponds to the minor axis). When the wafer magnification XY difference is zero, the wafer magnification in the X direction and the wafer magnification in the Y direction are equal, and the wafer WF is close to a perfect circle. When the wafer magnification XY difference is positive, the wafer magnification in the X direction is greater than that in the Y direction, and the wafer WF is deformed into an elongated shape (an ellipse where the X direction corresponds to the major axis and the Y direction corresponds to the minor axis).

[0088] <3-1> Method for forming a membrane stress adjustment layer Figure 18 is a flowchart showing an example of the process for forming the film stress adjustment layer AL included in the manufacturing process of a semiconductor device according to the embodiment. Figures 19 to 21 are schematic diagrams showing an example of the structure during the formation of the film stress adjustment layer AL of the semiconductor device according to the embodiment. (A) in each of Figures 19 to 21 shows an extracted portion of the planar structure in the region where the film stress adjustment layer AL is formed. (B) in each of Figures 19 to 21 shows an extracted portion of the cross-sectional structure in the region shown in (A). The process for forming the film stress adjustment layer AL will be described below with reference to Figure 18 as appropriate.

[0089] Once the wafer WF has been processed up to the point before the predetermined exposure process, the series of processes shown in Figure 18 begins (start). In this example, we illustrate the case where a film stress adjustment layer AL is formed on the wiring layer M1. We also assume that an insulating layer 150 is formed on the upper surface of the wafer WF that has been processed up to the point before the predetermined exposure process. In this example, the height to which the insulating layer 150 is formed includes the wiring layer M1.

[0090] First, a photolithography process is performed (S100). Specifically, a resist material 180 is first applied onto the insulating layer 150. In this example, the resist material 180 is a positive-type resist. The exposure apparatus 20 then transfers a predetermined mask pattern to the resist material 180 through an exposure process described later. After that, a development process is performed, and as shown in Figure 19, a line-and-space pattern is formed on the resist material 180. In this example, the dimensions (width) of the space portion of the line-and-space pattern of the resist material 180 are "L3", and the dimensions (width) of the line portion are "L4".

[0091] Next, an etching process is performed (S101). The etching process in S101 is an anisotropic etching process, for example, RIE (Reactive Ion Etching). As a result, as shown in Figure 20, a plurality of trenches 190 are formed on the upper part of the insulating layer 150 based on the shape of the resist material 180. The width of each trench 190 corresponds to the dimension L1 shown in Figure 8 and is based on the dimension L3 of the space portion of the resist material 180 and the processing characteristics of the etching process. The spacing between adjacent trenches 190 corresponds to the dimension L2 shown in Figure 8 and is based on the dimension L4 of the line portion of the resist material 180 and the processing characteristics of the etching process. Note that the process in S101 may be an isotropic etching process or an anisotropic etching process other than RIE, as long as it is possible to form the desired shape. After the process in S101, the resist material 180 is removed.

[0092] Next, the stress adjustment member 160 is formed (S102). Specifically, for example, the stress adjustment member 160 is formed by CVD (Chemical Vapor Deposition). As a result, multiple trenches 190 are filled with the stress adjustment member 160. Subsequently, the stress adjustment member 160 provided on the upper part of the wiring layer M1 is removed by CMP (Chemical Mechanical Polishing). This creates a structure in which the stress adjustment member 160 remains in multiple trenches 190, as shown in Figure 21. The method used to form the stress adjustment member 160 can be appropriately changed depending on the type of stress adjustment member 160. The strength of the compressive and tensile stresses of the stress adjustment member 160 can also vary depending on the method of forming the stress adjustment member 160.

[0093] As described above, the film stress adjustment layer AL is formed, and the series of processes shown in Figure 18 is completed (end).

[0094] <3-2> Exposure Method Figure 22 is a flowchart showing an example of an exposure method using the exposure apparatus 20 according to the embodiment. A specific example of a semiconductor device manufacturing method according to the embodiment, using the exposure apparatus 20, will be described below with reference to Figure 22. A semiconductor device (for example, a memory device 10) equipped with a film stress adjustment layer AL is manufactured using the following exposure method.

[0095] When the exposure apparatus 20 is notified by the coating and developing apparatus that the pre-treatment of the wafer WF is complete, it starts the exposure process (start).

[0096] First, the exposure apparatus 20 loads the wafer WF (S200). The wafer WF loaded from the coating and developing apparatus is held by the wafer stage 250.

[0097] Next, the exposure apparatus 20 checks the exposure recipe 220 (S201). Based on this, the control device 21 determines the processing conditions to be applied to the loaded wafer WF.

[0098] Next, the exposure apparatus 20 checks the correction value information 221 (S202). Based on this, the control device 21 determines the correction values, such as exposure amount and alignment, to be applied to the loaded wafer WF. These correction values ​​are based, for example, on the correction values ​​received from the server 40.

[0099] Next, the exposure apparatus 20 measures the alignment marks AM (S203). Specifically, the camera 254 photographs multiple alignment marks AM placed at predetermined positions on the wafer WF.

[0100] Next, the exposure apparatus 20 performs alignment correction processing (S204). Specifically, the control device 21 calculates alignment correction values ​​such as the shot arrangement and shot shape to be exposed on the wafer WF based on the measurement results of multiple alignment marks AM. The exposure apparatus 20 then applies the calculated alignment correction values ​​to the alignment processing parameters. Furthermore, when the exposure apparatus 20 performs exposure processing on multiple wafer WFs included in one lot in succession, it may apply different alignment correction values ​​to each wafer WF.

[0101] Next, the exposure apparatus 20 corrects the exposure dose based on the correction formula 222 (S205). Specifically, the control device 21 substitutes the difference between the wafer magnification component in the X direction and the wafer magnification component in the Y direction (D_MagXY) of the alignment correction value calculated in the process of S204 into the correction formula 222 to calculate the exposure dose correction value. Then, the control device 21 reflects the calculated exposure dose correction value in the exposure dose setting indicated by the exposure recipe 220. The process of S205 may be omitted if it is not a process related to the formation of the film stress adjustment layer AL.

[0102] Next, the exposure apparatus 20 executes the exposure sequence (S206). Specifically, the control device 21 controls the light source 252, wafer stage 250, and reticle stage 251 based on the alignment processing parameters determined in the S204 process and the exposure amount setting determined in the S205 process, to irradiate the wafer WF with light transmitted through the mask in a step-and-repeat manner.

[0103] When the wafer WF is unloaded, the exposure apparatus 20 terminates the exposure process (end).

[0104] In the S205 process described above, the exposure amount is adjusted so that the wafer magnification XY difference is small. However, it is not limited to this, and a target (reference) value for the wafer magnification XY difference may be set in the S205 process. For example, the wafer magnification XY difference of the wafers WF combined in the bonding process may be used as the reference value for the wafer magnification XY difference. In this case, the exposure amount is adjusted in the S205 process so that the wafer magnification XY difference of one of the two combined wafers WF approaches the value of the wafer magnification XY difference of the other wafer WF.

[0105] <3-3> Details of Correction Formula 222 Figure 23 is a graph showing an example of a correction formula 222 used in the exposure apparatus 20 according to the embodiment. In the graph shown in Figure 23, the horizontal axis represents the wafer magnification XY difference, and the vertical axis represents the exposure amount (Dose). As shown in Figure 23, the correction formula 222 is a mathematical formula that shows the relationship between the wafer magnification XY difference and the exposure amount. The correction formula 222 is, for example, expressed as a linear function, and is a function such that the exposure amount increases as the wafer magnification XY difference increases. The correction formula 222 may change depending on the arrangement of the film stress adjustment layer AL, the thickness of the stress adjustment member 160, the width (arrangement density) of the stress adjustment member 160, the definition of the wafer magnification XY difference, and the type of resist material used in the exposure process. Note that the difference between reference wafer magnifications of the exposure apparatus 20 may be considered as the definition of the wafer magnification XY difference. In this case, even with the same wafer WF, there may be differences in the wafer magnification XY difference for each exposure apparatus 20.

[0106] Figure 24 is a flowchart showing an example of a method for creating a correction formula 222 used in the exposure apparatus 20 according to the embodiment. An example of a method for creating a correction formula 222 will be described below with reference to Figure 24.

[0107] First, multiple wafers WF are prepared, having been processed up to the step before the formation of the film stress adjustment layer AL (S300).

[0108] Next, in the exposure process, the wafer magnification of the pattern on each wafer WF is measured by alignment mark measurement in the exposure apparatus 20 (S301). The measurement results of the wafer magnification in process S301 may be stored not only in the exposure apparatus 20 but also in the server 40.

[0109] Next, the exposure apparatus 20 performs alignment based on the results of S301 and exposes each wafer WF with varying exposure levels (S302). The range of exposure levels set in S302 is set so that, if there is a pattern to be formed simultaneously with the film stress adjustment layer AL, the dimensions of that pattern fall within the specifications of the finished product.

[0110] Next, each wafer WF is processed until the formation process of the film stress adjustment layer AL is completed (S303).

[0111] Next, in the process following the formation of the film stress adjustment layer AL, the wafer magnification of the pattern on each wafer WF is measured (S304). The pattern measured in process S304 may be the same as the pattern measured in process S301, or it may be the pattern formed in process S302. The positional misalignment between the pattern measured in process S301 and the pattern formed in process S302 is reduced to almost zero. Therefore, almost the same measurement value is obtained regardless of whether the pattern in S301 or S302 is used for alignment measurement. The measurement result of the wafer magnification in process S304 is stored in the exposure apparatus 20 or the server 40. The measurement of the wafer magnification in process S304 may be performed by the exposure apparatus 20 or by the overlay measurement device.

[0112] Next, based on the measurement results from S301 and S304, the change in wafer magnification XY difference for each wafer WF is calculated (S305). The calculated wafer magnification XY difference for each wafer WF is stored in the exposure apparatus 20 or the server 40.

[0113] Next, a relationship formula (correction formula 222) is created between the exposure amount used in S302 and the calculation result in S305 (S305). The process in S305 may be performed by the exposure apparatus 20 or by the server 40.

[0114] As described above, the correction formula 222 is generated (end). The generated correction formula 222 is stored in the exposure apparatus 20. The correction formula 222 may also be stored in the server 40. The correction formula 222 may be shared among multiple exposure apparatuses 20.

[0115] Figure 25 is a schematic diagram showing a specific example of how to create the correction formula 222 used in the exposure apparatus 20 according to the embodiment. The method for creating the correction formula 222 using three wafers WF1 to WF3 will be described below with reference to Figure 25. Note that the shapes of the wafers WF and shots shown in the drawings below are exaggerated.

[0116] First, the S300 process prepares three wafers, WF1 to WF3.

[0117] Next, the wafer magnification of each wafer WF1 to WF3 before the formation of the film stress adjustment layer AL is measured by the S301 process. In this example, for each of the wafers WF1 to WF3, the wafer magnification W_MagX in the X direction is WMX1, and the wafer magnification W_MagY in the Y direction is WMY1.

[0118] Next, in process S302, exposure processing with varying exposure doses is performed. In this example, the exposure dose applied to wafer WF1 is Dose_H, the exposure dose applied to wafer WF2 is Dose_M, and the exposure dose applied to wafer WF1 is Dose_L. The relationship between the exposure doses is Dose_H > Dose_M > Dose_L.

[0119] Next, in the S303 process, a film stress adjustment layer AL is formed on each of the wafers WF1 to WF3. When the exposure amount is varied during the formation of the film stress adjustment layer AL shown in Figure 9, the shape of the wafer WF changes according to the magnitude of the exposure amount. For example, the larger the exposure amount, the greater the change in the wafer magnification XY difference.

[0120] Next, the wafer magnification of each wafer WF1 to WF3 after the formation of the film stress adjustment layer AL is measured by the S304 process. In this example, for wafer WF1, W_MagX = WMX2 and W_MagY = WMY2. For wafer WF2, W_MagX = WMX3 and W_MagY = WMY3. For wafer WF3, W_MagX = WMX4 and W_MagY = WMY4.

[0121] Next, the wafer magnification XY difference is calculated by the S305 process. For example, the wafer magnification XY difference for wafer WF1 is calculated by D_MagXY1=(WMX1-WMY1)-(WMX2-WMY2). The wafer magnification XY difference for wafer WF2 is calculated by D_MagXY2=(WMX1-WMY1)-(WMX3-WMY3). The wafer magnification XY difference for wafer WF3 is calculated by D_MagXY3=(WMX1-WMY1)-(WMX4-WMY4).

[0122] Next, the correction formula 222 is created by the processing in S306. Specifically, the relationship between Dose_H and D_MagXY1 is plotted from the processing results of wafer WF1, the relationship between Dose_M and D_MagXY2 is plotted from the processing results of wafer WF2, and the relationship between Dose_L and D_MagXY3 is plotted from the processing results of wafer WF3. Then, for example, the correction formula 222 is calculated by performing regression analysis using each of the plotted points. The accuracy of the correction formula 222 increases as the number of wafers WF used as samples increases.

[0123] <3-4>Specific examples of wafer magnification correction methods using film stress adjustment layer AL The following describes a specific example of a method for correcting wafer magnification using a film stress adjustment layer (AL).

[0124] Figure 26 is a schematic diagram showing an example of the change in wafer magnification when a shrinkable film is used in the film stress adjustment layer AL of the semiconductor device according to the embodiment. Figure 26(A) corresponds to the case where the stretching direction of the stress adjustment member 160a is the Y direction. Figure 26(B) corresponds to the case where the stretching direction of the stress adjustment member 160a is the X direction. As shown in Figure 26, the width of the stress adjustment member 160a increases as the exposure amount increases.

[0125] In the example shown in Figure 26(A), the ratio of shrinkage films aligned in the X direction in the film stress adjustment layer AL increases as the exposure amount increases. In this case, as the ratio of shrinkage films aligned in the X direction increases, the compressive stress on the wafer WF in the X direction increases, and the wafer magnification W_MagX in the X direction tends to decrease. Therefore, in this example, the wafer magnification XY difference changes in the negative direction as the exposure amount increases.

[0126] On the other hand, in the example shown in Figure 26(B), the ratio of shrinkage films aligned in the Y direction in the film stress adjustment layer AL increases as the exposure amount increases. In this case, the higher the ratio of shrinkage films aligned in the Y direction, the greater the compressive stress in the Y direction on the wafer WF, and the smaller the wafer magnification W_MagY in the Y direction tends to be. Therefore, in this example, the wafer magnification XY difference changes in the positive direction as the exposure amount increases.

[0127] Figure 27 is a schematic diagram showing an example of the change in wafer magnification when an expanded film is used in the film stress adjustment layer AL of the semiconductor device according to the embodiment. Figure 27(A) corresponds to the case where the stretching direction of the stress adjustment member 160b is the Y direction. Figure 27(B) corresponds to the case where the stretching direction of the stress adjustment member 160b is the X direction. As shown in Figure 27, the width of the stress adjustment member 160b increases as the exposure amount increases.

[0128] In the example shown in Figure 27(A), the ratio of expanded film aligned in the X direction in the film stress adjustment layer AL increases as the exposure amount increases. In this case, the higher the ratio of expanded film aligned in the X direction, the greater the tensile stress on the wafer WF in the X direction, and the greater the wafer magnification W_MagX in the X direction tends to be. Therefore, in this example, the wafer magnification XY difference changes in the positive direction as the exposure amount increases.

[0129] On the other hand, in the example shown in Figure 27(B), the ratio of expanded film aligned in the Y direction in the film stress adjustment layer AL increases as the exposure amount increases. In this case, the higher the ratio of expanded film aligned in the Y direction, the greater the tensile stress in the Y direction on the wafer WF, and the greater the wafer magnification W_MagY in the Y direction tends to be. Therefore, in this example, the wafer magnification XY difference changes in the negative direction as the exposure amount increases.

[0130] In the above explanation, the example given is that the resist material 180 is positive type, but the explanation is not limited to this. A negative type resist material may be used in the exposure process when forming the film stress adjustment layer AL. In this case, the width of the stress adjustment member 160 becomes narrower as the exposure amount increases. Therefore, when a negative type resist material is used and a stress adjustment member 160a (shrinkage film) is used, the ratio of shrinkage films aligned in the X or Y direction increases as the exposure amount decreases, and the wafer magnification in the X or Y direction increases. When a negative type resist material is used and a stress adjustment member 160b (expansion film) is used, the ratio of expansion films aligned in the X or Y direction increases as the exposure amount decreases, and the wafer magnification in the X or Y direction increases. The exposure apparatus 20 may use multiple correction formulas 222 depending on the type and number of film stress adjustment layers AL provided in the semiconductor device.

[0131] <4> Effects of the Embodiment The exposure apparatus 20, exposure method, and semiconductor device manufacturing method described above can improve the yield of semiconductor devices. The details of this effect are described below.

[0132] In semiconductor devices formed by joining two wafers, the wafer magnification (i.e., wafer size) of one wafer and the other wafer before joining may differ. For example, the wafer magnification can vary depending on the film stress (i.e., wafer warpage) on the front and back surfaces of the wafers. Therefore, the variation in wafer magnification between one and the other wafer may differ depending on the design of the circuits and elements. Furthermore, the XY difference in wafer magnification may also differ depending on the differences between the exposure apparatus 20 used for the initial exposure process on the wafer.

[0133] As explained with reference to Figure 17, the bonding apparatus 30 can correct a common wafer magnification in the X and Y directions during the bonding process. On the other hand, the bonding apparatus 30 has difficulty correcting the XY difference in wafer magnification. Therefore, in order to improve the overlapping accuracy in the bonding process, it is preferable to match the XY difference in wafer magnification of one wafer with the XY difference in wafer magnification of the other wafer before the bonding process.

[0134] Therefore, the memory device 10 according to the embodiment is equipped with a film stress adjustment layer AL that can be used to adjust the amount of warping of the wafer. The exposure apparatus 20 according to the embodiment controls the dimensions of the line and space pattern in a predetermined process used to form the film stress adjustment layer AL by adjusting the exposure amount based on the alignment result.

[0135] FIG. 28 is a schematic diagram showing an example of adjusting wafer magnification in the method for manufacturing a semiconductor device according to the embodiment. The example shown in FIG. 28 illustrates a case where the film stress adjustment layer AL is formed on wafers WF4, WF5, and WF6 associated with a reference wafer RF using the exposure method described above. The wafer magnification XY difference of the reference wafer RF is D_MagXY5. In the reference wafer RF, the wafer magnification in the X direction is smaller than the wafer magnification in the Y direction. The wafer magnification XY differences of the wafers WF4, WF5, and WF6 are D_MagXY2, D_MagXY3, and D_MagXY4, respectively. Further, the magnitude relationship of these wafer magnification XY differences is D_MagXY5 ≒ D_MagXY2 > D_MagXY3 > D_MagXY4. In this case, when a shrinkable film is used as the stress adjustment member 160, the exposure amount settings during the process of S205 are Dose_L, Dose_M, and Dose_H corresponding to the wafers WF4, WF5, and WF6, respectively. Therefore, the amount of change in the wafer magnification XY difference satisfies WF4 < WF5 < WF6. Accordingly, after forming the film stress adjustment layer AL, the respective shapes of the wafers WF4, WF5, and WF6 are adjusted to D_MagXY5, similarly to the reference wafer RF.

[0136] As described above, the method for manufacturing a semiconductor device according to the embodiment can make the wafer magnification XY differences of two bonded wafers WF substantially equal, and thus can suppress overlay misalignment in the bonding process. Therefore, according to the exposure apparatus 20, the exposure method, and the method for manufacturing a semiconductor device according to the embodiment, the yield of semiconductor devices can be improved.

[0137] Note that in a case where the semiconductor device includes both a film stress adjustment layer AL having a plurality of stress adjustment members 160 with portions extending in the Y direction arranged at equal intervals along the X direction, and a film stress adjustment layer AL having a plurality of stress adjustment members 160 with portions extending in the X direction arranged at equal intervals along the Y direction, these film stress adjustment layers AL are preferably provided at different heights from each other. This makes it possible to suppress warpage of the wafer WF in a desired direction regardless of whether the wafer magnification XY difference is positive or negative.

[0138] Furthermore, when the memory device 10 is used as a semiconductor device, the memory device 10 has a memory chip MC including a structure in which memory cells are stacked in three dimensions, and a CMOS chip CC including other control circuits. Between the memory chip MC and the CMOS chip CC, the memory chip MC tends to have a larger variation in wafer magnification between wafers. Specifically, because the memory chip MC has a high-layered memory cell array 13, the variation in wafer warpage is larger, and the variation in wafer magnification can be larger. On the other hand, the arrangement of shots in the CMOS chip CC is closer to an ideal lattice with respect to the exposure apparatus. For this reason, when bonding is performed, it is preferable that the wafer on which the memory chip MC is formed is assigned to the lower wafer LW, which can correct the wafer magnification, and the wafer on which the CMOS chip CC is formed is assigned to the upper wafer UW. Furthermore, it is preferable that a film stress adjustment layer AL is appropriately placed on the memory chip MC according to the state of wafer warpage that occurs during manufacturing. This can improve the yield of the memory device 10.

[0139] <5> Modifications, etc. The flowchart used to describe the operation in the above embodiment is merely an example. The order of each operation described using the flowchart may be rearranged as much as possible, other processes may be added, or some processes may be omitted. In this specification, an MPU (Micro Processing Unit), ASIC (Application Specific Integrated Circuit), or FPGA (field-programmable gate array) may be used instead of a CPU. Furthermore, each of the processes described in the embodiment may be implemented by dedicated hardware. The processes described in the embodiment may be a mixture of processes executed by software and processes executed by hardware, or may consist of only one or the other.

[0140] In this specification, “connection” means being electrically connected and does not exclude the use of another element. “Electrically connected” may be via an insulator, as long as it is possible to operate in the same way as if electrically connected. “Plane view” corresponds to viewing the object perpendicular to the surface of the semiconductor substrate 140, for example. “Region” may be considered as the configuration included by the semiconductor substrate 140 of the CMOS chip CC. For example, if the semiconductor substrate 140 is specified to include a memory region MR, the memory region MR is associated with the region above the semiconductor substrate 140. The bonding pad BP may be called the “bonding metal”. The camera 254 of the exposure apparatus 20 may be configured with a separate optical system (microscope) and a light-receiving sensor. In this specification, “overlap misalignment” may be rephrased as “positional misalignment”.

[0141] In this specification, wafer warpage is expressed, for example, by the difference between the height of the outer edge of the wafer and the height of the center of the wafer. The unit of wafer warpage is, for example, micrometers (μm). Wafer warpage may also be expressed as a signed distance from a three-point reference plane, based on the measurement result of the height of the wafer center. Wafer warpage is set to a positive value if it is above the three-point reference plane, and a negative value if it is below. Wafer warpage can be measured, for example, by calculating the wafer shape (warpage) by measuring the height of each coordinate of the wafer using a laser displacement meter, confocal displacement meter, capacitive type, heterodyne interferometer, Fizeau interferometer, etc.

[0142] The configuration of the memory device 10 described in the embodiments is merely illustrative and not limited thereto. The circuit configuration, planar layout, and cross-sectional structure of the memory device 10 can be appropriately modified according to the design of the memory device 10. For example, in the third embodiment, the case in which a memory chip MC is provided on a CMOS chip CC is illustrated, but the CMOS chip CC may be provided on a memory chip MC. The case in which a memory chip MC is assigned to the lower wafer LW and a CMOS chip CC is assigned to the upper wafer UW is illustrated, but the memory chip MC may be assigned to the upper wafer UW and the CMOS chip CC may be assigned to the lower wafer LW. When applying the manufacturing method described in the embodiments, it is preferable that the wafer with a large variation in wafer magnification between wafers be assigned to the lower wafer LW. This suppresses overlap misalignment during the bonding process and can suppress the occurrence of defects caused by overlap misalignment.

[0143] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims and their equivalents. [Explanation of symbols]

[0144] 10...Memory device, 11...Memory interface, 12...Programmable logic controller, 13...Memory cell array, 14...Driver module, 15...Raw decoder module, 16...Sense amplifier module, 20...Exposure apparatus, 21...Control device, 22...Storage device, 23...Transport device, 24...Communication device, 25...Exposure unit, 30...Bonding apparatus, 31...Control device, 32...Transport device, 33...Communication device, 34...Bonding unit, 40...Server, 41...CPU, 42...ROM, 43...RAM, 44...Storage device, 45...Communication device, 110~118...Insulator layer, 120~126...Conductive layer, 130...Core component, 131...Semiconductor layer, 132...Laminated film, 133...Tunnel insulating film, 134...Insulating film, 135...Block Block insulating film, 140... Semiconductor substrate, 141-144... Conductive layer, 150... Insulator layer, 160, 160a, 160b... Stress adjustment member, 170... Insulator layer, 180... Resist material, 190... Trench section, 220... Exposure recipe, 221... Correction value information, 250... Wafer stage, 251... Reticle stage, 252... Light source, 253... Projection optical system, 254... Camera, 302... Bonding device, 340... Lower stage, 341... Stress device, 342... Camera, 343... Upper stage, 344... Pressing pin, 345... Camera, 3431... Stress device, BLK... Block, SU... String unit, BL... Bit line, WL... Word line, SGD, SGS... Select gate line, MT... Memory cell transistor, WF... Wafer

Claims

1. An exposure apparatus for exposing a substrate, The control device is configured to correct the exposure amount based on the measurement results of three or more alignment marks placed on the substrate, The control device is Based on the measurement results, an alignment is performed by correcting the magnification components of the first and second directions, which intersect each other and are parallel to the plane of the substrate. The exposure amount is corrected based on the difference between the magnification component in the first direction and the magnification component in the second direction. Exposure apparatus.

2. The control device corrects the exposure amount to a first exposure amount when the difference between the magnification component in the first direction and the magnification component in the second direction is a first value, and corrects the exposure amount to a second exposure amount that is smaller than the first exposure amount when the difference between the magnification component in the first direction and the magnification component in the second direction is a second value that is greater than the first value. The exposure apparatus according to claim 1.

3. The control device corrects the exposure amount to a first exposure amount when the difference between the magnification component in the first direction and the magnification component in the second direction is a first value, and corrects the exposure amount to a third exposure amount that is greater than the first exposure amount when the difference between the magnification component in the first direction and the magnification component in the second direction is a second value that is greater than the first value. The exposure apparatus according to claim 1.

4. The control device changes the space width of the line and space pattern formed on the substrate by correcting the exposure amount. The exposure apparatus according to claim 1.

5. The control device corrects the exposure amount based on the difference between the magnification component in the first direction and the magnification component in the second direction and the difference between that and a reference value. The exposure apparatus according to claim 1.

6. The control device creates a relationship formula between the measurement results of the three or more alignment marks and the exposure correction value, based on the exposure amount and alignment results of each of the multiple substrates in the first step and the exposure amount and alignment results of each of the multiple substrates in the second step following the first step. The exposure apparatus according to claim 1.

7. An exposure method for exposing a substrate, The exposure amount is corrected based on the measurement results of three or more alignment marks placed on the substrate, Based on the measurement results, the exposure position is adjusted by correcting the overlapping misalignment of the magnification components in the first and second directions, which intersect each other and are parallel to the plane of the substrate. The exposure correction is based on the difference between the magnification component in the first direction and the magnification component in the second direction. Exposure method.

8. In the aforementioned exposure amount correction, When the difference between the magnification component in the first direction and the magnification component in the second direction is a first value, the exposure amount is corrected to a first exposure amount. If the difference between the magnification component in the first direction and the magnification component in the second direction is a second value greater than the first value, the exposure amount is corrected to a second exposure amount smaller than the first exposure amount. The exposure method according to claim 7.

9. In the aforementioned exposure amount correction, When the difference between the magnification component in the first direction and the magnification component in the second direction is a first value, the exposure amount is corrected to a first exposure amount. If the difference between the magnification component in the first direction and the magnification component in the second direction is a second value greater than the first value, the exposure amount is corrected to a third exposure amount greater than the first exposure amount. The exposure method according to claim 7.

10. In the exposure amount correction described above, the exposure amount is corrected based on the difference between the magnification component in the first direction and the magnification component in the second direction, and the difference between that and a reference value. The exposure method according to claim 7.

11. The exposure correction value is calculated based on a relationship formula between the measurement results of the three or more alignment marks, which are created based on the exposure amounts and alignment results of each of the multiple substrates in the first step and the exposure amounts and alignment results of each of the multiple substrates in the second step following the first step, and the exposure correction value. The exposure method according to claim 7.

12. A method for manufacturing a semiconductor device having a substrate, The substrate is exposed with an exposure amount corrected based on the measurement results of three or more alignment marks placed on the substrate, Based on the measurement results, the exposure position is adjusted by correcting the overlapping misalignment of the magnification components in the first and second directions, which intersect each other and are parallel to the plane of the substrate. The exposure correction is based on the difference between the magnification component in the first direction and the magnification component in the second direction. A method for manufacturing a semiconductor device.

13. In the aforementioned exposure amount correction, When the difference between the magnification component in the first direction and the magnification component in the second direction is a first value, the exposure amount is corrected to a first exposure amount. If the difference between the magnification component in the first direction and the magnification component in the second direction is a second value greater than the first value, the exposure amount is corrected to a second exposure amount smaller than the first exposure amount. The method for manufacturing a semiconductor device according to claim 12.

14. In the aforementioned exposure amount correction, When the difference between the magnification component in the first direction and the magnification component in the second direction is a first value, the exposure amount is corrected to a first exposure amount. If the difference between the magnification component in the first direction and the magnification component in the second direction is a second value greater than the first value, the exposure amount is corrected to a third exposure amount greater than the first exposure amount. The method for manufacturing a semiconductor device according to claim 12.

15. By correcting the exposure amount, the space width of the line and space pattern formed on the substrate is changed. The method for manufacturing a semiconductor device according to claim 12.

16. In the exposure amount correction described above, the exposure amount is corrected based on the difference between the magnification component in the first direction and the magnification component in the second direction, and the difference between that and a reference value. The method for manufacturing a semiconductor device according to claim 12.

17. The exposure correction value is calculated based on a relationship formula between the measurement results of the three or more alignment marks, which are created based on the exposure amounts and alignment results of each of the multiple substrates in the first step and the exposure amounts and alignment results of each of the multiple substrates in the second step following the first step, and the exposure correction value. The method for manufacturing a semiconductor device according to claim 12.

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