Semiconductor equipment

Abstract

To provide a semiconductor device where it is easy to identify electrode pads.SOLUTION: A semiconductor device 100 includes a first electrode 21, a second electrode 22, first to fourth semiconductor regions 11 to 14, a first control electrode 31, a second control electrode 32, and first and second electrode pads. The first semiconductor region 11 is of a first conductivity type and provided on the first electrode 21. The second semiconductor region 12 is of a second conductivity type and provided on the first semiconductor region. The third semiconductor region 13 is of a first conductivity type and provided on the second semiconductor region. The fourth semiconductor region 14 is of second conductivity type and provided on a part of the third semiconductor region. The first control electrode 31 faces the second to fourth semiconductor regions via a first insulation film. The second control electrode 32 faces the second and third semiconductor regions via a second insulation film. The second electrode 22 is connected to the third and fourth semiconductor regions. The first electrode pad is connected to the first control electrode. The second electrode pad has a planar shape different from that of the first electrode pad connected to the second control electrode.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] Embodiments of the present invention relate to semiconductor devices. [Background technology]

[0002] In semiconductor devices such as IGBTs (Insulated Gate Bipolar Transistors), multiple electrode pads may be provided. It is desirable that these electrode pads be easily distinguishable. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Patent No. 3586193 [Overview of the project] [Problems that the invention aims to solve]

[0004] The problem that this invention aims to solve is to provide a semiconductor device in which the electrode pads are easily distinguishable. [Means for solving the problem]

[0005] The semiconductor device according to the embodiment includes a first electrode, a first semiconductor region, a second semiconductor region, a third semiconductor region, a fourth semiconductor region, a first control electrode, a second control electrode, a second electrode, a first electrode pad, and a second electrode pad. The first semiconductor region is provided on the first electrode and has a first conductivity type. The second semiconductor region is provided on the first semiconductor region and has a second conductivity type. The third semiconductor region is provided on the second semiconductor region and has a first conductivity type. The fourth semiconductor region is provided on a part of the third semiconductor region and has a second conductivity type. The first control electrode faces the second semiconductor region, the third semiconductor region, and the fourth semiconductor region, respectively, via a first insulating film. The second control electrode moves away from the first control electrode in a second direction perpendicular to a first direction from the first electrode towards the first semiconductor region. The second control electrode is electrically isolated from the first control electrode. The second control electrode faces the second semiconductor region and the third semiconductor region, respectively, via a second insulating film. The second electrode is located above the third semiconductor region and the fourth semiconductor region. The second electrode is electrically connected to the third semiconductor region and the fourth semiconductor region. The first electrode pad is electrically connected to the first control electrode. The second electrode pad is electrically connected to the second control electrode. The second electrode pad has a different planar shape from the first electrode pad. [Brief explanation of the drawing]

[0006] [Figure 1] Figure 1 is a schematic plan view illustrating a semiconductor device according to an embodiment. [Figure 2] Figure 2 is a schematic cross-sectional view illustrating a semiconductor device according to an embodiment. [Figure 3] Figure 3 is a schematic plan view illustrating a semiconductor device according to an embodiment. [Figure 4] Figure 4 is a schematic cross-sectional view illustrating a semiconductor device according to an embodiment. [Figure 5] Figure 5 is a schematic cross-sectional view illustrating a semiconductor device according to an embodiment. [Figure 6]Figures 6(a) and 6(b) are schematic diagrams illustrating the operation of a semiconductor device according to an embodiment. [Figure 7] Figure 7 is a schematic cross-sectional view illustrating a semiconductor module including a semiconductor device according to an embodiment. [Modes for carrying out the invention]

[0007] Each embodiment of the present invention will be described below with reference to the drawings. Drawings are schematic or conceptual, and the relationships between the thickness and width of each part, as well as the ratios of the sizes of different parts, are not necessarily identical to those of reality. Even when representing the same part, the dimensions and ratios may be depicted differently in different drawings. In this specification and in each figure, elements similar to those already described are denoted by the same reference numerals, and detailed explanations are omitted as appropriate. In the following description and drawings, n + , n, n - and p + The notation "p" indicates the relative level of each impurity concentration. That is, a notation with "+" indicates a relatively higher impurity concentration than a notation without either "+" or "-", and a notation with "-" indicates a relatively lower impurity concentration than a notation without either. When both p-type and n-type impurities are present in each region, these notations represent the relative level of the net impurity concentration after the impurities have compensated for each other. Each embodiment described below may be implemented by reversing the p-type (an example of the first conductivity type) and n-type (an example of the second conductivity type) of each semiconductor region.

[0008] Figure 1 is a schematic plan view illustrating a semiconductor device according to an embodiment. Figure 2 is a schematic cross-sectional view illustrating a semiconductor device according to an embodiment. Figure 2 corresponds to the cross-section of line AA shown in Figure 1. Note that in Figure 1, some elements such as the first wiring 51 and the second wiring 52 (described later in Figure 3, etc.) are not shown.

[0009] As illustrated in FIG. 2, the semiconductor device 100 includes a first electrode 21, a semiconductor layer 10, a second electrode 22, a plurality of first control electrodes 31, and a plurality of second control electrodes 32. The semiconductor layer 10 includes a first semiconductor region 11, a second semiconductor region 12, a third semiconductor region 13, and a plurality of fourth semiconductor regions 14. The semiconductor device 100 according to the embodiment is, for example, a semiconductor chip including an IGBT.

[0010] In the description of the embodiment, an XYZ orthogonal coordinate system is used. A direction from the first electrode 21 toward the second electrode 22 is defined as the Z direction (first direction). Two directions that are perpendicular to the Z direction and orthogonal to each other are defined as the X direction (third direction) and the Y direction (second direction). For the convenience of description, the direction from the first electrode 21 toward the second electrode 22 is referred to as "upper", and the opposite direction is referred to as "lower". These directions are based on the relative positional relationship between the first electrode 21 and the second electrode 22, and are independent of the direction of gravity.

[0011] The first electrode 21 is, for example, a collector electrode. The first electrode 21 is provided on the lower surface 10s side of the semiconductor layer 10. The second electrode 22 is, for example, an emitter electrode. The second electrode 22 is provided on the upper surface 10u side of the semiconductor layer 10.

[0012] The first semiconductor region 11 is provided on the first electrode 21 and is of a first conductivity type (p-type). The first semiconductor region 11 is electrically connected to the first electrode 21. The first semiconductor region 11 is, for example, p + -type collector region.

[0013] The second semiconductor region 12 is provided on the first semiconductor region 11 and is of a second conductivity type (n-type). The second semiconductor region 12 is electrically connected to the first semiconductor region 11. The second semiconductor region 12 is, for example, n - -type base region.

[0014] The third semiconductor region 13 is provided on the second semiconductor region 12 and is of the first conductivity type. The third semiconductor region 13 is electrically connected to the second semiconductor region 12. The third semiconductor region 13 is, for example, a p-type base region.

[0015] Note that a semiconductor region 12B of the second conductivity type may be provided between the second semiconductor region 12 and the third semiconductor region 13. The impurity concentration of the second conductivity type in the semiconductor region 12B is higher than the impurity concentration of the second conductivity type in the second semiconductor region 12. The semiconductor region 12B is, for example, an n-type barrier layer.

[0016] The fourth semiconductor region 14 is provided on part of the third semiconductor region 13 and is of the second conductivity type. A part of the third semiconductor region 13 (semiconductor portion 13c) is located between the fourth semiconductor region 14 and the second semiconductor region 12. The fourth semiconductor region 14 is, for example, n + -type emitter region.

[0017] In this example, the semiconductor layer 10 further includes a plurality of fifth semiconductor regions 15 and a plurality of sixth semiconductor regions 16. The fifth semiconductor region 15 is provided on part of the third semiconductor region 13 and is of the first conductivity type. A part of the third semiconductor region 13 (semiconductor portion 13d) is located between the fifth semiconductor region 15 and the second semiconductor region 12. The fifth semiconductor region 15 is separated from the fourth semiconductor region 14 in the Y direction. The impurity concentration of the first conductivity type in the fifth semiconductor region 15 is higher than the impurity concentration of the first conductivity type in the third semiconductor region 13. The fifth semiconductor region 15 is, for example, p + -type region.

[0018] The sixth semiconductor region 16 is provided on part of the third semiconductor region 13 and is of the first conductivity type. For example, the sixth semiconductor region 16 is aligned with the fourth semiconductor region 14 in the Y direction and is in contact with the fourth semiconductor region 14. The impurity concentration of the first conductivity type in the sixth semiconductor region 16 is higher than the impurity concentration of the first conductivity type in the third semiconductor region 13. The sixth semiconductor region 16 is, for example, p + -type region.

[0019] A trench T1 is provided on the upper surface 10u side of the semiconductor layer 10, extending in the Z direction and reaching the second semiconductor region 12. A first insulating film 81 is provided along the inner wall of the trench T1. The first control electrode 31 is laminated inside the first insulating film 81 within the trench T1 and is in contact with the first insulating film 81. The first control electrode 31 is insulated from the semiconductor layer 10 by the first insulating film 81.

[0020] The first control electrode 31 faces a portion of the second semiconductor region 12, the third semiconductor region 13 (semiconductor portion 13c), and the fourth semiconductor region 14, respectively, via the first insulating film 81. In other words, the first control electrode 31 is aligned in the Y direction with a portion of the second semiconductor region 12, the third semiconductor region 13 (semiconductor portion 13c), and the fourth semiconductor region 14, respectively. The first insulating film 81 is in contact with the second semiconductor region 12, the third semiconductor region 13 (semiconductor portion 13c), and the fourth semiconductor region 14, respectively. For example, the first control electrode 31 is a gate electrode, and the first insulating film 81 is a gate insulating film.

[0021] A trench T2 is provided on the upper surface 10u side of the semiconductor layer 10, extending in the Z direction and reaching the second semiconductor region 12. Trench T2 is separated from trench T1 in the Y direction. A second insulating film 82 is provided along the inner wall of trench T2. The second control electrode 32 is laminated inside the second insulating film 82 within the trench T2 and is in contact with the second insulating film 82. The second control electrode 32 is insulated from the semiconductor layer 10 by the second insulating film 82.

[0022] The second control electrode 32 faces a portion of the second semiconductor region 12, the third semiconductor region 13 (semiconductor portion 13d), and the fifth semiconductor region 15, respectively, via the second insulating film 82. In other words, the second control electrode 32 is aligned in the Y direction with a portion of the second semiconductor region 12, the third semiconductor region 13 (semiconductor portion 13d), and the fifth semiconductor region 15, respectively. The second insulating film 82 is in contact with the second semiconductor region 12, the third semiconductor region 13 (semiconductor portion 13d), and the fifth semiconductor region 15, respectively. For example, the second control electrode 32 is a gate electrode, and the second insulating film 82 is a gate insulating film. A semiconductor region of the second conductivity type in contact with the second insulating film 82 does not need to be provided on the third semiconductor region 13.

[0023] Thus, the second control electrode 32 is located away from the first control electrode 31 in the Y direction and is electrically isolated from the first control electrode 31. In other words, the second control electrode 32 is configured to be able to have a voltage different from the voltage of the first control electrode 31 applied to it.

[0024] The second electrode 22 is located above the third semiconductor region 13, the fourth semiconductor region 14, the fifth semiconductor region 15, and the sixth semiconductor region, respectively. The second electrode 22 is electrically connected to the third semiconductor region 13, the fourth semiconductor region 14, the fifth semiconductor region 15, and the sixth semiconductor region 16, respectively.

[0025] For example, an insulating film 70 and a conductive contact portion 41 are provided between the semiconductor layer 10 and the second electrode 22. For example, one contact portion 41 is in contact with the upper surfaces of the fourth semiconductor region 14 and the sixth semiconductor region 16 and the lower surface of the second electrode 22. In this way, the contact portion 41 electrically connects the fourth semiconductor region 14 and the sixth semiconductor region 16 with the second electrode 22. Also, for example, another contact portion 41 is in contact with the upper surfaces of the third semiconductor region 13 and the fifth semiconductor region 15 and the lower surface of the second electrode 22. In this way, the contact portion 41 electrically connects the third semiconductor region 13 and the fifth semiconductor region 15 with the second electrode 22.

[0026] Furthermore, the contact portion 41 does not have to be in direct contact with the third semiconductor region 13, for example, and the second electrode 22 may be electrically connected to the third semiconductor region 13 via at least any one of the fourth semiconductor region 14, the fifth semiconductor region 15, and the sixth semiconductor region 16.

[0027] The insulating film 70 is provided on the trench T1 and the trench T2, and on the fourth semiconductor region 14, the fifth semiconductor region 15, and the sixth semiconductor region 16. The second electrode 22 is insulated from each of the first control electrode 31 and the second control electrode 32.

[0028] Furthermore, the semiconductor device 100 may be an RC (reverse conducting)-IGBT. That is, between the first electrode 21 and the second semiconductor region 12, an n + -type semiconductor region (not shown) may be provided. This n + -type semiconductor region is aligned with the first semiconductor region 11 in the X direction or the Y direction, and is in contact with each of the first electrode 21 and the second semiconductor region 12.

[0029] As shown in FIG. 1, the semiconductor device 100 is provided with a first electrode pad 31P and a second electrode pad 32P. The first electrode pad 31P and the second electrode pad 32P are located above the semiconductor layer 10, for example. The first electrode pad 31P and the second electrode pad 32P are provided on an insulating film disposed on the semiconductor layer 10, for example.

[0030] The planar shape of the first electrode pad 31P is different from the planar shape of the second electrode pad 32P. The planar shape refers to a shape in the X-Y plane perpendicular to the Z direction, in other words, a shape in a plan view seen along the Z direction. In the example of FIG. 1, the planar shape of the first electrode pad 31P is circular. The planar shape of the first electrode pad 31P is not limited to a strict perfect circle, and may be, for example, an oblate circle. Further, in the example of FIG. 1, the planar shape of the second electrode pad 32P is a polygon, and more specifically, a rectangle (for example, a square). Note that a polygon or a rectangle is not limited to a strict polygon or rectangle, and may include, for example, a shape with rounded corners.

[0031] The thickness (length along the Z direction) of the first electrode pad 31P may be the same as the thickness of the second electrode pad 32P. The material of the first electrode pad 31P may be the same as the material of the second electrode pad 32P.

[0032] As shown in Figure 1, in the XY plane (in a plan view along the Z direction), the first electrode pad 31P and the second electrode pad 32P are arranged point-symmetrically with respect to the center P of the semiconductor device 100 (for example, the centroid of the planar shape of the semiconductor chip). In other words, the first electrode pad 31P and the second electrode pad 32P are located on the diagonal DL of the semiconductor device 100. The center P of the semiconductor device 100 is located between the first electrode pad 31P and the second electrode pad 32P. The shape of the semiconductor device 100 is a quadrilateral (for example, a rectangle) in a plan view along the Z direction.

[0033] More specifically, for example, in a plan view, point P1 in the region where the first electrode pad 31P is located (for example, the centroid of the planar shape of the first electrode pad 31P) and point P2 in the region where the second electrode pad 32P is located (for example, the centroid of the planar shape of the second electrode pad 32P) are arranged point-symmetrically with respect to the center P of the semiconductor device 100.

[0034] Furthermore, for example, in a plan view, the shape of the region R22 where the second electrode 22 is located may be point-symmetric with respect to the center P of the semiconductor device 100. Note that the center P and diagonal DL of the semiconductor device 100 may also be the center and diagonal of the semiconductor layer 10, respectively.

[0035] For example, the first electrode pad 31P and the second electrode pad 32P are provided on the same plane. The first electrode pad 31P extends, for example, along the XY plane. The second electrode pad 32P extends, for example, along the XY plane. The first electrode pad 31P and the second electrode pad 32P are, for example, on the same XY plane. Also, for example, the second electrode 22 extends along the XY plane. For example, the upper surface of the semiconductor layer 10 and the upper surface of the second electrode 22 may be surfaces that are aligned with the XY plane (for example, surfaces that are parallel to the XY plane).

[0036] Figure 3 is a schematic plan view illustrating a semiconductor device according to an embodiment. As shown in Figure 3, the semiconductor device 100 has a first wiring 51 and a second wiring 52. Figure 3 illustrates the planar arrangement of the first control electrode 31, the second control electrode 32, the first electrode pad 31P, the second electrode pad 32P, the first wiring 51, and the second wiring 52. Note that in Figure 3, some elements, such as the second electrode 22, are not shown.

[0037] Multiple first control electrodes 31 are arranged in the Y direction, and each first control electrode 31 extends in the X direction. Multiple second control electrodes 32 are arranged in the Y direction, and each second control electrode 32 extends in the X direction. Note that the example shown in Figure 3 is just one example, and the number of first control electrodes 31 and second control electrodes 32, and the shapes of the first wiring 51 and second wiring 52 are not limited to this example.

[0038] The first wiring 51 includes, for example, a plurality of first gate wiring sections 51a and a first connecting wiring section 51b. The plurality of first gate wiring sections 51a are arranged in the X direction, and each first gate wiring section 51a extends in the Y direction. The first connecting wiring section 51b extends in the X direction and electrically connects the Y-direction end of the first gate wiring section 51a to the first electrode pad 31P. Some of the first gate wiring sections 51a may be directly connected to the first electrode pad 31P without going through the first connecting wiring section 51b.

[0039] The second wiring 52 includes, for example, a plurality of second gate wiring sections 52a and a second connecting wiring section 52b. The plurality of second gate wiring sections 52a are arranged in the X direction, and each second gate wiring section 52a extends in the Y direction. The second connecting wiring section 52b extends in the X direction and electrically connects the Y-direction end of the second gate wiring section 52a to the second electrode pad 32P. Some of the second gate wiring sections 52a may be directly connected to the second electrode pad 32P without going through the second connecting wiring section 52b.

[0040] The first gate wiring section 51a and the second gate wiring section 52a are arranged alternately along the X direction between the first connection wiring section 51b and the second connection wiring section 52b. Each of the first wiring 51 and the second wiring 52 is aligned with the second electrode 22, as described in Figure 1, etc., in the X or Y direction and is insulated from the second electrode 22.

[0041] Figure 4 is a schematic cross-sectional view illustrating a semiconductor device according to an embodiment. Figure 4 corresponds to the cross-section of the BB line shown in Figure 3. As shown in Figure 4, the first wiring 51 is located above the third semiconductor region 13, the multiple first control electrodes 31, and the multiple second control electrodes 32.

[0042] For example, an insulating film 71 and conductive contact portions 42 are provided between the semiconductor layer 10 and the first wiring 51. One contact portion 42 is in contact with the upper surface of one first control electrode 31 and the lower surface of the first gate wiring portion 51a. In this way, the contact portion 42 electrically connects the first control electrode 31 and the first gate wiring portion 51a. One first gate wiring portion 51a (first wiring 51) is electrically connected to multiple first control electrodes 31.

[0043] The insulating film 71 is provided on the trench T2 and on the third semiconductor region 13. The first gate wiring portion 51a (first wiring 51) is insulated from the second control electrode 32.

[0044] Figure 5 is a schematic cross-sectional view illustrating a semiconductor device according to an embodiment. Figure 5 corresponds to the cross-section of the CC line shown in Figure 3. As shown in Figure 5, the second wiring 52 is located above the third semiconductor region 13, the multiple first control electrodes 31, and the multiple second control electrodes 32.

[0045] For example, an insulating film 72 and conductive contact portions 43 are provided between the semiconductor layer 10 and the second wiring 52. One contact portion 43 is in contact with the upper surface of one second control electrode 32 and the lower surface of the second gate wiring portion 52a. In this way, the contact portion 43 electrically connects the second control electrode 32 and the second gate wiring portion 52a. One second gate wiring portion 52a (second wiring 52) is electrically connected to multiple second control electrodes 32.

[0046] The insulating film 72 is provided on the trench T1 and on the third semiconductor region 13. The second gate wiring portion 52a (second wiring 52) is insulated from the first control electrode 31.

[0047] As explained with respect to Figures 3 to 5, the first electrode pad 31P is electrically connected to the first control electrode 31 via the first wiring 51. The second electrode pad 32P is electrically connected to the second control electrode 32 via the second wiring 52. The first electrode pad 31P and the second electrode pad 32P are exposed on the upper surface of the semiconductor device 100, for example, and are configured to be connectable to external terminals. By applying a voltage to the first electrode pad 31P via the external terminals, a voltage can be applied to the first control electrode 31. Similarly, by applying a voltage to the second electrode pad 32P via the external terminals, a voltage can be applied to the second control electrode 32.

[0048] An example of the materials used for each element of the semiconductor device 100 will be described below. Each semiconductor region of the semiconductor layer 10 (first semiconductor region 11 to sixth semiconductor region 16, etc.) contains silicon, silicon carbide, gallium nitride, or gallium arsenide as the semiconductor material. When silicon is used as the semiconductor material, arsenic, phosphorus, or antimony can be used as the n-type impurity. Boron can be used as the p-type impurity. The first control electrode 31 and the second control electrode 32 contain a conductive material such as polysilicon. The first insulating film 81, the second insulating film 82, and the insulating films 70-72 include an insulating material such as silicon oxide. The first electrode 21, the second electrode 22, the first wiring 51, the second wiring 52, the first electrode pad 31P, and the second electrode pad 32P contain a metal such as aluminum.

[0049] The operation of the semiconductor device 100 will be described. With a positive voltage applied to the first electrode 21 (e.g., collector electrode) relative to the second electrode 22 (e.g., emitter electrode), a voltage above a threshold is applied to the first and second control electrodes 31 and 32 (e.g., gate electrodes). This forms an inversion layer (n-type inversion layer) in the third semiconductor region 13 (e.g., p-type base region), and IGBT operation begins. For example, a channel (inversion layer) is formed in the region of the third semiconductor region 13 opposite the first control electrode 31. For example, electrons flow from the second electrode 22 through the fourth semiconductor region 14 (e.g., source region) and the channel to the second semiconductor region 12. For example, holes flow from the first electrode 21 through the first semiconductor region 11 (e.g., collector region) to the second semiconductor region 12. Subsequently, when the voltage applied to the first and second control electrodes 31 and 32 falls below the threshold, the inversion layer in the third semiconductor region 13 disappears, and IGBT operation ends.

[0050] For example, as shown in the schematic circuit diagram in Figure 1, the semiconductor device 100 is electrically connected to the control unit CC. The control unit CC includes a control circuit such as a CPU. The control unit CC is electrically connected to the first control electrode 31 via the first electrode pad 31P and the first wiring 51. The control unit CC is electrically connected to the second control electrode 32 via the second electrode pad 32P and the second wiring 52. The control unit CC is electrically connected to the second electrode 22. The control unit CC is also electrically connected to the first electrode 21 (see Figure 2).

[0051] The control unit CC sets the second electrode 22 to a reference potential V0. The reference potential V0 is, for example, the ground potential. The control unit CC applies a voltage VCE to, for example, the first electrode 21. The control unit CC applies a voltage V1 to the first control electrode 31. The control unit CC applies a voltage V2 to the second control electrode 32.

[0052] Figures 6(a) and 6(b) are schematic diagrams illustrating the operation of a semiconductor device according to an embodiment. The horizontal axis in Figures 6(a) and 6(b) represents time tm. Figures 6(a) and 6(b) illustrate the voltages V1 and V2 during IGBT operation of the semiconductor device 100. For example, before time tm1, voltages V1 and V2 are positive (on state). At this time, for example, an n-type inversion layer is formed at the interface between the third semiconductor region 13 and the first insulating film 81, and at the interface between the third semiconductor region 13 and the second insulating film 82. For example, electrons flow from the second electrode 22 to the second semiconductor region 12 through the n-type inversion layer formed at the interface between the third semiconductor region 13 and the first insulating film 81.

[0053] For example, at time tm1, voltage V2 changes from positive to negative (off state). As a result, for example, at the interface between the third semiconductor region 13 and the second insulating film 82, the n-type inversion layer disappears and a p-type storage layer is formed. For example, at time tm2, after time tm1, voltage V1 changes from positive to negative (off state). As a result, for example, at the interface between the third semiconductor region 13 and the first insulating film 81, the n-type inversion layer disappears and a p-type storage layer is formed. The potential of the first control electrode 31 or the second control electrode 32 in the off state is lower than the potential of the first control electrode 31 or the second control electrode 32 in the on state. For example, the potential of the first control electrode 31 or the second control electrode 32 in the off state is lower than the potential of the second electrode 22 (reference potential V0). For example, at time tm3, after time tm2, voltages V1 and V2 change from negative to positive.

[0054] In this way, the control unit CC turns off the second control electrode 32 before the first control electrode 31 turns off. This operation can reduce losses when the semiconductor device 100 turns off, for example. For example, during the period TD1 between time tm1 and time tm2, holes are discharged from the second semiconductor region 12 to the second electrode 22 via the p-type storage layer formed at the interface between the third semiconductor region 13 and the second insulating film 82. By controlling the concentration of stored carriers, losses when the first control electrode 31 turns off can be reduced, for example. As an example, the length of the period TD1 (the difference between time tm1 and time tm2) can be 5 μs or more and 100 μs or less.

[0055] Figure 7 is a schematic cross-sectional view illustrating a semiconductor module including a semiconductor device according to an embodiment. Figure 7 schematically shows a disassembled portion of the semiconductor module 300 according to the embodiment.

[0056] As shown in Figure 7, the semiconductor module 300 has a structure in which a first member 201, a wiring board 203, a plurality of semiconductor devices 100, and a second member 202 are stacked. The first member 201 is, for example, a housing including an insulator. The second member 202 is, for example, a cap member including an insulator. Although not shown in the figure, an intermediate member such as an insulating board or a frame or guide that restricts the position of the semiconductor devices 100 may be provided between the first member 201 and the second member 202 as needed. The semiconductor devices 100 are held by being indirectly sandwiched between the first member 201 and the second member 202. That is, the semiconductor devices 100 are held by being sandwiched between the member placed between the first member 201 and the second member 202. For example, the semiconductor devices 100 are pressed against the wiring board 203.

[0057] Specifically, in this example, the first electrode pad 31P of the semiconductor device 100 is connected to the wiring board 203 via a conductive member 211 (probe pin). The second electrode pad 32P of the semiconductor device 100 is connected to the wiring board 203 via a conductive member 212 (probe pin). The first electrode 21 is exposed on the surface of the semiconductor device 100 and connected to a conductive plate 215. The conductive plate 215 is insulated from the wiring board 203. The second electrode 22 is exposed on the surface of the semiconductor device 100 and connected to a conductive plate 216. The conductive plate 216 is electrically connected to the wiring board 203 via a conductive part (not shown), for example. The semiconductor device 100 and the wiring board 203 are pressed together in a direction that brings them closer to each other. That is, the semiconductor device 100 is indirectly pressed against the wiring board 203 via conductive members 211 and 212, etc. The semiconductor module 300 is a module assembled, for example, by pressure bonding.

[0058] The effects of this embodiment will be described. As explained with reference to Figure 1, etc., in the semiconductor device 100, the planar shape of the first electrode pad 31P is different from the planar shape of the second electrode pad 32P. This makes it easy to distinguish between the first electrode pad 31P and the second electrode pad 32P.

[0059] Furthermore, as explained with respect to Figure 1, in this embodiment, the first electrode pad 31P and the second electrode pad 32P are arranged point-symmetrically. That is, the first electrode pad 31P and the second electrode pad 32P are located on the diagonal DL of the semiconductor device 100, and the center P of the semiconductor device 100 is located between the first electrode pad 31P and the second electrode pad 32P. This makes it easier to equalize the pressure applied to the semiconductor device 100 when mounting it onto the wiring board 203. For example, as explained with respect to Figure 7, when the semiconductor device 100 is pressed against the wiring board 203 by pressure contact, uneven pressure on the semiconductor device 100 can be suppressed. Also, for example, it becomes easier to design the wiring layout of the wiring board 203.

[0060] However, if the first electrode pad 31P and the second electrode pad 32P are arranged point-symmetrically, it may become difficult to distinguish between the first electrode pad 31P and the second electrode pad 32P if the orientation of the semiconductor device 100 changes during, for example, chip testing or visual inspection. In contrast, in this embodiment, as described above, the planar shape of the first electrode pad 31P is different from the planar shape of the second electrode pad 32P. This makes it easier to distinguish between the first electrode pad 31P and the second electrode pad 32P.

[0061] Here, the capacitance between the first electrode pad 31P and the second electrode 22 is defined as the first gate capacitance (first electrical capacitance). The capacitance between the second electrode pad 32P and the second electrode 22 is defined as the second gate capacitance (second electrical capacitance). For example, as shown in Figure 3, the number of second control electrodes 32 is greater than the number of first control electrodes 31. In this case, the second gate capacitance is greater than the first gate capacitance. As explained with respect to Figure 6, by turning off the second control electrode 32 in front of the first control electrode 31, holes can be discharged and losses can be reduced. A larger number of second control electrodes 32 makes it easier to discharge holes and further reduce losses. For example, the number of second control electrodes 32 is between 1 and 11 times the number of first control electrodes 31, preferably between 6 and 11 times. For example, between 1 and 11 second control electrodes 32 can be placed between two adjacent first control electrodes 31 among a plurality of first control electrodes 31. In this embodiment, the first gate capacitance may be greater than the second gate capacitance.

[0062] Furthermore, the internal electrical resistance of the semiconductor device 100 to the current flowing through the first electrode pad 31P is defined as the first gate internal resistance (first electrical resistance). The first gate internal resistance is measured by changing the voltage of the first electrode pad 31P, for example, with respect to the potential of the second electrode 22. In this case, the electrical resistance of the semiconductor device 100 to the current flowing into (or out of) the semiconductor device 100 through the first electrode pad 31P can be defined as the first gate internal resistance. The first gate internal resistance includes a resistance component due to the first electrode pad 31P, a resistance component due to the first wiring 51, and a resistance component due to the first control electrode 31. When measuring the first gate internal resistance, the first electrode 21 may be subjected to a predetermined positive voltage VCE, and the second electrode pad 32P may be subjected to a predetermined voltage (for example, the second control electrode 32 may be in the off state), with respect to the potential of the second electrode 22.

[0063] Similarly, the internal electrical resistance of the semiconductor device 100 to the current flowing through the second electrode pad 32P is defined as the second gate internal resistance (second electrical resistance). The second gate internal resistance is measured by changing the voltage of the second electrode pad 32P, for example, with respect to the potential of the second electrode 22. In this case, the electrical resistance of the semiconductor device 100 to the current flowing into (or out of) the semiconductor device 100 through the second electrode pad 32P can be defined as the second gate internal resistance. The second gate internal resistance includes a resistance component due to the second electrode pad 32P, a resistance component due to the second wiring 52, and a resistance component due to the second control electrode 32. When measuring the second gate internal resistance, with respect to the potential of the second electrode 22, the first electrode 21 may be subjected to a predetermined positive voltage VCE, and the first electrode pad 31P may be subjected to a first predetermined voltage (for example, the first control electrode 31 may be in the off state).

[0064] For example, if the capacitance of the first gate is greater than that of the second gate, it is desirable that the internal resistance of the first gate be smaller than that of the second gate. When the capacitance of the first gate is greater than that of the second gate, the current flowing through the first electrode pad 31P tends to be larger than the current flowing through the second electrode pad 32P. In this case, a relatively small internal resistance of the first gate can suppress power loss when a large current flows.

[0065] Conversely, if the second gate capacitance is larger than the first gate capacitance, it is desirable that the internal resistance of the second gate be smaller than that of the first gate. When the second gate capacitance is larger than the first gate capacitance, the current flowing through the second electrode pad 32P tends to be larger than the current flowing through the first electrode pad 31P. In this case, a relatively small internal resistance of the second gate can suppress power loss when a large current flows.

[0066] For example, the area of ​​the first electrode pad 31P is different from the area of ​​the second electrode pad 32P. The area of ​​the electrode pad refers to the area of ​​the electrode pad in a plan view along the Z direction.

[0067] For example, if the first gate capacitance is greater than the second gate capacitance, it is desirable that the area of ​​the first electrode pad 31P be larger than the area of ​​the second electrode pad 32P. A relatively large area for the first electrode pad 31P reduces the resistive component of the first electrode pad 31P. This helps to suppress power loss when a relatively large current flows through the first electrode pad 31P.

[0068] Conversely, if the second gate capacitance is larger than the first gate capacitance, it is desirable that the area of ​​the second electrode pad 32P be larger than the area of ​​the first electrode pad 31P. A relatively large area of ​​the second electrode pad 32P reduces the resistance component of the second electrode pad 32P. This suppresses power loss when a relatively large current flows through the second electrode pad 32P.

[0069] In other words, for example, if the first gate capacitance is greater than the second gate capacitance, the resistance component of the first electrode pad 31P is smaller than the resistance component of the second electrode pad 32P, and if the second gate capacitance is greater than the first gate capacitance, the resistance component of the second electrode pad 32P is smaller than the resistance component of the first electrode pad 31P. The resistance component of the first electrode pad 31P is, for example, the electrical resistance of the first electrode pad 31P in the current path from any one of the first control electrodes 31 to the external circuit via the first electrode pad 31P. Similarly, the resistance component of the second electrode pad 32P is, for example, the electrical resistance of the second electrode pad 32P in the current path from any one of the second control electrodes 32 to the external circuit via the second electrode pad 32P.

[0070] As mentioned above, in this example, the second gate capacitance is larger than the first gate capacitance. Therefore, as shown in Figure 1, the area of ​​the second electrode pad 32P is larger than the area of ​​the first electrode pad 31P.

[0071] The embodiment may include the following configurations. (Composition 1) First electrode and, A first semiconductor region of a first conductivity type provided on the first electrode, A second semiconductor region of a second conductivity type is provided on the first semiconductor region, A third semiconductor region of a first conductivity type is provided on the second semiconductor region, A fourth semiconductor region of second conductivity type is provided on a part of the third semiconductor region, A first control electrode is connected to each of the second semiconductor region, the third semiconductor region, and the fourth semiconductor region via a first insulating film, In a second direction perpendicular to the first direction from the first electrode toward the first semiconductor region, the second control electrode is separated from the first control electrode and electrically isolated from the first control electrode, and is separated from the second control electrode facing the second semiconductor region and the third semiconductor region, respectively, via a second insulating film. A second electrode located above the third and fourth semiconductor regions and electrically connected to the third and fourth semiconductor regions, A first electrode pad electrically connected to the first control electrode, A second electrode pad is electrically connected to the second control electrode and has a different planar shape from the first electrode pad, A semiconductor device equipped with the following features. (Configuration 2) The semiconductor device according to configuration 1, wherein the area of ​​the first electrode pad is different from the area of ​​the second electrode pad. (Composition 3) The first capacitance between the first electrode pad and the second electrode is greater than the second capacitance between the second electrode pad and the second electrode, and the first electrical resistance of the semiconductor device to the current flowing through the first electrode pad is less than the second electrical resistance of the semiconductor device to the current flowing through the second electrode pad, or The semiconductor device according to claim 1 or 2, wherein the second capacitance is greater than the first capacitance, and the second electrical resistance is less than the first electrical resistance. (Composition 4) The first capacitance between the first electrode pad and the second electrode is greater than the second capacitance between the second electrode pad and the second electrode, and the area of ​​the first electrode pad is greater than the area of ​​the second electrode pad, or A semiconductor device according to any one of configurations 1 to 3, wherein the second capacitance is greater than the first capacitance, and the area of ​​the second electrode pad is greater than the area of ​​the first electrode pad. (Composition 5) The semiconductor device according to configuration 3 or 4, wherein the second capacitance is greater than the first capacitance. (Composition 6) Multiple first control electrodes are provided, Multiple second control electrodes are provided, A semiconductor device according to any one of configurations 1 to 5, wherein the number of second control electrodes is greater than the number of first control electrodes. (Composition 7) A semiconductor device according to any one of configurations 1 to 6, wherein the potential of the second control electrode changes from an ON state, which is higher than the reference potential, to an OFF state, which is lower than the reference potential, before the potential of the first control electrode changes from an ON state, which is higher than the reference potential, to an OFF state, which is lower than the reference potential. (Composition 8) A semiconductor device according to any one of configurations 1 to 7, wherein no semiconductor region of a second conductivity type in contact with the second insulating film is provided on the third semiconductor region. (Composition 9) In a plane perpendicular to the first direction, the first electrode pad and the second electrode pad are located on the diagonal of the semiconductor device. A semiconductor device according to any one of configurations 1 to 8, wherein the center of the semiconductor device is located between the first electrode pad and the second electrode pad within the plane. (Composition 10) The semiconductor device according to any one of configurations 1 to 9, wherein the first electrode pad and the second electrode pad are provided on the same plane.

[0072] According to this embodiment, a semiconductor device can be provided in which the electrode pads are easily distinguishable.

[0073] The relative levels of impurity concentrations between semiconductor regions in each embodiment described above can be confirmed, for example, using an SCM (Scanning Capacitive Microscope). The carrier concentration in each semiconductor region can be considered equal to the concentration of activated impurities in that region. Therefore, the relative levels of carrier concentrations between semiconductor regions can also be confirmed using an SCM. The relative levels of impurity concentrations between semiconductor regions can be considered equivalent to the relative levels of carrier concentrations between those regions. Furthermore, the impurity concentration in each semiconductor region can be measured, for example, by SIMS (Secondary Ion Mass Spectrometry).

[0074] In this specification, "electrically connected" includes not only cases where the connection is made by direct contact, but also cases where the connection is made via other conductive members or the like. The phrase "placed on top of" one element may include not only cases where the two elements are touching (or continuous) with each other, but also cases where another element is placed between the two elements. For example, the phrase "placed on top of" one element may include cases where one element is located above another element, regardless of whether the two elements are touching each other or not. In this specification, "perpendicular" and "parallel" do not mean strictly perpendicular and strictly parallel, but also include variations in the manufacturing process, for example, and it is sufficient if they are substantially perpendicular and substantially parallel.

[0075] Although several embodiments of the present invention have been illustrated above, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. Furthermore, the embodiments described above can be implemented in combination with each other. [Explanation of symbols]

[0076] 10: Semiconductor layer 10s: Bottom side 10u:Top surface 11: First Semiconductor Area 12: Second Semiconductor Area 12B: Semiconductor Domain 13: Third Semiconductor Area 13c: Semiconductor part 13d: Semiconductor portion 14: Fourth Semiconductor Area 15: Fifth Semiconductor Area 16: Semiconductor Domain 6 21: 1st electrode 22:Second electrode 31: First control electrode 31P: First electrode pad 32: Second control electrode 32P: Second electrode pad 41-43: Contact section 51: 1st wiring 51a: First gate wiring section 51b: First connection wiring section 52:Second wiring 52a: Second gate wiring section 52b: Second connection wiring section 70-72: Insulating film 81: First insulating film 82: Second insulating film 100: Semiconductor Devices 201: First component 202: Second component 203: Wiring board 211, 212: Conductive members 215, 216: Conductive plate 300: Semiconductor Module C1: Assembly CC: Control section DL: diagonal FR: Frame P: Center P1, P2: Point R22:Region T1, T2: Trench TD1: Period V0: Reference potential V1, V2, VCE: Voltage tm1~tm3: Time

Claims

1. First electrode and A first semiconductor region of a first conductivity type provided on the first electrode, A second semiconductor region of a second conductivity type is provided on the first semiconductor region, A third semiconductor region of a first conductivity type is provided on the second semiconductor region, A fourth semiconductor region of a second conductivity type is provided on a part of the third semiconductor region, A first control electrode facing each of the second semiconductor region, the third semiconductor region, and the fourth semiconductor region is separated by a first insulating film. In a second direction perpendicular to the first direction from the first electrode toward the first semiconductor region, the second control electrode is separated from the first control electrode and electrically isolated from the first control electrode, and is separated from the second control electrode facing the second semiconductor region and the third semiconductor region, respectively, via a second insulating film. A second electrode located above the third semiconductor region and the fourth semiconductor region and electrically connected to the third semiconductor region and the fourth semiconductor region, A first electrode pad electrically connected to the first control electrode, A second electrode pad is electrically connected to the second control electrode and has a different planar shape from the first electrode pad, A semiconductor device comprising, The first capacitance between the first electrode pad and the second electrode is greater than the second capacitance between the second electrode pad and the second electrode, and the first electrical resistance of the semiconductor device to the current flowing through the first electrode pad is less than the second electrical resistance of the semiconductor device to the current flowing through the second electrode pad, or A semiconductor device in which the second capacitance is greater than the first capacitance, and the second electrical resistance is less than the first electrical resistance.

2. The semiconductor device according to claim 1, wherein the area of ​​the first electrode pad is different from the area of ​​the second electrode pad.

3. The first electrode and A first semiconductor region of a first conductivity type provided on the first electrode, A second semiconductor region of a second conductivity type is provided on the first semiconductor region, A third semiconductor region of a first conductivity type is provided on the second semiconductor region, A fourth semiconductor region of a second conductivity type is provided on a part of the third semiconductor region, A first control electrode facing each of the second semiconductor region, the third semiconductor region, and the fourth semiconductor region is separated by a first insulating film. In a second direction perpendicular to the first direction from the first electrode toward the first semiconductor region, the second control electrode is separated from the first control electrode and electrically isolated from the first control electrode, and is separated from the second control electrode facing the second semiconductor region and the third semiconductor region, respectively, via a second insulating film. A second electrode located above the third semiconductor region and the fourth semiconductor region and electrically connected to the third semiconductor region and the fourth semiconductor region, A first electrode pad electrically connected to the first control electrode, A second electrode pad is electrically connected to the second control electrode and has a different planar shape from the first electrode pad, Equipped with, The first capacitance between the first electrode pad and the second electrode is greater than the second capacitance between the second electrode pad and the second electrode, and the area of ​​the first electrode pad is greater than the area of ​​the second electrode pad, or A semiconductor device in which the second capacitance is greater than the first capacitance, and the area of ​​the second electrode pad is greater than the area of ​​the first electrode pad.

4. The semiconductor device according to any one of claims 1 to 3, wherein the second capacitance is greater than the first capacitance.

5. Multiple first control electrodes are provided, Multiple second control electrodes are provided, The semiconductor device according to any one of claims 1 to 3, wherein the number of second control electrodes is greater than the number of first control electrodes.

6. The semiconductor device according to any one of claims 1 to 3, wherein the potential of the second control electrode changes from an ON state, which is higher than the reference potential, to an OFF state, which is lower than the reference potential, before the potential of the first control electrode changes from an ON state, which is higher than the reference potential, to an OFF state, which is lower than the reference potential.

7. The semiconductor device according to any one of claims 1 to 3, wherein no semiconductor region of a second conductivity type in contact with the second insulating film is provided on the third semiconductor region.

8. In a plane perpendicular to the first direction, the first electrode pad and the second electrode pad are located on the diagonal of the semiconductor device. The semiconductor device according to any one of claims 1 to 3, wherein the center of the semiconductor device is located between the first electrode pad and the second electrode pad in the plane.

9. The semiconductor device according to any one of claims 1 to 3, wherein the first electrode pad and the second electrode pad are provided on the same plane.

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