Semiconductor device and counting method

Abstract

To provide a semiconductor device for improving the processing capacity thereof.SOLUTION: According to an embodiment, a semiconductor device includes an oscillator 201 that outputs a first signal OSC and a counter 202 that counts the number of cycles of the first signal OSC. Before the oscillator 201 outputs the Nth cycle (N is an integer equal to or greater than 2) of the first signal, the counter 202 sets a count value CNT of the number of cycles of the first signal to N.SELECTED DRAWING: Figure 12

Description

Technical Field

[0001] Embodiments of the present invention relate to a semiconductor device including a counter and a counting method.

Background Art

[0002] A semiconductor device including a counter that counts the number of periods of a periodic signal is known.

Prior Art Literature

Patent Literature

[0003]

Patent Literature 1

Patent Literature 2

Patent Literature 3

Summary of the Invention

Problem to be Solved by the Invention

[0004] In one embodiment of the present invention, there is provided a semiconductor device capable of improving processing performance.

Means for Solving the Problem

[0005] A semiconductor device according to an embodiment includes an oscillator that outputs a first signal, and a counter that counts the number of cycles of the first signal. The counter sets the count value of the number of cycles of the first signal to N before the oscillator outputs the Nth cycle (N is an integer of 2 or more) of the first signal.

Brief Description of the Drawings

[0006] [Figure 1] A block diagram showing an example of the overall configuration of a memory system including the semiconductor device according to the first embodiment. [Figure 2]A block diagram showing an example of the configuration of a semiconductor device according to the first embodiment. [Figure 3] Circuit diagram of a memory cell array included in a semiconductor device according to the first embodiment. [Figure 4] A block diagram showing an example of the configuration of an input circuit included in the semiconductor device according to the first embodiment. [Figure 5] A diagram showing an example of the circuit configuration of an input circuit included in the semiconductor device according to the first embodiment. [Figure 6] A figure showing the amplitude waveforms of signals DQS and bDQS, and signal DQ, in the semiconductor device according to the first embodiment. [Figure 7] A diagram showing an example of the overall configuration of a replica circuit included in a semiconductor device according to the first embodiment. [Figure 8] A circuit diagram showing an example of the configuration of a counter included in the semiconductor device according to the first embodiment. [Figure 9] A table showing a specific example of address information for the count value CNT<15:0> in the status register of a semiconductor device according to the first embodiment. [Figure 10] A diagram showing an example of a command sequence for counting operation in a semiconductor device according to the first embodiment. [Figure 11] A diagram showing a comparative example of counting operations. [Figure 12] This figure shows a specific example of the count value CNT in the counting operation by a counter included in the semiconductor device according to the first embodiment. [Figure 13] A flowchart showing an example of the counting operation flow in a semiconductor device according to the first embodiment. [Figure 14] A block diagram showing an example of the configuration of a semiconductor device according to a modified example of the first embodiment. [Figure 15] This figure shows an example of a command sequence for command and address input when selecting a first mode in a semiconductor device according to a modified example of the first embodiment. [Figure 16] This figure shows an example of a command sequence for the get feature operation when the first mode is selected in a semiconductor device according to a modified example of the first embodiment. [Figure 17] FIG. 13 is a diagram illustrating an example of a command sequence for a counting operation when a first mode is selected in a semiconductor device according to a modification of the first embodiment. [Figure 18] FIG. 14 is a circuit diagram illustrating an example of a configuration of a counter included in a semiconductor device according to a second embodiment. [Figure 19] FIG. 15 is a diagram illustrating an example of a command sequence for a counting operation in a semiconductor device according to the second embodiment. [Figure 20] FIG. 16 is a flowchart illustrating an example of a flow of a counting operation in a semiconductor device according to the second embodiment. [Figure 21] FIG. 17 is a circuit diagram illustrating an example of a configuration of a counter included in a semiconductor device according to a third embodiment. [Figure 22] FIG. 18 is a diagram illustrating specific examples of respective signals in a counter included in a semiconductor device according to the third embodiment. [Figure 23] FIG. 19 is a flowchart illustrating an example of a flow of a counting operation in a semiconductor device according to the third embodiment. [Figure 24] FIG. 20 is a circuit diagram illustrating an example of a configuration of a counter included in a semiconductor device according to a fourth embodiment. [Figure 25] FIG. 21 is a diagram illustrating specific examples of a signal OSC, a signal OSC_CLK2, and a count value CNT in a counter included in a semiconductor device according to the fourth embodiment. [Figure 26] FIG. 22 is a diagram illustrating an example of a command sequence for a counting operation in a semiconductor device according to the fourth embodiment. [Figure 27] FIG. 23 is a flowchart illustrating an example of a flow of a counting operation in a semiconductor device according to the fourth embodiment. [Figure 28] FIG. 24 is a diagram illustrating an example of an overall configuration of a replica circuit included in a semiconductor device according to a modification of the fourth embodiment. [Figure 29] FIG. 25 is a circuit diagram illustrating an example of a configuration of a counter included in a semiconductor device according to a modification of the fourth embodiment. [Figure 30] FIG. 26 is a diagram illustrating an example of a command sequence for a counting operation in a semiconductor device according to a modification of the fourth embodiment. [Figure 31]A flowchart showing an example of the counting operation flow in a semiconductor device according to a modified example of the fourth embodiment. [Figure 32] A block diagram showing an example of the overall configuration of a semiconductor device according to the first example of the fifth embodiment. [Figure 33] A block diagram showing an example of the overall configuration of a semiconductor device according to the second example of the fifth embodiment. [Figure 34] A block diagram showing an example of the connection between an oscillator and an input / output port included in a semiconductor device according to the second example of the fifth embodiment. [Figure 35] A flowchart showing an example of the counting operation flow in a semiconductor device according to the second example of the fifth embodiment. [Modes for carrying out the invention]

[0007] Embodiments are described below with reference to the drawings. Each embodiment exemplifies an apparatus or method for realizing the technical idea of ​​the invention. The drawings are schematic or conceptual, and the dimensions and proportions shown in each drawing are not necessarily identical to those of actual objects. All descriptions of one embodiment also apply to other embodiments unless explicitly or obviously excluded. The technical idea of ​​the present invention is not defined by the shape, structure, arrangement, etc., of its components.

[0008] In the following description, components having substantially the same function and structure are assigned the same code. The numbers following the characters that constitute the reference code are used to distinguish elements that are referenced by reference codes containing the same character and have a similar structure. When there is no need to distinguish between elements indicated by reference codes containing the same character, these elements are each referenced by reference codes containing only the character.

[0009] 1. First Embodiment First, as a first embodiment, we will describe the case where the semiconductor device is a NAND flash memory. Note that the semiconductor device is not limited to a NAND flash memory; any semiconductor device having an oscillator and a counter is acceptable.

[0010] 1.1 Configuration 1.1.1 Memory System Configuration First, an example of the configuration of a memory system 1 having a semiconductor device will be described with reference to Figure 1. Figure 1 is a block diagram showing an example of the overall configuration of the memory system 1. In the example in Figure 1, some of the connections between each component are shown by arrow lines, but the connections between each component are not limited to these.

[0011] As shown in Figure 1, the memory system 1 is, for example, an SSD (Solid State Drive). The memory system 1 is connected to a host device (not shown). For example, the host device controls the memory system 1.

[0012] The memory system 1 includes a non-volatile memory 10 and a memory controller 20.

[0013] The non-volatile memory 10 is a non-volatile storage medium. The non-volatile memory 10 stores data received from the memory controller 20 in a non-volatile manner.

[0014] The memory controller 20 is, for example, a System On a Chip (SoC). The memory controller 20 commands the non-volatile memory 10 to perform read operations, write operations, erase operations, etc., based on requests (commands) from the host device, for example. The memory controller 20 also manages the memory space of the non-volatile memory 10.

[0015] Next, an example of the internal configuration of the non-volatile memory 10 will be described. The non-volatile memory 10 includes multiple memory chips 11. Each of the multiple memory chips 11 can operate independently. Each memory chip 11 is connected to the memory controller 20 via a NAND bus. Note that the non-volatile memory 10 may have only one memory chip 11.

[0016] The memory chip 11 is, for example, a semiconductor device equipped with NAND flash memory. The memory chip 11 stores data non-volatilely. Note that the memory chip 11 may be other types of non-volatile memory.

[0017] The memory chip 11 communicates with the memory controller 20 (more specifically, the memory interface circuit 27) via the NAND bus to send and receive signals such as the 8-bit signal DQ<7:0>, as well as signals DQS and bDQS. Hereafter, unless one of the signals DQ<7:0> is specified, it will simply be referred to as "signal DQ". Signal DQ is, for example, data, address, command, or status information. Signals DQS and bDQS are strobe signals (clock signals) used for input and output of signal DQ when signal DQ is data. Signal bDQS is the inverted signal of signal DQS.

[0018] In this embodiment, when data is transmitted from the memory controller 20 to the memory chip 11, the transmission of data (signal DQ) and the transmission of strobe signals (signals DQS and bDQS) are performed asynchronously. Hereinafter, this data input interface specification will be referred to as "Unmatched DQS".

[0019] The memory chip 11 receives various control signals from the memory controller 20 via the NAND bus. Details of the control signals will be described later.

[0020] Furthermore, the memory chip 11 transmits a ready / busy signal bRB to the memory controller 20 via the NAND bus. The ready / busy signal bRB indicates whether the memory chip 11 is in a state where it can or cannot receive commands from the memory controller 20. The ready state means that the memory chip 11 is in a state where it can receive commands from the memory controller 20. The busy state means that the memory chip 11 is in a state where it cannot receive commands from the memory controller 20. For example, the ready / busy signal bRB is set to "L" level when the memory chip 11 is in a busy state.

[0021] Next, an example of the internal configuration of the memory controller 20 will be described. The memory controller 20 includes a host interface circuit (host I / F) 21, a CPU (Central Processing Unit) 22, a ROM (Read Only Memory) 23, a RAM (Random Access Memory) 24, a buffer memory 25, an ECC (Error Checking and Correcting) circuit 26, and a memory interface circuit (memory I / F) 27. These circuits are connected to each other, for example, by the internal bus of the memory controller 20. Note that the functions of the host interface circuit 21, the ECC circuit 26, and the memory interface circuit 27 may be implemented by dedicated circuits, or they may be implemented by the CPU 22 executing firmware.

[0022] The host interface circuit 21 is an interface circuit connected to the host device. The host interface circuit 21 controls communication between the host device and the memory controller 20. The host interface circuit 21 transmits requests and data received from the host device to the CPU 22 and the buffer memory 25, respectively. The host interface circuit 21 also transmits data in the buffer memory 25 to the host device based on control by the CPU 22.

[0023] The CPU 22 is a processor. The CPU 22 controls the operation of the entire memory controller 20. For example, the CPU 22 commands write, read, and erase operations to the non-volatile memory 10 (memory chip 11) based on requests from the host device. The CPU 22 also manages the memory area of ​​the non-volatile memory 10.

[0024] The CPU 22 commands the non-volatile memory 10 (memory chip 11) to perform, for example, write training. Write training is an operation aimed at adjusting the timing between signal DQ and signals DQS and bDQS. For example, the CPU 22 causes the memory chip 11 to perform write operations for write training data and read operations for said data. At this time, the CPU 22 transmits signals DQS and bDQS, as well as signal DQ, to the memory chip 11 while changing the delay time of signal DQ relative to signals DQS and bDQS. The CPU 22 then sets the condition that provides the highest degree of agreement between the written data and the read data (the delay time of signal DQ relative to signals DQS and bDQS) as the data transmission condition. Hereinafter, the delay time of signal DQ relative to signals DQS and bDQS will be denoted as time tDQS2DQ.

[0025] For example, in the memory chip 11, the transmission path to the latch circuit that captures signal DQ differs between signals DQS and bDQS and signal DQ. Therefore, fluctuations in voltage or temperature in the memory chip 11 cause the optimal value of time tDQS2DQ to change. To address this, the CPU 22 performs write training at arbitrary timings as needed.

[0026] Furthermore, the CPU 22 periodically executes a counting operation on a clock signal (signal OSC, described later) generated by an oscillator in the memory chip 11. The clock signal is a pseudo-signal of signal DQS generated within the memory chip 11. The counting operation counts the number of cycles (clock count) of the clock signal. The CPU 22 controls the execution time of the counting operation (hereinafter also referred to as "count execution time"). The number of cycles (count count) of the clock signal in the memory chip 11 fluctuates due to changes in voltage or temperature in the memory chip 11, similar to the fluctuation of time tDQS2DQ. Based on the amount of change in the number of cycles, the CPU 22 predicts the fluctuation of time tDQS2DQ and determines whether or not to perform write training.

[0027] ROM23 is a non-volatile memory. For example, ROM23 is an EEPROM.TM It is (Electrically Erasable Programmable Read-Only Memory). ROM23 is a non-temporary storage medium that stores firmware and programs. For example, the CPU22 loads the firmware loaded from ROM23 into RAM24.

[0028] RAM24 is volatile memory. RAM24 is either DRAM (Dynamic Random Access Memory) or SRAM (Static Random Access Memory), etc. RAM24 can be used as a work area for the CPU22. For example, RAM24 stores firmware for managing non-volatile memory 10 and various management tables. For example, the results of counting operations are stored in RAM24.

[0029] The buffer memory 25 is volatile memory. The buffer memory 25 is DRAM or SRAM, etc. The buffer memory 25 temporarily holds data read by the memory controller 20 from the non-volatile memory 10, data received from the host device, etc.

[0030] The ECC circuit 26 is a circuit that performs ECC processing. ECC processing includes data encoding and decoding processing. For example, when data is written, the ECC circuit 26 performs data encoding to generate an error correction code (parity). The ECC circuit 26 then assigns the parity to the data. When data is read, the ECC circuit 26 performs decoding. In other words, the ECC circuit 26 performs error correction processing of the data using the parity.

[0031] The memory interface circuit 27 controls communication between the memory controller 20 and the non-volatile memory 10. The memory interface circuit 27 may have multiple channels CH (CH0, CH1, ...). Multiple memory chips 11 may be connected to each channel CH via a NAND bus. The memory interface circuit 27 transmits signals DQ, DQS and bDQS, as well as various control signals, to the memory chips 11. The memory interface circuit 27 also receives signals DQ, DQS and bDQS, as well as a ready / busy signal bRB, from the memory chips 11.

[0032] 1.1.2 Memory Chip Configuration Next, an example of the configuration of the memory chip 11 will be described with reference to Figure 2. Figure 2 is a block diagram showing an example of the configuration of the memory chip 11 (semiconductor device). In the example in Figure 2, some of the connections between each component are shown by arrow lines, but the connections between each component are not limited to these.

[0033] As shown in Figure 2, the memory chip (NAND flash memory) 11 includes an input / output circuit 101, a replica circuit 102, a logic control circuit 103, an address register 104, a command register 105, a status register 106, a sequencer 107, a ready / busy circuit 108, a voltage generation circuit 109, a memory cell array 120, a row decoder 121, a sense amplifier 122, a data register 123, and a column decoder 124.

[0034] The input / output circuit 101 is a circuit that performs input and output of signals DQ, DQS, and bDQS with the memory controller 20. The input / output circuit 101 is connected to the memory controller 2 via multiple pads PD (external connection terminals) corresponding to signals DQ<7:0> and DQS and bDQS. The input / output circuit 101 is also connected to the logic control circuit 103, address register 104, command register 105, status register 106, and data register 123.

[0035] The input / output circuit 101 includes an input circuit 131 and an output circuit 132.

[0036] The input circuit 131 is a circuit that receives the signal DQ from the memory controller 20. If the signal DQ is data DAT, the input circuit 131 captures the signal DQ based on signals DQS and bDQS. Then, the input circuit 131 sends the data DAT to the data register 123. If the signal DQ is address ADD, the input circuit 131 captures the signal DQ based on the write enable signal bWE, which will be described later. Then, the input circuit 131 sends the address ADD to the address register 104. If the signal DQ is command CMD, the input circuit 131 captures the signal DQ based on the write enable signal bWE. Then, the input circuit 131 sends the command CMD to the command register 105.

[0037] The output circuit 132 is a circuit that transmits signal DQ to the memory controller 20. The output circuit 132 transmits signal DQ to the memory controller 20 along with signals DQS and bDQS. The output circuit 132 transmits data DAT or status information STS read from the memory cell array 120 as signal DQ to the memory controller 20.

[0038] The replica circuit 102 is a circuit that generates a clock signal (signal OSC, described later) corresponding to the signal DQS and counts the number of cycles (clocks) of the clock signal. The replica circuit 102 includes a feedback oscillator for generating the clock signal. The feedback path of the oscillator has the same configuration as the transmission path of the signal DQS in the input circuit 131. For this reason, the replica circuit 102 can also be referred to as the "DQS oscillator". The replica circuit 102 is connected to the status register 106 and the sequencer 107. The replica circuit 102 transmits the count result from the counting operation to the status register 106.

[0039] The logic control circuit 103 is a circuit that performs logic control of the memory chip 11. The logic control circuit 103 is connected to the memory controller 20 via a plurality of pads PD corresponding to each control signal. The logic control circuit 103 is also connected to the input / output circuit 101 and the sequencer 107. The logic control circuit 103 controls the input / output circuit 101 and the sequencer 107 based on various control signals.

[0040] For example, the logic control circuit 103 receives the chip enable signal bCE, command latch enable signal CLE, address latch enable signal ALE, write enable signal bWE, and read enable signals RE and bRE as control signals.

[0041] The chip enable signal bCE is a signal used to enable the memory chip 11. The chip enable signal bCE is asserted, for example, at a Low ("L") level.

[0042] The command latch enable signal CLE indicates that signal DQ is a command. The command latch enable signal CLE is asserted, for example, at a High ("H") level.

[0043] The address latch enable signal ALE indicates that signal DQ is an address. The address latch enable signal ALE is asserted, for example, at the "H" level.

[0044] The write enable signal bWE is a signal used to capture signal DQ when it is either command CMD or address ADD. The write enable signal bWE is asserted, for example, at an "L" level, when the memory chip 11 captures command CMD or address ADD. Therefore, each time the write enable signal bWE is toggled, command CMD or address ADD is captured by the memory chip 11.

[0045] The read enable signals RE and bRE are signals that the memory controller 20 uses to read data from the memory chip 11. The read enable signal bRE is the inverse signal of the read enable signal RE. The read enable signals RE and bRE are asserted, for example, at an "L" level. For example, when outputting data, the memory chip 11 generates signals DQS and bDQS based on the read enable signals RE and bRE.

[0046] Address register 104 is a register that temporarily stores address ADD. Address register 104 is connected to the input / output circuit 101, the sequencer 107, the row decoder 121, and the column decoder 124. Address ADD includes the row address RAD and the column address CAD. Address register 104 transmits the row address RAD to the row decoder 121. Address register 104 also transmits the column address CAD to the column decoder 124.

[0047] Command register 105 is a register that temporarily stores command CMD. Command register 105 is connected to the input / output circuit 101 and the sequencer 107. Command register 105 sends command CMD to the sequencer 107.

[0048] The status register 106 is a register that temporarily stores status information STS. The status register 106 is connected to the input / output circuit 101, the replica circuit 102, and the sequencer 107. For example, the status information STS includes information about the results of write operations, read operations, and erase operations. The status information STS also includes information about the results of count operations in the replica circuit 102. The status information STS is transmitted to the memory controller 20 as signal DQ.

[0049] The sequencer 107 is a circuit that controls the operation of the entire memory chip 11. The sequencer 107 is connected to the replica circuit 102, logic control circuit 103, address register 104, command register 105, status register 106, ready / busy circuit 108, voltage generation circuit 109, row decoder 121, and sense amplifier 122, etc. The sequencer 107 controls the replica circuit 102, status register 106, ready / busy circuit 108, voltage generation circuit 109, row decoder 121, and sense amplifier 122, etc. Based on the command CMD, the sequencer 107 performs write, read, and erase operations. The sequencer 107 performs write training. The sequencer 107 also controls the count operation in the replica circuit 102.

[0050] The ready / busy circuit 108 is a circuit that generates a ready / busy signal bRB. The ready / busy circuit 108 is connected to the sequencer 107. The ready / busy circuit 108 generates the ready / busy signal bRB based on the control of the sequencer 107. The ready / busy circuit 108 transmits the ready / busy signal bRB to the memory controller 20.

[0051] The voltage generation circuit 109 generates various voltages used for writing, reading, and erasing operations based on the control of the sequencer 107. The voltage generation circuit 109 supplies these various voltages to the memory cell array 120, the row decoder 121, and the sense amplifier 122, etc.

[0052] The memory cell array 120 is a collection of multiple memory cell transistors (also referred to as "memory cells") arranged in a sequence. The memory cell array 120 includes multiple block BLKs. A block BLK is, for example, a collection of multiple memory cell transistors whose data is erased all at once. In the example in Figure 2, the memory cell array 120 includes four blocks BLK0, BLK1, BLK2, and BLK3. The number of block BLKs in the memory cell array 120 is arbitrary.

[0053] The row decoder 121 is a circuit for decoding row-address RADs. The row decoder 121 is connected to the address register 104, the sequencer 107, the voltage generation circuit 109, and the memory cell array 120. Based on the decoding result of the row-address RAD, the row decoder 121 selects one of the block BLKs. The row decoder 121 applies a voltage to the row-direction wiring (word lines and selection gate lines, described later) of the selected block BLK.

[0054] The sense amplifier 122 is a circuit that performs writing and reading of data DAT. The sense amplifier 122 is connected to the sequencer 107, the voltage generation circuit 109, the memory cell array 120, and the data register 123. During a read operation, the sense amplifier 122 reads the data DAT from the memory cell array 120. During a write operation, the sense amplifier 122 supplies a voltage to the memory cell array 120 corresponding to the data DAT to be written.

[0055] The data register 123 is a register that temporarily stores data DAT. The data register 123 is connected to the input / output circuit 101, the sequencer 107, the sense amplifier 122, and the column decoder 124. The data register 123 includes multiple latch circuits. Each latch circuit temporarily stores the data to be written or read.

[0056] The column decoder 124 is a circuit that decodes the column address CAD. The column decoder 124 is connected to the address register 104, the sequencer 107, and the data register 123. The column decoder 124 receives the column address CAD from the address register 104. Based on the decoding result of the column address CAD, the column decoder 124 selects a latch circuit in the data register 123.

[0057] 1.1.3 Circuit configuration of memory cell array Next, an example of the circuit configuration of the memory cell array 120 will be described with reference to Figure 3. Figure 3 is a circuit diagram of the memory cell array 120. Note that the example in Figure 3 shows the circuit configuration of one block BLK.

[0058] As shown in Figure 3, a block BLK contains multiple string units SU. A string unit SU is a collection of multiple NAND strings NS that are selected together, for example, during a write or read operation. In the example in Figure 3, the block BLK contains four string units SU0 to SU3. The number of string units SU included in a block BLK is arbitrary.

[0059] Next, the internal structure of the string unit SU will be described. The string unit SU contains multiple NAND strings NS. A NAND string NS is a collection of multiple memory cell transistors connected in series. For example, n+1 (where n is an integer greater than or equal to 1) NAND strings NS in the string unit SU are each connected to n+1 bit lines BL0 to BLn.

[0060] Next, the internal structure of the NAND string NS will be described. Each NAND string NS includes multiple memory cell transistors MC, as well as selection transistors ST1 and ST2. In the example shown in Figure 3, the NAND string NS includes eight memory cell transistors MC0 to MC7. The number of memory cell transistors MC in the NAND string NS is arbitrary.

[0061] A memory cell transistor (MC) stores data nonvolatilously. The memory cell transistor (MC) includes a control gate and a charge storage layer. The memory cell transistor (MC) may be of the MONOS (Metal-Oxide-Nitride-Oxide-Silicon) type or the FG (Floating Gate) type. The MONOS type uses an insulating layer in the charge storage layer. The FG type uses a conductive layer in the charge storage layer.

[0062] The selection transistors ST1 and ST2 are used to select the string unit SU during various operations. The number of selection transistors ST1 and ST2 is arbitrary. It is sufficient that one or more selection transistors ST1 and ST2 are included in each NAND string NS.

[0063] The current paths of the memory cell transistors MC and the selection transistors ST1 and ST2 within each NAND string NS are connected in series. More specifically, the current paths are connected in series in the order of selection transistor ST2, memory cell transistors MC0 to MC7, and selection transistor ST1. The drain of selection transistor ST1 is connected to one of the bit lines BL. The source of selection transistor ST2 is connected to the source line SL.

[0064] The control gates of multiple memory cell transistors MC0 to MC7 within the same block BLK are each connected in common to word lines WL0 to WL7. More specifically, for example, block BLK contains four string units SU0 to SU3. Each of the string units SU0 to SU3 contains multiple memory cell transistors MC0. The control gates of these multiple memory cell transistors MC0 within block BLK are all connected in common to a single word line WL0. The same applies to memory cell transistors MC1 to MC7.

[0065] The gates of multiple selection transistors ST1 within a string unit SU are connected in common to a single selection gate line SGD. More specifically, string unit SU0 contains multiple selection transistors ST1. The gates of multiple selection transistors ST1 within string unit SU0 are connected in common to selection gate line SGD0. Similarly, the gates of multiple selection transistors ST1 within string unit SU1 are connected in common to selection gate line SGD1. The gates of multiple selection transistors ST1 within string unit SU2 are connected in common to selection gate line SGD2. The gates of multiple selection transistors ST1 within string unit SU3 are connected in common to selection gate line SGD3.

[0066] The gates of multiple selection transistors ST2 within the same block BLK are connected in common to a single selection gate line SGS. More specifically, for example, block BLK includes four string units SU0 to SU3. Each of the string units SU0 to SU3 includes multiple selection transistors ST2. The gates of these multiple selection transistors ST2 within block BLK are connected in common to a single selection gate line SGS. Note that, similar to the selection gate line SGD, a different selection gate line SGS may be provided for each string unit SU.

[0067] Word lines WL0 to WL7, selection gate lines SGD0 to SGD3, and selection gate line SGS are connected to the row decoder 121, respectively.

[0068] Each bit line BL is connected in common to one NAND string NS within each string unit SU of each block BLK. Multiple NAND strings NS connected to a single bit line BL are assigned the same column address CAD. Each bit line BL is connected to sense amplifier 122.

[0069] Source lines SL are shared, for example, between multiple block lines BLK.

[0070] Within a single string unit SU, a collection of multiple memory cell transistors MC connected to a single word line WL is denoted as a "cell unit CU". For example, if a memory cell transistor MC stores 1 bit of data, the storage capacity of a cell unit CU is defined as "1 page of data". Based on the number of bits of data stored by the memory cell transistor MC, a cell unit CU may have a storage capacity of 2 pages of data or more.

[0071] 1.1.4 Input Circuit Configuration 1.1.4.1 Input Circuit Configuration Next, an example of the configuration of the input circuit 131 will be described with reference to Figure 4. Figure 4 is a block diagram showing an example of the configuration of the input circuit 131. Note that the example in Figure 4 shows the configuration when the signal DQ is data DAT, that is, when the signal DQ is acquired based on signals DQS and bDQS.

[0072] As shown in Figure 4, the input circuit 131 includes an input receiver (IREC) 141, a delay circuit 142, and a latch circuit 143.

[0073] The input receiver 141 is a receiving circuit for signals DQS and bDQS. The two input terminals of the input receiver 141 are connected to pad PD, which receives the signal DQS, and pad PD, which receives the signal bDQS, respectively. The output terminal of the input receiver 141 is connected to the delay circuit 142. For example, the input receiver 141 outputs an inverted signal synchronized with signals DQS and bDQS. The output signal of the input receiver 141 is input to the delay circuit 142.

[0074] The delay circuit 142 is a circuit that delays the signal received from the input receiver 141. The delay circuit 142 is connected to the latch circuit 143. Note that the delay circuit 142 may be omitted. Also, a driver or the like for the purpose of signal transmission may be provided in the wiring path between the input receiver 141 and the latch circuit 143. The output signal of the input receiver 141 is delayed by the delay circuit 142 and the wiring delay in the wiring path connecting the input receiver 141 and the latch circuit 143, and then input to the latch circuit 143. The signals input to the latch circuit 143 are denoted as signals CK and bCK. Signal CK is a strobe signal obtained by delaying signal DQS. Signal bCK is the inverted signal of signal CK. The delay time of signals CK and bCK relative to signals DQS and bDQS corresponds to time tDQS²DQ. That is, signals DQS and bDQS delayed by time tDQS²DQ are input to the latch circuit 143.

[0075] The latch circuit 143 is a circuit that captures signal DQ based on signals CK and bCK (signals DQS and bDQS delayed by time tDQS2DQ). The latch circuit 143 captures signal DQ <0> ~DQ <7> It is connected to eight pads PD to which the input is received. For example, the latch circuit 143 captures the odd bits of data of each signal DQ based on the signal CK, and captures the even bits of data of each signal DQ based on the signal bCK. For example, the latch circuit 143 may include multiple LTSAs (Latch-Type Voltage Sense Amplifiers) or multiple DTSAs (Double-Tail latch-Type Voltage Sense Amplifiers) corresponding to each signal DQ. <0> ~ <7> The corresponding signal is DQ_INT <0> ~DQ_INT <7> Outputs.

[0076] The latch circuit 143 is positioned relatively close to the pad PD to which the signal DQ is input. By positioning it relatively close, the wiring length connecting the pad PD and the latch circuit 143 can be made relatively short. Furthermore, the number of circuits in the path connecting the pad PD to which the signal DQ is input and the latch circuit 143 is less than the number of circuits (including the input receiver 141 and delay circuit 142) in the path connecting the pad PD to which the signal DQS is input and the latch circuit 143. This reduces the jitter and skew of the signal DQ in the latch circuit 143. In addition, a CTLE (Continuous Time Linear Equalizer) or the like may be placed between the pad PD and the latch circuit 143 for the purpose of correcting signal degradation. A CTLE is a circuit that reduces jitter by compensating for insertion loss.

[0077] 1.1.4.2 Circuit configuration of the input circuit Next, an example of the circuit configuration of the input circuit 131 will be described with reference to Figure 5. Figure 5 is a diagram showing an example of the circuit configuration of the input circuit 131. Note that in the example in Figure 5, for the sake of simplicity, the delay circuit 142 and signal DQ are omitted. <1> ~DQ <6> The latch circuits 143 corresponding to each of these are omitted. Also, in the example in Figure 5, the signal bCK is omitted.

[0078] As shown in Figure 5, the input receiver 141 includes a comparator 151. The comparator 151 includes a first input terminal to which the signal DQS is input, a second input terminal to which the signal bDQS is input, and an output terminal. The first input terminal is connected to pad PD to which the signal DQS is input. The second input terminal is connected to pad PD to which the signal bDQS is input. For example, the comparator 151 outputs an inverted signal synchronized with the signals DQS and bDQS. The output terminal is connected to the latch circuit 143 via drivers 152 and 153. For example, driver 152 is a CML (Current Mode Logic) circuit that amplifies the amplitude of the signal output by the comparator 151. Also, for example, driver 153 is a C2C (Cml To Cmos) circuit that converts the signal amplified by driver 152 to CMOS level.

[0079] The latch circuit 143 includes multiple comparators 154 corresponding to each signal DQ. Note that multiple comparators 154 may be provided for a single signal DQ. For example, for a single signal DQ, there may be a comparator 154 that operates based on signal CK and another comparator 154 that operates based on signal bCK.

[0080] Comparator 154 includes a first input terminal, a second input terminal, a clock signal input terminal, and an output terminal. The first input terminal is connected to pad PD, to which the corresponding signal DQ is input. The second input terminal is, for example, to which a reference voltage VREF is input. The reference voltage VREF is a reference voltage used to determine the logic level of signal DQ. The clock signal input terminal is, for example, to which the signal CK is input. The clock signal input terminal is connected to driver 153. The wiring delay that occurs in the wiring path connecting the output terminal of comparator 151 and the clock signal input terminal of comparator 154 corresponds to time tDQS2DQ. The signal DQ_INT is output from the output terminal of comparator 154. In the example in Figure 5, comparator 154 outputs the result of comparing signal DQ with the reference voltage VREF when signal CK is at a High ("H") level. For example, comparator 154 outputs a Low ("L") level signal DQ_INT when the voltage of signal DQ is higher than the reference voltage VREF.

[0081] A different comparator 154 is provided for each signal DQ. Therefore, the wiring path (wiring length) connecting the output terminal of comparator 151 and the clock signal input terminal of comparator 154 differs for each comparator 154. Consequently, the amount of wiring delay that occurs in the wiring path differs for each signal DQ. In other words, the time tDQS2DQ may differ for each signal DQ. For example, in light training, an optimal time tDQS2DQ may be set for each signal DQ.

[0082] 1.1.4.3 Input timing of signals DQS, bDQS, and DQ Next, an example of the input timing of signals DQS and bDQS and signal DQ will be described with reference to Figure 6. Figure 6 shows the amplitude waveforms of signals DQS and bDQS and signal DQ. The example in Figure 6 shows the amplitude waveforms of signals DQS and bDQS and signal DQ in pad PD, and the amplitude waveforms of signals CK and bCK (delayed signals DQS and bDQS) and signal DQ in latch circuit 143.

[0083] As shown in Figure 6, in this embodiment, data (signal DQ) and strobe signals (signals DQS and bDQS) are input asynchronously to the memory chip 11. That is, the timing of the input of signals DQS and bDQS to the pad PD is not synchronized with the timing of the input of signal DQ. The time difference between signals DQS and bDQS and signal DQ is time tDQS²DQ.

[0084] The latch circuit 143 is positioned relatively close to the pad PD corresponding to the signal DQ. Therefore, the latch circuit 143 receives the signal DQ from the pad PD with relatively little delay. The latch circuit 143 also receives signals CK and bCK, which are delayed versions of signals DQS and bDQS. In the latch circuit 143, the input timing of signals CK and bCK is synchronized with the input timing of signal DQ. This allows the latch circuit 143 to capture signal DQ based on signals CK and bCK. In light training, the timing of signal DQ is optimized so that the delay time of signals CK and bCK corresponding to signals DQS and bDQS is time tDQS²DQ.

[0085] 1.1.5 Replica Circuit Configuration 1.1.5.1 Overall Configuration of the Replica Circuit First, an example of the overall configuration of the replica circuit 102 will be described with reference to Figure 7. Figure 7 is a diagram showing an example of the overall configuration of the replica circuit 102.

[0086] As shown in Figure 7, the replica circuit 102 includes an oscillator 201 and a counter 202.

[0087] In this embodiment, the replica circuit 102 controls the signal DQ. <0> ~DQ <7> The case where the replica circuit 102 includes one set of oscillators 201 and counters 202 corresponding to one of the time values ​​tDQS2DQ is described below. Note that the replica circuit 102 may include multiple sets of oscillators 201 and counters 202 corresponding to multiple signals DQ.

[0088] If the replica circuit 102 includes one pair of oscillator 201 and counter 202, the pair of oscillator 201 and counter 202 may correspond to the signal DQ input to the comparator 154 with the longest wiring length (largest wiring delay) between the comparator 151 of the input receiver 141 and the comparator 154 of the latch circuit 143. Alternatively, the pair of oscillator 201 and counter 202 may correspond to the signal DQ input to the comparator 154 with the average wiring length, or to the signal DQ input to the comparator 154 with the shortest wiring length. That is, the pair of oscillator 201 and counter 202 may correspond to the signal DQ with the longest time tDQS2DQ, or to the signal DQ with the average time tDQS2DQ, or to the signal DQ with the shortest time tDQS2DQ.

[0089] Oscillator 201 is a feedback-type oscillator circuit. Oscillator 201 outputs a signal OSC, which is a clock signal. Oscillator 201 includes comparator 203 and drivers 204 and 205.

[0090] Comparator 203 has a configuration similar to, for example, comparator 151 of input receiver 141. The output terminal of comparator 203 is connected to the first input terminal and the second input terminal of comparator 203. That is, the output signal is fed back. Comparator 203 inverts the logic level of the signal input to the first input terminal and outputs it. As a result, the output signal of oscillator 201 oscillates. For example, when a "L" level signal (the output signal of comparator 203) is input to the first input terminal of comparator 203, it outputs a "H" level signal.

[0091] The wiring path (feedback path) connecting the output terminal of comparator 203 to the first input terminal and the second input terminal has the same configuration and wiring length as the wiring path connecting the output terminal of comparator 151 of input receiver 141 and the clock signal input terminal of comparator 154 of latch circuit 143, as explained using Figure 5. For example, drivers 204 and 205 are provided in the wiring path connecting the output terminal of comparator 203 to the first input terminal and the second input terminal, similar to the input circuit 131. For example, driver 204 is a CML circuit with the same configuration as driver 152. For example, driver 205 is a C2C circuit with the same configuration as driver 153. In the wiring path connecting the output terminal of comparator 203 to the first input terminal and the second input terminal, a wiring delay of time tDQS2DQ occurs, similar to the input circuit 131. Therefore, the logic level of the output signal of comparator 203 is inverted every time tDQS2DQ. Therefore, the time for one cycle (one period) of the signal OSC is twice the time tDQS2DQ, i.e., 2 × (tDQS2DQ).

[0092] The signal OSC output from oscillator 201 is input to counter 202. Counter 202 counts the number of cycles of signal OSC. Counter 202 outputs a count value CNT as the count result. For example, the count value CNT may be a 16-bit signal. In this case, counter 202 outputs a 16-bit count value CNT<15:0>. The replica circuit 102 sends the count value CNT<15:0> to the status register 106. The number of bits in the count value CNT is arbitrary.

[0093] 1.1.5.2 Counter Configuration Next, an example of the configuration of counter 202 will be described with reference to Figure 8. Figure 8 is a circuit diagram showing an example of the configuration of counter 202.

[0094] As shown in Figure 8, the counter 202 of this embodiment counts up the cycle count at the falling edge of the OSC signal, that is, at the timing when it transitions from the "H" level to the "L" level. The counter 202 then outputs the result of adding +1 to the cycle count as the count value CNT<15:0>.

[0095] The counter 202 includes an inverter 211, an AND gate 212, a number of flip-flops 213, and an adder 214. For example, if the count value CNT is a 16-bit signal, the counter 202 includes 16 flip-flops 213. (The following describes the count value CNT.) <0> ~CNT <15> When specifying which flip-flops 213 correspond to each of these, they are denoted as flip-flops 213_0 to 213_15.

[0096] Inverter 211 inverts the signal OSC and outputs it. The input terminal of inverter 211 is connected to oscillator 201. The signal OSC is input to the input terminal of inverter 211. The output terminal of inverter 211 is connected to the first input terminal of AND circuit 212.

[0097] The second input terminal of the AND circuit 212 receives the enable signal EN. The enable signal EN is the enable signal for oscillator 201 and counter 202. For example, while the enable signal EN is at the "H" level, oscillator 201 outputs the signal OSC. Also, counter 202 performs counting operations. The enable signal EN is supplied, for example, from sequencer 107. The output terminal of the AND circuit 212 is connected to the clock signal input terminal of flip-flop 213_0. The AND circuit 212 outputs the result of a logical AND operation between the inverted signal of signal OSC and the enable signal EN as the signal OSC_CLK. When the enable signal EN is at the "H" level, the signal OSC_CLK is the inverted clock signal of signal OSC. For example, when the enable signal EN is at the "H" level and the inverted signal of signal OSC is at the "H" level (i.e., signal OSC is at the "L" level), the signal OSC_CLK is at the "H" level.

[0098] Flip-flop 213 is a D flip-flop, with multiple units provided corresponding to the number of bits in the count value CNT. Flip-flop 213 includes a clock signal input terminal, a data input terminal D, a reset signal input terminal R, an output terminal Q, and an inverting output terminal Qn.

[0099] Flip-flop 213 captures (stores) data input from data input terminal D at the rising edge of the clock signal input to the clock signal input terminal, i.e., at the timing when it transitions from "L" level to "H" level. This updates the output data. The data input terminal D of flip-flop 213 is connected to the inverting output terminal Qn of the flip-flop 213. Therefore, flip-flop 213 inverts the signals output from output terminal Q and inverting output terminal Qn at the rising edge of the clock signal input to the clock signal input terminal. A reset signal RST is input to the reset signal input terminal R of flip-flop 213. When an "H" level reset signal RST is input to the reset signal input terminal R, flip-flop 213 is reset. That is, an "L" level signal is output from output terminal Q of flip-flop 213, and an "H" level signal is output from inverting output terminal Qn. The reset signal RST is supplied, for example, from sequencer 107.

[0100] Flip-flops 213_0 to 213_15 are connected in multiple stages. More specifically, the OSC_CLK signal is input to the clock signal input terminal of flip-flop 213_0. The inverted data of the output from the output terminal Q of the preceding flip-flop 213 is input to the clock signal input terminals of flip-flops 213_1 to 213_15. For example, flip-flop 213 is denoted as flip-flop 213_k using the variable k (where k is an integer between 1 and 15). In this case, the inverted data of the output from the output terminal Q of the preceding flip-flop 213_(k-1) is input to the clock signal input terminal of flip-flop 213_k.

[0101] For example, the signal output from the output terminal Q of flip-flop 213 is denoted as signal preCNT. The signal preCNT is output from the output terminal Q of flip-flops 213_0 to 213_15. <0> ~preCNT <15> The following are output. Signal preCNT <0> ~preCNT <15> This indicates the number of cycles of the OSC signal.

[0102] The adder 214 is connected to the output terminal Q of each flip-flop 213. The adder 214 receives the signal preCNT <0> ~preCNT <15> The result of adding +1 to the 16-bit data represented by the 16-bit count value CNT is obtained. <0> ~CNT <15> It outputs as follows: In other words, adder 214 adds +1 to the number of cycles of signal OSC counted on the falling edge.

[0103] 1.1.6 Specific Example of Assigning the Count Value CNT in the Status Register Next, with reference to Figure 9, a specific example of the allocation of the count value CNT in the status register 106 will be explained. Figure 9 is a table showing a specific example of the address information for the count value CNT<15:0> in the status register 106.

[0104] As shown in Figure 9, for example, the 16-bit count value CNT<15:0> is stored in the registers corresponding to addresses "Bx" and "By" in the status register 106. More specifically, the register corresponding to address "Bx" stores the signal DQ. <0> ~DQ <7> Corresponding to the count value CNT <0> ~CNT <7> This is stored. And the register corresponding to address "By" contains the signal DQ. <0> ~DQ <7> Corresponding to the count value CNT <8> ~CNT <15> This is stored. Note that the register in which the count value CNT<15:0> is stored can be set as appropriate.

[0105] For example, the memory controller 20 performs an operation to read status information STS from the status register 106 to the target memory chip 11 (hereinafter referred to as the "get feature operation"). The memory controller 20 sends a command set to perform the get feature operation and reads the status information STS, which includes the count value CNT<15:0>.

[0106] 1.2 Count operation Next, we will explain the counting operation of the signal OSC in the replica circuit 102.

[0107] 1.2.1 Command Sequence for Counting Operation First, an example of a command sequence for counting operation will be explained with reference to Figure 10. Figure 10 is a diagram showing an example of a command sequence for counting operation. Note that in the example in Figure 10, the signals DQS and bDQS, the chip enable signal bCE, the read enable signals RE and bRE, and the ready / busy signal bRB are omitted.

[0108] As shown in Figure 10, the counting operation of the signal OSC in the replica circuit 102 is performed based on a command set corresponding to the counting operation transmitted from the memory controller 20. The command set is a combination of commands, addresses, and data corresponding to the operation performed by the memory chip 11.

[0109] During the period from time t100 to t110, the memory controller 20 first sends the command "CMD" to the memory chip 11 and asserts the command latch enable signal CLE by setting it to "H" level. The command "CMD" sent here is a command that instructs the execution of a count operation. The memory chip 11 receives the command "CMD" in accordance with the toggle of the write enable signal bWE.

[0110] Next, the memory controller 20 sends the address "LUN" to the memory chip 11 and asserts the address latch enable signal ALE by setting it to "H" level. The address "LUN" is the address information of the memory chip 11 that is the target of the count operation. The memory chip 11 receives the address "LUN" in accordance with the toggle of the write enable signal bWE.

[0111] Next, the memory controller 20 sends the address "xxh" to the memory chip 11 and asserts the address latch enable signal ALE by setting it to "H" level. The address "xxh" is information (recipe) indicating whether the memory chip 11 to be counted is a single memory chip 11 or all memory chips 11 connected to one channel CH of the memory interface circuit 27 are targeted. For example, if the address "xxh" is "00h", one memory chip 11 is targeted. If the address "xxh" is "01h", all memory chips 11 connected to one channel CH are targeted. The memory chip 11 receives the address "xxh" in accordance with the toggle of the write enable signal bWE. Note that the example in Figure 10 shows the case where "xxh" is an address, but it is not limited to this. "xxh" may also be a command. In this case, the command latch enable signal is set to "H" level and the address latch enable signal ALE is set to "L" level.

[0112] When the sequencer 107 receives the address "xxh", it sends a high-level signal OSC_ST to the replica circuit 102 during the period from time t110 to t120. The OSC_ST signal is an internal signal that notifies the replica circuit 102 (counter 202) to execute a counting operation. After sending one pulse of the OSC_ST signal, the sequencer 107 sets the OSC_ST signal to a low level.

[0113] Next, the sequencer 107 sends a "H" level reset signal RST to the replica circuit 102. Upon receiving the "H" level reset signal RST, each flip-flop 213 of the counter 202 is reset. That is, the flip-flop 213 outputs a "L" level signal from output terminal Q and a "H" level signal from inverting output terminal Qn. After sending the one-pulse reset signal RST, the sequencer 107 sets the reset signal RST to "L" level.

[0114] Next, at time t120, the memory controller 20 transmits the address "00h" to the memory chip 11 and asserts the address latch enable signal ALE by setting it to "H" level. The address "00h," which is transmitted after the address "xxh," is information that instructs the start of the count operation. The memory chip 11 receives the address "00h" in accordance with the toggle of the write enable signal bWE. Note that the example in Figure 10 shows the case where "00h" is an address, but it is not limited to this. "00h" may also be a command.

[0115] When the sequencer 107 receives address "00h", it sends an "H" level enable signal EN to the replica circuit 102 at time t130. When the oscillator 201 receives the "H" level enable signal EN, it starts oscillating the signal OSC. During the period from time t130 to t150, i.e., while the enable signal EN is at the "H" level, the AND circuit 212 outputs the signal OSC_CLK, which is the inverted signal OSC. The counter 202 counts up in accordance with the rising edge of the signal OSC_CLK. In other words, the counter 202 counts up in accordance with the falling edge of the signal OSC. The counter 202 outputs the count value CNT<15:0>, which is the result of the count-up plus 1.

[0116] Next, the memory controller 20 transmits the address "00h" to instruct the start of the count operation, and after a predetermined execution time (hereinafter referred to as "count execution time tRuntime") has elapsed, at time t140, it transmits the address "00h" again to the memory chip 11 and asserts the address latch enable signal ALE to the "H" level. Here, the address "00h" is information instructing the end of the count operation. The memory chip 11 receives the address "00h" in accordance with the toggle of the write enable signal bWE. In other words, the count execution time tRuntime is the interval between the toggle of the write enable signal bWE corresponding to the address "00h" instructing the start of the count operation and the toggle of the write enable signal bWE corresponding to the address "00h" instructing the end of the count operation. Note that the example in Figure 10 shows the case where "00h" is an address, but it is not limited to this. "00h" may also be a command. Furthermore, the address that signals the start of the counting operation and the address that signals the end of the counting operation may be different.

[0117] When the sequencer 107 receives address "00h", it sets the enable signal EN to "L" level at time t150. When the oscillator 201 receives the enable signal EN at "L" level, it stops oscillating the signal OSC. When the enable signal EN is set to "L" level in the counter 202, the AND gate 212 outputs the signal OSC_CLK at "L" level. As a result, the counter 202 terminates its counting operation.

[0118] 1.2.2 Specific Examples of Count Values Next, specific examples of the count value CNT will be described with reference to Figures 11 and 12. Figure 11 shows a comparative example of the counting operation. Figure 12 shows a specific example of the count value CNT in the counting operation by the counter 202 of this embodiment.

[0119] In the following explanation, the count value CNT, which is predetermined in the specifications, will be referred to as the "CNT specification value." The CNT specification value is set based on the number of cycles of the OSC signal during the count execution time tRuntime. Therefore, the CNT specification value is a value that is counted up based on the rising edge (start position of one cycle) of the OSC signal. In the following explanation, the CNT specification value and the count value CNT will be described using decimal numbers.

[0120] First, let's explain the comparative example. As a comparative example, we will explain the case where the count value CNT is counted up on the rising edge of the OSC signal, similar to the CNT specification value. In this case, counter 202 counts up the number of cycles (count) on the rising edge of the OSC signal and outputs the counted value as is, as the count value CNT.

[0121] As shown in Figure 11, in the comparative example, when oscillator 201 starts oscillating (outputting) the signal OSC, counter 202 starts counting up the count value CNT at the rising edge of the signal OSC. Therefore, the count value CNT represents the number of cycles of the signal OSC, similar to the CNT specification value. In this case, counter 202 outputs the count value CNT "1" at the start position of the signal OSC oscillation ("Start" in Figure 11). Counter 202 counts up the count value CNT for each cycle of the signal OSC. Oscillator 201 stops oscillating the signal OSC after the count execution time tRuntime has elapsed. The end position of the signal OSC oscillation ("Stop" in Figure 11) varies with respect to the waveform of the signal OSC.

[0122] For example, if the CNT specification value is "N" (where N is an integer greater than or equal to 1), the period during which the count value CNT is also "N" is the period from when the count value CNT is counted up to "N" until just before it is counted up to "N+1". For example, if the end position of the oscillation of the signal OSC is just before the count value CNT is counted up to "N+1", the error in the end position of the signal OSC relative to the CNT specification value "N" (hereinafter also referred to as the granularity error) is at most equivalent to approximately one cycle of the signal OSC. In other words, the granularity error in the replica circuit 102 is at most one cycle of the signal OSC. One cycle of the signal OSC is 2 × (tDQS2DQ). Therefore, the maximum value of the granularity error that occurs during the count execution time tRuntime can be expressed as 2 × (tDQS2DQ) / tRuntime.

[0123] Next, the counting operation of this embodiment will be described.

[0124] As shown in Figure 12, counter 202 counts up the cycle count on the falling edge of the signal OSC and outputs the result of adding +1 to the counted value as the count value CNT. Therefore, the timing at which the CNT specification value counts up is different from the timing at which the count value CNT counts up. Counter 202 counts up the count value CNT to N on the falling edge of the N-1th cycle of the signal OSC. That is, counter 202 counts up the count value CNT to N after 0.5 cycles have elapsed since the N-1th cycle. In other words, the count value CNT is counted up 0.5 cycles earlier than the CNT specification value (number of cycles of the signal OSC). For this reason, the period during which the count value CNT is "N" is from the falling edge of the N-1th cycle of the signal OSC to the falling edge of the Nth cycle. Therefore, the granularity error of the signal OSC's end position relative to the CNT specification value "N" is reduced to a maximum of approximately 0.5 cycles of the signal OSC. The maximum granularity error that occurs during the count execution time tRuntime can be expressed as tDQS2DQ / tRuntime.

[0125] 1.2.3 Counting Operation Flow Next, we will explain an example of the counting operation flow with reference to Figure 13. Figure 13 is a flowchart of an example of the counting operation flow.

[0126] As shown in Figure 13, first, the CPU 22 of the memory controller 20 issues a command set instructing the memory chip 11 to perform a counting operation (S1). The CPU 22 sends the command set to the memory chip 11. For example, the memory controller 20 causes the memory chip 11 to perform a counting operation periodically. The memory system 1 may also have a mechanism to monitor changes in voltage or temperature at the memory chip 11. For example, the CPU 22 may determine whether or not to perform a counting operation based on the monitoring results of voltage or temperature at the memory chip 11.

[0127] When the sequencer 107 of the memory chip 11 receives a command set for counting, it starts the counting operation in the replica circuit 102 (S2). More specifically, as explained with reference to Figure 10, during the period from time t100 to t110, the sequencer 107 receives the command "CMD", address "LUN", and address "xxh" from the memory controller 20. During the period from time t110 to t120, the sequencer 107 transmits a single-pulse signal OSC_ST and a reset signal RST.

[0128] Oscillator 201 begins outputting the signal OSC (S3). More specifically, at time t120 as described in Figure 10, sequencer 107 receives address "00h" from memory controller 20 to instruct it to start. At time t130 as described in Figure 10, sequencer 107 sets the enable signal EN to "H" level. Based on the "H" level enable signal EN, oscillator 201 begins outputting the signal OSC.

[0129] Counter 202 counts up the number of cycles of signal OSC on the falling edge of signal OSC during the period from time t130 to t150 as explained using Figure 10 (S4).

[0130] Counter 202 outputs the count value CNT as the cycle count plus 1 (S5). The count value CNT is stored in status register 106.

[0131] When the counting operation is complete, the CPU 22 reads the count value CNT from the memory chip 11 (S6). For example, the CPU 22 issues a command set for the get feature operation and reads the count value CNT from the status register 106 of the memory chip 11.

[0132] The CPU 22 calculates the difference between the read count value CNT and the count value CNT from the previous counting operation (S7). For example, the count value from the previous counting operation is stored in RAM 24.

[0133] CPU22 checks if the absolute value of the difference is greater than a pre-set threshold (S8).

[0134] If the absolute value of the difference is greater than a preset threshold (S8_Yes), the CPU 22 performs write training (S9). That is, the sequencer 107 of the memory chip 11 performs write training based on the instructions of the CPU 22.

[0135] On the other hand, if the absolute value of the difference is less than or equal to a preset threshold (S8_No), CPU22 terminates the counting operation.

[0136] 1.3 Effects according to this embodiment With the configuration according to this embodiment, the processing power of the semiconductor device can be improved. This effect will be described in detail below.

[0137] For example, when signals DQ, DQS, and bDQS are received asynchronously by the memory chip 11, the time tDQS2DQ is larger compared to when signals DQ, DQS, and bDQS are received synchronously. The optimal value of time tDQS2DQ changes due to fluctuations in voltage or temperature in the memory chip 11. For this reason, the memory controller 20 periodically performs write training to adjust the timing of transmitting signals DQ, DQS, and bDQS. However, the execution time of write training is relatively long. Also, write and read operations cannot be performed while write training is in progress. Therefore, if the frequency of write training increases, the processing capacity of the memory chip 11 decreases.

[0138] In contrast, in the configuration according to this embodiment, the memory chip 11 (semiconductor device) has a replica circuit 102 that includes an oscillator 201 that outputs a signal OSC and a counter 202 that counts the number of cycles of the signal OSC. The memory chip 11 can perform counting operations in the replica circuit 102 based on the control of the memory controller 20. The memory controller 20 can determine whether or not to perform write training based on the result of the counting operation. Therefore, the timing of performing write training can be optimized, and the processing capacity of the memory chip 11 can be improved.

[0139] Furthermore, with the configuration according to this embodiment, the counter 202 can count up 0.5 cycles faster than the number of cycles of the signal OSC. Therefore, the granularity error of the count value CNT relative to the count execution time tRuntime can be reduced to half compared to the case where the count is increased in accordance with the number of cycles of the signal OSC. Consequently, with the configuration according to this embodiment, the same level of counting accuracy as when the count is increased in accordance with the number of cycles of the signal OSC can be achieved with half the count execution time tRuntime. Thus, the processing power of the memory chip 11 can be improved.

[0140] Furthermore, with the configuration according to this embodiment, the particle size error can be reduced by half, thereby improving the accuracy of the counting operation.

[0141] 1.4 Modifications of the First Embodiment Next, a modified version of the first embodiment will be described. In this modified version, the method of sending commands and addresses will differ from that of the first embodiment. The following description will focus on the differences from the first embodiment.

[0142] 1.4.1 Memory Chip Configuration First, an example of the configuration of the memory chip 11 will be described with reference to Figure 14. Figure 14 is a block diagram showing an example of the configuration of the memory chip 11 (semiconductor device). In the example in Figure 14, some of the connections between each component are shown by arrow lines, but the connections between each component are not limited to these.

[0143] The memory chip 11 in this example has two modes for inputting and outputting data and information with the memory controller 20.

[0144] The first mode is a mode in which the signal DQ is used for input and output of data DAT, but not for input of command CMD and address ADD, or output of status information STS. The protocol of the first mode is also referred to as the "SCA (Separate Command Address input) protocol". In the first mode, the logic control circuit 103 performs the input of command CMD and address ADD, and the output of status information STS. In the first mode, the logic control circuit 103 may also output a ready / busy signal bRB. In this case, the ready / busy circuit 108 is connected to the logic control circuit 103.

[0145] The second mode is the mode described in the first embodiment in which the signal DQ is used for input and output of data DAT, input of command CMD and address ADD, and output of status information STS. The second mode is the same as in the first embodiment, so its description is omitted.

[0146] As shown in Figure 14, the memory chip (NAND flash memory) 11 in this example includes an input / output circuit 101, a replica circuit 102, a logic control circuit 103, an address register 104, a command register 105, a status register 106, a sequencer 107, a ready / busy circuit 108, a voltage generation circuit 109, a memory cell array 120, a row decoder 121, a sense amplifier 122, a data register 123, and a column decoder 124, similar to Figure 2 of the first embodiment. The configuration of the replica circuit 102, address register 104, command register 105, status register 106, sequencer 107, ready / busy circuit 108, voltage generation circuit 109, memory cell array 120, row decoder 121, sense amplifier 122, data register 123, and column decoder 124 is the same as in the first embodiment.

[0147] When the first mode is selected, the input / output circuit 101 receives the command CMD and address ADD from the logic control circuit 103. The input / output circuit 101 also sends status information STS to the logic control circuit 103.

[0148] The logic control circuit 103 receives signals CA_bCE, CA_CLK, read enable signals RE and bRE, and signal SCA from the memory controller 20. The logic control circuit 103 also sends and receives signals CA1 and CA0 to and from the memory controller 20.

[0149] The signal CA_bCE corresponds to the chip enable signal bCE described in the first embodiment. The signal CA_bCE is asserted, for example, at a Low ("L") level.

[0150] Signals CA0 and CA1, in the first mode, are signals indicating command, address, or status information STS. In the second mode, the command latch enable signal CLE is input to the input terminal of signal CA1, and the address latch enable signal ALE is input to the input terminal of signal CA0.

[0151] In the first mode, the signal CA_CLK is the strobe signal of signals CA0 and CA1. For example, when the command CMD or address ADD is input, the logic control circuit 103 captures signals CA0 and CA1 on the rising and falling edges of signal CA_CLK. Also, when the status information STS is output, the logic control circuit 103 outputs signals CA0 and CA1 based on signal CA_CLK. In the second mode, the write enable signal bWE is input to the terminal corresponding to signal CA_CLK.

[0152] In the first mode, the read enable signals RE and bRE are used for the output of signal DQ, but not for the output of status information STS.

[0153] The SCA signal is a control signal for mode switching. For example, when the SCA signal is at an "H" level, the first mode is selected, and when the SCA signal is at an "L" level, the second mode is selected.

[0154] 1.4.2 Command Sequence for Command and Address Input in Mode 1 Next, an example of a command sequence for command and address input in the first mode will be described with reference to Figure 15. Figure 15 is a diagram showing an example of a command sequence for command and address input in the first mode. Note that in the example in Figure 15, signals DQ, DQS and bDQS, read enable signals RE and bRE, and ready / busy signal bRB are omitted.

[0155] As shown in Figure 15, in the first mode, the combination of 6-bit signal CA0 and 6-bit signal CA1 indicates the type of information and 8 bits of information. Hereafter, the combination of signal CA0 and signal CA1 will be referred to as a "frame". The type of information indicates, for example, whether it is a command CMD, an address ADD, or status information STS.

[0156] A frame consists of a combination of a header set that indicates the type of information and a body set that indicates the content of the information.

[0157] The header set is a 4-bit set (each bit is referred to as a "header") consisting of the first 2 bits of signal CA0 and the first 2 bits of signal CA1. In both signal CA0 and signal CA1, the first bit in the header set is referred to as the first header, and the second bit in the header set is referred to as the second header.

[0158] The body set is an 8-bit set (each bit is referred to as a "body") consisting of the last 4 bits of signal CA0 and the last 4 bits of signal CA1. In both signal CA0 and signal CA1, the first bit in the body set is referred to as the first body. The second bit in the body set is referred to as the second body. The third bit in the body set is referred to as the third body. The fourth bit in the body set is referred to as the fourth body. For example, the first body of signal CA0 corresponds to signal DQ in the second mode. <0> Corresponding to this, the first body of signal CA1 corresponds to signal DQ in the second mode. <1> This corresponds to the second body of signal CA0, which corresponds to signal DQ in the second mode. <2> Corresponding to this, the second body of signal CA1 is signal DQ in the second mode. <3> Corresponds to the third body of signal CA0, which corresponds to signal DQ in the second mode. <4> Corresponding to this, the third body of signal CA1 is signal DQ in the second mode. <5> Corresponds to the fourth body of signal CA0, which corresponds to signal DQ in the second mode. <6> Corresponding to this, the fourth body of signal CA1 is signal DQ in the second mode. <7> It corresponds to.

[0159] When the memory controller 20 selects the first mode, it sets the signal CA_bCE to "L" level and the signal SCA to "H" level. As a result, the first mode is selected in the target memory chip 11.

[0160] First, the memory controller 20 sends a first header of signals CA0 and CA1 to the memory chip 11. The memory chip 11 captures the first header in accordance with the rising edge of signal CA_CLK at time t0.

[0161] Next, the memory controller 20 sends a second header containing signals CA0 and CA1 to the memory chip 11. The memory chip 11 captures the second header in accordance with the falling edge of signal CA_CLK at time t1.

[0162] Next, the memory controller 20 transmits the first bodies of signals CA0 and CA1 to the memory chip 11. The memory chip 11 captures the first bodies in accordance with the rising edge of signal CA_CLK at time t2.

[0163] Next, the memory controller 20 transmits the second bodies of signals CA0 and CA1 to the memory chip 11. The memory chip 11 captures the second bodies in accordance with the falling edge of signal CA_CLK at time t3.

[0164] Next, the memory controller 20 transmits the third bodies of signals CA0 and CA1 to the memory chip 11. The memory chip 11 captures the third bodies in accordance with the rising edge of signal CA_CLK at time t4.

[0165] Next, the memory controller 20 transmits the fourth bodies of signals CA0 and CA1 to the memory chip 11. The memory chip 11 captures the fourth bodies in accordance with the falling edge of signal CA_CLK at time t5.

[0166] For example, when the transmission of a frame is finished, the memory controller 20 sets the signal CA_bCE to "H" level and the signal SCA to "L" level.

[0167] As explained above, when the first mode is selected, the signals DQ, DQS, and bDQS, as well as RE and bRE, are not used for the input of the command CMD and address ADD. Therefore, the input of the command CMD and address ADD can be performed in parallel with the input and output of data DAT using signals DQ, DQS, and bDQS. The memory controller 20 can instruct the memory chip 11 to perform a count operation without using signals DQ, DQS, and bDQS.

[0168] 1.4.3 Command Sequence for Get Feature Operation in Mode 1 Next, with reference to Figure 16, the command sequence for the Get Feature operation in the first mode will be described. Figure 16 shows an example of the command sequence for the Get Feature operation in the first mode. Note that in the example in Figure 16, signals DQ, DQS and bDQS, CA_bCE, SCA, read-enable signals RE and bRE, and ready / busy signal bRB are omitted.

[0169] As shown in Figure 16, first, at times t10 to t15, the input operation for the frame corresponding to the command CMD that instructs the execution of the get feature operation is performed. The interval between each time point from t10 to t21 is denoted as "tCLK1".

[0170] More specifically, at time t10, a first header is input, for example, a signal CA0 indicating "0" and a signal CA1 indicating "0".

[0171] Next, at time t11, a second header is input, for example, signal CA0 indicating "1" and signal CA1 indicating "1". For example, a header set of "0", "0", "1", "1" indicates that the next input body set is the command CMD.

[0172] Next, between times t12 and t15, the body set of command CMD is input. More specifically, at time t12, signals CA0 and CA1, which indicate the first body, are input. Next, at time t13, signals CA0 and CA1, which indicate the second body, are input. Next, at time t14, signals CA0 and CA1, which indicate the third body, are input. Next, at time t15, signals CA0 and CA1, which indicate the fourth body, are input.

[0173] Next, between times t16 and t21, the input operation for the frame corresponding to address ADD in status register 106 is performed.

[0174] More specifically, first, at time t16, a signal CA0 indicating "0" and a signal CA1 indicating "0" are input as the first header.

[0175] Next, at time t17, a second header is input, for example, a signal CA0 indicating "0" and a signal CA1 indicating "1". For example, a header set of "0", "0", "0", "1" indicates that the next input body set is address ADD.

[0176] Next, between times t18 and t21, the body set for address ADD is input. More specifically, at time t18, signals CA0 and CA1, indicating the first body, are input. Then, at time t19, signals CA0 and CA1, indicating the second body, are input. Then, at time t20, signals CA0 and CA1, indicating the third body, are input. Then, at time t21, signals CA0 and CA1, indicating the fourth body, are input.

[0177] At time t21, once the input of address ADD is complete, the sequencer 107 sets the ready / busy signal bRB to "L" level and begins reading status information STS (e.g., count value CNT) from the target address in the status register 106 to the logic control circuit 103. The reading operation is performed during the period tFEAT in which the ready / busy signal bRB is at "L" level, and the read status information STS is stored in a register (not shown) of the logic control circuit 103. Once the reading operation is complete, the sequencer 107 sets the ready / busy signal bRB to "H" level.

[0178] When the memory controller 20 receives a ready / busy signal bRB at the "H" level, it sends a header set to the memory chip 11 instructing it to output status information STS (DOUT).

[0179] More specifically, first, at time t22, the first header consists of, for example, a signal CA0 indicating "0" and a signal CA1 indicating "0".

[0180] Next, at time t22, a second header is input, for example, a signal CA0 indicating "0" and a signal CA1 indicating "0". For example, the header set "0", "0", "0", "0" is a header set that instructs the logic control circuit 103 to output status information STS.

[0181] After this header set is input and a predetermined waiting time (period tW2R) has elapsed, the memory controller 20 sends the signal CA_CLK to the memory chip 11 to specify the timing for outputting status information STS. More specifically, at time t24, the memory controller 20 sends the "H" level signal CA_CLK to the memory chip 11. Also, at time t25, the memory controller 20 sends the "L" level signal CA_CLK to the memory chip 11. From time t25 onward, the memory controller 20 repeatedly toggles the signal CA_CLK (switching between "L" level and "H" level). For example, the interval between the toggling of the signal CA_CLK in the output operation of status information STS (the interval between the rising and falling edges of the signal CA_CLK) is defined as period tCLK2. Period tCLK2 may be shorter than period tCLK1.

[0182] Based on the signal CA_CLK, the output operation of the status information STS is performed. The logic control circuit 103 outputs the signal CA1 as the status information STS. The logic control circuit 103 also outputs the signal CA0 as the strobe signal of signal CA1. The logic control circuit 103 generates the signal CA0 based on the signal CA_CLK. Therefore, the toggle interval of signal CA0 is the same as that of signal CA_CLK, which is the period tCLK2.

[0183] The status information STS is output as signal CA1 in sync with the rising and falling edges of signal CA0. Therefore, the 8-bit body set of signal CA1 corresponds to the 8-bit data output of the status information STS. Signal CA1 is output in sync with the rising or falling edge of signal CA0. Therefore, even if signal CA1 outputs consecutive "0"s or consecutive "1"s, it is possible to determine the data boundaries.

[0184] When the status information STS is output, for example, as shown in Figure 16, a header set instructing the output of data may be input once, and then multiple body sets constituting the status information STS may be output sequentially. In other words, the input of a header set may be omitted until the output of the status information STS is completed.

[0185] 1.4.4 Command Sequence for Counting Operation Next, an example of a command sequence for counting operation will be described with reference to Figure 17. Figure 17 shows an example of a command sequence for counting operation in the first mode. Note that in the example in Figure 17, signals DQ, DQS and bDQS, signal CA_bCE, read-enable signals RE and bRE, and ready / busy signal bRB are omitted.

[0186] As shown in Figure 17, in this example, corresponding to the first mode, signals CA0, CA1, and CA_CLK are transmitted from the memory controller 20 to the memory chip 11. The internal signals generated within the memory chip 11 (signal OSC_ST, reset signal RST, enable signal EN, signal OSC, signal OSC_CLK, and count value CNT<15:0>) are the same as those in Figure 10 of the first embodiment.

[0187] More specifically, during the period from time t100 to t110, the memory controller 20 first sends a frame corresponding to the command "CMD" to the memory chip 11 as signals CA0 and CA1. The memory chip 11 captures signals CA0 and CA1 in accordance with the rising and falling edges of signal CA_CLK.

[0188] Next, the memory controller 20 sends a frame corresponding to address "LUN" to the memory chip 11 as signals CA0 and CA1. The memory chip 11 captures signals CA0 and CA1 in accordance with the rising and falling edges of signal CA_CLK.

[0189] Next, the memory controller 20 sends a frame corresponding to address "xxh" to the memory chip 11 as signals CA0 and CA1. The memory chip 11 captures signals CA0 and CA1 in accordance with the rising and falling edges of signal CA_CLK. Note that "xxh" may also be a command.

[0190] When the sequencer 107 receives the address "xxh", it sends a high-level signal OSC_ST to the replica circuit 102 during the period from time t110 to t120. After sending the single-pulse signal OSC_ST, the sequencer 107 sets the signal OSC_ST to a low level.

[0191] Next, the sequencer 107 sends a reset signal RST at the "H" level to the replica circuit 102. Upon receiving the "H" level reset signal RST, each flip-flop 213 of the counter 202 is reset. After sending the one-pulse reset signal RST, the sequencer 107 sets the reset signal RST to the "L" level.

[0192] Next, at time t120, the memory controller 20 sends a frame corresponding to address "00h" to the memory chip 11 as signals CA0 and CA1. The memory chip 11 receives signals CA0 and CA1 in accordance with the rising and falling edges of signal CA_CLK. Note that "00h" may also be a command.

[0193] When the sequencer 107 receives address "00h", it sends an "H" level enable signal EN to the replica circuit 102 at time t130. When the oscillator 201 receives the "H" level enable signal EN, it starts oscillating (outputting) the signal OSC. During the period from time t130 to t150, i.e., while the enable signal EN is at the "H" level, the AND circuit 212 outputs the signal OSC_CLK, which is the inverted signal OSC. The counter 202 counts up in accordance with the rising edge of the signal OSC_CLK. In other words, the counter 202 counts up in accordance with the falling edge of the signal OSC. The counter 202 outputs the count value CNT<15:0>, which is the result of the count-up plus 1.

[0194] Next, the memory controller 20 transmits the address "00h" to instruct the start of the counting operation, and after the counting execution time tRuntime has elapsed, at time t140, transmits the frame corresponding to the address "00h" to the memory chip 11 as signals CA0 and CA1. The memory chip 11 captures signals CA0 and CA1 in accordance with the rising and falling edges of signal CA_CLK. Note that "00h" may also be a command. Furthermore, the address instructing the start of the counting operation and the address instructing the end of the counting operation may be different.

[0195] When the sequencer 107 receives address "00h", it sets the enable signal EN to "L" level at time t150. When the oscillator 201 receives the enable signal EN at "L" level, it stops oscillating the signal OSC. When the enable signal EN is set to "L" level, the counter 202 outputs the signal OSC_CLK at "L" level from the AND gate 212. In other words, the counter 202 terminates its counting operation.

[0196] 1.4.5 Effects of Modified Examples of the First Embodiment With the configuration according to this modified example, the same effects as in the first embodiment can be obtained.

[0197] Furthermore, with the configuration described in this modified example, the SCA protocol can be applied when commands and addresses are input to the memory chip 11. The SCA protocol does not use signals DQ, DQS, and bDQS, nor read-enable signals RE and bRE, for command and address input. Therefore, command and address input and data input / output can be executed in parallel. In other words, counting operations and data input / output operations can be executed in parallel. As a result, the memory chip 11 can suppress the reduction in processing power caused by counting operations.

[0198] 2. Second Embodiment Next, a second embodiment will be described. In the second embodiment, a counter 202 different from that of the first embodiment will be described. The following description will focus on the differences from the first embodiment.

[0199] 2.1 Counter Configuration First, let's refer to Figure 18 to explain an example of the configuration of counter 202. Figure 18 is a circuit diagram showing an example of the configuration of counter 202.

[0200] As shown in Figure 18, the counter 202 of this embodiment counts up the cycle count based on the rising edge of the signal OSC_ST and the falling edge of the signal OSC. The counter 202 then outputs the count result as the count value CNT<15:0>.

[0201] The counter 202 includes an inverter 211, an AND circuit 212, a plurality of flip-flops 213, a delay circuit 221, and an OR circuit 222. For example, the counter 202, similar to the first embodiment, has a count value CNT <0> ~CNT <15> Each of these includes the corresponding flip-flops 213_0 to 213_15.

[0202] The configuration of the inverter 211 and the AND circuit 212 is the same as the configuration of the counter 202 described using Figure 8 of the first embodiment. The output terminal of the AND circuit 212 is connected to the first input terminal of the OR circuit 222.

[0203] The delay circuit 221 is a circuit that delays the signal OSC_ST. The signal OSC_ST is input to the input terminal of the delay circuit 221. The output terminal of the delay circuit 221 is connected to the second input terminal of the OR circuit 222. The delay circuit 221 outputs the signal OSC_ST_DL, which is the delayed version of the signal OSC_ST.

[0204] The output terminal of OR circuit 222 is connected to the clock signal input terminal of flip-flop 213_0. OR circuit 222 outputs the result of a logical OR operation between the signal OSC_CLK and the signal OSC_ST_DL as the signal CNT_CLK. The signal CNT_CLK is at the "H" level if at least one of the signals OSC_CLK and OSC_ST_DL is at the "H" level.

[0205] The flip-flop 213 includes a clock signal input terminal, a data input terminal D, a reset signal input terminal R, an output terminal Q, and an inverting output terminal Qn.

[0206] The configuration of the flip-flop 213 is the same as in Figure 8 of the first embodiment. The signal CNT_CLK is input to the clock signal input terminal of the flip-flop 213_0.

[0207] In this embodiment, the signal output from the output terminal Q of the flip-flops 213_0 to 213_15 is a 16-bit count value CNT <0> ~CNT <15> It will be output as follows.

[0208] As described above, in the counter 202 of this embodiment, the count value CNT is output at the same timing as in the first embodiment.

[0209] 2.2 Command Sequence for Counting Operation Next, an example of a command sequence for counting operation will be described with reference to Figure 19. Figure 19 is a diagram showing an example of a command sequence for counting operation. Note that in the example in Figure 19, the signals DQS and bDQS, the chip enable signal bCE, the read enable signals RE and bRE, and the ready / busy signal bRB are omitted.

[0210] As shown in Figure 19, during the period from time t100 to t110, the memory controller 20 sequentially transmits the command "CMD", address "LUN", and address "xxh" to the memory chip 11, similar to the explanation using Figure 10 of the first embodiment.

[0211] When the sequencer 107 receives the address "xxh", it sends a high-level signal OSC_ST to the replica circuit 102 during the period from time t110 to t120. After sending the single-pulse signal OSC_ST, the sequencer 107 sets the signal OSC_ST to a low level.

[0212] Next, the sequencer 107 sends a reset signal RST at the "H" level to the replica circuit 102. Upon receiving the "H" level reset signal RST, each flip-flop 213 of the counter 202 is reset. After sending the one-pulse reset signal RST, the sequencer 107 sets the reset signal RST to the "L" level.

[0213] At time t111, counter 202 receives a reset signal RST at the "H" level, resets flip-flop 213, and then the delayed signal OSC_ST_DL rises to the "H" level. As a result, the signal CNT_CLK rises to the "H" level. Counter 202 counts up on the rising edge of signal CNT_CLK. Therefore, counter 202 increments the count value CNT by +1 in response to one pulse of signal OSC_ST before oscillator 201 starts oscillating signal OSC. That is, the count value CNT is set to "1".

[0214] Next, at time t120, the memory controller 20 transmits the address "00h" to the memory chip 11 to instruct it to start the counting operation, similar to the explanation using Figure 10 of the first embodiment.

[0215] When the sequencer 107 receives address "00h", it sends an "H" level enable signal EN to the replica circuit 102 at time t130. When the oscillator 201 receives the "H" level enable signal EN, it starts oscillating the signal OSC. During the period from time t130 to t150, i.e., while the enable signal EN is at the "H" level, the AND circuit 212 outputs the signal OSC_CLK, which is the inverted signal OSC. Then, the OR circuit 222 outputs the signal CNT_CLK, which is synchronized with the signal OSC_CLK. The counter 202 counts up in accordance with the rising edge of the signal CNT_CLK. That is, the counter 202 counts up in accordance with the falling edge of the signal OSC. At this time, the counter 202 counts up from a state where the count value CNT is "1".

[0216] Next, the memory controller 20, similar to the explanation using Figure 10 of the first embodiment, sends the address "00h" to instruct the start of the counting operation, and after the counting execution time tRuntime has elapsed, sends the address "00h" again to the memory chip 11 at time t140.

[0217] When the sequencer 107 receives address "00h", it sets the enable signal EN to "L" level at time t150. When the oscillator 201 receives the enable signal EN at "L" level, it stops oscillating the signal OSC. The counter 202 stops its counting operation.

[0218] 2.3 Counting Operation Flow Next, we will explain an example of the counting operation flow with reference to Figure 20. Figure 20 is a flowchart showing an example of the counting operation flow.

[0219] As shown in Figure 20, steps S1 and S2 are performed first. The operation of steps S1 and S2 is the same as described in Figure 13 of the first embodiment.

[0220] Counter 202 increments the count value CNT to 1 in response to one pulse of the signal OSC_ST (S21). More specifically, at time t111 as explained using Figure 19, the signal OSC_ST_DL, which is a delayed version of the signal OSC_ST, rises to a "H" level. As a result, the signal CNT_CLK rises to a "H" level. Counter 202 increments the count value to 1 on the rising edge of the signal CNT_CLK.

[0221] Next, steps S3 and S4 are performed. The operation of steps S3 and S4 is the same as described in Figure 13 of the first embodiment.

[0222] Next, steps S6 to S9 are executed. The operation of steps S6 to S9 is the same as described in Figure 13 of the first embodiment.

[0223] 2.4 Effects of this embodiment With the configuration according to this embodiment, the same effects as in the first embodiment can be obtained.

[0224] Furthermore, modifications of the first embodiment can be applied to this embodiment.

[0225] 3. Third Embodiment Next, a third embodiment will be described. In the third embodiment, a counter 202 that differs from that of the first and second embodiments will be described. The following description will focus on the differences from the first and second embodiments.

[0226] 3.1 Counter Configuration First, let's refer to Figure 21 to explain an example of the configuration of counter 202. Figure 21 is a circuit diagram showing an example of the configuration of counter 202.

[0227] As shown in Figure 21, the counter 202 of this embodiment counts up the cycle count based on the rising edge of the signal OSC. The counter 202 then outputs the result of adding 0 or +1 to the cycle count based on the result of an exclusive OR (exOR) operation between the 1 bit data corresponding to the rising edge of the signal OSC and the 1 bit data corresponding to the falling edge of the signal OSC, as the count value CNT<15:0>.

[0228] The counter 202 includes a number of flip-flops 213, an AND gate 231, an inverter 232, an AND gate 233, a flip-flop 234, an exOR gate 235, and a logic gate 236. For example, the counter 202, similar to the first embodiment, has a count value CNT <0> ~CNT <15> Each of these includes the corresponding flip-flops 213_0 to 213_15.

[0229] The signal OSC is input to the first input terminal of AND gate 231. The first input terminal of AND gate 231 is connected to oscillator 201. The enable signal EN is input to the second input terminal of AND gate 231. The output terminal of AND gate 231 is connected to the clock signal input terminal of flip-flop 213_0. AND gate 231 outputs the result of a logical AND operation between the signal OSC and the enable signal EN as the signal OSC_CLK_rise. The signal OSC_CLK_rise is a clock signal synchronized with the signal OSC when the enable signal EN is at the "H" level.

[0230] The flip-flop 213 includes a clock signal input terminal, a data input terminal D, a reset signal input terminal R, an output terminal Q, and an inverting output terminal Qn.

[0231] The configuration of flip-flop 213 is the same as in Figure 8 of the first embodiment. The signal OSC_CLK_rise is input to the clock signal input terminal of flip-flop 213_0. Flip-flop 213_0 captures data on the rising edge of the signal OSC_CLK_rise, i.e., the OSC signal. Therefore, flip-flops 213_0 to 213_15 count up on the rising edge of the OSC signal.

[0232] For example, the signal output from the output terminal Q of flip-flop 213 is denoted as signal CNT_rise. The signal CNT_rise is output from the output terminal Q of flip-flops 213_0 to 213_15. <0> ~CNT_rise <15> These will be output respectively.

[0233] Inverter 232 inverts the signal OSC and outputs it. The input terminal of inverter 232 is connected to oscillator 201. The signal OSC is input to the input terminal of inverter 232. The output terminal of inverter 232 is connected to the first input terminal of AND circuit 233.

[0234] The enable signal EN is input to the second input terminal of the AND circuit 233. The output terminal of the AND circuit 233 is connected to the clock signal input terminal of the flip-flop 234. The AND circuit 233 outputs the result of a logical AND operation between the inverted signal of signal OSC and the enable signal EN as the signal OSC_CLK_fall. The signal OSC_CLK_fall is the inverted clock signal of signal OSC when the enable signal EN is at the "H" level. For example, when the enable signal EN is at the "H" level and the inverted signal of signal OSC is at the "H" level (i.e., signal OSC is at the "L" level), the signal OSC_CLK_fall is at the "H" level.

[0235] The flip-flop 234 includes a clock signal input terminal, a data input terminal D, a reset signal input terminal R, an output terminal Q, and an inverting output terminal Qn.

[0236] The configuration of flip-flop 234 is the same as that of flip-flop 213. The signal OSC_CLK_fall is input to the clock signal input terminal of flip-flop 234. Flip-flop 234 captures data on the rising edge of the signal OSC_CLK_fall, i.e., the falling edge of the signal OSC. The data input terminal D of flip-flop 234 is connected to the inverting output terminal Qn of the flip-flop 234. Therefore, flip-flop 234 inverts the signals output from output terminal Q and inverting output terminal Qn on the rising edge of the signal OSC_CLK_fall input to the clock signal input terminal. The reset signal RST is input to the reset signal input terminal R of flip-flop 234.

[0237] For example, the signal output from the output terminal Q of flip-flop 234 is the signal CNT_fall <0> This is how it is written.

[0238] The first input terminal of the exOR circuit 235 is connected to the output terminal Q of the flip-flop 213_0. The signal CNT_rise is connected to the first input terminal of the exOR circuit 235. <0> The signal CNT_fall is input. The second input terminal of the exOR circuit 235 is connected to the output terminal Q of the flip-flop 234. <0> The following is input. The exOR circuit 235 receives the signal CNT_rise. <0> and signal CNT_fall <0> Outputs the result of an exclusive OR (exOR) operation between two signals. For example, the signal CNT_rise. <0> and signal CNT_fall <0> If both are at the "H" level ("1") or the "L" level ("0"), the output signal of the exOR circuit 235 is set to the "L" level (exOR=0). Also, the signal CNT_rise <0> and signal CNT_fall <0> If any one of the values ​​is at the "H" level ("1"), the output signal of the exOR circuit 235 is at the "H" level (exOR=1).

[0239] The logic circuit 236 is connected to the output terminal Q of each flip-flop 213 and the output terminal of the exOR circuit 235. The logic circuit 236 receives the signal CNT_rise <0> ~CNT_rise <15> The output signal of the exOR circuit 235 is input. Based on the output signal of the exOR circuit 235, the logic circuit 236 generates the signal CNT_rise. <0> ~CNT_rise <15> The result of adding 0 or +1 to the 16-bit data represented by the 16-bit data is given by a 16-bit count value CNT. <0> ~CNT <15> It outputs as follows. More specifically, if exOR=0, the logic circuit 236 outputs the signal CNT_rise. <0> ~CNT_rise <15> The result of adding +1 to the 16-bit data represented by the count value CNT is obtained. <0> ~CNT <15> It outputs as follows. On the other hand, if exOR=1, the logic circuit 236 outputs the signal CNT_rise. <0> ~CNT_rise <15> The 16-bit data represented by the count value CNT <0> ~CNT <15> Output as follows.

[0240] 3.2 Specific Examples of Count Values Next, we will explain a specific example of the count value CNT with reference to Figure 22. Figure 22 is a diagram showing specific examples of each signal in counter 202. In the example in Figure 22, for the sake of simplicity, the CNT specification value, the signal CNT_rise<15:0>, and the count value CNT are expressed in decimal.

[0241] As shown in Figure 22, at time t200, when oscillator 201 starts oscillating the signal OSC, the CNT specification value counts up to "1" on the rising edge of the signal OSC. Signal CNT_rise <0> This inverts the signal OSC to a "H" level at its rising edge and outputs "1". (Signal CNT_fall) <0> Since the value is "0" ("L" level), the exOR circuit 235 outputs "1" ("H" level). Therefore, the logic circuit 236 does not add to the signal CNT_rise<15:0>. Since the signal CNT_rise<15:0> is "1", the counter 202 outputs "1" as the count value CNT.

[0242] Next, at time t201, the signal CNT_fall <0> This inverts to a "H" level at the falling edge of the OSC signal and outputs "1". (Signal CNT_rise) <0> and signal CNT_fall <0> Since both are "1", the exOR circuit 235 outputs "0". Therefore, the logic circuit 236 adds +1 to the signal CNT_rise<15:0>. As a result, the counter 202 outputs "2" as the count value CNT.

[0243] Next, at time t202, the CNT specification value is incremented to "2". Signal CNT_rise <0> This inverts the signal OSC to a "L" level at its rising edge and outputs "0". (Signal CNT_fall) <0> Since the value is "1", the exOR circuit 235 outputs "1". Therefore, the logic circuit 236 does not add to the signal CNT_rise<15:0>. Since the signal CNT_rise<15:0> is "2", the counter 202 continues to output "2" as the count value CNT.

[0244] Next, at time t203, the signal CNT_fall <0> This is inverted to an "L" level and outputs "0". Signal CNT_rise <0> and signal CNT_fall <0> Since both are "0", the exOR circuit 235 outputs "0". Therefore, the logic circuit 236 adds +1 to the signal CNT_rise<15:0>. As a result, the counter 202 outputs "3" as the count value CNT.

[0245] Next, at time t204, the CNT specification value is incremented to "3". Signal CNT_rise <0> This inverts the signal OSC to a "L" level at its rising edge and outputs "0". (Signal CNT_fall) <0> Since the value is "1", the exOR circuit 235 outputs "1". Therefore, the logic circuit 236 does not add to the signal CNT_rise<15:0>. Since the signal CNT_rise<15:0> is "3", the counter 202 continues to output "3" as the count value CNT.

[0246] Next, at time t205, the signal CNT_fall <0> This is inverted to an "H" level and outputs "1". Signal CNT_rise <0> and signal CNT_fall <0> Since both are "1", the exOR circuit 235 outputs "0". Therefore, the logic circuit 236 adds +1 to the signal CNT_rise<15:0>. As a result, the counter 202 outputs "4" as the count value CNT.

[0247] Next, at time t206, the CNT specification value counts up to "4". Signal CNT_rise <0> This inverts the signal OSC to a "H" level at its rising edge and outputs "1". (Signal CNT_fall) <0> Since the value is "0", the exOR circuit 235 outputs "1". Therefore, the logic circuit 236 does not add to the signal CNT_rise<15:0>. Since the signal CNT_rise<15:0> is "4", the counter 202 continues to output "4" as the count value CNT.

[0248] As described above, in the counter 202 of this embodiment, the count value CNT is output at the same timing as in the first embodiment.

[0249] 3.3 Counting Operation Flow Next, we will explain an example of the counting operation flow with reference to Figure 23. Figure 23 is a flowchart showing an example of the counting operation flow.

[0250] As shown in Figure 23, steps S1 to S3 are executed first. The operation of steps S1 to S3 is the same as described in Figure 13 of the first embodiment.

[0251] As explained using Figure 22, counter 202 increments the number of cycles of signal OSC(OSC_CLK_rise) on the rising edge of signal OSC(OSC_CLK_rise) (S31).

[0252] The exOR circuit 235 performs an exclusive OR (exOR) operation on the signal CNT_rise<0> and the signal CNT_fall<0>. When the operation result is 0 (exOR=0) (S32_Yes), the logic circuit 236 outputs a value obtained by adding +1 to the number of cycles (S33) as the count value CNT.

[0253] On the other hand, when the operation result is 1 (exOR=1) (S32_No), the logic circuit 236 outputs the number of cycles as the count value CNT.

[0254] Next, steps S6 to S9 are executed. The operations of steps S6 to S9 are the same as those described with reference to FIG. 13 in the first embodiment.

[0255] 3.4 Effects of the Present Embodiment With the configuration according to the present embodiment, the same effects as those of the first embodiment can be obtained.

[0256] Note that the modified example of the first embodiment can be applied to the present embodiment.

[0257] 4. Fourth Embodiment Next, a fourth embodiment will be described. In the fourth embodiment, a counter 202 that is different from those in the first to third embodiments will be described. The following description focuses on points that differ from the first to third embodiments.

[0258] 4.1 Configuration of Counter First, an example of the configuration of the counter 202 will be described with reference to FIG. 24. FIG. 24 is a circuit diagram showing an example of the configuration of the counter 202.

[0259] As shown in FIG. 24, the counter 202 of the present embodiment counts up the number of cycles based on a rising edge of the signal OSC (signal OSC_CLK2). Then, when the count execution time tRuntime ends while the signal OSC is at "L" level, the counter 202 sets the signal OSC_CLK2 to "H" level and adds +1 to the number of cycles. The counter 202 outputs the number of cycles as the count value CNT<15:0>.

[0260] The counter 202 includes a plurality of flip-flops 213 and an OR gate 241. For example, the counter 202, similar to the first embodiment, has a count value CNT <0> ~CNT <15> Each of these includes the corresponding flip-flops 213_0 to 213_15.

[0261] The signal OSC is input to the first input terminal of OR circuit 241. The first input terminal of AND circuit 231 is connected to oscillator 201. The enable signal bEN is input to the second input terminal of OR circuit 241. The enable signal bEN is set to "H" level when the counting operation is not performed. The counting operation is performed while the enable signal bEN is at the "L" level. That is, while the enable signal bEN is at the "L" level, oscillator 201 causes the signal OSC to oscillate. The output terminal of OR circuit 241 is connected to the clock signal input terminal of flip-flop 213_0. OR circuit 241 outputs the result of a logical OR operation between the signal OSC and the enable signal bEN as the signal OSC_CLK2. Therefore, the signal OSC_CLK2 is at the "H" level when the enable signal bEN is at the "H" level. Also, when the enable signal bEN is at the "L" level, the signal OSC_CLK2 is a clock signal synchronized with the signal OSC.

[0262] The flip-flop 213 includes a clock signal input terminal, a data input terminal D, a reset signal input terminal R, an output terminal Q, and an inverting output terminal Qn.

[0263] The configuration of the flip-flop 213 is the same as in Figure 8 of the first embodiment. The signal OSC_CLK2 is input to the clock signal input terminal of the flip-flop 213_0. The flip-flop 213_0 captures data on the rising edge of the signal OSC_CLK2, i.e., the signal OSC.

[0264] In this embodiment, the signal output from the output terminal Q of the flip-flops 213_0 to 213_15 is a 16-bit count value CNT <0> ~CNT <15> It will be output as follows.

[0265] 4.2 Specific examples of count values Next, we will explain a specific example of the count value CNT with reference to Figure 25. Figure 25 is a diagram showing specific examples of the signal OSC, the signal OSC_CLK2, and the count value CNT in counter 202. In the example in Figure 25, for the sake of simplicity, the CNT specification value and the count value CNT are expressed in decimal.

[0266] As shown in Figure 25, the counter 202 counts up the cycle count on the rising edge of the signal OSC_CLK2 (i.e., signal OSC). When the OR gate 241 of the counter 202 receives an enable signal bEN at the "H" level, the oscillator 201 stops oscillating the signal OSC. If the signal OSC is at the "L" level at the end of the counting operation ("Stop" in Figure 25), the OR gate 241 outputs the signal OSC_CLK2 at the "H" level because the enable signal bEN is at the "H" level. In other words, the signal OSC_CLK2 rises to the "H" level. As a result, the counter 202 outputs a count value CNT which is the cycle count of the signal OSC plus +1. Therefore, during the N-1th cycle of the signal OSC, while it is at the "L" level, the count value CNT is "N".

[0267] Furthermore, if the signal OSC is at a "H" level at the end of the counting operation, the OR gate 241 maintains the output of the signal OSC_CLK2 at a "H" level. As a result, the counter 202 outputs a count value CNT that has not been incremented by +1. Therefore, during the Nth cycle of the signal OSC, while it is at a "H" level, the count value CNT is set to "N".

[0268] Therefore, the period during which the count value CNT is "N" is, as in the first embodiment, from the falling edge of the (N-1)th cycle of the signal OSC to the falling edge of the Nth cycle. As a result, the granularity error of the signal OSC's end position relative to the CNT specification value "N" is reduced to a maximum of approximately 0.5 cycles of the signal OSC.

[0269] As described above, in the counter 202 of this embodiment, the count value CNT is output at the same timing as in the first embodiment.

[0270] 4.3 Command Sequence for Counting Operation Next, an example of a command sequence for counting operation will be described with reference to Figure 26. Figure 26 is a diagram showing an example of a command sequence for counting operation. Note that in the example in Figure 26, the signals DQS and bDQS, the chip enable signal bCE, the read enable signals RE and bRE, and the ready / busy signal bRB are omitted.

[0271] As shown in Figure 26, during the period from time t100 to t110, the memory controller 20 sequentially transmits the command "CMD", address "LUN", and address "xxh" to the memory chip 11, similar to the explanation using Figure 10 of the first embodiment.

[0272] When the sequencer 107 receives the address "xxh", it sends a high-level signal OSC_ST to the replica circuit 102 during the period from time t110 to t120. After sending the single-pulse signal OSC_ST, the sequencer 107 sets the signal OSC_ST to a low level.

[0273] Next, the sequencer 107 sends a reset signal RST at the "H" level to the replica circuit 102. Upon receiving the "H" level reset signal RST, each flip-flop 213 of the counter 202 is reset. After sending the one-pulse reset signal RST, the sequencer 107 sets the reset signal RST to the "L" level.

[0274] Next, at time t120, the memory controller 20 transmits the address "00h" to the memory chip 11 to instruct it to start the counting operation, similar to the explanation using Figure 10 of the first embodiment.

[0275] When the sequencer 107 receives address "00h", at time t130, it changes the enable signal bEN from "H" level to "L" level. When the oscillator 201 receives the enable signal bEN at "L" level, it starts oscillating the signal OSC. During the period from time t130 to t150, i.e., while the enable signal bEN is at "L" level, the OR gate 241 outputs the signal OSC_CLK2, which is synchronized with the signal OSC. The counter 202 counts up in accordance with the rising edge of the signal OSC_CLK2. In other words, the counter 202 counts up in accordance with the rising edge of the signal OSC.

[0276] Next, the memory controller 20, similar to the explanation using Figure 10 of the first embodiment, sends the address "00h" to instruct the start of the counting operation, and after the counting execution time tRuntime has elapsed, sends the address "00h" again to the memory chip 11 at time t140.

[0277] When the sequencer 107 receives address "00h", it sets the enable signal bEN to "H" level at time t150. When the oscillator 201 receives the "H" level enable signal bEN, it stops oscillating the signal OSC. At this time, if the signal OSC is at the "L" level, the OR gate 241 outputs the "H" level signal OSC_CLK2 based on the "H" level enable signal bEN. The counter 202 counts up the cycle count based on the "H" level signal OSC_CLK2 and then terminates its counting operation.

[0278] 4.4 Counting Operation Flow Next, an example of the flow of a count operation will be described with reference to FIG. 27. FIG. 27 is a flowchart illustrating an example of the flow of a count operation.

[0279] As shown in FIG. 27, first, steps S1 to S3 are executed. The operations of steps S1 to S3 are the same as those described with reference to FIG. 13 in the first embodiment.

[0280] The counter 202 counts up the number of cycles of the signal OSC at a rising edge of the signal OSC_CLK2 (i.e., the signal OSC) during the period from time t130 to t150 described with reference to FIG. 26 (S41).

[0281] When the oscillator 201 receives the high-level enable signal bEN at time t150 described with reference to FIG. 26, the oscillator 201 terminates output of the signal OSC (S42).

[0282] If the output of the signal OSC is terminated when the signal OSC_CLK2 (i.e., the signal OSC) is at low level (S43_Yes), as described with reference to FIG. 25, the OR circuit 241 shifts the signal OSC_CLK2 to high level based on the high-level enable signal bEN (S44). As a result, the count value CNT is incremented by +1.

[0283] On the other hand, if the output of the signal OSC is terminated when the signal OSC_CLK2 (i.e., the signal OSC) is at high level (S43_No), the OR circuit 241 maintains the high-level signal OSC_CLK2. As a result, the count value CNT is not incremented by +1.

[0284] Next, steps S6 to S9 are executed. The operations of steps S6 to S9 are the same as those described with reference to FIG. 13 in the first embodiment.

[0285] 4.5 Effects according to the present embodiment With the configuration according to the present embodiment, the same effects as those of the first embodiment can be obtained.

[0286] Furthermore, modifications of the first embodiment can be applied to this embodiment.

[0287] 4.6 Modification of the Fourth Embodiment Next, a modified example of the fourth embodiment will be described. In this modified example, the configuration of the replica circuit 102 differs from that of the first embodiment. The following description will focus on the differences from the first to fourth embodiments.

[0288] 4.6.1 Overall Configuration of the Replica Circuit First, an example of the overall configuration of the replica circuit 102 will be described with reference to Figure 28. Figure 28 is a diagram showing an example of the overall configuration of the replica circuit 102.

[0289] As shown in Figure 28, the replica circuit 102 includes an oscillator 201 and a counter 202.

[0290] Oscillator 201 outputs (oscillates) the signal OSC. Oscillator 201 includes comparators 203, drivers 204 and 205, a pull-up circuit 251, and a disable circuit 252.

[0291] The comparator 203 and drivers 204 and 205 are the same as those described with reference to Figure 7 of the first embodiment.

[0292] The pull-up circuit 251 pulls the output signal of the comparator 203, i.e., the signal oscillator, up to the "H" level. The pull-up circuit 251 includes a P-channel MOS transistor 301.

[0293] For example, a power supply voltage is applied to the source of transistor 301. The drain of transistor 301 is connected to the output terminal of comparator 203. That is, the drain of transistor 301 is connected to the wiring path that transmits the signal OSC. An enable signal EN is input to the gate of transistor 301. Transistor 301 is turned on when an enable signal EN at the "L" level is input. That is, during periods when the counting operation is not being performed, the signal OSC is raised to the "H" level.

[0294] The deactivation circuit 252 stops the operation of the comparator 203 (outputting a "L" level). The deactivation circuit 252 includes an N-channel MOS transistor 302.

[0295] The drain of transistor 302 is connected to comparator 203. The source of transistor 302 is grounded (connected to the ground wire). The gate of transistor 302 is input to the enable signal bEN. Transistor 302 is turned ON when an enable signal bEN at the "H" level is input. That is, during periods when the counting operation is not being performed, the output of comparator 203 is at the "L" level.

[0296] 4.6.2 Counter Configuration Next, an example of the configuration of counter 202 will be described with reference to Figure 29. Figure 29 is a circuit diagram showing an example of the configuration of counter 202.

[0297] As shown in Figure 29, the counter 202 of this embodiment counts up the cycle count based on the rising edge of the OSC signal. The counter 202 then outputs the cycle count as the count value CNT<15:0>.

[0298] The counter 202 includes a number of flip-flops 213. For example, the counter 202, as in the first embodiment, has a count value CNT <0> ~CNT <15> Each of these includes the corresponding flip-flops 213_0 to 213_15.

[0299] The flip-flop 213 includes a clock signal input terminal, a data input terminal D, a reset signal input terminal R, an output terminal Q, and an inverting output terminal Qn.

[0300] The configuration of the flip-flop 213 is the same as in Figure 8 of the first embodiment. The signal OSC is input to the clock signal input terminal of the flip-flop 213_0. The flip-flop 213_0 captures data on the rising edge of the signal OSC.

[0301] In this embodiment, the signal output from the output terminal Q of the flip-flops 213_0 to 213_15 is a 16-bit count value CNT <0> ~CNT <15> It will be output as follows.

[0302] 4.6.3 Command Sequence for Counting Operation Next, an example of a command sequence for counting operation will be described with reference to Figure 30. Figure 30 is a diagram showing an example of a command sequence for counting operation. Note that in the example in Figure 30, the signals DQS and bDQS, the chip enable signal bCE, the read enable signals RE and bRE, and the ready / busy signal bRB are omitted.

[0303] As shown in Figure 30, during the period from time t100 to t110, the memory controller 20 sequentially transmits the command "CMD", address "LUN", and address "xxh" to the memory chip 11, similar to the explanation using Figure 10 of the first embodiment.

[0304] When the sequencer 107 receives the address "xxh", it sends a high-level signal OSC_ST to the replica circuit 102 during the period from time t110 to t120. After sending the single-pulse signal OSC_ST, the sequencer 107 sets the signal OSC_ST to a low level.

[0305] Next, the sequencer 107 sends a reset signal RST at the "H" level to the replica circuit 102. Upon receiving the "H" level reset signal RST, each flip-flop 213 of the counter 202 is reset. After sending the one-pulse reset signal RST, the sequencer 107 sets the reset signal RST to the "L" level.

[0306] Next, at time t120, the memory controller 20 transmits the address "00h" to the memory chip 11 to instruct it to start the counting operation, similar to the explanation using Figure 10 of the first embodiment.

[0307] When the sequencer 107 receives address "00h", at time t130, it changes the enable signal EN, which is at an "L" level, from "L" to an "H" level. It also changes the enable signal bEN, which is at an "H" level, from an "H" level to an "L" level. When the oscillator 201 receives the enable signal EN at an "H" level and the enable signal bEN at an "L" level, it starts oscillating the signal OSC. During the period from time t130 to t150, i.e., while the enable signal bEN is at an "L" level, the OR gate 241 outputs the signal OSC_CLK2, which is synchronized with the signal OSC. The counter 202 counts up in accordance with the rising edge of the signal OSC_CLK2. In other words, the counter 202 counts up in accordance with the rising edge of the signal OSC.

[0308] Next, the memory controller 20, similar to the explanation using Figure 10 of the first embodiment, sends the address "00h" to instruct the start of the counting operation, and after the counting execution time tRuntime has elapsed, sends the address "00h" again to the memory chip 11 at time t140.

[0309] When the sequencer 107 receives address "00h", at time t150, it sets the enable signal EN to "L" level and the enable signal bEN to "H" level. When the oscillator 201 receives the "H" level enable signal bEN, it stops oscillating the signal OSC. At this time, if the signal OSC is at the "L" level, the pull-up circuit 251 of the oscillator 201 is turned on, so the oscillator 201 outputs the "H" level signal OSC. The counter 202 counts up the cycle count based on the "H" level signal OSC, and then terminates its counting operation.

[0310] 4.6.4 Counting Operation Flow Next, we will explain an example of the counting operation flow with reference to Figure 31. Figure 31 is a flowchart of an example of the counting operation flow.

[0311] As shown in Figure 31, steps S1 to S3 are executed first. The operation of steps S1 to S3 is the same as described in Figure 13 of the first embodiment.

[0312] Counter 202 counts up the number of cycles of signal OSC on the rising edge of signal OSC during the period from time t130 to t150 as explained using Figure 30 (S51).

[0313] When oscillator 201 receives an "H" level enable signal bEN at time t150, as explained using Figure 30, it terminates the output of signal OSC (S52). More specifically, the pull-up circuit 251 is turned on based on the "L" level enable signal EN, that is, it pulls signal OSC up to "H" level. Also, the deactivation circuit 252 is turned on based on the "H" level enable signal bEN.

[0314] If the output of the OSC signal ends while it is at the "L" level (S53_Yes), the OSC signal is raised to the "H" level. As a result, the count value CNT is increased by +1.

[0315] On the other hand, if the output of signal OSC ends while signal OSC is at the "H" level (S53_No), signal OSC remains at the "H" level. Therefore, +1 is not added to the count value CNT.

[0316] Next, steps S6 to S9 are executed. The operation of steps S6 to S9 is the same as described in Figure 13 of the first embodiment.

[0317] 4.6.5 Structure related to this modified example With the configuration according to this modified example, the same effects as in the first embodiment can be obtained.

[0318] Furthermore, modifications of the first embodiment can be applied to this embodiment.

[0319] 5. Fifth Embodiment Next, a fifth embodiment will be described. In the fifth embodiment, two examples are shown in which the replica circuit is applied to different semiconductor devices. The following description will focus on the differences from the first to fourth embodiments.

[0320] 5.1 Example 1 The first example describes the case where the semiconductor device is a DRAM.

[0321] Referring to Figure 32, an example of the overall configuration of the semiconductor device 400 will be described. Figure 32 is a block diagram showing an example of the overall configuration of the semiconductor device 400. Note that in Figure 32, some of the connections between each component are shown by arrow lines, but the connections between components are not limited to these.

[0322] As shown in Figure 32, the semiconductor device 400 includes, for example, a memory cell array 401, a row decoder 402, a column decoder 403, a logic control circuit 404, a command / address input circuit 405, a sense amplifier circuit 406, a replica circuit 407, a transfer gate 408, a read / write amplifier (RWAMP) 409, an input / output circuit 410, a clock input / output circuit 411, and a voltage generation circuit 412.

[0323] The memory cell array 401 includes multiple memory cells MC. Each memory cell MC of the semiconductor device 400 includes a cell capacitor CC and a cell transistor CT. The gate of the cell transistor CT is connected to one of several word lines WL. One end of the current path of the cell transistor CT is connected to a bit line BL. The other end of the current path of the cell transistor CT is connected to one end of the cell capacitor CC. The other end of the cell capacitor CC is connected to a ground node. The cell capacitor CC can store an amount of charge corresponding to the data to be stored. The cell transistor CT switches conduction / non-conductivity (selection / deselection of the memory cell) between the memory cell MC and the bit line BL. Multiple memory cells MC are arranged in a two-dimensional or three-dimensional array within the memory cell array 401. For example, the memory cell array 401 includes multiple banks. Each bank is a control unit containing multiple memory cells MC. Multiple banks can operate independently of each other.

[0324] The row decoder 402 controls the selection / deselection of row-direction wiring (e.g., word lines WL) of the memory cell array 401 based on the decoding results of the address information and the decoding results of the command.

[0325] The column decoder 403 controls the selection / deselection of column-direction wiring (e.g., bit lines BL) of the memory cell array 401 based on the decoding results of the address information and the decoding results of the command.

[0326] The logic control circuit 404 is a circuit that performs logic control of the entire semiconductor device 400.

[0327] The logic control circuit 404 performs, for example, light training as appropriate. Similar to the first to fourth embodiments, light training is performed for purposes such as timing adjustment between signal DQ and signals DQS and bDQS.

[0328] Furthermore, the logic control circuit 404 periodically causes the replica circuit 407 to perform a clock signal count operation. The clock signal is a pseudo-signal of the signal DSQ. The logic control circuit 404 determines whether or not to perform write training based on the amount of change in the count value.

[0329] The logic control circuit 404 includes an address decoder 421, a mode register 422, and a command decoder 423.

[0330] The address decoder 421 decodes the address information received from the command / address input circuit 405. The address decoder 421 then sends the decoded address information to the row decoder 402 and the column decoder 403, respectively.

[0331] The mode register 422 stores the count value received from the replica circuit 407.

[0332] The command decoder 423 decodes the command received from the command / address input circuit 405. The command decoder 423 then sends the decoded command result to the row decoder 402 and the column decoder 403, respectively.

[0333] The command / address input circuit 405 receives a command / address signal CA supplied from an external source (external device not shown). The command / address signal CA includes command and address information. The command / address input circuit 405 sends the command and address information to the command decoder 423 and the address decoder 421, respectively.

[0334] The sense amplifier circuit 406 senses and amplifies the signal from the memory cell MC during read operation. The sense amplifier circuit 406 sends the signal from the memory cell MC as read data to the input / output circuit 410 via the transfer gate 408 and RWAMP 409. The sense amplifier circuit 406 receives write data from the input / output circuit 410 via the transfer gate 408 and RWAMP 409. The sense amplifier circuit 406 outputs a signal corresponding to the write data to the bit line BL.

[0335] The replica circuit 407 is a circuit that generates a clock signal corresponding to the signal DQS and counts the number of cycles (clocks) of the clock signal. The replica circuit 407 includes a feedback oscillator for generating the clock signal and a counter as described in any of the first to fourth embodiments. The feedback path of the oscillator has the same configuration as the transmission path of the signal DQS. The replica circuit 407 transmits the count result from the counting operation to the mode register 422.

[0336] The transfer gate 408 controls the data transfer between the sense amplifier circuit 406 and the RWAMP 409.

[0337] The RWAMP409 amplifies the signal level (signal value) according to the read data, and the signal level according to the written data.

[0338] The input / output circuit 410 functions as an interface circuit for the signal DQ transferred between the memory cell array 401 and the outside of the semiconductor device 400. The input / output circuit 410 sends write data to the memory cell array 401 at a timing synchronized with the internal clock signal CLK received from the clock input / output circuit 411. The input / output circuit 410 also sends read data to a device outside of the semiconductor device 400. For example, the input / output circuit 410 receives a data mask signal DM. Based on the data mask signal DM, the input / output circuit 410 performs masking on the signal DQ (data).

[0339] The clock input / output circuit 411 is a transmission and reception circuit for signals DQS and bDQS. The clock input / output circuit 411 transmits and receives signals DQS and bDQS between the semiconductor device 400 and the outside. When data is input to the semiconductor device 400, the clock input / output circuit 411 transmits an internal clock signal CLK, based on the signals DQS and bDQS received from the outside, to the input / output circuit 410. In this example, the internal clock signal CLK is a delayed signal of signal DQS. In the input / output circuit 410, the input timing of the internal clock signal CLK and the input timing of signal DQ are synchronized. As a result, the input / output circuit 410 can acquire signal DQ based on the internal clock signal CLK. In light training, the timing of signal DQ is optimized so that the delay time of signal CLK corresponding to signals DQS and bDQS is time tDQS²DQ. Therefore, the delay time of the internal clock signal CLK relative to signal DQS corresponds to time tDQS²DQ. Furthermore, when the semiconductor device 400 outputs data, the clock input / output circuit 411 outputs the generated signals DQS and bDQS to the outside.

[0340] The voltage generation circuit 412 uses an external power supply voltage (the voltage applied to the power supply node VDD and the voltage applied to the ground node VSS) to generate multiple voltages used for each of the various operating sequences of the semiconductor device 400. The voltage generation circuit 412 sends the generated voltages to other circuits (for example, RWAMP 409).

[0341] In the first example of the fifth embodiment, the semiconductor device 400 is exemplified as being a DRAM, but it is not limited to this. The semiconductor device 400 may be a random access memory other than a DRAM. For example, the semiconductor device 400 may be an SRAM (Static RAM).

[0342] In the semiconductor device 400 according to the first example of the fifth embodiment, for example, the replica circuit 102 described in the first to fourth embodiments above can be applied to the replica circuit 407.

[0343] 5.2 Second Example In the first example, we will describe the case where the semiconductor device 500 is a microcontroller.

[0344] 5.2.1 Semiconductor device configuration First, an example of the overall configuration of the semiconductor device 500 will be described with reference to Figure 33. Figure 33 is a block diagram showing the overall configuration of the semiconductor device 500. Note that in Figure 33, some of the connections between each component are shown by arrow lines, but the connections between components are not limited to these.

[0345] As shown in Figure 33, the semiconductor device 500 includes, for example, a processor 501, a bus control circuit 502, a flash memory 503, a RAM 504, a DA conversion circuit 505, an AD conversion circuit 506, a timer 507, an input / output (I / O) port 508, an oscillator 509, an interrupt controller 510, a skew measurement circuit 511, and a replica circuit 512. The bus of the semiconductor device 500 is connected to the processor 501, the bus control circuit 502, the flash memory 503, the RAM 504, the DA conversion circuit 505, the AD conversion circuit 506, the timer 507, the input / output port 508, the oscillator 509, the interrupt controller 510, the skew measurement circuit 511, and the replica circuit 512. The bus of the semiconductor device 500 is the transmission path for signals and data within the semiconductor device 500.

[0346] The processor 501 performs various processes within the semiconductor device 500. The processor 501 performs various processes on the supplied data. The processor 501 is, for example, a CPU.

[0347] The processor 501 performs training as appropriate, for example. In this example, training is performed for purposes such as adjusting the timing between the signals received at the input / output port 508 and the internal clocks CLK and bCLK.

[0348] Furthermore, the processor 501 periodically causes the replica circuit 512 to perform a clock signal count operation. The clock signal is a pseudo-signal of the internal clock CLK. The processor 501 determines whether or not to perform training based on the amount of change in the count value.

[0349] The bus control circuit 502 controls the bus of the semiconductor device 500. The bus control circuit 502 may be located within the processor 501.

[0350] The flash memory 503 is a storage device capable of storing data non-volatilely. The flash memory 503 is, for example, a NOR-type flash memory. However, the flash memory 503 may also be a NAND-type flash memory.

[0351] RAM504 is a memory device that temporarily stores data. RAM504 is a random access memory, such as SRAM or DRAM.

[0352] The DA conversion circuit 505 converts a digital signal (digital value) into an analog signal (analog value).

[0353] The AD conversion circuit 506 converts analog signals into digital signals.

[0354] Timer 507 manages the time (operation timing) within the semiconductor device 500.

[0355] The input / output port 508 functions as an interface circuit in the semiconductor device 500. The input / output port 508 includes, for example, four ports P1, P2, P3, and P4. The number of ports provided by the input / output port 508 may be three or fewer, or five or more. The input / output port 508 performs signal input and output at timings synchronized with the internal clock CLK and bCLK received from the oscillator 509. That is, the input / output port 508 receives signals, including data and addresses, from outside the semiconductor device 500 (for example, a host not shown) via each of ports P1, P2, P3, and P4. The input / output port 508 sends signals, such as data, to the outside of the semiconductor device 500 via each of ports P1, P2, P3, and P4. The input / output port 508 conforms to standards such as GPIO (General Purpose Input / Output), USART (Universal Synchronous / Asynchronous Receiver Transmitter), or I2C (Inter-integrated Circuit).

[0356] Oscillator 509 outputs a clock signal as a synchronization signal to processor 501. The clock signal has a certain period (number of clock cycles). As a result, processor 501 performs various processes at timings synchronized with the clock signal. The period of the clock signal can be, for example, 4MHz, 8MHz, 12MHz, or 24MHz. Oscillator 509 also outputs the internal clock CLK and bCLK to input / output port 508. The internal clock bCLK is the inverted signal of the internal clock CLK.

[0357] The interrupt controller 510 receives external interrupt instructions. For example, the interrupt controller 510 has registers for managing the status of interrupt requests. Based on the received external interrupt instructions, the interrupt controller 510 sends various interrupt requests to the processor 501. In response to the interrupt request, the processor 501 temporarily suspends the process it is currently running and executes the processing of the interrupt request. After the processing of the interrupt request is completed, the processor 501 resumes the suspended process.

[0358] The skew measurement circuit 511 is a circuit that measures the timing difference (skew) between the internal clock CLK and bCLK and the input signal at the input / output port 508.

[0359] Furthermore, the skew measurement circuit 511 causes the replica circuit 512 to perform a clock signal count operation based on the control of the processor 501. The clock signal used by the replica circuit 512 is a pseudo-signal of the internal clock CLK.

[0360] The replica circuit 512 is a circuit that generates a clock signal corresponding to the internal clock CLK and counts the number of cycles (clocks) of the clock signal. The replica circuit 512 includes a feedback oscillator for generating the clock signal and a counter as described in the first to fourth embodiments. The feedback path of the oscillator has the same configuration as the transmission path of the internal clock CLK2. The replica circuit 512 transmits the count result obtained from the counting operation to the processor 501.

[0361] The semiconductor device 500 may be a system-on-a-chip (SoC), a system-in-package (SIP), or a system-on-a-package (SoP). The semiconductor device 500 is used, for example, in embedded systems. The semiconductor device 500 may be used, for example, in automotive devices, home appliances, computers, industrial machinery, railway vehicles, aircraft, and ships.

[0362] Furthermore, the semiconductor device 500 may be classified based on its bus width, memory structure, and instruction set. Bus width refers to the size of the data bus. For example, based on its bus width, the semiconductor device 500 can be classified as an 8-bit microcontroller, a 16-bit microcontroller, or a 32-bit microcontroller. A higher bus width allows the semiconductor device 500 to achieve better performance.

[0363] Furthermore, in the semiconductor device 500 according to the second example of the fifth embodiment, for example, the replica circuit 102 described in the first to fourth embodiments above can be applied to the replica circuit 512.

[0364] 5.2.2 Connecting the Oscillator and Input / Output Ports Next, an example of the connection between oscillator 509 and input / output port 508 will be described with reference to Figure 34. Figure 34 is a block diagram showing an example of the connection between oscillator 509 and input / output port 508.

[0365] As shown in Figure 34, the semiconductor device 500 further includes an input receiver 520 and a delay circuit 521. The input / output port 508 also includes a latch circuit 522.

[0366] The input receiver 520 is a receiving circuit for the internal clock CLK and bCLK. The output terminal of the input receiver 520 is connected to the delay circuit 521. For example, the input receiver 520 outputs a signal synchronized with the internal clock CLK and bCLK.

[0367] The delay circuit 521 is a circuit that delays the signal received from the input receiver 520. The delay circuit 521 is connected to the latch circuit 522. The output signal of the input receiver 520 is delayed by the delay circuit 521 and the wiring delay in the wiring path connecting the input receiver 520 and the latch circuit 522, and then input to the latch circuit 522. This delay time is denoted as time tSkew. That is, the latch circuit 522 receives the internal clock CLK and bCLK, which have been delayed by time tSkew.

[0368] The latch circuit 522 is a circuit that captures input signals via ports P1, P2, P3, and P4, respectively, based on the delayed internal clocks CLK and bCLK. The latch circuit 522 is connected to ports P1, P2, P3, and P4.

[0369] 5.2.3 Counting Operation Flow Next, we will explain an example of the counting operation flow with reference to Figure 35. Figure 35 is a flowchart showing an example of the counting operation flow.

[0370] As shown in Figure 35, first, the processor 501 instructs the skew measurement circuit 511 to perform a count operation in the replica circuit 512 (S101).

[0371] When the skew measurement circuit 511 receives a counting operation command from the processor 501, it causes the replica circuit 512 to execute the counting operation (S102).

[0372] When the replica circuit 512 finishes its counting operation, it sends the count value CNT to the processor 501 (S103).

[0373] The processor 501 calculates the difference between the received count value CNT and the count value CNT from the previous count operation (S104).

[0374] Processor 501 checks whether the difference is greater than or equal to a preset threshold (S105).

[0375] If the difference is greater than or equal to a preset threshold (S105_Yes), processor 501 performs training (S106) to adjust the skew (time tSkew).

[0376] On the other hand, if the difference is less than a preset threshold (S105_No), the processor 501 terminates the counting operation.

[0377] 5.3 Effects of this embodiment With the configurations according to the first and second examples of this embodiment, the same effects as in the first embodiment can be obtained.

[0378] 6. Variations, etc. The semiconductor device (11) according to the above embodiment includes an oscillator (201) that outputs a first signal (OSC) and a counter (202) that counts the number of cycles of the first signal. The counter sets the count value of the number of cycles of the first signal to N before the oscillator outputs the Nth cycle of the first signal (N is an integer of 2 or more).

[0379] By applying the above embodiment, a semiconductor device capable of improving processing performance can be provided.

[0380] Furthermore, the embodiments are not limited to the forms described above, and various modifications are possible.

[0381] In the above embodiment, "connection" also includes a state in which something else, such as a transistor or resistor, is interposed between the two parties for an indirect connection.

[0382] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims and their equivalents. [Explanation of Symbols]

[0383] 1...Memory system, 10...Non-volatile memory, 11...Memory chip, 20...Memory controller, 21...Host interface circuit, 22...CPU, 23...ROM, 24, 504...RAM, 25...Buffer memory, 26...ECC circuit, 27...Memory interface circuit, 101, 410...Input / output circuit, 102, 407, 512...Replica circuit, 103...Logic control circuit, 104...Address register, 105...Command register, 106...Status register, 107...Sequencer, 108...Reader i / busy circuit, 109...voltage generation circuit, 120, 401...memory cell array, 121, 402...row decoder, 122...sense amplifier, 123...data register, 124, 403...column decoder, 131...input circuit, 132...output circuit, 141, 520...input receiver, 142, 221, 521...delay circuit, 143, 522...latch circuit, 151, 154, 203...comparator, 152, 153, 204, 205...driver, 201, 509...oscillator, 202...counter, 211, 232...i 212, 231, 233…AND gates, 213, 234…Flip-flops, 214…Adders, 222, 241…OR gates, 235…exOR gates, 236…Logic circuits, 251…Pull-up circuits, 252…Invalidation circuits, 301…P-channel MOS transistors, 302…N-channel MOS transistors, 400, 500…Semiconductor equipment, 404…Logic control circuits, 405…Command / address input circuits, 406…Sense amplifier circuits, 408…Transfer gates, 411…Clock input / output circuits, 412…Voltage Generation circuit, 421…Address decoder, 422…Mode register, 423…Command decoder, 501…Processor, 502…Bus control circuit, 503…Flash memory, 505…DA conversion circuit, 506…AD conversion circuit, 507…Timer, 508…Input / output port, 510…Interrupt controller, 511…Skew measurement circuit, BL…Bit line, BLK…Block, MC…Memory cell transistor, SGD…Selection gate line, ST1, ST2…Selection transistor, SU…String unit, WL…Word line

Claims

1. An oscillator that outputs the first signal, A counter for counting the number of cycles of the first signal and Equipped with, The counter sets the count value of the cycle number of the first signal to N before the oscillator outputs the Nth cycle (where N is an integer of 2 or more) of the first signal. Semiconductor equipment.

2. The counter sets the count value of the number of cycles of the first signal to N after 0.5 cycles have elapsed since the oscillator began outputting the (N-1)th cycle of the first signal. The semiconductor device according to claim 1.

3. The first signal alternately repeats a first edge that transitions from a first logic level to a second logic level different from the first logic level, and a second edge that transitions from the second logic level to the first logic level. When the oscillator starts outputting the first signal and the first edge occurs, the counter uses the second edge to count up the number of cycles of the first signal. The semiconductor device according to claim 1.

4. The counter includes an adder and outputs a value obtained by adding 1 to the number of cycles of the first signal as the count value. The semiconductor device according to claim 3.

5. The counter adds 1 to the number of cycles of the first signal based on a second signal that notifies the start of a counting operation received before the oscillator starts outputting the first signal. The semiconductor device according to claim 3.

6. The first signal alternately repeats a first edge that transitions from a first logic level to a second logic level different from the first logic level, and a second edge that transitions from the second logic level to the first logic level. When the oscillator starts outputting the first signal and the first edge occurs, the counter uses the first edge to count up the number of cycles of the first signal. The semiconductor device according to claim 1.

7. The aforementioned counter is A first flip-flop that operates based on the first edge of the first signal, A second flip-flop that operates based on the second edge of the first signal, A first circuit that performs an exclusive OR operation between the first output signal of the first flip-flop and the second output signal of the second flip-flop, A logic circuit that determines whether or not to add 1 to the number of cycles of the first signal based on the calculation result of the first circuit, including, The semiconductor device according to claim 6.

8. The logic circuit adds 1 to the number of cycles of the first signal if the logic level of the first output signal and the logic level of the second output signal are the same, and does not add 1 to the number of cycles of the first signal if the logic levels of the first output signal and the logic level of the second output signal are different. The semiconductor device according to claim 7.

9. When the oscillator terminates outputting the first signal while the first signal is at a first logic level, the counter increments the number of cycles of the first signal by 1. When the oscillator terminates outputting the first signal while the first signal is at the second logic level, the counter does not increment the number of cycles of the first signal by 1. The semiconductor device according to claim 6.

10. The oscillator outputs the first signal during the period when the third signal is at the first logic level. The aforementioned counter is A second circuit outputs a fourth signal based on the result of a logical OR operation between the first signal and the third signal, A third flip-flop that operates based on the first edge of the fourth signal and including, The semiconductor device according to claim 9.

11. The oscillator described above is A third circuit including an output terminal that outputs the first signal and an input terminal that receives the first signal output from the output terminal, The pull-up circuit connected to the output terminal of the third circuit and including, The semiconductor device according to claim 9.

12. The system further includes a latch circuit that captures a seventh signal input from an external source based on a sixth signal obtained by delaying a fifth signal input from an external source. One cycle of the first signal is equal to the delay time of the sixth signal relative to the fifth signal. The semiconductor device according to claim 1.

13. The fifth signal and the seventh signal are input asynchronously. The semiconductor device according to claim 12.

14. The maximum value of the granularity error of the count value that occurs during the first period in which the counter performs the counting operation is equal to the value obtained by dividing the delay time by the length of the first period. The semiconductor device according to claim 12.

15. The first period is based on the command set received from the external controller. The aforementioned delay time is based on the time difference between the fifth signal and the seventh signal received from the external controller. The semiconductor device according to claim 14.

16. The first pad to which the fifth signal is input from the external source, The second pad to which the seventh signal is input from the external source, Furthermore, The number of circuits provided in the first path connecting the first pad and the latch circuit is greater than the number of circuits provided in the second path connecting the second pad and the latch circuit. The semiconductor device according to claim 12.

17. The system further includes a control circuit configured to perform an operation to adjust the timing between the fifth signal and the seventh signal if the absolute difference between the count value output by the counter and the previously measured count is greater than a preset threshold. The semiconductor device according to claim 12.

18. A counting method using an oscillator that outputs a first signal and a counter that counts the number of cycles of the first signal, To start outputting the first signal, Before the Nth cycle (where N is an integer greater than or equal to 2) of the first signal is output, the count value of the cycle number of the first signal is set to N. Equipped with, Counting method.

19. Setting the count value to N means setting the count value of the cycle number of the first signal to N 0.5 cycles after the output of the (N-1)th cycle of the first signal has started. including, The counting method according to claim 18.

20. Initiating the output of the first signal includes generating a first edge that first transitions from a first logic level to a second logic level different from the first logic level, Setting the count value to N includes counting up the number of cycles of the first signal based on the second edge transitioning from the second logic level to the first logic level. The counting method according to claim 18.

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