Detection circuit, semiconductor integrated circuit, semiconductor device, and control method

Abstract

To provide a detection circuit suitable for appropriately protecting a power device from overcurrent.SOLUTION: According to one embodiment, there is provided a detection circuit having a comparison circuit and a signal generation circuit. The comparison circuit has a first input node, a second input node, and an output node. The first input node is connected to one end of the power device. The second input node is connected to a threshold voltage. The signal generation circuit has a first input node and an output node. The first input node is connected to the output node of the comparison circuit. The output node is connected to a control node of a protection circuit of the power device.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] This embodiment relates to a detection circuit, a semiconductor integrated circuit, a semiconductor device, and a control method. [Background technology]

[0002] A semiconductor device connected to the control terminal of a power device drives the power device. Power devices are connected to loads through which relatively large currents flow and are used to switch the load. In semiconductor devices, it is desirable to adequately protect the power device from overcurrent. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] U.S. Patent Application Publication No. 2018 / 0097515 [Overview of the project] [Problems that the invention aims to solve]

[0004] One embodiment aims to provide a detection circuit, a semiconductor integrated circuit, a semiconductor device, and a control method suitable for properly protecting a power device from overcurrent. [Means for solving the problem]

[0005] According to one embodiment, a detection circuit is provided having a comparator circuit and a signal generation circuit. The comparator circuit has a first input node, a second input node and an output node. The first input node is a power device High-voltage side terminal It connects to the network. The power device has a control terminal, a high-voltage terminal, and a low-voltage terminal. The second input node is connected to the threshold voltage. The threshold voltage corresponds to the falling edge of the voltage waveform at the high-voltage terminal of the power device. The signal generation circuit has a first input node and The second input node and It has an output node. The first input node is connected to the output node of the comparator circuit. The output node is Protection It is connected to the control node of the protection circuit. The protection circuit can detect when an overcurrent begins to flow through a power device and perform a protective operation to turn off the power device accordingly. The protection circuit has an input node, a control node, and an output node. The output node of the protection circuit is connected to the control terminal of the power device via a drive circuit. The second input node of the signal generation circuit is connected to the input node of the protection circuit. The comparator circuit outputs a first comparison result if the voltage at the high-voltage terminal of the power device is higher than the threshold voltage. The comparator circuit outputs a second comparison result if the voltage at the high-voltage terminal of the power device is lower than the threshold voltage. The signal generation circuit measures a first time. The first time is between a first timing and a second timing. At the first timing, the waveform of the input signal supplied to the input node of the protection circuit rises. At the second timing, the comparison result of the comparator circuit transitions from the first comparison result to the second comparison result. The signal generation circuit outputs a control signal to the control node of the protection circuit instructing it to disable the protective operation, depending on whether the second time has elapsed from the first timing. The second time is the time corresponding to the first time. The signal generation circuit outputs a control signal to the control node of the protection circuit instructing it to activate the protection operation, either when a second time has elapsed from the first timing, or when the comparison result of the comparison circuit is inverted. [Brief explanation of the drawing]

[0006] [Figure 1] A circuit diagram showing the configuration of a semiconductor device according to an embodiment. [Figure 2] A diagram illustrating the concept of DESAT in an embodiment. [Figure 3] A waveform diagram showing the operation of a semiconductor device according to an embodiment. [Figure 4] A circuit diagram showing the configuration of a semiconductor device according to a first modified example of the embodiment. [Figure 5] A circuit diagram showing the configuration of the time history generation circuit in a first modified example of the embodiment. [Figure 6] A waveform diagram showing the operation of the time history generation circuit according to the first modified embodiment. [Figure 7] A circuit diagram showing the configuration of a semiconductor device according to a second modified example of the embodiment. [Figure 8] A circuit diagram showing the configuration of a semiconductor device according to a third modified example of the embodiment. [Figure 9] A circuit diagram showing the configuration of a semiconductor device according to a fourth modified example of the embodiment. [Figure 10] A circuit diagram showing the configuration of a semiconductor device according to a fifth modified example of the embodiment. [Modes for carrying out the invention]

[0007] A semiconductor device according to an embodiment will be described in detail below with reference to the attached drawings. However, the present invention is not limited to this embodiment.

[0008] (Embodiment) The semiconductor device according to this embodiment is connected to the control terminal of a power device and drives the power device, but measures are taken to properly protect the power device from overcurrent.

[0009] The semiconductor device 1 may be connected to the control terminal G of the power device PT as shown in Figure 1, and may drive the power device PT. Figure 1 is a circuit diagram showing the configuration of the semiconductor device 1.

[0010] The power device PT is connected to a load LD that operates with a relatively large current and is used to switch the load LD. The load LD may include a resistive component LDa and an inductive component LDb. For example, the load LD may be part of a DC motor and its drive circuit (e.g., an H-bridge circuit), and the power device PT may be another part of the drive circuit. Alternatively, the load LD may be part of an AC motor and its drive circuit (e.g., an inverter circuit), and the power device PT may be another part of the drive circuit.

[0011] The power device PT can be any device capable of handling relatively large currents. The power device PT may be an IGBT (Insulated Gate Bipolar Transistor), a power MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), or a bipolar transistor. The substrate used for the device structure of the power device PT may be a SiC substrate or a Si substrate.

[0012] If a short circuit or other malfunction occurs in the load LD, an overcurrent may flow through the power device PT. To protect the power device PT from overcurrent, it is effective to detect when an overcurrent begins to flow through the power device PT and to perform a protective operation that turns off the power device PT accordingly. The start of an overcurrent flowing through the power device PT can be detected by detecting DESAT (hereinafter referred to as DESAT detection).

[0013] DESAT can be defined as shown in Figure 2. Figure 2 is a diagram illustrating DESAT.

[0014] For example, when the power device PT is an N-type IGBT, as shown in FIG. 2(a), one end of the power device PT is a collector C, the other end is an emitter E, and the control terminal is a gate G.

[0015] As shown in FIG. 2(b), when the voltage V between the gate G and the emitter E of the power device PT CE exceeds a predetermined value and the power device PT is turned on, in the region RG1, with an increase in the voltage V between the collector C and the emitter E CE , the current I flowing from the collector C to the emitter E C increases sharply. In the region RG2 on the higher voltage side, with an increase in the voltage V CE , the current I C increases gradually.

[0016] As indicated by the open arrow in FIG. 2(b), the transition from the region RG1 where the current I C increases sharply to the region RG2 where the current I C increases gradually is referred to as DESAT. The region RG1 may be referred to as a saturation region. The region RG2 may be referred to as an active region.

[0017] Note that when the power device PT is a P-type IGBT, the polarity of the voltage between the gate G and the emitter E that turns on the device is reversed, and the collector current flows in a direction from the emitter E to the collector C; otherwise, this case is the same as when the power device PT is an N-type IGBT.

[0018] Alternatively, when the power device PT is an N-type power MOSFET, as shown in FIG. 2(c), one end of the power device PT is a drain D, the other end is a source S, and the control terminal is a gate G.

[0019] As shown in FIG. 2(d), when the voltage V between the gate G and the source S of the power device PT GS exceeds a predetermined value and the power device PT is turned on, in the region RG11, with an increase in the voltage V between the drain D and the source S DS , the current I of the drain D D increases sharply. In the region RG12 on the higher voltage side, the voltage V DSCurrent I D The number will begin to increase gradually.

[0020] As shown by the white arrow in Figure 2(d), current I D The current I is from the steep region RG11. D The transition to the gradual region RG12 will be called DESAT. Region RG11 is sometimes called the linear region. Region RG12 is sometimes called the saturated region.

[0021] Furthermore, if the power device PT is a P-type power MOSFET, the polarity of the voltage between the gate G and source S when it is turned on is reversed, and the drain current flows from source S to drain D. Except for this, the behavior is the same as when the power device PT is an N-type power MOSFET.

[0022] Although not shown in the diagram, if the power device PT is a bipolar transistor, one end of the power device PT is the collector, the other end is the emitter, and the control terminal is the base. The transition from a region where the current at both ends is steep to a region where the current at both ends is gentle will be called DESAT.

[0023] The following explanation focuses primarily on the case where the power device PT is an N-type power MOSFET. The one end, the other end, and the control terminal of the power device PT are denoted as D, S, and G, respectively. The following explanation is also applicable to other types of power devices PT.

[0024] The semiconductor device 1 shown in Figure 1 has input nodes 1a to 1c and an output node 1d. Input node 1a is connected to an external device (e.g., a higher-level controller) and receives an input signal INPUT from the external device. Input node 1b is connected to one end D of a power transistor PT and one end of a load LD. Input node 1c is connected to one end D of a power transistor PT and one end of a load LD. Output node 1d is connected to the control terminal G of a power transistor PT.

[0025] The power device PT has one end D connected to the input nodes 1b and 1c of the semiconductor device 1 and one end of the load LD, the other end S connected to the ground potential GND, and the control terminal G connected to the output node 1d of the semiconductor device 1.

[0026] The semiconductor device 1 consists of a semiconductor integrated circuit 2 and a rectifier element D. DESAT , Capacitive element C DESAT , resistive element R DESAT , rectifier element D DET , resistive element R DET It holds.

[0027] The semiconductor integrated circuit 2 may consist of a single chip or may be divided into multiple chips. The semiconductor integrated circuit 2 is provided with terminals INPUT, VDDET, DESAT, and GATE_DRIVE.

[0028] Rectifier element D DESAT It is connected between terminal DESAT and one end D of power device PT. Rectifier element D DESAT The forward direction is defined as the direction from terminal DESAT towards terminal D. Rectifier element D DESAT This could be a diode.

[0029] Capacitive element C DESAT One end is connected to terminal DESAT and rectifier element D DESAT It is connected to the node between them, and the other end is connected to ground potential. Capacitive element C DESAT The capacitance value can be predetermined according to the operating characteristics required of the protection circuit 4. Capacitive element C DESAT The capacitance value is the capacitance element C required for DESAT detection of the power device PT. DESAT The charging characteristics (for example, RC time constant, or charging time by the current source 43) can be predetermined.

[0030] Resistive element R DESAT This involves terminal DESAT and rectifier element D DESAT A resistor R is connected between them. DESAT The resistance value of the resistor R can be predetermined according to the characteristics required of the protection circuit 4. DESATThe resistance value of the resistor R can be predetermined according to the operating characteristics required of the protection circuit 4. DESAT The resistance value of the capacitive element C required for DESAT detection of the power device PT is DESAT It can be predetermined according to the charging characteristics (e.g., RC time constant).

[0031] Rectifier element D DET It is connected between terminal VDDET and one end D of power device PT. Rectifier element D DET The forward direction is defined as the direction from terminal VDDET towards terminal D. Rectifier element D DET This could be a diode.

[0032] Resistive element R DET This is the terminal VDDET and the rectifier element D DET A resistor R is connected between them. DET The resistance value of the resistor R can be predetermined according to the operating characteristics required of the detection circuit 3. DET The resistance value of the resistor R required for detecting the falling edge of the voltage at one end D of the power device PT is DET It can be predetermined according to the resistance characteristics (e.g., transient current limiting).

[0033] The semiconductor integrated circuit 2 includes a detection circuit 3, a protection circuit 4, and a drive circuit 5.

[0034] The detection circuit 3 is connected between terminal INPUT, protection circuit 4, and terminal VDDET. The detection circuit 3 can detect the falling edge of the voltage at one end D of the power device PT via terminal VDDET. When the detection circuit 3 detects the falling edge of the voltage at one end D, it generates a signal to activate the protection circuit 4 and supplies it to the protection circuit 4.

[0035] The detection circuit 3 includes a comparison circuit 31, a voltage source 32, a current source 33, a capacitive element 34, a switch 35, and a control unit (signal generation circuit) 36.

[0036] The comparison circuit 31 has an input node 31a, an input node 31b, and an output node 31c. The input node 31a has terminal VDDET and a resistor R DET and rectifier element D DET It is connected to one end D of the power device PT via [a specific device]. The input node 31b is connected to the voltage source 32. The output node 31c is connected to the control unit 36.

[0037] The voltage source 32 has one end connected to the input node 31b of the comparator circuit 31 and the other end connected to ground potential. The voltage source 32 may also be a constant voltage source and generates a reference voltage corresponding to the threshold voltage Vth1. The threshold voltage Vth1 is the voltage V at one end D of the power device PT. D This corresponds to the falling edge of the waveform (see Figure 3).

[0038] For example, the comparison circuit 31 checks the voltage V at terminal VDDET. VDDET This is compared with the threshold voltage Vth1.

[0039] When input node 31a is a non-inverting input node and input node 31b is an inverting input node, the comparator circuit 31 has a voltage V VDDET If the voltage is higher than the threshold voltage Vth1, the comparison result at the H level will be output, and the voltage V VDDET If the value is lower than the threshold voltage Vth1, the comparison result at the L level is output.

[0040] When input node 31a is an inverting input node and input node 31b is a non-inverting input node, the comparator circuit 31 has a voltage V VDDET If the voltage is higher than the threshold voltage Vth1, the comparison result of the L level is output, and the voltage V VDDET If the value is lower than the threshold voltage Vth1, the comparison result at the H level will be output.

[0041] The current source 33 has one end connected to the power supply potential and the other end connected to the node between the input node 31a and terminal VDDET of the comparator circuit 31. The current source 33 may also be a constant current source and capable of supplying a constant current to the capacitive element 34. The constant current supplied by the current source 33 can be predetermined according to the operating characteristics required of the detection circuit 3. The constant current supplied by the current source 33 can be predetermined according to the charging characteristics of the capacitive element 34 required for detecting the falling edge of the voltage at one end D of the power device PT.

[0042] One end of the capacitive element 34 is connected to the node between the input node 31a and terminal VDDET of the comparator circuit 31, and the other end is connected to ground potential. The capacitance value of the capacitive element 34 can be predetermined according to the operating characteristics required of the detection circuit 3. The capacitance value of the capacitive element 34 can be predetermined according to the charging characteristics of the capacitive element 34 required for detecting the falling edge of the voltage at one end D of the power device PT.

[0043] Switch 35 is connected between one end of the capacitive element 34 and the ground potential. One end of switch 35 is connected to the node between the input node 31a of the comparator circuit 31 and terminal VDDET, the other end is connected to the ground potential, and the control terminal is connected to the control unit 36.

[0044] When switch 35 receives a non-active level (e.g., L level) control signal MASK1 from the control unit 36, it turns off, disconnecting one end of the capacitive element 34 from ground potential and making the capacitive element 34 rechargeable. When switch 35 receives an active level (e.g., H level) control signal MASK1 from the control unit 36, it turns on, connecting one end of the capacitive element 34 to ground potential, drawing charge from one end of the capacitive element 34, setting the input node 31a of the comparator circuit 31 to ground potential, and disabling the function of the detection circuit.

[0045] The control unit 36 ​​has input node 36a connected to terminal INPUT, input node 36b connected to comparator circuit 31, output node 36d connected to switch 35, and output node 36e connected to protection circuit 4.

[0046] The control unit 36 ​​generates a control signal MASK in response to the input signal INPUT and supplies it to the switch 35.

[0047] The control unit 36 ​​generates a control signal EN_DESAT to activate the protection circuit 4 and supplies it to the protection circuit 4 in response to the inversion of the comparison result of the comparison circuit 31.

[0048] When input node 31a of the comparison circuit 31 is a non-inverting input node and input node 31b is an inverting input node, the control unit 36 ​​supplies a non-active level control signal EN_DESAT to the protection circuit 4 during period TP1 when the comparison circuit 31 outputs a comparison result at an H level. The control unit 36 ​​supplies an active level control signal EN_DESAT to the protection circuit 4 during period TP2 when the comparison circuit 31 outputs a comparison result at an L level.

[0049] When input node 31a of the comparison circuit 31 is an inverting input node and input node 31b is a non-inverting input node, the control unit 36 ​​supplies a non-active level control signal EN_DESAT to the protection circuit 4 during period TP11 when the comparison circuit 31 outputs a comparison result at an L level. The control unit 36 ​​supplies an active level control signal EN_DESAT to the protection circuit 4 during period TP12 when the comparison circuit 31 outputs a comparison result at an H level.

[0050] The protection circuit 4 is connected between terminal INPUT, detection circuit 3, drive circuit 5, and terminal DESAT. The protection circuit 4 can detect the DESAT of the power device PT via terminal DESAT. When the protection circuit 4 detects the DESAT of the power device PT, it supplies the signal OFF_CTR to the drive circuit 5, instructing it to shut down the power device PT.

[0051] The protection circuit 4 includes a comparison circuit 41, a voltage source 42, a current source 43, a switch 45, a filter 47, and a control unit (signal generation circuit) 46.

[0052] The comparison circuit 41 has an input node 41a, an input node 41b, and an output node 41c. The input node 41a has terminal DESAT and a resistor R DESAT and rectifier element D DESAT It is connected to one end D of the power device PT via [a certain device]. The input node 41b is connected to the voltage source 42. The output node 41c is connected to the control unit 46 via the filter 47.

[0053] The filter 47 is connected between the comparison circuit 41 and the control unit 46. The filter 47 rejects short pulse signals that result in a misjudgment in relation to the comparison result of the comparison circuit 41 and supplies them to the control unit 46.

[0054] The voltage source 42 has one end connected to the input node 41b of the comparator circuit 41 and the other end connected to ground potential. The voltage source 42 may also be a constant voltage source and generates a reference voltage corresponding to the threshold voltage Vth2. The threshold voltage Vth2 is the voltage V at one end D of the power device PT. D This corresponds to the rising edge of the waveform (see Figure 3).

[0055] For example, the comparison circuit 41 measures the voltage V at terminal DESAT. DESAT This is compared with the threshold voltage Vth2.

[0056] When input node 41a is a non-inverting input node and input node 41b is an inverting input node, the comparator circuit 41 has a voltage V DESAT If the voltage is higher than the threshold voltage Vth2, the comparison result at the H level will be output, and the voltage V DESAT If the value is lower than the threshold voltage Vth2, the comparison result at the L level will be output.

[0057] When input node 41a is an inverting input node and input node 41b is a non-inverting input node, the comparator circuit 41 has a voltage V DESAT If the voltage is higher than the threshold voltage Vth2, the comparison result at the L level will be output, and the voltage V DESAT If the value is lower than the threshold voltage Vth2, the comparison result at the H level will be output.

[0058] The current source 43 has one end connected to the power supply potential and the other end connected to the node between the input node 41a and terminal DESAT of the comparator circuit 41. The current source 43 may also be a constant current source, supplying a constant current to the capacitive element C via terminal DESAT. DESAT It can supply power to the current source 43. The constant current supplied by the current source 43 can be predetermined according to the operating characteristics required of the protection circuit 4. The constant current supplied by the current source 43 is supplied to the capacitive element C required for DESAT detection of the power device PT. DESAT This can be predetermined depending on the charging characteristics.

[0059] Switch 45 is a capacitive element C DESAT It is connected between one end and the ground potential. One end of the switch 45 is connected to the node between the input node 41a of the comparator circuit 41 and terminal DESAT, the other end is connected to the ground potential, and the control terminal is connected to the control unit 46.

[0060] When switch 45 receives a non-active level (e.g., L level) control signal MASK2 from the control unit 46, it turns off, disconnecting one end of the capacitive element 34 from ground potential and making the capacitive element 34 ready for charging. When switch 45 receives an active level (e.g., H level) control signal MASK2 from the control unit 46, it turns on, connecting one end of the capacitive element 34 to ground potential and making the capacitive element 34 ready for charging. K The charge is drawn out from one end and discharged to ground potential.

[0061] The control unit 46 has an input node 46a connected to terminal INPUT, an input node 46b connected to a comparator circuit 41 via a filter 47, a control node 46c connected to a detection circuit 3, an output node 46d connected to a switch 45, and an output node 46e connected to a drive circuit 5.

[0062] The control unit 46 generates a control signal OFF_CTR instructing the power device PT to shut down when the comparison result of the comparison circuit 41 is inverted, and supplies it to the drive circuit 5.

[0063] When input node 41a of the comparison circuit 41 is a non-inverting input node and input node 41b is an inverting input node, the control unit 46 supplies an active-level control signal OFF_CTR to the drive circuit 5 during period TP21 when the comparison circuit 41 outputs an H-level comparison result. The control unit 46 supplies a non-active-level control signal OFF_CTR to the drive circuit 5 during period TP22 when the comparison circuit 41 outputs an L-level comparison result.

[0064] When input node 41a of the comparison circuit 41 is an inverting input node and input node 41b is a non-inverting input node, the control unit 46 supplies an active-level control signal OFF_CTR to the drive circuit 5 during period TP11 when the comparison circuit 41 outputs a comparison result at an L level. The control unit 46 supplies a non-active-level control signal OFF_CTR to the drive circuit 5 during period TP12 when the comparison circuit 41 outputs a comparison result at an H level.

[0065] The drive circuit 5 has an input node 5a, an output node 5b, and a control node 5c. The input node 5a is connected to the INPUT terminal. The output node 5b is connected to the control terminal G of the power transistor PT. The control node 5c is connected to the protection circuit 4.

[0066] While the drive circuit 5 receives a non-active level control signal Shutdown, it generates a drive signal DRV that switches in response to the input signal IN and supplies it to the control terminal G of the power transistor PT. This allows the power transistor PT to be switched.

[0067] When the drive circuit 5 receives the active-level control signal Shutdown, it generates a drive signal DRV that keeps the power transistor PT in the off state, regardless of the input signal IN, and supplies it to the control terminal G of the power transistor PT. This keeps the power transistor PT in the off state. As a result, the power transistor PT can be protected from overcurrents generated in the load LD.

[0068] In the semiconductor device 1 shown in Figure 1, DESAT detection is performed during the period from timing t4 to t8, as shown in Figure 3. Figure 3 is a waveform diagram showing the operation of the semiconductor device 1.

[0069] During the period from timing t4 to t8, protection circuit 4 is activated, and DESAT detection by protection circuit 4 is enabled. The DESAT detection period (t4 to t8) is within the period from timing t4 to t10 when power device PT is ON.

[0070] In DESAT detection, when excessive current flows into the power device PT while it is ON, the protection circuit 4 checks the voltage V at one end D of the power device PT. D The system detects an increase that exceeds the threshold voltage Vth2. In Figure 3, during the period from timing t4 to t8, the voltage V D The threshold voltage Vth2 is maintained below this level, and the voltage V D An example is when an increase exceeding the threshold voltage Vth2 is not detected.

[0071] Note that the voltage V is not shown in the diagram. D If an increase exceeding the threshold voltage Vth2 is detected, the protection circuit 4 will, accordingly, transition the control signal OFF_CTR to the active level and supply it to the drive circuit 5. In response, the drive circuit 5 will supply the drive signal V GATE_DRIVE The state is transitioned to a non-active level (e.g., L level), and the power device PT is turned off. This controls the power device PT to turn off.

[0072] The start timing for "DESAT enabled," which enables DESAT detection, is determined when the input signal INPUT becomes active (e.g., high level), and accordingly, the drive signal V of the power device PT is activated. GATE_DRIVE The decision is triggered by the timing t1 when the drive signal V reaches an active level (e.g., H level). GATE_DRIVE The period t1 to t8 during which the signal is maintained at the active level is referred to as the "on control signal".

[0073] At this time, as shown in Figure 3, the drive signal V GATE_DRIVE The voltage V at the control terminal G is measured after the voltage reaches the active level. G The delay time Td1 corresponds to the dead time until the voltage V begins to rise, and the voltage V G There exists a delay time Td2 which corresponds to the switching time from when the voltage starts to rise until the power device PT transitions to the ON state.

[0074] Here, the dead time and switching time are measured in advance, and the blanking time T is defined as the delay time (= dead time + switching time) from the trigger timing t1 to the start timing of "DESAT enabled". BLANK It is conceivable to determine this experimentally in advance and then permanently set it in the protection circuit 4.

[0075] For example, in the protection circuit 4, the timer 461 of the control unit 46 is set in advance for a blanking time T BLANK A predetermined value may be set accordingly. In this case, immediately before timing t1, the protection circuit 4 sets the count value of timer 461 to an initial value and sets the control signal MASK2 to an active level. When the protection circuit 4 detects the rising edge of the waveform of the input signal INPUT, it starts the counting operation of timer 461, and when the count value reaches a predetermined value, it sets the control signal MASK2 to a non-active level to turn off switch 45 and activate DESAT detection.

[0076] However, of the dead time and switching time, at least the switching time tends to vary due to factors such as manufacturing variations of power devices (PTs) and ambient temperature.

[0077] Fixed blanking time T BLANK If the blanking time T is longer than the actual "dead time + switching time", the power device PT will transition to the ON state. BLANKDESAT detection is not possible during the period until this time has elapsed. If excessive current flows into the ON-state power device PT during this period, the power device PT may be damaged. In other words, it may become difficult to properly perform DESAT detection.

[0078] Fixed blanking time T BLANK If the blanking time T is shorter than the actual "dead time + switching time", the power device PT is in the off state. BLANK This period may elapse, potentially leading to a false detection of DESAT. During this time, even though no excessive current flows into the power device PT, the voltage V at terminal D remains off because the power device PT is in the off state. D If the threshold voltage Vth is exceeded, there is a possibility of a false detection of a DESAT occurring. In other words, it may become difficult to properly detect a DESAT.

[0079] Therefore, in semiconductor device 1, the voltage V at one end D of the power device PT D The falling edge is detected by the detection circuit 3, and the DESAT detection by the protection circuit 4 is activated according to the detection timing, thereby optimizing the start timing of DESAT activation.

[0080] For example, immediately before timing t1, detection circuit 3 sets the control signal MASK1 to an active level and keeps switch 35 in the ON state. This disables the waveform falling edge detection by detection circuit 3. Detection circuit 3 sets the control signal EN_DESAT to a non-active level. Protection circuit 4 sets the control signal MASK2 to an active level and keeps switch 45 in the ON state. This disables DESAT detection by protection circuit 4.

[0081] At timing t1, when the rising edge of the input signal INPUT waveform is detected, the drive circuit 5 controls the drive signal V GATE_DRIVE Set it to the active level.

[0082] Further, when detecting a rising edge of the waveform of the input signal INPUT, the detection circuit 3 sets the control signal MASK1 to an inactive level and turns off the switch 35. In response, the detection circuit 3 detects the voltage V at one terminal D of the power device PT D , falling edge detection of the waveform thereof is enabled. That is, the detection circuit 3 enters a state capable of detecting the falling edge of the waveform of the voltage V D .

[0083] At this time, the power device PT is off, and the voltage V at one terminal D D is maintained at a predetermined level (for example, H level). In response, the rectifying element D DET is cut off, the current from the current source 33 is charged into the capacitive element 34, the voltage at the terminal VDDET is higher than the threshold voltage Vth1, and the comparison result V of the comparison circuit 31 31 becomes H level. Until an active-level control signal EN_DESAT is received from the detection circuit 3, the protection circuit 4 sets the control signal MASK2 to an active level and maintains the switch 45 in an on state, so the voltage at the terminal DESAT is lower than the threshold voltage Vth2, and the comparison result V of the comparison circuit 41 41 is at L level.

[0084] At timing t2, the voltage V at the control terminal G G starts to rise, the power device PT starts to turn on in response thereto, and at timing t3, the voltage V at one terminal D D starts to decrease.

[0085] At timing t4, when the voltage V at one terminal D D falls below the threshold voltage Vth1, the comparison result V of the comparison circuit 31 31 is inverted. That is, the detection circuit 3 detects the falling edge of the waveform of the voltage V at one terminal D D . In response, the detection circuit 3 sets the control signal EN_DESAT to an active level and supplies it to the protection circuit 4.

[0086] In response to the active level control signal EN_DESAT, the protection circuit 4 sets the control signal MASK2 to a non-active level and turns off switch 45. Accordingly, DESAT detection is enabled in the protection circuit 4. That is, the protection circuit 4 becomes capable of detecting the DESAT of the power device PT. In Figure 3, the blanking period from timing t1 to t4 is labeled "blanking".

[0087] Immediately afterward, at timing t5, the transition of the power device PT to the ON state is completed.

[0088] At timing t7, the voltage V at the control terminal G G The temperature reaches a predetermined level (e.g., level H) and is maintained there.

[0089] At timing t8, when the falling edge of the waveform of the input signal INPUT is detected, the drive circuit 5 controls the drive signal V GATE_DRIVE Set it to a non-active level. In Figure 3, the drive signal V GATE_DRIVE The period t1 to t8 during which the signal is maintained at the active level is referred to as the "on control signal".

[0090] Furthermore, when the falling edge of the waveform of the input signal INPUT is detected, the detection circuit 3 sets the control signal MASK1 to an active level and turns on switch 35. This once again disables the waveform falling edge detection by the detection circuit 3. The detection circuit 3 then sets the control signal EN_DESAT to a non-active level and supplies it to the protection circuit 4. The protection circuit 4 sets the control signal MASK2 to an active level and turns on switch 45. This once again disables the DESAT detection by the protection circuit 4. In Figure 3, the period from timing t4 to t8 when DESAT detection is enabled is labeled "DESAT enabled".

[0091] At timing t9, the voltage V at control terminal G G As the voltage begins to fall, and accordingly, at the timing t10 ​​immediately afterward, the power device PT begins to turn off, and the voltage V at one end D Dstarts to rise. In FIG. 3, the period from timing t5 to t10 in which the power device PT is maintained in an on-state is described as "power device on-state".

[0092] At timing t11, the voltage V at one terminal D D reaches a predetermined level (e.g., H level) and is maintained.

[0093] At subsequent timing t12, the voltage V at the control terminal G G drops to a reference level (e.g., L level), and the transition of the power device PT to the off-state is completed.

[0094] As shown in FIG. 3, the transition timing of the power device PT to the on-state is determined from the detection result of the falling edge of the voltage V D at one terminal D of the power device PT, and is set as the activation timing for DESAT detection. This makes it possible to end the blanking time and start activating DESAT detection at a timing close to the completion of transition of the power device PT to the on-state, without being affected by manufacturing variations or temperature dependence of the power device PT.

[0095] As described above, in the embodiment, in the semiconductor device 1, the falling edge of the voltage V D at one terminal D of the power device PT is detected by the detection circuit 3, and DESAT detection by the protection circuit 4 is activated according to the detection timing. Accordingly, the start timing of DESAT activation can be optimized. In addition, the need for margin design for the activation timing of DESAT detection in a system is eliminated, the load of system design can be reduced, and quick turn-around time (QTAT) system design can be achieved.

[0096] Note that in the detection circuit 3 shown in FIG. 1, the capacitive element 34 may be omitted. In this case, the current source 33 charges its current to the parasitic capacitance of the line connecting the comparison circuit 31 and the terminal VDDET.

[0097] In the semiconductor device 1 shown in FIG. 1, the capacitive element C DESATThis may be omitted. In this case, the current source 43 of the protection circuit 4 will charge the parasitic capacitance of the line connecting the comparator circuit 41 and terminal DESAT with its current.

[0098] The control unit 46 of the protection circuit 4 shown in Figure 1 activates the control signal MASK2 in response to the control signal EN_DESAT received from the detection circuit 3, without using a timer 461. For this reason, the timer 461 may be omitted in the control unit 46.

[0099] (First modified example of the embodiment) Also, the voltage V at one end D of the power device PT D When DESAT detection is enabled by detecting a falling edge, depending on the timing of a failure or malfunction of the load (e.g., inverter device) LD, the voltage V at one end D may be affected when the power device PT is turned on. D It is also possible that the voltage does not fall down. Therefore, the voltage V at one end D D You may also record a history of the falling edge detection time and enable DESAT detection based on past time history.

[0100] In the semiconductor device 1i, the detection circuit 3i of the semiconductor integrated circuit 2i may have a control unit 36i instead of the control unit 36 ​​(see Figure 1), as shown in Figure 4. Figure 4 is a diagram showing the configuration of the semiconductor device 1i according to a first modified example of the embodiment. The control unit 36i has a time history generation unit 361i.

[0101] In the control unit 36i, the time history generation unit 361i calculates the comparison result V from the comparison circuit 31 from the rising edge of the waveform of the input signal INPUT. 31 The time until the waveform reverses is measured and the measured time Δt is stored. The time history generation unit 361i generates a control signal EN_DESAT to activate the protection circuit 4 and supplies it to the protection circuit 4 when a predetermined time has elapsed corresponding to the time Δt (see Figure 3) measured from the rising edge of the waveform of the input signal INPUT. The predetermined time is the history time Δt plus an offset time t offset The time may also be the sum of the offset time t. offsetAny time greater than 0 can be used.

[0102] The time history generation unit 361i may be configured as shown in Figure 5. Figure 5 is a circuit diagram showing the configuration of the time history generation unit 361i in a first modified example of the embodiment.

[0103] The time history generation unit 361i includes a counter 361i1, a latch circuit 361i2, an adder 361i3, a setting circuit 361i4, and a timer 361i5.

[0104] Counter 361i1 has node S￣ connected to terminal INPUT and node S￣ of counter 361i1, node E connected to comparator circuit 31, and node O connected to node D of latch circuit 36ii2. Counter 361i1 has a voltage V at terminal D. D Count the falling time of the voltage V at one end D. D The fall time is the transition of the input signal INPUT from low level to high level to the voltage V at one end. D This is the time until the falling edge is detected. In other words, the counter 361i1 starts counting in response to the rising edge of the input signal INPUT received at node S, and the comparison result V of the comparison circuit 31 received at node E. 31 The counting operation terminates in response to the reversal. Counter 361i1 outputs the count value to latch circuit 361i2. The count value represents the time Δt measured by counter 361i1.

[0105] The latch circuit 361i2 has node CK connected to terminal INPUT and node Q connected to adder 361i3. The falling edge time of the voltage VD at one end, counted by counter 361i1, is held in the latch circuit 361i2 at the timing of the transition from high level to low level of the input signal INPUT. In other words, the latch circuit 361i2 latches the count value of counter 361i1 in accordance with the falling edge of the input signal INPUT received at node CK, and outputs the latched value from node Q to adder 361i3.

[0106] The setting circuit 361i4 has an output node connected to the adder 361i3. The setting circuit 361i4 has an offset time t offset This is set in advance. The setting circuit 361i4 has an offset time t offset The value indicating this is output to adder 361i3.

[0107] Adder 361i3 has its first input node connected to latch circuit 361i2, its second input node connected to setting circuit 361i4, and its output node connected to node E of timer-361i5. Adder 361i3 takes a latched value (i.e., a value indicating the measured time Δt) and an offset time t offset The value shown is added to the value shown, and the summed value is output to timer 361i5. The summed value is set for a predetermined time Δt+t offset This indicates.

[0108] Timer-361i5 has node O connected to protection circuit 4. Timer-361i5 receives the sum result value at node G. In the reset state, Timer-361i5 outputs the non-active bell control signal EN_DESAT from node O to protection circuit 4. Timer-361i5 starts counting in response to the rising edge of the input signal INPUT received at node S, and when the count value reaches the sum result value received at node G, it terminates the counting operation and transitions the control signal EN_DESAT to the active level and supplies it to protection circuit 4.

[0109] For example, the time history generation unit 361i may operate as shown in Figure 6. Figure 6 is a waveform diagram showing the operation of the time history generation unit 361i in a first modified example of the embodiment.

[0110] At timing t21, the counter 361i1 of the time history generation unit 361i starts counting for time Δt in response to the rising edge of the input signal INPUT. The timer 361i5 starts counting for a predetermined time (Δt0+t) in response to the rising edge of the input signal INPUT. offset The counting operation of ) begins. Δt0 is the time measured last time as Δt. The comparison circuit 31 shows the H level comparison result V31 It starts outputting.

[0111] At timing t22, counter 361i1 is the comparison result V of the comparison circuit 31. 31 As the signal level reverses from high to low, the counting operation for time Δt is terminated, and the count value measured for time Δt=Δt1 is output to the latch circuit 361i2.

[0112] From timing t21 to a predetermined time (Δt0+t) offset At timing t23, when the count value has elapsed, the timer 361i5 will set the count value to a predetermined time (Δt0+t offset It reaches a value corresponding to ).

[0113] Immediately after that, at timing t24, timer 361i5 supplies the control signal EN_DESAT to the protection circuit 4 at an active level. In response, DESAT is activated in the protection circuit 4.

[0114] At timing t25, the latch circuit 361i2 latches the count value of counter 361i1 in response to the falling edge of the input signal INPUT, and begins outputting the latched value to adder 361i3. In response, adder 361i3 begins outputting a value obtained by adding an offset to the latched value. The sum of the values ​​from adder 361i3 is output to timer 361i5 and set as the value to be counted by timer 361i5.

[0115] Timer 361i5 supplies the control signal EN_DESAT to the protection circuit 4 at a non-active level in response to the falling edge of the input signal INPUT. Accordingly, DESAT is disabled in the protection circuit 4.

[0116] At timing t26, the counter 361i1 of the time history generation unit 361i starts counting for time Δt in response to the rising edge of the input signal INPUT. The timer 361i5 starts counting for a predetermined time (Δt1+t) in response to the rising edge of the input signal INPUT. offsetThe counting operation of ) begins. Δt1 is the time measured as Δt in the previous measurement. The comparison circuit 31 shows the comparison result V at the H level. 31 It starts outputting.

[0117] At timing t27, counter 361i1 is the comparison result V of the comparison circuit 31. 31 As the signal level reverses from high to low, the counting operation for time Δt is terminated, and the count value measured for time Δt=Δt2 is output to the latch circuit 361i2.

[0118] From timing t26 to a predetermined time (Δt1+t offset At timing t28, when the count value has elapsed, the timer 361i5 will set the count value to a predetermined time (Δt1+t offset It reaches a value corresponding to ).

[0119] Immediately afterward, at timing t29, timer 361i5 supplies the control signal EN_DESAT to the protection circuit 4 at an active level. In response, DESAT is activated in the protection circuit 4.

[0120] At timing t30, the latch circuit 361i2 latches the count value of counter 361i1 in response to the falling edge of the input signal INPUT, and begins outputting the latched value to adder 361i3. In response, adder 361i3 begins outputting a value obtained by adding an offset to the latched value. The sum of the values ​​from adder 361i3 is output to timer 361i5 and set as the value to be counted by timer 361i5.

[0121] Timer 361i5 supplies the control signal EN_DESAT to the protection circuit 4 at a non-active level in response to the falling edge of the input signal INPUT. Accordingly, DESAT is disabled in the protection circuit 4.

[0122] Thus, in semiconductor device 1i, the detection circuit 3i detects the voltage V at one end D. DThe detection history of the falling edge is recorded, and DESAT detection is enabled based on the past time history. For example, detection circuit 4 enables DESAT detection using a predetermined time obtained by adding an offset tooffset that takes fluctuations into account to the time Δt measured immediately before. This also allows for the optimization of the start timing of DESAT activation.

[0123] (Second modified example of the embodiment) Alternatively, the operation of the embodiment and the operation of the first modified example may be combined to determine the start timing of "DESAT enabled," which enables DESAT detection. For example, the start timing of "DESAT enabled" is determined by the falling timing of the voltage VD at one end D of the power transistor PT and a predetermined time (Δt+t) from the rising edge of the waveform of the input signal INPUT. offset You may also choose to correspond to the earlier of the following two timings: the time when ) has elapsed or the time when ) has elapsed.

[0124] In this case, in the semiconductor device 1j, the detection circuit 3j of the semiconductor integrated circuit 2j may have a control unit 36j instead of a control unit 36i (see Figure 4), as shown in Figure 7. Figure 7 is a diagram showing the configuration of the semiconductor device 1j according to a second modified example of the embodiment.

[0125] The control unit 36j processes the comparison result V from the comparison circuit 31. 31 The waveform inverts, or a predetermined time (Δt+t) is taken from the rising edge of the input signal INPUT waveform. offset As time passes, the control unit 36j generates a control signal EN_DESAT to activate the protection circuit 4. For example, the control unit 36j receives the comparison result V from the comparison circuit 31. 31 The timing of the inversion and the predetermined time (Δt+t) from the rising edge of the input signal INPUT waveform offset Depending on the earlier of the timing when ) has elapsed, a control signal EN_DESAT to activate the protection circuit 4 may be generated.

[0126] The control unit 36j may further include an operator 362j. The operator 362j has a first input node connected to the output node 31c of the comparison circuit 31, a logic inversion of the second input node connected to the output node of the time history generation unit 361i, and the output node connected to the protection circuit 4.

[0127] The logical OR operator 362j is used to obtain the comparison result V from the comparison circuit 31. 31 The logical inversion of the signal and the control signal EN_DESAT (see Figure 5) output by the time history generation unit 361i are calculated as a logical OR, and the control signal EN_DESAT is generated as the result of the calculation. The control signal EN_DESAT is calculated by the falling timing of the voltage VD at one end D of the power transistor PT and a predetermined time (Δt+t) determined by the time history generation unit 361i. offset The transition from non-active level to active level occurs at the earlier of the following timings: the falling edge timing of the voltage VD at one end D of the power transistor PT and a predetermined time (Δt+t) determined by the time history generation unit 361i. offset ) can be done at whichever is earlier.

[0128] Thus, in the semiconductor device 1j, the detection circuit 3j detects the comparison result V of the comparison circuit 31. 31 The waveform inverts, or a predetermined time (Δt+t) is taken from the rising edge of the input signal INPUT waveform. offset As time progresses, a control signal EN_DESAT is generated to activate the protection circuit 4. This also allows for optimizing the start timing of DESAT activation.

[0129] (Third modified example of the embodiment) The semiconductor device 1k may have a simplified configuration, as shown in Figure 8. Figure 8 shows the configuration of the semiconductor device 1k according to a third modified example of the embodiment.

[0130] The semiconductor integrated circuit 2k of the semiconductor device 1k is formed by merging the detection circuit 3 and the protection circuit 4 (see Figure 1) to create a protection circuit 4k that includes the detection circuit 3k. The detection circuit 3k omits the current source 33, the capacitive element 34, the switch 35, and the control unit 36. The protection circuit 4k has a control unit 46k instead of the control unit 46 (see Figure 1).

[0131] The control unit 46k has additional functions compared to the control unit 36. When the comparison result of the comparison circuit 31 is inverted, the control unit 46k activates the protection circuit 4k and enables DESAT detection by the protection circuit 4k.

[0132] Furthermore, the semiconductor device 1k includes a capacitive element C DESAT (See Figure 1) is omitted, and instead the protection circuit 4k is replaced with a capacitive element C DESAT1 A capacitive element C is added. DESAT1 The capacitance value is required for detecting the falling edge of the voltage at one end D of the power device PT, which is the capacitance element C. DESAT1 This can be predetermined depending on the charging characteristics.

[0133] In this way, a protection circuit 4k including a detection circuit 3k is configured in the semiconductor integrated circuit 2k of the semiconductor device 1k, simplifying the configuration. As a result, the circuit size of the semiconductor integrated circuit 2k can be reduced, which in turn allows for space saving in the semiconductor device 1k and lowers the cost of the semiconductor device 1k.

[0134] In the configuration shown in Figure 8, the capacitive element C DESAT1 This can be omitted. In this case, the current source 43 of the protection circuit 4k will charge the parasitic capacitance of the line connecting the comparator circuit 41 and terminal DESAT with its current.

[0135] (Fourth modified example of the embodiment) The semiconductor device 1n may have a simplified configuration, as shown in Figure 9. Figure 9 shows the configuration of the semiconductor device 1n according to a fourth modification of the embodiment.

[0136] In the semiconductor device 1n, the semiconductor integrated circuit 2n is formed by merging the detection circuit 3i and the protection circuit 4 (see Figure 4) to create a protection circuit 4n that includes the detection circuit 3n. The detection circuit 3n omits the current source 33, the capacitive element 34, the switch 35, and the control unit 36i. The protection circuit 4n has a control unit 46n instead of the control unit 46i (see Figure 4).

[0137] The control unit 46n has additional functions compared to the control unit 36i. The control unit 46n detects the rise of the waveform of the input signal INPUT for a predetermined time (Δt+t offset As time elapses, the protection circuit 4n is activated, and DESAT detection by the protection circuit 4n is enabled. For example, the control unit 46n determines the time elapsed from the rising edge of the waveform of the input signal INPUT to a predetermined time (Δt+t offset As time passes, DESAT detection is enabled. This puts the protection circuit 4n into a state where DESAT detection of the power transistor PT is possible.

[0138] Furthermore, the semiconductor device 1n includes a capacitive element C DESAT (See Figure 1) is omitted, and instead the protection circuit 4k is replaced with a capacitive element C DESAT1 A capacitive element C is added. DESAT1 The capacitance value is required for detecting the falling edge of the voltage at one end D of the power device PT, which is the capacitance element C. DESAT1 This can be predetermined depending on the charging characteristics.

[0139] Thus, in the semiconductor integrated circuit 2n of the semiconductor device 1n, a protection circuit 4n including a detection circuit 3n is configured, simplifying the configuration. As a result, the circuit size of the semiconductor integrated circuit 2n can be reduced, allowing for a more compact semiconductor device 1n and lowering its cost.

[0140] In the configuration shown in Figure 9, the capacitive element C DESAT1 This can be omitted. In this case, the current source 43 of the protection circuit 4n will charge the parasitic capacitance of the line connecting the comparator circuit 41 and terminal DESAT with its current.

[0141] (Fifth modified example of the embodiment) The semiconductor device 1p may have a simplified configuration, as shown in Figure 10. Figure 10 shows the configuration of the semiconductor device 1p according to a fifth modification of the embodiment.

[0142] In semiconductor device 1p, the semiconductor integrated circuit 2p is formed by merging the detection circuit 3j and the protection circuit 4 (see Figure 7) to create a protection circuit 4p that includes the detection circuit 3p. The detection circuit 3p omits the current source 33, capacitive element 34, switch 35, and control unit 36j. The protection circuit 4p has a control unit 46p instead of the control unit 46j (see Figure 7).

[0143] Control unit 46p has additional functions added to control unit 36j. Control unit 46p detects when the comparison result of the comparison circuit 31 is inverted, or when a predetermined time (Δt+t) has elapsed from the rising edge of the waveform of the input signal INPUT. offset As time elapses, the protection circuit 4p is activated, and DESAT detection by the protection circuit 4p is enabled. For example, the control unit 46p determines the time elapsed from the rising edge of the waveform of the input signal INPUT to a predetermined time (Δt+t offset As time passes, for example, the control unit 46p determines the start timing of "DESAT enabled" based on the falling timing of the voltage VD at one end D of the power transistor PT and a predetermined time (Δt+t) determined by the time history generation unit 361i. offset DESAT detection can be enabled at the earlier of the two timings. This allows the protection circuit 4p to be in a state where DESAT detection of the power transistor PT is possible.

[0144] Furthermore, the semiconductor device 1k includes a capacitive element C DESAT (See Figure 1) is omitted, and instead the protection circuit 4k is replaced with a capacitive element C DESAT1 A capacitive element C is added. DESAT1 The capacitance value is required for detecting the falling edge of the voltage at one end D of the power device PT, which is the capacitance element C. DESAT1 This can be predetermined depending on the charging characteristics.

[0145] In this way, a protection circuit 4p including a detection circuit 3p is configured in the semiconductor integrated circuit 2p of the semiconductor device 1p, simplifying the configuration. As a result, the circuit size of the semiconductor integrated circuit 2p can be reduced, which in turn allows for space saving in the semiconductor device 1p and lowers the cost of the semiconductor device 1p.

[0146] In the configuration shown in Figure 10, the capacitive element C DESAT1 This may be omitted. In this case, the current source 43 of the protection circuit 4p will charge the parasitic capacitance of the line connecting the comparator circuit 41 and terminal DESAT with its current.

[0147] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of symbols]

[0148] 1,1i,1j,1k,1n,1p semiconductor devices, 2,2i,2j,2k,2n,2p semiconductor integrated circuits, 3,3i,3j,3k,3n,3p detection circuits, 4,4k,4n,4p protection circuits.

Claims

1. A comparison circuit having a first input node connected to the high-voltage terminal of a power device having a control terminal, a high-voltage terminal, and a low-voltage terminal, a second input node connected to a threshold voltage corresponding to the falling edge of the voltage waveform of the high-voltage terminal of the power device, and an output node, A signal generation circuit having a first input node connected to the output node of the comparison circuit, a second input node, and an output node connected to the control node of a protection circuit which has an input node, a control node, and an output node connected to the control terminal of the power device via a drive circuit, and which is capable of detecting when an overcurrent has started to flow through the power device and performing a protection operation to turn off the power device accordingly, Equipped with, The second input node of the signal generation circuit is connected to the input node of the protection circuit. The comparison circuit outputs a first comparison result if the voltage at the high-voltage terminal of the power device is higher than the threshold voltage, and outputs a second comparison result if the voltage at the high-voltage terminal of the power device is lower than the threshold voltage. The signal generation circuit measures a first time interval between a first timing when the waveform of the input signal supplied to the input node of the protection circuit rises and a second timing when the comparison result of the comparison circuit transitions from the first comparison result to the second comparison result. If a second time interval corresponding to the first time interval has not elapsed from the first timing interval, the circuit outputs a control signal to the control node of the protection circuit instructing the deactivation of the protection operation. If the second time interval has elapsed from the first timing interval, or if the comparison result of the comparison circuit inverts, the circuit outputs a control signal to the control node of the protection circuit instructing the activation of the protection operation. Detection circuit.

2. The detection circuit according to claim 1, A protection circuit having an input node connected to the high-voltage terminal of a power device having a control terminal, a high-voltage terminal, and a low-voltage terminal, a control node connected to the output node of the detection circuit, and an output node connected to the control terminal of the power device, A drive circuit having an input node connected to an input terminal, a control node connected to the output node of the protection circuit, and an output node connected to the control terminal of the power device, A semiconductor integrated circuit equipped with [a specific feature / ability].

3. The semiconductor integrated circuit according to claim 2, A first rectifier element connected between the detection circuit and one end of the power device, A second rectifier element connected between the protection circuit and one end of the power device, A semiconductor device equipped with the following features.

4. A power device having a control terminal, a high-voltage terminal, and a low-voltage terminal, which compares the voltage of the high-voltage terminal with a threshold voltage corresponding to the falling edge of the voltage waveform of the high-voltage terminal of the power device, The protection circuit is capable of detecting when an overcurrent has started to flow through the power device and performing a protection operation to turn off the power device accordingly, and measures a first time between the first timing at which the waveform of the input signal supplied to the input node of the protection circuit is raised and the second timing at which the result of the comparison is reversed, the protection circuit having an input node, a control node and an output node connected to the control node of the drive circuit connected to the control terminal of the power device, In response to the fact that a second time corresponding to the first time has not elapsed from the first timing, a control signal instructing the disabling of the protection operation is output to the control node of the protection circuit, Depending on the elapsed time from the first timing, or depending on the reversal of the comparison result, a control signal instructing the activation of the protection operation is output to the control node of the protection circuit, A control method including

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