Amplifier circuit

Abstract

To keep a rise settling time and a fall settling time short in an amplifier circuit.SOLUTION: An amplifier circuit includes a first transistor of a first conductivity type having a first control terminal, a second transistor of a second conductivity type different from the first conductivity type and having a second control terminal connected to the input terminal and a fourth current terminal connected to the first control terminal, a third transistor, and a fourth transistor of a fourth conductivity type different from the first conductivity type, having a fourth control terminal connected to the first control terminal at an equal potential, and a seventh current terminal connected to the third fixed potential.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The technology disclosed in this specification relates to amplification circuits and composite circuits. [Background technology]

[0002] In electronic circuits, there is a demand for amplifier circuits that have low output impedance and high driving force for the output load. One example of such an amplifier circuit is the super-source follower (SSF) circuit.

[0003] The SSF circuit is an inverted Darlington circuit in which the bipolar junction transistor (BJT) is replaced with a field-effect transistor (FET).

[0004] For example, Japanese Patent Publication No. 2013-179077 (i.e., Patent Document 1) discloses an SSF circuit comprising an input transistor, a current source load transistor, a current source transistor composed of a P-type metal-oxide-semiconductor field-effect transistor (i.e., MOSFET), and a feedback transistor composed of a P-type MOSFET. Also, for example, International Publication No. 2019 / 107084 (i.e., Patent Document 2) discloses a low-output impedance Class AB SSF circuit. [Prior art documents] [Patent Documents]

[0005] [Patent Document 1] Japanese Patent Publication No. 2013-179077 [Patent Document 2] International Publication No. 2019 / 107084 [Overview of the project] [Problems that the invention aims to solve]

[0006] However, in the SSF circuit disclosed in Patent Document 1, large overshoot and undershoot occur in the rising and falling edges of the output waveform, resulting in longer rising and falling edge settling times.

[0007] The technology disclosed in this specification was developed in consideration of the problems described above, and is a technology for reducing the rise time and fall time in an amplifier circuit. [Means for solving the problem]

[0008] An amplifier circuit, which is a first aspect of the technology disclosed in this specification, is an amplifier circuit that amplifies a signal input to an input terminal and outputs it to an output terminal, and comprises: a first transistor which is a field-effect transistor of a first conductivity type having a first control terminal which is a gate terminal, a first current terminal which is a source terminal connected to a first potential, and a second current terminal which is a drain terminal connected to the output terminal; a second transistor which is a field-effect transistor of a second conductivity type different from the first conductivity type having a second control terminal which is a gate terminal connected to the input terminal, a third current terminal which is a source terminal, and a fourth current terminal which is a drain terminal connected to the first control terminal which is the gate terminal of the first transistor; a third control terminal which is a gate terminal connected to a first fixed potential, a fifth current terminal which is a source terminal connected to a second potential, and a drain terminal connected to the third current terminal which is the source terminal of the second transistor The device comprises: a third transistor which is a field-effect transistor of a second conductivity type and has a sixth current terminal; a fourth transistor which is a field-effect transistor of a second conductivity type and has a fourth control terminal which is a gate terminal connected at the same potential as the first control terminal which is the gate terminal of the first transistor; a seventh current terminal which is a source terminal connected to a third fixed potential; and an eighth current terminal which is a drain terminal connected to the output terminal; a current source element which supplies current to the fourth current terminal which is the drain terminal of the second transistor; a differential amplifier whose first differential input terminal is connected to the connection point between the third current terminal which is the source terminal of the second transistor and the sixth current terminal which is the drain terminal of the third transistor, and whose second differential input terminal is connected to the output terminal; and a switch which can switch whether or not to connect the first differential input terminal and the second differential input terminal of the differential amplifier. [Effects of the Invention]

[0009] According to at least a first aspect of the technology disclosed in this specification, the rise time and fall time can be shortened in an amplification circuit.

[0010] Furthermore, the purposes, features, aspects, and advantages related to the technology disclosed in this specification will become even clearer from the detailed description and accompanying drawings provided below. [Brief explanation of the drawing]

[0011] [Figure 1] This figure schematically shows an example of the configuration of an amplifier circuit according to an embodiment. [Figure 2] This figure shows an example of a conventional source follower circuit configuration. [Figure 3] Figure 2 shows an example of a small-signal equivalent circuit of a source follower circuit. [Figure 4] This figure shows an example of the configuration of an SSF circuit. [Figure 5] Figure 4 shows an example of a small-signal equivalent circuit of the SSF circuit. [Figure 6] This figure shows an example of a small-signal equivalent circuit of the amplifier circuit shown in Figure 1. [Figure 7] This is a schematic diagram showing an example of the output waveform of an amplifier circuit. [Figure 8] This figure shows an example of the configuration of an amplifier circuit relating to a first modified example of the embodiment. [Figure 9] This figure shows an example of the configuration of an amplifier circuit according to a second modified example of the embodiment. [Figure 10] This graph shows the relationship between input voltage and through-current in a CMOS inverter consisting of feedback P-type FETs and feedback N-type FETs. [Figure 11] This figure shows an example of the configuration of an amplification circuit according to an embodiment. [Figure 12] This figure shows an example of a conventional source follower circuit configuration. [Figure 13] This figure shows an example of a small-signal equivalent circuit of the source follower circuit shown in Figure 12. [Figure 14] This figure shows an example of the configuration of an SSF circuit. [Figure 15] Figure 14 shows an example of a small-signal equivalent circuit of an SSF circuit. [Figure 16] This figure shows an example of a small-signal equivalent circuit of the amplifier circuit shown in Figure 11. [Figure 17] This figure shows an example of the configuration of an amplifier circuit relating to a first modified example of the embodiment. [Figure 18] This figure shows an example of the configuration of an amplifier circuit according to a second modified example of the embodiment. [Figure 19] This figure shows an example of the configuration of an amplification circuit according to an embodiment. [Figure 20] This figure shows an example of a small-signal equivalent circuit of the amplifier circuit shown in Figure 19. [Figure 21] This figure shows an example of the configuration of an amplifier circuit according to the embodiment. [Figure 22] This figure shows an example of a small-signal equivalent circuit of the amplifier circuit shown in Figure 21. [Figure 23] This figure shows an example of the configuration of an amplifier circuit according to the embodiment. [Figure 24] This figure shows an example of the configuration of a conventional FET input ID circuit. [Figure 25] Figure 24 shows an example of a small-signal equivalent circuit for an FET input ID circuit. [Figure 26] This figure shows an example of a small-signal equivalent circuit of the amplifier circuit shown in Figure 23. [Figure 27] This figure shows an example of the configuration of an amplifier circuit according to the embodiment. [Figure 28] This figure shows an example of the configuration of a conventional FET input ID circuit. [Figure 29] Figure 28 shows an example of a small-signal equivalent circuit for an FET input ID circuit. [Figure 30] This figure shows an example of a small-signal equivalent circuit of the amplifier circuit shown in Figure 27. [Figure 31] This figure shows an example of the configuration of an amplifier circuit according to the embodiment. [Figure 32] This figure shows an example of a conventional emitter follower circuit configuration. [Figure 33] This figure shows an example of a small-signal equivalent circuit of the emitter follower circuit shown in Figure 32. [Figure 34] This figure shows an example of a conventional ID circuit configuration. [Figure 35] This figure shows an example of a small-signal equivalent circuit for the ID circuit in Figure 34. [Figure 36] This figure shows an example of a small-signal equivalent circuit of the amplifier circuit shown in Figure 31. [Figure 37] This figure shows an example of the configuration of an amplifier circuit according to the embodiment. [Figure 38] This figure shows an example of a conventional emitter follower circuit configuration. [Figure 39] This figure shows an example of a small-signal equivalent circuit of the emitter follower circuit shown in Figure 38. [Figure 40] This figure shows an example of a conventional ID circuit configuration. [Figure 41] This figure shows an example of a small-signal equivalent circuit for the ID circuit in Figure 40. [Figure 42] This figure shows an example of a small-signal equivalent circuit of the amplifier circuit shown in Figure 37. [Figure 43] This figure shows an example of the configuration of an amplifier circuit according to the embodiment. [Figure 44] This figure shows an example of a small-signal equivalent circuit of the amplifier circuit shown in Figure 43. [Figure 45] This figure shows an example of the configuration of an amplifier circuit according to the embodiment. [Figure 46] This figure shows an example of a small-signal equivalent circuit of the amplifier circuit shown in Figure 45. [Figure 47] This figure shows an example of the configuration of an amplifier circuit according to the embodiment. [Figure 48] This figure shows an example of a small-signal equivalent circuit of the amplifier circuit shown in Figure 47. [Figure 49] This figure shows an example of the configuration of an amplifier circuit according to the embodiment. [Figure 50] This figure shows an example of a small-signal equivalent circuit of the amplifier circuit shown in Figure 49. [Figure 51] This figure shows a modified version of the configuration shown in Figure 1. [Figure 52] This figure shows a modified example of the configuration shown in Figure 2. [Figure 53] This figure shows a modified example of the configuration shown in Figure 3. [Figure 54]This figure shows a modified version of the configuration shown in Figure 11. [Figure 55] This figure shows a modified example of the configuration shown in Figure 17. [Figure 56] This figure shows a modified version of the configuration shown in Figure 18. [Figure 57] This figure shows a modified example of the configuration shown in Figure 19. [Figure 58] This figure shows a modified example of the configuration shown in Figure 21. [Figure 59] This figure shows a modified example of the configuration shown in Figure 23. [Figure 60] This figure shows a modified example of the configuration shown in Figure 27. [Figure 61] This figure shows a modified example of the configuration shown in Figure 31. [Figure 62] This figure shows a modified example of the configuration shown in Figure 37. [Figure 63] This figure shows a modified example of the configuration shown in Figure 43. [Figure 64] This figure shows other variations of the configuration shown in Figure 43. [Figure 65] This figure shows a modified example of the configuration shown in Figure 45. [Figure 66] This figure shows other variations of the configuration shown in Figure 45. [Figure 67] This figure shows a modified example of the configuration shown in Figure 47. [Figure 68] This figure shows other variations of the configuration shown in Figure 47. [Figure 69] This figure shows a modified example of the configuration shown in Figure 49. [Figure 70] This figure shows other variations of the configuration shown in Figure 49. [Modes for carrying out the invention]

[0012] The embodiments will be described below with reference to the attached drawings. In the following embodiments, detailed features will be shown for the purpose of explaining the technology, but these are illustrative, and not all of them are necessarily essential features for the embodiments to be implementable.

[0013] Please note that the drawings are for illustrative purposes only, and for the sake of clarity, some components may be omitted or simplified as appropriate. Furthermore, the relative sizes and positions of components shown in different drawings are not necessarily accurately represented and may be modified as appropriate. In addition, hatching may be used in drawings other than cross-sectional views, such as plan views, to facilitate understanding of the embodiment.

[0014] Furthermore, in the following explanations, similar components will be denoted by the same symbols, and their names and functions will also be the same. Therefore, detailed explanations of them may be omitted to avoid redundancy.

[0015] Furthermore, in the descriptions below, when a component is described as "having," "including," or "possessing," it is not an exclusive expression that excludes the existence of other components unless otherwise specified.

[0016] Furthermore, even if ordinal numbers such as "first" or "second" are used in the following descriptions, these terms are used for convenience to facilitate understanding of the embodiments and are not limited to the order that may result from these ordinal numbers.

[0017] <First Embodiment> The amplification circuit and composite circuit according to this embodiment will be described below.

[0018] <Regarding the configuration of the amplification circuit> Figure 1 is a schematic diagram showing an example of the configuration of an amplifier circuit 100 according to this embodiment. The amplifier circuit 100 is a form of source follower circuit. The amplifier circuit 100 can be used, for example, as an electronic circuit to drive an image sensor.

[0019] The amplification circuit 100 comprises a drive N-type FET 101, a load FET 102, a current source FET 103, a feedback P-type FET 104, and a feedback N-type FET 105. Here, the drive N-type FET 101, the load FET 102, and the feedback N-type FET 105 are all N-type FETs. The current source FET 103 and the feedback P-type FET 104 are all P-type FETs.

[0020] Here, "N-type" and "P-type," which represent the conductivity types of the FET, are examples of "first conductivity type," "second conductivity type," "third conductivity type," and "fourth conductivity type." The first conductivity type may be N-type and the second conductivity type may be P-type, or vice versa. Also, the first conductivity type may be N-type and the fourth conductivity type may be P-type, or vice versa.

[0021] The source (i.e., source terminal) of the load FET 102 is connected to GND, and the drain (i.e., drain terminal) of the load FET 102 is connected to the source of the drive N-type FET 101.

[0022] The drain of the current source FET 103 is connected to the drain of the drive N-type FET 101, and the source of the current source FET 103 is connected to the power supply.

[0023] In other words, the current source FET 103, the drive N-type FET 101, and the load FET 102 are connected in series between the power supply and GND.

[0024] Note that "power supply" above refers to the power supply terminal or power supply potential, and "GND" refers to the ground potential. "Power supply" and "GND" are examples of "first potential" and "second potential." The first potential may be the power supply and the second potential may be GND, or vice versa.

[0025] The gate (i.e., gate terminal) of the drive N-type FET 101 is connected to the input terminal IN of the amplification circuit 100. Additionally, a fixed potential V1 is input to the gate of the load FET 102. As a result, the load FET 102 functions as a constant current source.

[0026] Note that the "gate," "source," and "drain" of an FET are examples of "control terminals," "current terminals," etc.

[0027] The connection point between the source of the drive N-type FET 101 and the drain of the load FET 102 is connected to the output terminal OUT.

[0028] Furthermore, the source of the feedback P-type FET 104 is connected to the power supply, and the drain of the feedback P-type FET 104 is connected to the drain of the feedback N-type FET 105.

[0029] The source of the feedback N-type FET 105 is connected to a fixed potential V3. The gates of both the feedback P-type FET 104 and the feedback N-type FET 105 are connected at the same potential to the connection point between the drain of the current source FET 103 and the drain of the driving N-type FET 101.

[0030] Furthermore, the connection point between the drain of the feedback P-type FET 104 and the drain of the feedback N-type FET 105 is connected to the output terminal OUT.

[0031] <About the operation of the amplifier circuit> The small-signal operation of the amplifier circuit 100 will be explained in comparison with the small-signal operation of conventional source follower circuits and SSF circuits.

[0032] Figure 2 shows an example of the configuration of a conventional source follower circuit 110. In Figure 2, the source of the load FET 102 is connected to GND, and the drain of the load FET 102 is connected to the source of the drive N-type FET 101. The drain of the drive N-type FET 101 is also connected to the power supply.

[0033] In other words, the drive N-type FET 101 and the load FET 102 are arranged in series between the power supply and GND.

[0034] The connection point between the source of the drive N-type FET 101 and the drain of the load FET 102 is connected to the output terminal OUT. Furthermore, the gate of the load FET 102 is connected to a fixed potential V1, and the load FET 102 functions as a constant current source.

[0035] Compared to the amplifier circuit 100 shown in Figure 1, the source follower circuit 110 corresponds to a configuration in which the current source FET 103, feedback P-type FET 104, and feedback N-type FET 105 are omitted from the amplifier circuit 100.

[0036] Figure 3 shows an example of the small-signal equivalent circuit of the source follower circuit 110 shown in Figure 2. The output resistance of the source follower circuit 110 is expressed by the following equation (1).

[0037]

number

[0038] Here, r dn This indicates the output resistance of the drive N-type FET101, and r ln This indicates the output resistance of the load FET102, and gm dn This represents the transconductance of the drive N-type FET 101. In equation (1), the symbol " / / " is defined in the following equation (2).

[0039]

number

[0040] In an ideal FET without channel length modulation, r ln →∞, gm dn Since >>1, equation (1) can be approximated as equation (3) below.

[0041]

number

[0042] FIG. 4 is a diagram showing an example configuration of the SSF circuit 120. The SSF circuit 120 shown in FIG. 4 corresponds to a configuration obtained by adding a current source FET 103 and a feedback P-type FET 104 to the source follower circuit 110 shown in FIG. 3. Also, compared with the amplifier circuit 100 shown in FIG. 1, the SSF circuit 120 shown in FIG. 4 corresponds to a configuration obtained by omitting the feedback N-type FET 105 from the amplifier circuit 100.

[0043] FIG. 5 is a diagram showing an example of a small-signal equivalent circuit of the SSF circuit 120 shown in FIG. 4. From Kirchhoff's current law at the drain of the driving N-type FET 101 and the output terminal, the following formulas (4) and (5) hold.

[0044]

Mathematics

[0045]

Mathematics

[0046] Here, V fb represents the drain voltage of the driving N-type FET 101, r cp represents the output resistance of the current source FET 103, gm fbp represents the transconductance of the feedback P-type FET 104, and r fbp represents the output resistance of the feedback P-type FET 104.

[0047] V in = 0, the output resistance can be calculated from formulas (4) and (5) as the following formula (6).

[0048]

Mathematics

[0049] For an ideal FET without channel length modulation, rln →∞, r cp →∞, gm dn r dn >>1, and gm fbp r fbp Since >>1, equation (6) can be approximated as equation (7).

[0050]

number

[0051] Comparing equation (7) with equation (3), the output resistance of the SSF circuit 120 is 1 / r of that of the source follower circuit 110. dn gm fbp It can be seen that the reduction is doubled. Therefore, the driving force of the output load in the SSF circuit 120 is higher than that of the source follower circuit 110.

[0052] Next, we will return to Figure 4 and explain the small-signal operation of the SSF circuit 120.

[0053] When the voltage at the input terminal increases, the gate voltage of the drive N-type FET 101 increases, which in turn increases the source-drain current of the drive N-type FET 101. As a result, the source voltage of the drive N-type FET 101 increases, and the drain voltage decreases. Since the output terminal is connected to the source of the drive N-type FET 101, an increase in the source voltage of the drive N-type FET 101 is equivalent to an increase in the voltage at the output terminal.

[0054] Simultaneously, as the drain voltage of the driving N-type FET 101 decreases, the gate voltage of the feedback P-type FET 104 decreases, increasing the source-drain current. Here, since the load FET 102 is a constant current source, Kirchhoff's current law at the output terminal causes the source-drain current of the driving N-type FET 101 to decrease. This suppresses the rise in the source voltage and the fall in the drain voltage of the driving N-type FET 101. Suppressing the rise in the source voltage of the driving N-type FET 101 is equivalent to suppressing the voltage rise at the output terminal.

[0055] Conversely, when the voltage at the input terminal drops, the gate voltage of the driving N-type FET 101 drops, so the source-drain current of the driving N-type FET 101 decreases. As a result, the source voltage of the driving N-type FET 101 drops and the drain voltage thereof rises. A drop in the source voltage of the driving N-type FET 101 is equivalent to a drop in the voltage at the output terminal. At the same time, the rise in the drain voltage of the driving N-type FET 101 increases the gate voltage of the feedback P-type FET 104, thereby decreasing the source-drain current thereof. Since the load FET 102 is a constant current source, according to Kirchhoff's current law at the output terminal, the source-drain current of the driving N-type FET 101 starts to increase. This suppresses the drop in the source voltage and the rise in the drain voltage of the driving N-type FET 101. Suppression of the drop in the source voltage of the driving N-type FET 101 is equivalent to suppression of the voltage drop at the output terminal.

[0056] From the above, in the SSF circuit 120, output fluctuation transitions more quickly from a transient state to a steady state compared to the source follower circuit 110.

[0057] Next, a driving method of the SSF circuit 120 will be described.

[0058] A ground potential is applied to the source of the load FET 102, and a power supply potential Vdd is applied to the source of the current source FET 103 and the source of the feedback P-type FET 104. By applying a fixed potential V1 to the gate of the load FET 102, the load FET 102 is operated in a saturation region to serve as a constant current source, and by applying a fixed potential V2 to the gate of the current source FET 103, the current source FET 103 is operated in a saturation region to serve as a constant current source. Provided that the relationship Vdd > V2 > V1 > ground potential (GND) is satisfied.

[0059] Here, the fixed potential V1, the fixed potential V2, the fixed potential V3, and the like are examples of "a first fixed potential", "a second fixed potential", "a third fixed potential", and the like.

[0060] In this state, an input signal is input to the input terminal connected to the gate of the driving N-type FET 101, and an output signal is output from the output terminal connected to the source of the driving N-type FET 101.

[0061] Next, the small-signal operation of the amplifier circuit 100 according to the present embodiment will be described. FIG. 6 is a diagram showing an example of a small-signal equivalent circuit of the amplifier circuit 100 in FIG. 1. From Kirchhoff's current law at the drain and output terminal of the driving N-type FET 101, Equation (4) and the following Equation (8) hold.

[0062] [[NUMERICAL]]

[0063] Here, gm fbn is the transconductance of the feedback N-type FET 105, and r fbn is the output resistance of the feedback N-type FET 105.

[0064] V in =0, the output resistance can be calculated as shown in the following Equation (9) from Equation (4) and Equation (8).

[0065] [[NUMERICAL]]

[0066] In an ideal FET without channel length modulation, r ln →∞, r cp →∞, gm dn r dn >>1, gm fbp r fbp >>1, and gm fbn r fbn >>1, so Equation (9) can be approximated as shown in the following Equation (10).

[0067] [[NUMERICAL]]

[0068] Comparing equation (10) with equation (7), in the amplifier circuit 100, the output resistance is the gm of the SSF circuit 120. fbp / (gm fbn +gm fbp It can be seen that it is reduced by a factor of 1. Therefore, the driving force of the output load in the amplification circuit 100 is higher than that of the SSF circuit 120.

[0069] Next, we will return to Figure 1 and explain the small-signal operation of the amplifier circuit 100.

[0070] When the voltage at the input terminal increases, the gate voltage of the drive N-type FET 101 increases, which in turn increases the source-drain current of the drive N-type FET 101. As a result, the source voltage of the drive N-type FET 101 increases, and the drain voltage decreases. An increase in the source voltage of the drive N-type FET 101 is equivalent to an increase in the voltage at the output terminal.

[0071] Simultaneously, as the drain voltage of the driving N-type FET 101 decreases, the gate voltage of the feedback P-type FET 104 decreases, increasing the source-drain current, and the gate voltage of the feedback N-type FET 105 decreases, reducing the source-drain current. Here, since the load FET 102 is a constant current source, Kirchhoff's current law at the output terminal causes the source-drain current of the driving N-type FET 101 to decrease. This suppresses the rise in the source voltage and the fall in the drain voltage of the driving N-type FET 101. Suppressing the rise in the source voltage of the driving N-type FET 101 is equivalent to suppressing the voltage rise at the output terminal.

[0072] Conversely, when the voltage at the input terminal decreases, the gate voltage of the driving N-type FET 101 decreases, thus reducing the source-drain current of the driving N-type FET 101. As a result, the source voltage of the driving N-type FET 101 decreases, and the drain voltage increases. A decrease in the source voltage of the driving N-type FET 101 is equivalent to a decrease in the voltage at the output terminal.

[0073] Simultaneously, the increase in the drain voltage of the driving N-type FET 101 causes the gate voltage of the feedback P-type FET 104 to rise, decreasing the source-drain current, and the gate voltage of the feedback N-type FET 105 to rise, increasing the source-drain current. Since the load FET 102 is a constant current source, Kirchhoff's current law at the output terminal causes the source-drain current of the driving N-type FET 101 to increase. This suppresses the decrease in the source voltage and the increase in the drain voltage of the driving N-type FET 101. Suppression of the decrease in the source voltage of the driving N-type FET 101 is equivalent to suppression of the voltage decrease at the output terminal.

[0074] From the above, in the amplifier circuit 100 of this embodiment, the output feedback speed is increased compared to the SSF circuit 120 because a feedback N-type FET 105 is added, and the output fluctuation transitions quickly from a transient state to a steady state. In particular, the output feedback speed is greater during the falling edge than during the rising edge of the output waveform. Therefore, in the output waveform of the amplifier circuit 100, the rising and falling edges are steep, while the rising and falling edge overshoots and undershoots are suppressed, and oscillation of the output waveform is also suppressed. As a result, as shown in Figure 7, the rising time t of the output waveform of the amplifier circuit 100 r and fall time t f This shortens the rise time to t, allowing for an amplification circuit capable of transmitting faster clock signals. sr and fall settling time t sf This shortens the output voltage, resulting in an amplifier circuit capable of driving larger output loads. Figure 7 is a schematic diagram showing an example of the output waveform of the amplifier circuit 100. In Figure 7, the vertical axis represents the signal output, and the horizontal axis represents time.

[0075] Furthermore, in the amplification circuit 100, since the gate-source voltages of the feedback P-type FET 104 and the feedback N-type FET 105 are aligned, an inverter can be constructed consisting of feedback transistors with symmetrical design parameters (threshold voltage, ratio of gate length to gate width, gate oxide capacitance, etc.), thereby increasing design flexibility and versatility.

[0076] Next, a method for driving the amplifier circuit 100 will be described.

[0077] A ground potential is applied to the source of the load FET 102, and a power supply potential Vdd is applied to the source of the current source FET 103 and the source of the feedback P-type FET 104. Further, by applying a fixed potential V1 to the gate of the load FET 102, the load FET 102 is operated in a saturation region to serve as a constant current source; by applying a fixed potential V2 to the gate of the current source FET 103, the current source FET 103 is operated in a saturation region to serve as a constant current source; and by applying a fixed potential V3 to the source of the feedback N-type FET 105, the gate-source voltage is reduced. Provided that the relationship Vdd>V2>V1>ground potential (GND) and V A ≧V3≧ground potential (GND) is satisfied.

[0078] In this state, an input signal is input to an input terminal connected to the gate of the driving N-type FET 101, and an output signal is output from an output terminal connected to the source of the driving N-type FET 101.

[0079] A conventional amplifier circuit as disclosed in Patent Document 2 (International Publication No. WO 2019 / 107084) has lower output impedance than a normal SSF, so it has high driving force and is suitable for high-speed signal transmission or driving of a large external load. It also facilitates impedance matching with a subsequent-stage circuit. Furthermore, in the waveform of the output signal, since the rising edge and falling edge are steep, the rise time and fall time are short; conversely, overshoot and undershoot are less likely to occur at the rising and falling edges, so the settling time is short, or ringing due to oscillation is less likely to occur.

[0080] However, in such conventional amplifier circuits, since design conditions are not optimized, the rising characteristics and falling characteristics of the output waveform are asymmetric and not optimized for the shortest delay, power consumption is large, and more hot carriers may be generated in some cases. The amplifier circuit 100 according to the present embodiment has a steady state I outThe objective is to perform a large-signal analysis in the case where the value is 0 and provide an amplifier circuit with optimized design conditions.

[0081] The large-signal operation of the amplifier circuit 100 will be explained below in comparison with the large-signal operation of conventional source follower and SSF circuits. For simplicity, channel length modulation effects and substrate bias effects will not be considered here. Also, the threshold voltages Vth of the drive N-type FET 101, load FET 102, and feedback N-type FET 105 will be explained below. dn , Vth ln , Vth fbn Let be a positive value, and each gain coefficient β dn , β ln , β fbn The value is assumed to be positive. Also, the threshold voltage Vth of the current source FET103 and the feedback P-type FET104 are assumed to be positive. cp , Vth fbp Let be a negative value, and each gain coefficient β cp , β fbp This value is considered positive.

[0082] In Figure 2, which shows an example of the configuration of a conventional source follower circuit 110, the gate-source voltage of the driving N-type FET 101 is Vgs dn =V in -V out Therefore, the gate-source voltage of the load FET102 is Vgs ln =V1.

[0083] Therefore, β x =μ x C x W x / L x Therefore, the drain-source currents Ids of the drive N-type FET 101 and load FET 102 when operating in the saturation region are as follows: dn Ids ln This can be expressed by the following equations (101) and (102).

[0084]

number

[0085]

number

[0086] In Figure 2, Ids dn =Ids ln Therefore, V out and V in The relationship is given by the following equation (103).

[0087]

number

[0088] From this equation, V out ≠V in Therefore, it can be seen that there exists an offset voltage Vos, which is represented by the following equation (104).

[0089]

number

[0090] In Figure 4, which shows an example of the configuration of the SSF circuit 120, the gate-source voltage of the current source FET 103 is Vgs cp =V2-Vdd-Vth cp Therefore, the gate-source voltage of the feedback P-type FET 104 is Vgs fbp =V in -V out Therefore, the drain-source currents Ids of the current source FET103 and the feedback P-type FET104 when operating in the saturation region are as follows: cp Ids fbp This can be expressed by the following equations (105) and (106).

[0091]

number

[0092]

number

[0093] Here, V A This represents the voltage at node (connection point) A, as illustrated in Figure 4.

[0094] In Figure 4, Ids dn =-Ids cp Therefore, V out and V in The relationship is given by equation (107) below.

[0095]

number

[0096] From this equation, V out ≠V in Therefore, it can be seen that there exists an offset voltage Vos, which is represented by the following equation (108).

[0097]

number

[0098] In Figure 1, which shows an example of the configuration of the amplifier circuit 100 according to this embodiment, the gate-source voltage of the feedback N-type FET 105 is V A -V3-Vth fbn Therefore, the drain-source current Ids when the feedback N-type FET 105 operates in the saturation region is fbn This can be expressed by the following equation (109).

[0099]

number

[0100] In Figure 1, Ids dn =-Ids cp Therefore, V out and V in The relationship is given by the following equation (110).

[0101] [Math.]

[0102] From this formula, V out ≠V in holds, and it can be seen that an offset voltage Vos represented by the following formula (111) exists.

[0103] [Math.]

[0104] In FIG. 1, let I0 be the current flowing between the source of the driving N-type FET 101 and the drain of the load FET 102, and the drain of the feedback P-type FET 104 and the drain of the feedback N-type FET 105. Further, let I out be the current flowing into and out of the output terminal OUT. When the amplifier circuit 100 operates in a transient state, I out ≠0, while when it operates in a steady state, I out = 0.

[0105] The amplifier circuit 100 according to the present embodiment differs from the conventional SSF circuit 120 in that I0 = 0 in the steady state (I out = 0). That is, in the steady state, no current flows between the connection point (node X) between the source of the driving N-type FET 101 and the drain of the load FET 102, and the output terminal OUT. Further, in the amplifier circuit 100, I0 satisfies -1 μA ≦ I0 ≦ +1 μA in the steady state (I out = 0).

[0106] In contrast, in the conventional SSF circuit 120, I0 ≠ 0 in both the steady state (I out = 0) and the transient state (I out ≠ 0).

[0107] Here, when the channel length modulation effect is incorporated into formula (102) and formula (105), the following formula (112) and formula (113) are obtained, respectively.

[0108] ["Numerical"

[0109] "Numerical"

[0110] Here, λ ln is the channel length modulation coefficient of the load FET 102, and λ cp is the channel length modulation coefficient of the current source FET 103.

[0111] When I0=0, the currents of the driving N-type FET 101, the load FET 102, and the current source FET 103 do not flow between the feedback P-type FET 104 and the feedback N-type FET 105, so Ids ln =-Ids cp holds, and the relationship expressed by the following formula (114) is established between the fixed potential V1 which is the gate voltage of the load FET 102 and the fixed potential V2 which is the gate voltage of the current source FET 103.

[0112] "Numerical"

[0113] In particular, when there is no channel length modulation effect, that is, when λ ln =λ cp =0, the relationship expressed by the following formula (115) is established between V1 and V2.

[0114] "Numerical"

[0115] In particular, when Vth ln =-Vth cp , and β ln =β cp , the relational expression between V1 and V2 is represented by the following formula (116).

[0116] "Numerical"

[0117] Similarly, when I0=0, the current in the feedback P-type FET 104 and the feedback N-type FET 105 does not flow in or out between the driving N-type FET 101, the load FET 102, and the current source FET 103, so -Ids is the same as in the steady state of a CMOS inverter. fbp =Ids fbn Therefore, the threshold voltage Vth fbp and Vth fbn Between and the gain coefficient β fbp and β fbn The following relationship (117) holds between them.

[0118]

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[0119] Therefore, theoretically, I0=0 when equations (115) and (117) are satisfied. However, in actual circuits, due to manufacturing variations, I0 may deviate slightly from 0. In that case, I0=0 can be achieved by adjusting V1 or V2 using the method described below.

[0120] Figure 8 shows an example of the configuration of an amplifier circuit 150 according to a first modified example of this embodiment. Compared to amplifier circuit 100, amplifier circuit 150 does not have a connection between the source of the drive N-type FET 101 and the drain of the load FET 102 (node ​​X in the figure), and between the drain of the feedback P-type FET 104 and the drain of the feedback N-type FET 105 (output terminal OUT).

[0121] When a differential amplifier or galvanometer is connected between node X and output terminal OUT of the amplification circuit 150, it becomes a Wheatstone bridge. In this Wheatstone bridge, in order to make I0=0, V1 or V2 should be varied so that the output of the differential amplifier becomes 0V, or the galvanometer needle reaches the zero point.

[0122] Here, when amplifier circuits 100 and 150 are located near each other on the same chip, the condition for V1 or V2 to make I0=0 in amplifier circuit 150 is considered to be equal to the condition for V1 or V2 to make I0=0 in amplifier circuit 100. Therefore, after extracting the condition for V1 or V2 to make I0=0 using amplifier circuit 150, this condition can be applied to amplifier circuit 100 to make I0=0. Alternatively, after adjusting V1 or V2 in amplifier circuit 150 to make I0=0, node X and output terminal OUT of amplifier circuit 150 may be short-circuited and used.

[0123] For example, the amplification circuit 150 may be a TEG (Test Element Group) circuit used to extract at least one of the conditions V1 and V2 such that I0=0. Furthermore, the amplification circuit 100 and the amplification circuit 150, which functions as a TEG circuit, may be a composite circuit formed on the same chip (the same semiconductor device, the same integrated circuit, etc.).

[0124] Figure 9 shows an example of the configuration of an amplifier circuit 160 relating to a second modification of this embodiment. Compared to the amplifier circuit 100, the amplifier circuit 160 further includes a switch 161 and a differential amplifier 162.

[0125] Switch 161 and differential amplifier 162 are connected between node X (the connection point between the source of the drive N-type FET 101 and the drain of the load FET 102) and the output terminal OUT. In the amplification circuit 160, to make I0=0, switch 161 is turned OFF to disconnect node X and the output terminal OUT, and V1 or V2 is adjusted so that the output voltage of the differential amplifier 162 becomes 0V. When using the amplification circuit 160, switch 161 is turned ON to short-circuit node X and the output terminal OUT.

[0126] Thus, in the amplification circuit 100, node X and the output terminal OUT may be configured to be short-circuited retrospectively, that is, after adjusting V1 or V2 so that I0=0.

[0127] From the above, in the amplifier circuits 100, 150, and 160 of this embodiment, unlike the conventional SSF circuit 120, steady state I out When I0 = 0, the source-drain currents of the feedback P-type FET 104 and the feedback N-type FET 105 become equivalent. Therefore, the input-output characteristics of the CMOS inverter consisting of the feedback P-type FET 104 and the feedback N-type FET 105 become symmetrical, and the excess steady-state current in the amplification circuit is reduced. In other words, the rise and fall characteristics of the output waveforms of amplification circuits 100, 150, and 160 become symmetrical and shortest, and the power consumption of amplification circuits 100, 150, and 160 is reduced.

[0128] Referring to Figure 10, the amplifier circuit 100 in this embodiment will be further described. Unlike the conventional SSF circuit 120, the amplifier circuit 100 has enhancement type (Normally OFF) feedback P-type FET 104 and feedback N-type FET 105. For simplicity, Vth = -Vth fbp =Vth fbn , β=β fbp =β fbn Let's explain the case. Generally, when Vth > 0, it is called the enhancement type (Normally OFF), and when Vth ≤ 0, it is called the depression type (Normally On).

[0129] Figure 10 is a graph showing the relationship between input voltage and through-current in a CMOS inverter consisting of a feedback P-type FET 104 and a feedback N-type FET 105. In Figure 10, the vertical axis represents the current value and the horizontal axis represents the voltage value. As shown in the example in Figure 10, the maximum value of the through-current Imax is expressed by the following equation (118).

[0130]

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[0131] Furthermore, the time constant τ of the CMOS inverter consisting of the feedback P-type FET 104 and the feedback N-type FET 105 is expressed by the following equation (119). Here, τ corresponds to the rise time and fall time. out This is the load capacitance of the output terminal.

[0132]

number

[0133] From equations (118) and (119), we can see that there is a trade-off where increasing Vth decreases Imax but increasing τ (increasing delay), and a trade-off where decreasing β decreases Imax but increasing τ. Therefore, we will consider whether to control Vth or β when trying to reduce Imax while suppressing the increase in τ, and optimize the driving conditions of the feedback P-type FET 104 and feedback N-type FET 105. Note that Imax can be reduced by controlling Vdd-V3, but Vdd-V3 is V in It should be noted that there is a constraint on determining the voltage range.

[0134] Imax is a quadratic expression in Vth, and τ is a linear expression in Vth. Therefore, the decrease in Imax due to an increase in Vth is large, while the increase in τ is small. In contrast, since both Imax and τ are linear expressions in β, the decrease in Imax due to a decrease in β is equivalent to the increase in τ. Therefore, to decrease Imax while suppressing the increase in τ, one can increase Vth rather than decreasing β.

[0135] From the above, in the amplifier circuit 100 of this embodiment, since the feedback P-type FET 104 and feedback N-type FET 105 are enhancement type (normally OFF), unlike the depletion type (normally On), the threshold voltage Vth = -Vth fbp =Vth fbnThis value becomes greater than 0. As a result, the through-current of the CMOS inverter consisting of the feedback P-type FET 104 and the feedback N-type FET 105 is reduced, and the power consumption of the amplification circuit 100 is reduced.

[0136] Furthermore, in the amplifier circuit 100 of this embodiment, unlike the conventional SSF circuit 120, the drive N-type FET 101, load FET 102, and current source FET 103 are depletion type (Normally On). For simplicity, here we use Vth = -Vth cp =Vth ln =Vth dn , β=β cp =β ln =β dn Let's explain the case.

[0137] When the drive N-type FET 101 and the current source FET 103 are operating in the saturation region, equation (107) holds, and therefore the V of the amplifier circuit 100 in and V out The relationship is linear. However, when the drive N-type FET 101 and the current source FET 103 operate in the linear region, it deviates from equation (107), so V in and V out The linearity of the relationship decreases. Therefore, in order to maintain the linearity of the input / output characteristics of the amplifier circuit 100, the drive N-type FET 101, load FET 102, and current source FET 103 are optimized assuming that the FETs operate in the saturation region.

[0138] The conditions for an FET to operate in the saturation region are Vds≧Vgs-Vth≧0 for an N-type FET and Vds≦Vgs+Vth≦0 for a P-type FET. Therefore, the driving N-type FET 101, load FET 102, and current source FET 103 operate in the saturation region when the following three equations (120), (121), and (122) hold.

[0139]

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[0140]

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[0141]

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[0142] Here, Vds ln =V out Vds dn =V A -V out , and Vds cp =V A -Vdd and Vgs ln =V1, Vgs dn =V in -V out , and Vgs cp =V2-Vdd. Substituting these into equations (120), (121), and (122), we obtain the following equations (123), (124), and (125).

[0143]

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[0144]

number

[0145]

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[0146] Furthermore, combining equations (123), (124), and (125) yields equation (126).

[0147]

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[0148] From equation (126), the drive N-type FET 101, load FET 102, and current source FET 103 are V1 ≤ V inIt operates in the saturation region for ≤V2+2Vth, and in this case V in and V out The linearity of the relationship is maintained. Here, the lower limit of V1 is Vth, and the upper limit of V2 is Vdd-Vth, so V in The maximum range is Vth ≤ V in The voltage range is ≤Vdd + Vth (Voltage range is Vdd).

[0149] Therefore, by reducing Vth, V in and V out The relationship with V is linear. in The range shifts downward overall. Therefore, it is possible to suppress the generation of hot carriers in N-type FETs. Also, V in Similarly, V out (=Vds ln ) also shifted downward overall, and the channel length modulation effect λVds ln Ids ln Because this is reduced, power consumption is reduced.

[0150] From the above, in the amplification circuit 100 of this embodiment, since the drive N-type FET 101 and the current source FET 103 are depletion type (Normally On), unlike the enhancement type (Normally OFF), the threshold voltage Vth = -Vth cp =Vth ln =Vth dn This becomes 0 or less. Therefore, the input voltage of the amplification circuit 100 can be reduced, and the power consumption of the amplification circuit 100 and the generation of hot carriers can be suppressed.

[0151] As described above, the amplifier circuit 100 in this embodiment has symmetrical input / output characteristics for the CMOS inverter consisting of the feedback P-type FET 104 and the feedback N-type FET 105, and reduces excess steady-state current within the amplifier circuit. As a result, the rise and fall characteristics of the output waveform become symmetrical and shorter, and power consumption can be reduced. In addition, power consumption is reduced because the through-current flowing through the CMOS inverter consisting of the feedback P-type FET 104 and the feedback N-type FET 105 is reduced. Furthermore, since the range in which the input / output characteristics are linear is shifted overall, the power consumption of the amplifier circuit is reduced, and hot carrier generation can be suppressed.

[0152] <Second Embodiment> An amplification circuit and a composite circuit according to this embodiment will be described. In the following description, components similar to those described in the embodiments described above will be denoted by the same reference numerals, and their detailed descriptions will be omitted as appropriate.

[0153] <Regarding the configuration of the amplification circuit> Figure 11 shows an example of the configuration of the amplifier circuit 200 according to this embodiment. The amplifier circuit 200 is a form of source follower circuit. In the amplifier circuit 200 of this embodiment, unlike the amplifier circuit 100 in the first embodiment, the driving FET is a P-type FET.

[0154] The amplification circuit 200 comprises a drive P-type FET 201, a load FET 202, a current source FET 203, a feedback P-type FET 104, and a feedback N-type FET 105. The drive P-type FET 201, load FET 202, and feedback P-type FET 104 are all P-type FETs. The current source FET 203 and feedback N-type FET 105 are all N-type FETs.

[0155] The source of the load FET202 is connected to the power supply, and the drain of the load FET202 is connected to the source of the driver P-type FET201. The drain of the current source FET203 is connected to the drain of the driver P-type FET201, and the source of the current source FET203 is connected to GND.

[0156] The gate of the drive P-type FET 201 is connected to the input terminal IN of the amplification circuit 200. A fixed potential V1 is input to the gate of the load FET 202. As a result, the load FET 202 functions as a constant current source.

[0157] The connection point between the source of the drive P-type FET201 and the drain of the load FET202 is connected to the output terminal OUT.

[0158] The source of the feedback P-type FET 104 is connected to a fixed potential V3, and the drain of the feedback P-type FET 104 is connected to the drain of the feedback N-type FET 105. The source of the feedback N-type FET 105 is connected to GND. The gates of both the feedback P-type FET 104 and the feedback N-type FET 105 are connected at the same potential to the connection point between the drain of the current source FET 203 and the drain of the driver P-type FET 201.

[0159] The connection point between the drain of the feedback P-type FET 104 and the drain of the feedback N-type FET 105 is connected to the output terminal OUT.

[0160] <About the operation of the amplifier circuit> Next, the operating principle of the amplifier circuit 200 will be explained in comparison with the operating principles of conventional source follower circuits and SSF circuits.

[0161] Figure 12 shows an example of the configuration of a conventional source follower circuit 210. In Figure 12, the source of the load FET 202 is connected to the power supply, and the drain of the load FET 202 is connected to the source of the driver P-type FET 201. The drain of the driver P-type FET 201 is connected to GND. The connection point between the source of the driver P-type FET 201 and the drain of the load FET 202 is connected to the output terminal OUT. The gate of the load FET 202 is connected to a fixed potential V1, and the load FET 202 functions as a constant current source.

[0162] Figure 13 shows an example of the small-signal equivalent circuit of the source follower circuit 210 in Figure 12. The output resistance of the source follower circuit 210 is expressed by the following equation (11).

[0163]

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[0164] Here, r dp r is the output resistor of the drive P-type FET201. lp The output resistance of the load FET202, gm dp This is the transconductance of the driving P-type FET201.

[0165] In an ideal FET without channel length modulation, r ln →∞, gm dn Since >>1, equation (11) can be approximated as equation (12).

[0166]

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[0167] Figure 14 shows an example of the configuration of the SSF circuit 220. The SSF circuit 220 in Figure 14 has a configuration in which a current source FET 203 and a feedback N-type FET 105 are added to the source follower circuit 210 in Figure 12. Compared with the amplifier circuit 200 in Figure 11, the SSF circuit 220 in Figure 14 has a configuration in which the feedback P-type FET 104 is omitted from the amplifier circuit 200.

[0168] Figure 15 shows an example of the small-signal equivalent circuit of the SSF circuit 220 in Figure 14. From Kirchhoff's current law at the drain and output terminals of the driving P-type FET 201, the following equations (13) and (14) hold.

[0169]

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[0170]

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[0171] Here, r cn This is the output resistance of the current source FET203.

[0172] V in If we set = 0, the output resistance can be calculated from equations (13) and (14) as shown in equation (15).

[0173]

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[0174] In an ideal FET without channel length modulation, r lp →∞, r cn →∞, gm dp r dp >>1, and gm fbn r fbn Since >>1, equation (15) can be approximated as equation (16).

[0175]

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[0176] Comparing equation (16) with equation (12), the output resistance of the SSF circuit 220 is 1 / r of that of the source follower circuit 210. dp gm fbn It can be seen that the reduction is doubled. Therefore, the driving force of the output load in the SSF circuit 220 is higher than that of the source follower circuit 210.

[0177] Next, we will return to Figure 14 and explain the small-signal operation of the SSF circuit 220.

[0178] When the voltage at the input terminal increases, the gate voltage of the drive P-type FET 201 increases, causing the source-drain current of the drive P-type FET 201 to decrease. As a result, the source voltage of the drive P-type FET 201 increases and the drain voltage decreases. Since the output terminal is connected to the source of the drive P-type FET 201, an increase in the source voltage of the drive P-type FET 201 is equivalent to an increase in the voltage at the output terminal.

[0179] Simultaneously, as the drain voltage of the driving P-type FET 201 decreases, the gate voltage of the feedback N-type FET 105 decreases, reducing the source-drain current. Here, since the load FET 202 is a constant current source, Kirchhoff's current law at the output terminal causes the source-drain current of the driving P-type FET 201 to increase. This suppresses the rise in the source voltage and the fall in the drain voltage of the driving P-type FET 201. Suppressing the rise in the source voltage of the driving P-type FET 201 is equivalent to suppressing the voltage rise at the output terminal.

[0180] Conversely, when the voltage at the input terminal decreases, the gate voltage of the driving P-type FET 201 decreases, causing the source-drain current of the driving P-type FET 201 to increase. As a result, the source voltage of the driving P-type FET 201 decreases and the drain voltage increases. The decrease in the source voltage of the driving P-type FET 201 is equivalent to a decrease in the voltage at the output terminal. Simultaneously, the increase in the drain voltage of the driving P-type FET 201 causes the gate voltage of the feedback N-type FET 105 to increase, increasing the source-drain current. Since the load FET 202 is a constant current source, Kirchhoff's current law at the output terminal causes the source-drain current of the driving P-type FET 201 to decrease. This suppresses the decrease in the source voltage and the increase in the drain voltage of the driving P-type FET 201. Suppression of the decrease in the source voltage of the driving P-type FET 201 is equivalent to suppression of the decrease in the voltage at the output terminal.

[0181] Based on the above, the SSF circuit 220 allows the output fluctuation to transition from a transient state to a steady state more quickly than the source follower circuit 210.

[0182] Next, we will explain how to drive the SSF circuit 220.

[0183] The power supply potential Vdd is applied to the source of the load FET 202, and the ground potential is applied to the source of the current source FET 203 and the source of the feedback N-type FET 105. By applying a fixed potential V1 to the gate of the load FET 202, it is operated in the saturation region and made the load FET 202 a constant current source, and by applying a fixed potential V2 to the gate of the current source FET 203, it is operated in the saturation region and made the current source FET 203 a constant current source. However, the relationship Vdd > V1 > V2 > ground potential (GND) is satisfied.

[0184] In this state, the input signal is input to the input terminal connected to the gate of the drive P-type FET 201, and the output signal is output from the output terminal connected to the source of the drive P-type FET 201.

[0185] Next, the operating principle of the amplifier circuit 200 according to this embodiment will be described. Figure 16 is a diagram showing an example of the small-signal equivalent circuit of the amplifier circuit 200 of Figure 11. From Kirchhoff's current law at the drain and output terminals of the driving P-type FET 201, equations (13) and (17) hold.

[0186]

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[0187] V in If we set = 0, the output resistance can be calculated from equations (13) and (17) as shown in equation (18).

[0188]

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[0189] In an ideal FET without channel length modulation, r lp →∞, r cn →∞, gm dp r dp >>1, gmfbn r fbn >>1, and gm fbp r fbp Since >>1, equation (18) can be approximated as equation (19).

[0190]

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[0191] Comparing equation (19) with equation (16), in the amplifier circuit 200, the output resistance is the gm of the SSF circuit 220. fbn / (gm fbn +gm fbp It can be seen that it is reduced by a factor of 1. Therefore, the driving force of the output load in the amplification circuit 200 is higher than that of the SSF circuit 220.

[0192] Next, we will return to Figure 11 and explain the small-signal operation of the amplifier circuit 200.

[0193] When the voltage at the input terminal increases, the gate voltage of the drive P-type FET 201 increases, causing the source-drain current of the drive P-type FET 201 to decrease. As a result, the source voltage of the drive P-type FET 201 increases and the drain voltage decreases. An increase in the source voltage of the drive P-type FET 201 is equivalent to an increase in the voltage at the output terminal.

[0194] Simultaneously, as the drain voltage of the driving P-type FET 201 decreases, the gate voltage of the feedback P-type FET 104 decreases, increasing the source-drain current, and the gate voltage of the feedback N-type FET 105 decreases, decreasing the source-drain current. Here, since the load FET 202 is a constant current source, Kirchhoff's current law at the output terminal causes the source-drain current of the driving P-type FET 201 to increase. This suppresses the rise in the source voltage and the fall in the drain voltage of the driving P-type FET 201. Suppression of the rise in the source voltage of the driving P-type FET 201 is equivalent to suppression of the voltage rise at the output terminal.

[0195] Conversely, when the voltage at the input terminal decreases, the gate voltage of the drive P-type FET 201 decreases, causing the source-drain current of the drive P-type FET 201 to increase. As a result, the source voltage of the drive P-type FET 201 decreases and the drain voltage increases. A decrease in the source voltage of the drive P-type FET 201 is equivalent to a decrease in the voltage at the output terminal.

[0196] Simultaneously, the increase in the drain voltage of the driving P-type FET 201 causes the gate voltage of the feedback P-type FET 104 to rise, decreasing the source-drain current, and the gate voltage of the feedback N-type FET 105 to rise, increasing the source-drain current. Since the load FET 202 is a constant current source, Kirchhoff's current law at the output terminal causes the source-drain current of the driving P-type FET 201 to decrease. This suppresses the decrease in the source voltage and the increase in the drain voltage of the driving P-type FET 201. Suppression of the decrease in the source voltage of the driving P-type FET 201 is equivalent to suppression of the voltage decrease at the output terminal.

[0197] From the above, in the amplifier circuit 200 of this embodiment, the output feedback speed is increased compared to the SSF circuit 220 because a feedback P-type FET 104 is added, and the output fluctuation transitions quickly from a transient state to a steady state. In particular, the output feedback speed is greater during the rising edge than during the falling edge of the output waveform. Therefore, in the output waveform of the amplifier circuit 200, the rising and falling edges are steep, while the rising and falling edge overshoots and undershoots are suppressed, and oscillation of the output waveform is also suppressed. As a result, the rising time t of the output waveform of the amplifier circuit 200 r and fall time t f This shortens the rise time to t, allowing for an amplification circuit capable of transmitting faster clock signals. sr and fall settling time t sf This allows for a shorter circuit, resulting in an amplifier circuit capable of driving larger output loads.

[0198] Furthermore, in the amplification circuit 200, since the gate-source voltages of the feedback P-type FET 104 and the feedback N-type FET 105 are aligned, an inverter can be constructed consisting of feedback transistors with symmetrical design parameters (threshold voltage, ratio of gate length to gate width, gate oxide capacitance, etc.), thereby increasing design flexibility and versatility.

[0199] Next, the method for driving the amplifier circuit 200 will be explained.

[0200] The power supply potential Vdd is applied to the source of the load FET 202, and the ground potential is applied to the source of the current source FET 203 and the source of the feedback N-type FET 105. Furthermore, by applying a fixed potential V1 to the gate of the load FET 202, it is operated in the saturation region, making the load FET 202 a constant current source. By applying a fixed potential V2 to the gate of the current source FET 203, it is operated in the saturation region, making the current source FET 203 a constant current source. Finally, by applying a fixed potential V3 to the source of the feedback P-type FET 104, the gate-source voltage is reduced. However, Vdd > V1 > V2 > ground potential (GND), and Vdd ≥ V3 ≥ V A Assume that the following relationship is satisfied.

[0201] In this state, the input signal is input to the input terminal connected to the gate of the drive P-type FET 201, and the output signal is output from the output terminal connected to the source of the drive P-type FET 201.

[0202] The large-signal operation of the amplifier circuit 200 will be explained below in comparison with the large-signal operation of conventional source follower and SSF circuits. For simplicity, channel length modulation effects and substrate bias effects will not be considered here. Also, the threshold voltages Vth of the drive P-type FET 201, load FET 202, and feedback P-type FET 104 will be explained. dp , Vth lp , Vth fbp Let be a negative value, and each gain coefficient β dp , β lp , β fbp The value is assumed to be positive. The threshold voltages Vth of the current source FET203 and the feedback N-type FET105, respectively. cn , Vthfbn Let be a positive value, and each gain coefficient β cn , β fbn This value is considered positive.

[0203] In Figure 12, which shows an example of the configuration of a conventional source follower circuit 210, the gate-source voltage of the driving P-type FET 201 is Vgs dp =V in -V out Therefore, the gate-source voltage of the load FET202 is Vgs lp =V1-Vdd.

[0204] Therefore, β x =μ x C x W x / L x Therefore, the drain-source currents Ids of the drive P-type FET 201 and load FET 202 when operating in the saturation region are dp Ids lp This can be expressed by the following equations (201) and (202).

[0205]

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[0206]

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[0207] In Figure 12, -Ids dn =-Ids ln Therefore, V out and V in The relationship is given by the following equation (203).

[0208]

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[0209] From this equation, V out ≠V inTherefore, it can be seen that there exists an offset voltage Vos, which is represented by the following equation (204).

[0210]

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[0211] In Figure 14, which shows an example of the configuration of the SSF circuit 220, the gate-source voltage of the current source FET 203 is Vgs cn =V2-Vth cn Therefore, the gate-source voltage of the feedback N-type FET 105 is Vgs fbn =V A -Vdd-Vth fbn Therefore, the drain-source currents Ids of the current source FET203 and the feedback N-type FET105 when operating in the saturation region are as follows: cn Ids fbn This can be expressed by the following equations (205) and (206).

[0212]

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[0213]

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[0214] In Figure 14, -Ids dp =Ids cn Therefore, V out and V in The relationship is given by equation (207) below.

[0215]

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[0216] From this equation, V out ≠V in Therefore, it can be seen that there exists an offset voltage Vos, which is represented by the following equation (208).

[0217]

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[0218] In Figure 11, which shows an example of the configuration of the amplifier circuit 200 according to this embodiment, the gate-source voltage of the feedback P-type FET 104 is V A -Vdd-Vth fbp Therefore, the drain-source current Ids when the feedback P-type FET 104 operates in the saturation region is fbp This can be expressed by the following equation (209).

[0219]

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[0220] In Figure 11, -Ids dp =Ids cn Therefore, V out and V in The relationship is given by equation (210) below.

[0221]

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[0222] From this equation, V out ≠V in Therefore, it can be seen that there exists an offset voltage Vos, which is represented by the following equation (211).

[0223]

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[0224] In Figure 11, let I0 be the current flowing between the source of the drive P-type FET 201 and the drain of the load FET 202, and between the drain of the feedback P-type FET 104 and the drain of the feedback N-type FET 105. Also, let I be the current flowing in and out of the output terminal OUT. out Let's assume that when the amplifier circuit 200 is operating in a transient state, Iout ≠0, but when operating in a steady state, I out = 0

[0225] Unlike the conventional SSF circuit 220, the amplification circuit 200 in this embodiment maintains a steady state (I out In the steady state (I = 0), I0 = 0. Also, the amplifier circuit 200 is in a steady state (I out At (=0), I0 satisfies -1μA ≤ I0 ≤ +1μA.

[0226] In contrast, in the conventional SSF circuit 220, the steady state (I out =0) and transient state (I out In all cases (≠0), I0 ≠ 0.

[0227] Now, by introducing the channel length modulation effect into equations (202) and (205), we obtain equations (212) and (213), respectively.

[0228]

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[0229]

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[0230] Here, .'' lp λ is the channel length modulation coefficient of the load FET202. cn This is the channel length modulation coefficient of the current source FET203.

[0231] When I0=0, the current from the drive P-type FET201, load FET202, and current source FET203 does not flow in or out between the feedback P-type FET104 and feedback N-type FET105, so Ids lp =-Ids cn Therefore, the following relationship (214) holds between the fixed potential V1, which is the gate voltage of the load FET202, and the fixed potential V2, which is the gate voltage of the current source FET203.

[0232]

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[0233] In particular, when there is no channel length modulation effect, i.e., λ lp =λ cn When = 0, the following relationship (215) holds between V1 and V2.

[0234]

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[0235] In particular, Vth lp =-Vth cn , and β lp =β cn In this case, the relationship between V1 and V2 is given by the following equation (223).

[0236]

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[0237] Similarly, when I0=0, the current in the feedback P-type FET 104 and feedback N-type FET 105 does not flow in or out with the drive N-type FET 101, load FET 102, and current source FET 103, so -Ids is the same as in the steady state of a CMOS inverter. fbp =Ids fbn Therefore, the threshold voltage Vth fbp and Vth fbn Between and the gain coefficient β fbp and β fbn The following relationship (224) holds between them.

[0238]

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[0239] Therefore, theoretically, I0=0 when equations (215) and (224) are satisfied. However, in actual circuits, manufacturing variations may cause I0 to deviate slightly from 0. In that case, I0=0 can be achieved by adjusting V1 or V2 using the method described below.

[0240] Figure 17 shows an example of the configuration of an amplifier circuit 250 according to a first modified example of this embodiment. Compared to the amplifier circuit 200, the amplifier circuit 250 does not have a connection between the source of the drive P-type FET 201 and the drain of the load FET 202 (node ​​X in the figure), and between the drain of the feedback P-type FET 104 and the drain of the feedback N-type FET 105 (output terminal OUT).

[0241] A Wheatstone bridge is formed by connecting a differential amplifier or galvanometer between node X and output terminal OUT of the amplifier circuit 250. In this Wheatstone bridge, to make I0=0, V1 or V2 should be varied so that the output of the differential amplifier becomes 0V, or the galvanometer needle reaches the zero point.

[0242] Here, when amplifier circuits 200 and 250 are located near each other on the same chip, the condition for V1 or V2 to make I0=0 in amplifier circuit 250 is considered to be equal to the condition for V1 or V2 to make I0=0 in amplifier circuit 200. Therefore, after extracting the condition for V1 or V2 to make I0=0 using amplifier circuit 250, this condition can be applied to amplifier circuit 200 to make I0=0. Alternatively, after adjusting V1 or V2 in amplifier circuit 250 to make I0=0, node X and output terminal OUT of amplifier circuit 250 may be short-circuited and used.

[0243] For example, the amplification circuit 250 may be a TEG circuit used to extract at least one of the conditions V1 and V2 such that I0=0. Alternatively, the amplification circuit 200 and the amplification circuit 250, which functions as a TEG circuit, may be a composite circuit formed on the same chip.

[0244] Figure 18 shows an example of the configuration of an amplifier circuit 260 relating to a second modification of this embodiment. Compared to the amplifier circuit 200, the amplifier circuit 260 further includes a switch 261 and a differential amplifier 262.

[0245] Switch 261 and differential amplifier 262 are connected between node X and output terminal OUT. To make I0=0 in the amplification circuit 260, switch 261 is turned OFF to disconnect node X and output terminal OUT, and V1 or V2 is adjusted so that the output voltage of differential amplifier 262 becomes 0V. When using the amplification circuit 260, switch 261 is turned ON to short-circuit node X and output terminal OUT.

[0246] Thus, in the amplification circuit 200, node X and the output terminal OUT may be configured to be short-circuited retrospectively, that is, after adjusting V1 or V2 so that I0=0.

[0247] From the above, in the amplifier circuits 200, 250, and 260 of this embodiment, unlike the conventional SSF circuit 120, steady state I out When I0 = 0, the source-drain currents of the feedback P-type FET 104 and the feedback N-type FET 105 become equivalent. Therefore, the input-output characteristics of the CMOS inverter consisting of the feedback P-type FET 104 and the feedback N-type FET 105 become symmetrical, and the excess steady-state current in the amplification circuit is reduced. In other words, the rise and fall characteristics of the output waveforms of amplification circuits 200, 250, and 260 become symmetrical and shortest, and the power consumption of amplification circuits 200, 250, and 260 is reduced.

[0248] In the amplification circuit 200, unlike the conventional SSF circuit 220, the feedback P-type FET 104 and feedback N-type FET 105 are enhancement type (Normally OFF). In this embodiment as well, the graph showing the relationship between the input voltage and the through-current in the CMOS inverter consisting of the feedback P-type FET 104 and feedback N-type FET 105 is the same as in Figure 10, and the maximum value of the through-current Imax is expressed by the aforementioned equation (118). Furthermore, the time constant τ of the CMOS inverter consisting of the feedback P-type FET 104 and feedback N-type FET 105 is expressed by the aforementioned equation (119). As mentioned above, in order to reduce Imax while suppressing the increase in τ, for example, instead of decreasing β, one should increase Vth.

[0249] From the above, in the amplifier circuit 200 of this embodiment, since the feedback P-type FET 104 and feedback N-type FET 105 are enhancement type (Normally OFF), unlike the depletion type (Normally On), the threshold voltage Vth = -Vth fbp =Vth fbn This value becomes greater than 0. As a result, the through-current of the CMOS inverter consisting of the feedback P-type FET 104 and the feedback N-type FET 105 is reduced, and the power consumption of the amplification circuit 200 is reduced.

[0250] Furthermore, in the amplifier circuit 200 of this embodiment, unlike the conventional SSF circuit 220, the drive P-type FET 201, load FET 202, and current source FET 203 are depletion type (normally on). For simplicity, here Vth = Vth cn =-Vth lp =-Vth dp , β=β cn =β lp =β dp Let's explain the case.

[0251] When the drive P-type FET 201 and the current source FET 203 are operating in the saturation region, equation (207) holds, and therefore the V of the amplifier circuit 200 in and V outThe relationship is linear. However, when the drive P-type FET 201 and the current source FET 203 operate in the linear region, it deviates from equation (207), so V in and V out The linearity of the relationship decreases. Therefore, in order to maintain the linearity of the input / output characteristics of the amplifier circuit 200, the drive P-type FET 201, load FET 202, and current source FET 203 are optimized assuming that the FETs operate in the saturation region.

[0252] The conditions for an FET to operate in the saturation region are Vds≧Vgs-Vth≧0 for an N-type FET and Vds≦Vgs+Vth≦0 for a P-type FET. Therefore, the driving P-type FET 201, the load FET 202, and the current source FET 203 operate in the saturation region when the following three equations (225), (216), and (217) hold.

[0253]

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[0254]

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[0255]

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[0256] Here, Vds lp =V out -Vdd, Vds dp =V A -V out , and Vds cn =V A And Vgs lp =V1-Vdd, Vgs dp =V in -V out , and Vgs cn =V2. Substituting these into equations (225), (216), and (217), we obtain the following equations (218), (219), and (220).

[0257]

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[0258]

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[0259]

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[0260] Furthermore, combining equations (218), (219), and (220) yields equation (221).

[0261]

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[0262] From equation (221), the drive P-type FET 201, load FET 202, and current source FET 203 have a V2-2Vth ≤ V in It operates in the saturation region for ≤V1, and in this case V in and V out The linearity of the relationship is maintained. Here, the lower limit of V2 is Vth, and the upper limit of V1 is Vdd-Vth, so V in The maximum range is -Vth ≤ V in The voltage range is Vdd.

[0263] Therefore, by reducing Vth, V in and V out The relationship with V is linear. in The range shifts upward overall. Therefore, it is possible to suppress the generation of hot carriers in P-type FETs. Also, V in Similarly, V out (=Vdd+Vds lp ) also shifts upward overall, and the channel length modulation effect λVds lp Ids lp Because this is reduced, power consumption is reduced.

[0264] From the above, in the amplification circuit 200 of this embodiment, since the drive P-type FET 201 and the current source FET 203 are depletion type (Normally On), unlike the enhancement type (Normally OFF), the threshold voltage Vth = Vth cn =-Vth lp =-Vth dp This becomes 0 or less. Therefore, the input voltage of the amplification circuit 200 can be reduced, and the power consumption of the amplification circuit 200 and the generation of hot carriers can be suppressed.

[0265] As described above, the amplifier circuit 200 in this embodiment has symmetrical input / output characteristics for the CMOS inverter consisting of the feedback P-type FET 104 and the feedback N-type FET 105, and reduces excess steady-state current within the amplifier circuit. Therefore, the rise and fall characteristics of the output waveform are symmetrical and shortest, and power consumption can be reduced. In addition, power consumption is reduced because the through-current flowing through the CMOS inverter consisting of the feedback P-type FET 104 and the feedback N-type FET 105 is reduced. Furthermore, since the range in which the input / output characteristics are linear is shifted overall, the power consumption of the amplifier circuit is reduced, and hot carrier generation can be suppressed.

[0266] <Third Embodiment> The amplifier circuit according to this embodiment will now be described. In the following description, components similar to those described in the embodiments described above will be denoted by the same reference numerals, and their detailed descriptions will be omitted as appropriate.

[0267] <Regarding the configuration of the amplification circuit> Figure 19 shows an example of the configuration of the amplifier circuit 500 according to this embodiment. The amplifier circuit 500 has the same configuration as the amplifier circuit 100 shown in Figure 1, except for the connection of the gate of the current source FET 103. That is, the gate of the current source FET 103 is connected to a fixed potential V2 in the amplifier circuit 100, but in the amplifier circuit 500 it is connected to the input terminal. As a result, the drive N-type FET 101 and the current source FET 103 form an inverter circuit.

[0268] <About the operation of the amplifier circuit> Figure 20 shows an example of the small-signal equivalent circuit of the amplifier circuit 500 in Figure 19. From Kirchhoff's current law at the drain and output terminals of the driving N-type FET 101, equations (20) and (26) hold.

[0269]

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[0270]

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[0271] V in If we set = 0, the output resistance can be calculated from equations (20) and (26) as shown in equation (27).

[0272]

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[0273] Equation (27) is identical to equation (9), which shows the output resistance of the amplifier circuit 100 in the first embodiment. Therefore, it can be seen that the output resistance of the amplifier circuit 100 and the amplifier circuit 500 in this embodiment are the same, and the driving force of the output load is also the same.

[0274] Next, we will return to Figure 19 and explain the small-signal operation of the amplifier circuit 500.

[0275] When the voltage at the input terminals increases, the gate voltages of the drive N-type FET 101 and the current source FET 103 increase, causing the source-drain current of the drive N-type FET 101 to increase and the source-drain current of the current source FET 103 to decrease. As a result, the source voltage of the drive N-type FET 101 increases and the drain voltage decreases more rapidly than in the SSF circuit 120. The increase in the source voltage of the drive N-type FET 101 is equivalent to an increase in the voltage at the output terminals.

[0276] Simultaneously, as the drain voltage of the driving N-type FET 101 decreases, the gate voltage of the feedback P-type FET 104 decreases, increasing the source-drain current, and the gate voltage of the feedback N-type FET 105 decreases, reducing the source-drain current. Here, since the load FET 102 is a constant current source, Kirchhoff's current law at the output terminal causes the source-drain current of the driving N-type FET 101 to decrease. This suppresses the rise in the source voltage and the fall in the drain voltage of the driving N-type FET 101. Suppressing the rise in the source voltage of the driving N-type FET 101 is equivalent to suppressing the voltage rise at the output terminal.

[0277] Conversely, when the voltage at the input terminal decreases, the gate voltages of the drive N-type FET 101 and the current source FET 103 decrease, causing the source-drain current of the drive N-type FET 101 to decrease and the source-drain current of the current source FET 103 to increase. As a result, the source voltage of the drive N-type FET 101 decreases and the drain voltage increases more rapidly than in the SSF circuit 120. The decrease in the source voltage of the drive N-type FET 101 is equivalent to a decrease in the voltage at the output terminal.

[0278] Simultaneously, the increase in the drain voltage of the driving N-type FET 101 causes the gate voltage of the feedback P-type FET 104 to rise, decreasing the source-drain current, and the gate voltage of the feedback N-type FET 105 to rise, increasing the source-drain current. Since the load FET 102 is a constant current source, Kirchhoff's current law at the output terminal causes the source-drain current of the driving N-type FET 101 to increase. This suppresses the decrease in the source voltage and the increase in the drain voltage of the driving N-type FET 101. Suppression of the decrease in the source voltage of the driving N-type FET 101 is equivalent to suppression of the voltage decrease at the output terminal.

[0279] From the above, in the amplifier circuit 500 of this embodiment, the output feedback speed is increased compared to the SSF circuit 120 because a feedback N-type FET 105 is added, and the output fluctuation transitions quickly from a transient state to a steady state. In particular, the output feedback speed is greater during the falling edge than during the rising edge of the output waveform. Therefore, in the output waveform of the amplifier circuit 500, the rising and falling edges are steep, while the rising and falling edge overshoots and undershoots are suppressed, and oscillation of the output waveform is also suppressed. As a result, the rising time t of the output waveform of the amplifier circuit 500 r and fall time t f This shortens the rise time to t, allowing for an amplification circuit capable of transmitting faster clock signals. sr and fall settling time t sf This allows for a shorter circuit, resulting in an amplifier circuit capable of driving larger output loads.

[0280] Furthermore, in the amplification circuit 500, since the gate-source voltages of the feedback P-type FET 104 and the feedback N-type FET 105 are the same, an inverter can be constructed consisting of feedback transistors with symmetrical design parameters (threshold voltage, ratio of gate length to gate width, gate oxide capacitance, etc.), thereby increasing design flexibility and versatility.

[0281] Next, we will explain how to drive the amplifier circuit 500.

[0282] The ground potential is applied to the source of the load FET 102 and the source of the feedback N-type FET 105, and the power supply potential Vdd is applied to the source of the current source FET 103 and the source of the feedback P-type FET 104. In addition, by applying a fixed potential V1 to the gate of the load FET 102, it is operated in the saturation region and the load FET 102 is made a constant current source, and by applying a fixed potential V3 to the source of the feedback N-type FET 105, the gate-source voltage is lowered. However, Vdd > V1 > ground potential (GND), and V A Assume that the relationship ≥V3 ≥ ground potential (GND) is satisfied.

[0283] In this state, an input signal is input to the input terminal connected to the gate of the drive N-type FET 101 and the gate of the current source FET 103, and an output signal is output from the output terminal connected to the source of the drive N-type FET 101.

[0284] <Fourth Embodiment> The amplifier circuit according to this embodiment will now be described. In the following description, components similar to those described in the embodiments described above will be denoted by the same reference numerals, and their detailed descriptions will be omitted as appropriate.

[0285] <Regarding the configuration of the amplification circuit> Figure 21 shows an example of the configuration of the amplifier circuit 600 according to this embodiment. The amplifier circuit 600 has the same configuration as the amplifier circuit 200 shown in Figure 11, except for the connection of the gate of the current source FET 203. That is, the gate of the current source FET 203 is connected to a fixed potential V2 in the amplifier circuit 200, but in the amplifier circuit 600 it is connected to the input terminal. As a result, the drive P-type FET 201 and the current source FET 203 form an inverter circuit.

[0286] <About the operation of the amplifier circuit> Figure 22 shows an example of the small-signal equivalent circuit of the amplifier circuit 600 in Figure 21. From Kirchhoff's current law at the drain and output terminals of the driving P-type FET 201, equations (23) and (28) hold.

[0287]

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[0288]

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[0289] V in If we set = 0, the output resistance can be calculated from equations (23) and (28) as shown in equation (29).

[0290]

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[0291] Equation (29) is identical to equation (18), which shows the output resistance of the amplifier circuit 200 in the second embodiment. Therefore, it can be seen that the output resistance of the amplifier circuit 200 and the amplifier circuit 600 in this embodiment are the same, and the driving force of the output load is also the same.

[0292] Next, we will return to Figure 21 and explain the small-signal operation of the amplifier circuit 600.

[0293] As the voltage at the input terminals increases, the gate voltages of the drive P-type FET 201 and the current source FET 203 increase, causing the source-drain current of the drive P-type FET 201 to decrease and the source-drain current of the current source FET 203 to increase. As a result, the source voltage of the drive P-type FET 201 increases and the drain voltage decreases more rapidly than in the SSF circuit 220. The increase in the source voltage of the drive P-type FET 201 is equivalent to an increase in the voltage at the output terminals.

[0294] Simultaneously, as the drain voltage of the driving P-type FET 201 decreases, the gate voltage of the feedback P-type FET 104 decreases, increasing the source-drain current, and the gate voltage of the feedback N-type FET 105 decreases, decreasing the source-drain current. Here, since the load FET 202 is a constant current source, Kirchhoff's current law at the output terminal causes the source-drain current of the driving P-type FET 201 to increase. This suppresses the rise in the source voltage and the fall in the drain voltage of the driving P-type FET 201. Suppression of the rise in the source voltage of the driving P-type FET 201 is equivalent to suppression of the voltage rise at the output terminal.

[0295] Conversely, when the voltage at the input terminal decreases, the gate voltages of the drive P-type FET 201 and the current source FET 203 decrease, causing the source-drain current of the drive P-type FET 201 to increase and the source-drain current of the current source FET 203 to decrease. As a result, the source voltage of the drive P-type FET 201 decreases and the drain voltage increases more rapidly than in the SSF circuit 220. The decrease in the source voltage of the drive P-type FET 201 is equivalent to a decrease in the voltage at the output terminal.

[0296] Simultaneously, the increase in the drain voltage of the driving P-type FET 201 causes the gate voltage of the feedback P-type FET 104 to rise, decreasing the source-drain current, and the gate voltage of the feedback N-type FET 105 to rise, increasing the source-drain current. Since the load FET 202 is a constant current source, Kirchhoff's current law at the output terminal causes the source-drain current of the driving P-type FET 201 to decrease. This suppresses the decrease in the source voltage and the increase in the drain voltage of the driving P-type FET 201. Suppression of the decrease in the source voltage of the driving P-type FET 201 is equivalent to suppression of the voltage decrease at the output terminal.

[0297] From the above, in the amplifier circuit 600 of this embodiment, the output feedback speed is increased compared to the SSF circuit 220 because a feedback P-type FET 104 is added, and the output fluctuation transitions quickly from a transient state to a steady state. In particular, the output feedback speed is greater during the rising edge than during the falling edge of the output waveform. Therefore, in the output waveform of the amplifier circuit 600, the rising and falling edges are steep, while the rising and falling edge overshoots and undershoots are suppressed, and oscillation of the output waveform is also suppressed. As a result, the rising time t of the output waveform of the amplifier circuit 600 r and fall time t f This shortens the rise time to t, allowing for an amplification circuit capable of transmitting faster clock signals. sr and fall settling time t sf This allows for a shorter circuit, resulting in an amplifier circuit capable of driving larger output loads.

[0298] Furthermore, in the amplification circuit 600, since the gate-source voltages of the feedback P-type FET 104 and the feedback N-type FET 105 are aligned, an inverter can be constructed consisting of feedback transistors with symmetrical design parameters (threshold voltage, ratio of gate length to gate width, gate oxide capacitance, etc.), thereby increasing design flexibility and versatility.

[0299] Next, the method for driving the amplifier circuit 600 will be explained.

[0300] The power supply potential Vdd is applied to the source of the load FET 202 and the source of the feedback P-type FET 104, and the ground potential is applied to the source of the current source FET 203 and the source of the feedback N-type FET 105. By applying a fixed potential V1 to the gate of the load FET 202, it is operated in the saturation region and the load FET 202 is made a constant current source, and by applying a fixed potential V3 to the source of the feedback P-type FET 104, the gate-source voltage is lowered. However, Vdd > V1 > ground potential (GND), and Vdd ≥ V3 ≥ V A Assume that the following relationship is satisfied.

[0301] In this state, an input signal is input to the input terminal connected to the gate of the drive P-type FET 201 and the gate of the current source FET 203, and an output signal is output from the output terminal connected to the source of the drive P-type FET 201.

[0302] <Fifth Embodiment> The amplifier circuit according to this embodiment will now be described. In the following description, components similar to those described in the embodiments described above will be denoted by the same reference numerals, and their detailed descriptions will be omitted as appropriate.

[0303] <Regarding the configuration of the amplification circuit> Figure 23 shows an example of the configuration of an amplifier circuit 700 according to this embodiment. The amplifier circuit 700 is a form of Darlington circuit. The amplifier circuit 700 comprises a drive N-type FET 101, a load FET 102, a feedback N-type FET 105, and a feedback PNP bipolar transistor (BJT, Bipolar Junction Transistor) 504.

[0304] The source of the load FET 102 is connected to GND, and the drain of the load FET 102 is connected to the source of the drive N-type FET 101.

[0305] The drain of the drive N-type FET 101 is connected to the base of the feedback PNP-type BJT 504. The gate of the drive N-type FET 101 is connected to the input terminal IN of the amplification circuit 100. A fixed potential V1 is input to the gate of the load FET 102.

[0306] Here, "PNP type" and "NPN type," which represent the conductivity types of BJT, are examples of "first conductivity type," "second conductivity type," "third conductivity type," and "fourth conductivity type." The first conductivity type may be PNP type and the second conductivity type may be NPN type, or vice versa. Also, the first conductivity type may be PNP type and the fourth conductivity type may be NPN type, or vice versa.

[0307] Furthermore, the "base," "emitter," and "collector" of a BJT are examples of "control terminals," "current terminals," and so on, respectively.

[0308] The connection point between the source of the drive N-type FET 101 and the drain of the load FET 102 is connected to the output terminal OUT.

[0309] The emitter of the feedback PNP type BJT504 is connected to the power supply, and its collector is connected to the drain of the feedback N type FET105. The source of the feedback N type FET105 is connected to a fixed potential V3. The base of the feedback PNP type BJT504 and the gate of the feedback N type FET105 are both connected to the drain of the driver N type FET101.

[0310] The connection point between the collector of the feedback PNP type BJT504 and the drain of the feedback N type FET105 is connected to the output terminal OUT.

[0311] Compared with the amplifier circuit 100 of the first embodiment shown in Figure 1, the amplifier circuit 700 has a configuration in which the feedback P-type FET 104 is replaced with a feedback PNP-type BJT 504 and the current source FET 103 is removed.

[0312] <About the operation of the amplifier circuit> The small-signal operation of the amplifier circuit 700 will be explained in comparison with the operating principles of the conventional source follower circuit 110 (see Figure 2) and the conventional FET input inverted Darlington (ID) circuit.

[0313] Figure 24 shows an example of the configuration of a conventional FET input ID circuit 720. In addition to the source follower circuit 110 shown in Figure 2, the FET input ID circuit 720 includes a feedback PNP type BJT 504.

[0314] The emitter of the feedback PNP type BJT504 is connected to the power supply, the collector of the feedback PNP type BJT504 is connected to the output terminal OUT, and the base of the feedback PNP type BJT504 is connected to the drain of the driving N type FET 101. In this way, the feedback PNP type BJT504 constitutes a feedback circuit. Compared with the amplifier circuit 700 in Figure 23, the FET input ID circuit 720 has a configuration that omits the feedback N type FET 105 from the amplifier circuit 700.

[0315] Figure 25 shows an example of the small-signal equivalent circuit of the FET input ID circuit 720 in Figure 24. From Kirchhoff's current law at the drain and output terminals of the driving N-type FET 101, the following equations (30) and (31) hold.

[0316]

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[0317]

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[0318] Here, r fbp_b The base resistor of the feedback PNP type BJT504, r fbp_c This is the collector resistor of the feedback PNP type BJT504.

[0319] V in If we set = 0, the output resistance can be calculated from equations (30) and (31) as shown in equation (32).

[0320]

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[0321] In an ideal FET without channel length modulation, r ln →∞, r dn >>r fbp_b , gm dn r dn >>1, and gm fbp rfbp_c Since >>1, equation (32) can be approximated as equation (33).

[0322]

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[0323] Comparing equation (33) with equation (3), in the FET input ID circuit 720, the output resistance is 1 / gm of the source follower circuit 110. fbp r fbp_b It can be seen that the reduction is doubled. Therefore, the driving force of the output load in the FET input ID circuit 720 is higher than that of the source follower circuit 110.

[0324] Next, we will return to Figure 24 and explain the small-signal operation of the FET input ID circuit 720.

[0325] When the voltage at the input terminal increases, the gate voltage of the drive N-type FET 101 increases, which in turn increases the source-drain current of the drive N-type FET 101. As a result, the source voltage of the drive N-type FET 101 increases, and the drain voltage decreases. An increase in the source voltage of the drive N-type FET 101 is equivalent to an increase in the voltage at the output terminal.

[0326] Simultaneously, as the drain voltage of the drive N-type FET 101 decreases, the base voltage of the feedback PNP-type BJT 504 decreases, increasing the collector current. Here, since the load FET 102 is a constant current source, Kirchhoff's current law at the output terminal causes the source-drain current of the drive N-type FET 101 to decrease. This suppresses the rise in the source voltage and the fall in the drain voltage of the drive N-type FET 101. Suppressing the rise in the source voltage of the drive N-type FET 101 is equivalent to suppressing the voltage rise at the output terminal.

[0327] Conversely, when the voltage at the input terminal decreases, the gate voltage of the driving N-type FET 101 decreases, thus reducing the source-drain current of the driving N-type FET 101. As a result, the source voltage of the driving N-type FET 101 decreases and the drain voltage increases. The decrease in the source voltage of the driving N-type FET 101 is equivalent to a decrease in the voltage at the output terminal. Simultaneously, the increase in the drain voltage of the driving N-type FET 101 causes the base voltage of the feedback PNP-type BJT 504 to increase, reducing the collector current. Here, since the load FET 102 is a constant current source, Kirchhoff's current law at the output terminal causes the source-drain current of the driving N-type FET 101 to increase. This suppresses the decrease in the source voltage and the increase in the drain voltage of the driving N-type FET 101. Suppression of the decrease in the source voltage of the driving N-type FET 101 is equivalent to suppression of the voltage decrease at the output terminal.

[0328] Based on the above, the FET input ID circuit 720 exhibits a more rapid transition from transient to steady state in terms of output fluctuations compared to the source follower circuit 110.

[0329] Next, we will explain how to drive the FET input ID circuit 720.

[0330] The ground potential is applied to the source of the load FET 102, and the power supply potential Vdd is applied to the emitter of the feedback PNP type BJT 504. By applying a fixed potential V1 to the gate of the load FET 102, it is operated in the saturation region and the load FET 102 is made a constant current source. However, the relationship Vdd > V1 > ground potential (GND) is assumed to be satisfied.

[0331] In this state, an input signal is input to the input terminal connected to the gate of the drive N-type FET 101, and an output signal is output from the output terminal connected to the source of the drive N-type FET 101.

[0332] Next, the small-signal operation of the amplifier circuit 700 according to this embodiment will be described. Figure 26 is a diagram showing an example of the small-signal equivalent circuit of the amplifier circuit 700 of Figure 23. From Kirchhoff's current law at the drain and output terminals of the driving N-type FET 101, equations (30) and (34) hold.

[0333]

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[0334] V in If we set = 0, the output resistance can be calculated from equations (30) and (34) as shown in equation (35).

[0335]

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[0336] In an ideal FET without channel length modulation, r ln →∞, r dn >>r fbp_b , gm dn r dn >>1, gm fbn r fbn , and gm fbp r fbp_c Since >>1, equation (35) can be approximated as equation (36).

[0337]

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[0338] Comparing equation (36) with equation (33), in the amplifier circuit 700, the output resistance is the gm of the FET input ID circuit 720. fbp / (gm fbn +gm fbp It can be seen that it is reduced by a factor of 1. Therefore, the driving force of the output load in the amplification circuit 700 is higher than that of the FET input ID circuit 720.

[0339] Next, we will return to Figure 23 and explain the small-signal operation of the amplifier circuit 700.

[0340] When the voltage at the input terminal increases, the gate voltage of the drive N-type FET 101 increases, which in turn increases the source-drain current of the drive N-type FET 101. As a result, the source voltage of the drive N-type FET 101 increases, and the drain voltage decreases. An increase in the source voltage of the drive N-type FET 101 is equivalent to an increase in the voltage at the output terminal.

[0341] Simultaneously, as the drain voltage of the drive N-type FET 101 decreases, the base voltage of the feedback PNP-type BJT 504 decreases, increasing the collector current, and the gate voltage of the feedback N-type FET 105 decreases, reducing the source-drain current. Here, since the load FET 102 is a constant current source, Kirchhoff's current law at the output terminal causes the source-drain current of the drive N-type FET 101 to decrease. This suppresses the rise in the source voltage and the fall in the drain voltage of the drive N-type FET 101. Suppressing the rise in the source voltage of the drive N-type FET 101 is equivalent to suppressing the voltage rise at the output terminal.

[0342] Conversely, when the voltage at the input terminal decreases, the gate voltage of the driving N-type FET 101 decreases, thus reducing the source-drain current of the driving N-type FET 101. As a result, the source voltage of the driving N-type FET 101 decreases, and the drain voltage increases. A decrease in the source voltage of the driving N-type FET 101 is equivalent to a decrease in the voltage at the output terminal.

[0343] Simultaneously, the increase in the drain voltage of the drive N-type FET 101 causes the base voltage of the feedback PNP-type BJT 504 to rise, decreasing the collector current, and the gate voltage of the feedback N-type FET 105 to rise, increasing the source-drain current. Here, since the load FET 102 is a constant current source, Kirchhoff's current law at the output terminal causes the source-drain current of the drive N-type FET 101 to increase. This suppresses the decrease in the source voltage and the increase in the drain voltage of the drive N-type FET 101. Suppression of the decrease in the source voltage of the drive N-type FET 101 is equivalent to suppression of the voltage decrease at the output terminal.

[0344] From the above, in the amplifier circuit 700 of this embodiment, the output feedback speed is increased because a feedback N-type FET 105 is added compared to the FET input ID circuit 720, and the output fluctuation transitions quickly from the transient state to the steady state. In particular, the output feedback speed is greater during the falling edge than during the rising edge of the output waveform. Therefore, in the output waveform of the amplifier circuit 700, the rising and falling edges are steep, while the rising and falling edge overshoots and undershoots are suppressed, and oscillation of the output waveform is also suppressed. As a result, the rising time t of the output waveform of the amplifier circuit 700 r and fall time t f This shortens the rise time to t, allowing for an amplification circuit capable of transmitting faster clock signals. sr and fall settling time t sf This allows for a shorter circuit, resulting in an amplifier circuit capable of driving larger output loads.

[0345] Next, the method for driving the amplifier circuit 700 will be explained.

[0346] The ground potential is applied to the source of the load FET 102, and the power supply potential Vdd is applied to the emitter of the feedback PNP type BJT 504. Furthermore, by applying a fixed potential V1 to the gate of the load FET 102, it is operated in the saturation region, making the load FET 102 a constant current source, and by applying a fixed potential V3 to the source of the feedback N type FET 105, the gate-source voltage is lowered. However, Vdd > V1 > ground potential (GND), and V A Assume that the relationship ≥V3 ≥ ground potential (GND) is satisfied.

[0347] In this state, an input signal is input to the input terminal connected to the gate of the drive N-type FET 101, and an output signal is output from the output terminal connected to the source of the drive N-type FET 101.

[0348] In this embodiment, the feedback N-type FET 105 cannot be changed to a feedback NPN-type BJT 605. This is because, in that case, the emitter-base current of the feedback PNP-type BJT 504 would become the base-emitter current of the feedback NPN-type BJT 605, resulting in a constant collector current flowing through both the feedback PNP-type BJT 504 and the feedback NPN-type BJT 605.

[0349] <Sixth Embodiment> The amplifier circuit according to this embodiment will now be described. In the following description, components similar to those described in the embodiments described above will be denoted by the same reference numerals, and their detailed descriptions will be omitted as appropriate.

[0350] <Regarding the configuration of the amplification circuit> Figure 27 shows an example of the configuration of the amplifier circuit 800 according to this embodiment. The amplifier circuit 800 is a form of Darlington circuit. The amplifier circuit 800 comprises a drive P-type FET 201, a load FET 202, a feedback P-type FET 104, and a feedback NPN-type BJT 605. In the amplifier circuit 800 of this embodiment, unlike the amplifier circuit 700 of the fifth embodiment, the drive FET is a P-type FET.

[0351] The source of the load FET202 is connected to the power supply, and the drain of the load FET202 is connected to the source of the drive P-type FET201.

[0352] The drain of the drive P-type FET 201 is connected to the base of the feedback NPN-type BJT 605. The gate of the drive P-type FET 201 is connected to the input terminal IN of the amplifier circuit 800. A fixed potential V1 is input to the gate of the load FET 202.

[0353] The connection point between the source of the drive P-type FET201 and the drain of the load FET202 is connected to the output terminal OUT.

[0354] The source of the feedback P-type FET 104 is connected to a fixed potential V3, and the drain of the feedback P-type FET 104 is connected to the collector of the feedback NPN-type BJT 605. The emitter of the feedback NPN-type BJT 605 is connected to GND. The gate of the feedback P-type FET 104 and the base of the feedback NPN-type BJT 605 are both connected to the drain of the driver P-type FET 201.

[0355] The connection point between the drain of the feedback P-type FET104 and the collector of the feedback NPN-type BJT605 is connected to the output terminal OUT.

[0356] <About the operation of the amplifier circuit> The small-signal operation of the amplifier circuit 800 will be explained in comparison with the operating principles of the conventional source follower circuit 110 (see Figure 2) and the conventional FET input inverted Darlington (ID) circuit.

[0357] Figure 28 shows an example of the configuration of a conventional FET input ID circuit 820. In addition to the source follower circuit 110 shown in Figure 2, the FET input ID circuit 820 includes a feedback NPN type BJT 605.

[0358] The emitter of the feedback NPN BJT605 is connected to GND, the collector of the feedback NPN BJT605 is connected to the output terminal OUT, and the base of the feedback NPN BJT605 is connected to the source of the driver P-type FET201. In this way, the feedback NPN BJT605 constitutes a feedback circuit. Compared with the amplifier circuit 800 in Figure 27, the FET input ID circuit 820 has a configuration that omits the feedback P-type FET104 from the amplifier circuit 800.

[0359] Figure 29 shows an example of the small-signal equivalent circuit of the FET input ID circuit 820 in Figure 28. From Kirchhoff's current law at the drain and output terminals of the drive P-type FET 201, the following equations (37) and (38) hold.

[0360]

number

[0361]

number

[0362] Here, r fbn_b is the base resistor of the feedback NPN type BJT605, r fbn_c This is the collector resistor of the feedback NPN type BJT605.

[0363] V in If we set = 0, the output resistance can be calculated from equations (37) and (38) as shown in equation (39).

[0364]

number

[0365] In an ideal FET without channel length modulation, r lp →∞, r dn >>r fbn_b , gm dp r dp >>1, and gm fbn rfbn_c Since >>1, equation (39) can be approximated as equation (40).

[0366]

number

[0367] Comparing equation (40) with equation (3), in the FET input ID circuit 820, the output resistance is 1 / gm of the source follower circuit 110. fbn r fbn_b It can be seen that the reduction is doubled. Therefore, the driving force of the output load in the FET input ID circuit 820 is higher than that of the source follower circuit 110.

[0368] Next, we will return to Figure 28 and explain the small-signal operation of the FET input ID circuit 820.

[0369] When the voltage at the input terminal increases, the gate voltage of the drive P-type FET 201 increases, causing the source-drain current of the drive P-type FET 201 to decrease. As a result, the source voltage of the drive P-type FET 201 increases and the drain voltage decreases. An increase in the source voltage of the drive P-type FET 201 is equivalent to an increase in the voltage at the output terminal.

[0370] Simultaneously, as the drain voltage of the drive P-type FET 201 decreases, the base voltage of the feedback NPN-type BJT 605 decreases, reducing the collector current. Here, since the load FET 202 is a constant current source, Kirchhoff's current law at the output terminal causes the source-drain current of the drive P-type FET 201 to increase. This suppresses the rise in the source voltage and the fall in the drain voltage of the drive P-type FET 201. Suppressing the rise in the source voltage of the drive P-type FET 201 is equivalent to suppressing the voltage rise at the output terminal.

[0371] Conversely, when the voltage at the input terminal decreases, the gate voltage of the drive P-type FET 201 decreases, causing the source-drain current of the drive P-type FET 201 to increase. As a result, the source voltage of the drive P-type FET 201 decreases and the drain voltage increases. The decrease in the source voltage of the drive P-type FET 201 is equivalent to a decrease in the voltage at the output terminal. Simultaneously, the increase in the drain voltage of the drive P-type FET 201 causes the base voltage of the feedback NPN-type BJT 605 to increase, increasing the collector current. Here, since the load FET 202 is a constant current source, Kirchhoff's current law at the output terminal causes the source-drain current of the drive P-type FET 201 to decrease. This suppresses the decrease in the source voltage and the increase in the drain voltage of the drive P-type FET 201. Suppression of the decrease in the source voltage of the drive P-type FET 201 is equivalent to suppression of the voltage decrease at the output terminal.

[0372] Based on the above, the FET input ID circuit 820 exhibits a more rapid transition from transient to steady state in terms of output fluctuations compared to the source follower circuit 110.

[0373] Next, we will explain how to drive the FET input ID circuit 820.

[0374] The power supply potential Vdd is applied to the source of the load FET 102, and the ground potential is applied to the emitter of the feedback NPN type BJT 605. By applying a fixed potential V1 to the gate of the load FET 202, it is operated in the saturation region and the load FET 202 is made a constant current source. However, the relationship Vdd > V1 > ground potential (GND) is assumed to be satisfied.

[0375] In this state, an input signal is input to the input terminal connected to the gate of the drive P-type FET201, and an output signal is output from the output terminal connected to the source of the drive P-type FET201.

[0376] Next, the small-signal operation of the amplifier circuit 800 according to this embodiment will be described. Figure 30 shows an example of the small-signal equivalent circuit of the amplifier circuit 800 of Figure 27. From Kirchhoff's current law at the drain and output terminals of the driving P-type FET 201, equations (37) and (41) hold.

[0377]

number

[0378] V in If we set = 0, the output resistance can be calculated from equations (37) and (41) as shown in equation (42).

[0379]

number

[0380] In an ideal FET without channel length modulation, r lp →∞, r dn >>r fbn_b , gm dp r dp >>1, gm fbn r fbn_c , and, gm fbp r fbp Since >>1, equation (42) can be approximated as equation (43).

[0381]

number

[0382] Comparing equation (43) with equation (30), in the amplifier circuit 800, the output resistance is the gm of the FET input ID circuit 820. fbn / (gm fbn +gm fbp It can be seen that the power is reduced by a factor of 1. Therefore, the driving force of the output load in the amplification circuit 800 is higher than that of the FET input ID circuit 820.

[0383] Next, we will return to Figure 27 and explain the operating principle of the amplifier circuit 800.

[0384] When the voltage at the input terminal increases, the gate voltage of the drive P-type FET 201 increases, causing the source-drain current of the drive P-type FET 201 to decrease. As a result, the source voltage of the drive P-type FET 201 increases and the drain voltage decreases. An increase in the source voltage of the drive P-type FET 201 is equivalent to an increase in the voltage at the output terminal.

[0385] Simultaneously, as the drain voltage of the drive P-type FET 201 decreases, the gate voltage of the feedback P-type FET 104 decreases, increasing the source-drain current, and the base voltage of the feedback NPN-type BJT 605 decreases, reducing the collector current. Here, since the load FET 202 is a constant current source, Kirchhoff's current law at the output terminal causes the source-drain current of the drive P-type FET 201 to increase. This suppresses the rise in the source voltage and the fall in the drain voltage of the drive P-type FET 201. Suppression of the rise in the source voltage of the drive P-type FET 201 is equivalent to suppression of the voltage rise at the output terminal.

[0386] Conversely, when the voltage at the input terminal decreases, the gate voltage of the drive P-type FET 201 decreases, causing the source-drain current of the drive P-type FET 201 to increase. As a result, the source voltage of the drive P-type FET 201 decreases and the drain voltage increases. A decrease in the source voltage of the drive P-type FET 201 is equivalent to a decrease in the voltage at the output terminal.

[0387] Simultaneously, the increase in the drain voltage of the drive P-type FET 201 causes the gate voltage of the feedback P-type FET 104 to rise, decreasing the source-drain current, and the base voltage of the feedback NPN-type BJT 605 to rise, increasing the collector current. Here, since the load FET 202 is a constant current source, Kirchhoff's current law at the output terminal causes the source-drain current of the drive P-type FET 201 to decrease. This suppresses the decrease in the source voltage and the increase in the drain voltage of the drive P-type FET 201. Suppression of the decrease in the source voltage of the drive P-type FET 201 is equivalent to suppression of the voltage decrease at the output terminal.

[0388] From the above, in the amplifier circuit 800 of this embodiment, the output feedback speed is increased because a feedback P-type FET 104 is added compared to the FET input ID circuit 820, and the output fluctuation transitions quickly from a transient state to a steady state. In particular, the output feedback speed is greater during the rising edge than during the falling edge of the output waveform. Therefore, in the output waveform of the amplifier circuit 800, the rising and falling edges are steep, while the rising and falling edge overshoots and undershoots are suppressed, and oscillation of the output waveform is also suppressed. As a result, the rising time t of the output waveform of the amplifier circuit 300 r and fall time t f This shortens the rise time to t, allowing for an amplification circuit capable of transmitting faster clock signals. sr and fall settling time t sf This allows for a shorter circuit, resulting in an amplifier circuit capable of driving larger output loads.

[0389] Next, we will explain how to drive the amplifier circuit 800.

[0390] The power supply potential Vdd is applied to the source of the load FET 202, and the ground potential is applied to the emitter of the feedback NPN type BJT 605. Furthermore, by applying a fixed potential V1 to the gate of the load FET 202, it is operated in the saturation region to act as a constant current source, and by applying a fixed potential V3 to the source of the feedback P type FET 104, the gate-source voltage is lowered. However, Vdd > V1 > ground potential (GND), and Vdd ≥ V3 ≥ V A Assume that the following relationship is satisfied.

[0391] In this state, the input signal is input to the input terminal connected to the gate of the drive P-type FET 201, and the output signal is output from the output terminal connected to the source of the drive P-type FET 201.

[0392] In this embodiment, the feedback P-type FET 104 cannot be changed to a feedback PNP-type BJT 504. This is because, in that case, the emitter-base current of the feedback PNP-type BJT 504 would become the base-emitter current of the feedback NPN-type BJT 605, resulting in a constant collector current flowing through both the feedback PNP-type BJT 504 and the feedback NPN-type BJT 605.

[0393] <Seventh Embodiment> The amplifier circuit according to this embodiment will now be described. In the following description, components similar to those described in the embodiments described above will be denoted by the same reference numerals, and their detailed descriptions will be omitted as appropriate.

[0394] <Regarding the configuration of the amplification circuit> Figure 31 shows an example of the configuration of the amplifier circuit 900 according to this embodiment. The amplifier circuit 900 is a form of Darlington circuit.

[0395] Compared with the amplifier circuit 700 of the fifth embodiment shown in Figure 23, the amplifier circuit 900 has a configuration in which the driving N-type FET 101 is changed to a driving NPN-type BJT 701 in the amplifier circuit 700.

[0396] The collector of the driving NPN BJT701 is connected to the base of the feedback PNP BJT504 and the gate of the feedback N-type FET105. The emitter of the driving NPN BJT701 is connected to the drain of the load FET102. The base of the driving NPN BJT701 is connected to the input terminal IN. The connection point between the emitter of the driving NPN BJT701 and the drain of the load FET102 is connected to the output terminal OUT.

[0397] <About the operation of the amplifier circuit> The small-signal operation of the amplifier circuit 900 will be explained in comparison with the operating principles of conventional emitter follower circuits and ID circuits.

[0398] Figure 32 shows an example of the configuration of a conventional emitter follower circuit 910. In Figure 32, the source of the load FET 102 is connected to GND, and the drain of the load FET 102 is connected to the emitter of the driving NPN type BJT 701. The collector of the driving NPN type BJT 701 is connected to the power supply. In other words, the driving NPN type BJT 701 and the load FET 102 are arranged in series between the power supply and GND.

[0399] The connection point between the emitter of the driving NPN type BJT701 and the drain of the load FET102 is connected to the output terminal OUT. The gate of the load FET102 is connected to a fixed potential V1, and the load FET102 functions as a constant current source.

[0400] Compared to the amplifier circuit 900 in Figure 31, the emitter follower circuit 910 has a configuration that omits the feedback PNP type BJT 504 and the feedback N type FET 105 from the amplifier circuit 900.

[0401] Figure 33 shows an example of the small-signal equivalent circuit of the emitter follower circuit 910 in Figure 32. The output resistance of the emitter follower circuit 910 is expressed by the following equation (44).

[0402]

number

[0403] Here, r s The signal source is V in Output resistance, gm dn The transconductance of the driven NPN type BJT701 is r dn_b r is the base resistor of the drive NPN type BJT701. dn_c This is the collector resistor of the driving NPN type BJT701.

[0404] In an ideal FET without channel length modulation, r ln →∞. Also, in an ideal BJT without the early effect, r dn_c →∞ and gm dn r dn_b Since >>1, equation (44) can be approximated as equation (45).

[0405]

number

[0406] Figure 34 shows an example of the configuration of a conventional ID circuit 920. The ID circuit 920 in Figure 34 has a configuration in which a feedback PNP type BJT 504 is added to the emitter follower circuit 910 in Figure 32. Compared with the amplifier circuit 900 in Figure 31, the ID circuit 920 in Figure 34 has a configuration in which the feedback N type FET 105 is omitted from the amplifier circuit 900.

[0407] Figure 35 shows an example of the small-signal equivalent circuit of the ID circuit 920 in Figure 34. From Kirchhoff's current law at the collector and output terminals of the driving NPN type BJT701, the following equations (46) and (47) hold.

[0408]

number

[0409]

number

[0410] V in If we set = 0, the output resistance can be calculated from equations (46) and (47) as shown in equation (48).

[0411]

number

[0412] In an ideal FET without channel length modulation, r ln →∞. Regarding BJT, r dn_c >>r fbp_b That is. Also, gm dn r dn_c >>1, gm fbp r fbp_c >>1, and gm dn r dn_b Since >>1, equation (48) can be approximated as equation (49).

[0413]

number

[0414] Comparing equation (49) with equation (45), in the ID circuit 920, the output resistance is equal to A of the emitter follower circuit 910. 920 / 910 It can be seen that it is reduced by a factor of two. Here, A 920 / 910 The answer is given by equation (50) below.

[0415]

number

[0416] Therefore, the driving force of the output load in the ID circuit 920 is higher than that of the emitter follower circuit 910.

[0417] Next, we will return to Figure 34 and explain the small-signal operation of the ID circuit 920.

[0418] When the voltage at the input terminals increases, the base voltage of the driving NPN type BJT701 increases, which in turn increases the emitter current of the driving NPN type BJT701. As a result, the emitter voltage of the driving NPN type BJT701 increases, and the collector voltage decreases. The increase in the emitter voltage of the driving NPN type BJT701 is equivalent to an increase in the voltage at the output terminals.

[0419] Simultaneously, the decrease in the collector voltage of the driving NPN BJT701 causes the base voltage of the feedback PNP BJT504 to decrease, increasing the collector current. Here, since the load FET102 is a constant current source, Kirchhoff's current law at the output terminal causes the emitter current of the driving NPN BJT701 to decrease. This suppresses the rise in the emitter voltage and the fall in the collector voltage of the driving NPN BJT701. Suppressing the rise in the emitter voltage of the driving NPN BJT701 is equivalent to suppressing the voltage rise at the output terminal.

[0420] Conversely, when the voltage at the input terminal decreases, the base voltage of the driving NPN BJT701 decreases, thus reducing the emitter current of the driving NPN BJT701. As a result, the emitter voltage of the driving NPN BJT701 decreases, and the collector voltage increases. The decrease in the emitter voltage of the driving NPN BJT701 is equivalent to a decrease in the voltage at the output terminal. Simultaneously, the increase in the collector voltage of the driving NPN BJT701 causes the base voltage of the feedback PNP BJT504 to increase, reducing the collector current. Here, since the load FET102 is a constant current source, Kirchhoff's current law at the output terminal causes the emitter current of the driving NPN BJT701 to begin increasing. This suppresses the decrease in the emitter voltage and the increase in the collector voltage of the driving NPN BJT701. Suppressing the drop in the emitter voltage of the driven NPN type BJT701 is equivalent to suppressing the voltage drop at the output terminal.

[0421] Based on the above, the ID circuit 920 allows the output fluctuation to transition from a transient state to a steady state more quickly than the emitter follower circuit 910.

[0422] Next, we will explain how to drive the ID circuit 920.

[0423] The ground potential is applied to the source of the load FET 102, and the power supply potential Vdd is applied to the emitter of the feedback PNP type BJT 504. By applying a fixed potential V1 to the gate of the load FET 102, it is operated in the saturation region and the load FET 102 is made a constant current source. However, the relationship Vdd > V1 > ground potential (GND) is assumed to be satisfied.

[0424] In this state, an input signal is input to the input terminal connected to the base of the drive NPN type BJT701, and an output signal is output from the output terminal connected to the emitter of the drive NPN type BJT701.

[0425] Next, the small-signal operation of the amplifier circuit 900 according to this embodiment will be described. Figure 36 shows an example of the small-signal equivalent circuit of the amplifier circuit 900 in Figure 31. From Kirchhoff's current law at the collector and output terminals of the driving NPN type BJT701, equations (46) and (51) hold.

[0426]

number

[0427] V in If we set = 0, the output resistance can be calculated from equations (46) and (51) as shown in equation (52).

[0428]

number

[0429] In an ideal FET without channel length modulation, r ln →∞. Regarding BJT, r dn_c >>r fbp_b That is. Also, gm dn r dn_c >>1, gm fbn r fbn >>1, gmfbp r fbp_c >>1, and gm dn r dn_b Since >>1, equation (52) can be approximated as equation (53).

[0430]

number

[0431] Comparing equation (53) with equation (49), in the amplification circuit 900, the output resistance is A of the ID circuit 920. 900 / 920 It can be seen that it is reduced by a factor of two. Here, A 900 / 920 The answer is given by equation (54) below.

[0432]

number

[0433] Therefore, the driving force of the output load in the amplification circuit 900 is higher than that of the ID circuit 920.

[0434] Next, we will return to Figure 31 and explain the small-signal operation of the amplifier circuit 900.

[0435] When the voltage at the input terminals increases, the base voltage of the driving NPN type BJT701 increases, which in turn increases the emitter current of the driving NPN type BJT701. As a result, the emitter voltage of the driving NPN type BJT701 increases, and the collector voltage decreases. The increase in the emitter voltage of the driving NPN type BJT701 is equivalent to an increase in the voltage at the output terminals.

[0436] Simultaneously, as the collector voltage of the driving NPN BJT701 decreases, the base voltage of the feedback PNP BJT504 decreases, increasing the collector current, and the gate voltage of the feedback N-type FET105 decreases, reducing the source-drain current. Here, since the load FET102 is a constant current source, Kirchhoff's current law at the output terminal causes the emitter current of the driving NPN BJT701 to decrease. This suppresses the rise in the emitter voltage and the fall in the collector voltage of the driving NPN BJT701. Suppressing the rise in the emitter voltage of the driving NPN BJT701 is equivalent to suppressing the voltage rise at the output terminal.

[0437] Conversely, when the voltage at the input terminal decreases, the base voltage of the driving NPN type BJT701 decreases, thus reducing the emitter current of the driving NPN type BJT701. As a result, the emitter voltage of the driving NPN type BJT701 decreases, and the collector voltage increases. A decrease in the emitter voltage of the driving NPN type BJT701 is equivalent to a decrease in the voltage at the output terminal.

[0438] Simultaneously, the collector voltage of the driving NPN BJT701 increases, causing the base voltage of the feedback PNP BJT504 to rise and the collector current to decrease, while the gate voltage of the feedback N-type FET105 increases and the source-drain current to increase. Here, since the load FET102 is a constant current source, Kirchhoff's current law at the output terminal causes the emitter current of the driving NPN BJT701 to increase. This suppresses the decrease in the emitter voltage and the increase in the collector voltage of the driving NPN BJT701. Suppression of the decrease in the emitter voltage of the driving NPN BJT701 is equivalent to suppression of the voltage decrease at the output terminal.

[0439] From the above, in the amplifier circuit 900 of this embodiment, the output feedback speed is increased compared to the ID circuit 920 because a feedback N-type FET 105 is added, and the output fluctuation transitions quickly from a transient state to a steady state. In particular, the output feedback speed is greater during the falling edge than during the rising edge of the output waveform. Therefore, in the output waveform of the amplifier circuit 900, the rising and falling edges are steep, while the rising and falling edge overshoots and undershoots are suppressed, and oscillation of the output waveform is also suppressed. As a result, the rising time t of the output waveform of the amplifier circuit 900 r and fall time t f This shortens the rise time to t, allowing for an amplification circuit capable of transmitting faster clock signals. sr and fall settling time t sf This allows for a shorter circuit, resulting in an amplifier circuit capable of driving larger output loads.

[0440] Next, the method for driving the amplification circuit 900 will be explained.

[0441] The ground potential is applied to the source of the load FET 102, and the power supply potential Vdd is applied to the emitter of the feedback PNP type BJT 504. Furthermore, by applying a fixed potential V1 to the gate of the load FET 102, it is operated in the saturation region, making the load FET 102 a constant current source, and by applying a fixed potential V3 to the source of the feedback N type FET 105, the gate-source voltage is lowered. However, Vdd > V1 > ground potential (GND), and V A Assume that the relationship ≥V3 ≥ ground potential (GND) is satisfied.

[0442] In this state, an input signal is input to the input terminal connected to the gate of the driven NPN type BJT701, and an output signal is output from the output terminal connected to the emitter of the driven NPN type BJT701.

[0443] In this embodiment, the feedback N-type FET 105 cannot be changed to a feedback NPN-type BJT 605. This is because, in that case, the emitter-base current of the feedback PNP-type BJT 504 would become the base-emitter current of the feedback NPN-type BJT 605, resulting in a constant collector current flowing through both the feedback PNP-type BJT 504 and the feedback NPN-type BJT 605.

[0444] <Eighth Embodiment> The amplifier circuit according to this embodiment will now be described. In the following description, components similar to those described in the embodiments described above will be denoted by the same reference numerals, and their detailed descriptions will be omitted as appropriate.

[0445] <Regarding the configuration of the amplification circuit> Figure 37 shows an example of the configuration of the amplifier circuit 1000 according to this embodiment. The amplifier circuit 1000 is a form of Darlington circuit.

[0446] Compared with the amplifier circuit 800 of the sixth embodiment shown in Figure 27, the amplifier circuit 1000 has a configuration in which the driving P-type FET 201 is changed to a driving PNP-type BJT 801 in the amplifier circuit 800.

[0447] The collector of the driver PNP type BJT801 is connected to the gate of the feedback P type FET 104 and the base of the feedback NPN type BJT605. The emitter of the driver PNP type BJT801 is connected to the drain of the load FET 202. The base of the driver PNP type BJT801 is connected to the input terminal IN. The connection point between the emitter of the driver PNP type BJT801 and the drain of the load FET 202 is connected to the output terminal OUT.

[0448] <About the operation of the amplifier circuit> The small-signal operation of the amplifier circuit 1000 will be explained in comparison with the operating principles of conventional emitter follower circuits and ID circuits.

[0449] Figure 38 shows an example of the configuration of a conventional emitter follower circuit 1010. In Figure 38, the source of the load FET 202 is connected to the power supply, and the drain of the load FET 202 is connected to the emitter of the driver PNP type BJT 801. The collector of the driver PNP type BJT 801 is connected to GND. In other words, the load FET 202 and the driver PNP type BJT 801 are arranged in series between the power supply and GND.

[0450] The connection point between the drain of the load FET202 and the emitter of the driver PNP type BJT801 is connected to the output terminal OUT. The gate of the load FET202 is connected to a fixed potential V1, and the load FET202 functions as a constant current source.

[0451] Compared to the amplifier circuit 1000 in Figure 37, the emitter follower circuit 1010 has a configuration that omits the feedback P-type FET 104 and the feedback NPN-type BJT 605 from the amplifier circuit 1000.

[0452] Figure 39 shows an example of the small-signal equivalent circuit of the emitter follower circuit 1010 shown in Figure 38. The output resistance of the emitter follower circuit 1010 is expressed by the following equation (55).

[0453]

number

[0454] Here, gm dp The transconductance of the driving PNP type BJT801 is r dp_b is the base resistor of the drive PNP type BJT801, r dp_c This is the collector resistor of the PNP type BJT801.

[0455] In an ideal FET without channel length modulation, r lp →∞. Also, in an ideal BJT without the early effect, r dp_c →∞ and gm dp r dp_b Since >>1, equation (55) can be approximated as equation (56).

[0456]

number

[0457] Figure 40 shows an example of the configuration of a conventional ID circuit 1020. The ID circuit 1020 in Figure 40 has a configuration in which a feedback NPN type BJT 605 is added to the emitter follower circuit 1010 in Figure 39. Compared with the amplifier circuit 1000 in Figure 37, the ID circuit 1020 in Figure 40 has a configuration in which the feedback P type FET 104 is omitted from the amplifier circuit 1000.

[0458] Figure 41 shows an example of the small-signal equivalent circuit of the ID circuit 1020 in Figure 40. From Kirchhoff's current law at the collector and output terminals of the driving PNP type BJT801, the following equations (57) and (58) hold.

[0459]

number

[0460]

number

[0461] V in If we set = 0, the output resistance can be calculated from equations (57) and (58) as shown in equation (59).

[0462]

number

[0463] In an ideal FET without channel length modulation, r lp →∞. Regarding BJT, r dp_c >>r fbn_b That is. Also, gm dp r dp_c >>1, gm fbn r fbn_c >>1, and gm dp rdp_b Since >>1, equation (59) can be approximated as equation (60).

[0464]

number

[0465] Comparing equation (60) with equation (56), in ID circuit 1020, the output resistance is equal to A of emitter follower circuit 1010. 1020 / 1010 It can be seen that it is reduced by a factor of two. Here, A 1020 / 1010 The answer is given by equation (61) below.

[0466]

number

[0467] Therefore, the driving force of the output load in the ID circuit 1020 is higher than that of the emitter follower circuit 1010.

[0468] Next, we will return to Figure 40 and explain the small-signal operation of the ID circuit 1020.

[0469] When the voltage at the input terminals increases, the base voltage of the driving PNP type BJT801 increases, causing the emitter current of the driving PNP type BJT801 to decrease. As a result, the emitter voltage of the driving PNP type BJT801 increases, and the collector voltage decreases. The increase in the emitter voltage of the driving PNP type BJT801 is equivalent to an increase in the voltage at the output terminals.

[0470] Simultaneously, the decrease in the collector voltage of the driving PNP BJT801 causes the base voltage of the feedback NPN BJT605 to decrease, reducing the collector current. Here, since the load FET202 is a constant current source, Kirchhoff's current law at the output terminal causes the emitter current of the driving PNP BJT801 to increase. This suppresses the rise in the emitter voltage and the fall in the collector voltage of the driving PNP BJT801. Suppressing the rise in the emitter voltage of the driving PNP BJT801 is equivalent to suppressing the voltage rise at the output terminal.

[0471] Conversely, when the voltage at the input terminal decreases, the base voltage of the driving PNP type BJT801 decreases, causing the emitter current of the driving PNP type BJT801 to increase. As a result, the emitter voltage of the driving PNP type BJT801 decreases and the collector voltage increases. The decrease in the emitter voltage of the driving PNP type BJT801 is equivalent to a decrease in the voltage at the output terminal. Simultaneously, the increase in the collector voltage of the driving PNP type BJT801 causes the base voltage of the feedback NPN type BJT605 to increase, increasing the collector current. Here, since the load FET202 is a constant current source, Kirchhoff's current law at the output terminal causes the emitter current of the driving PNP type BJT801 to decrease. This suppresses the decrease in the emitter voltage and the increase in the collector voltage of the driving PNP type BJT801. Suppressing the drop in the emitter voltage of the driven PNP type BJT801 is equivalent to suppressing the drop in the output terminal voltage.

[0472] Based on the above, the ID circuit 1020 allows the output fluctuation to transition from a transient state to a steady state more quickly than the emitter follower circuit 1010.

[0473] Next, the method for driving the ID circuit 1020 will be explained.

[0474] The power supply potential Vdd is applied to the source of the load FET 202, and the ground potential is applied to the emitter of the feedback NPN type BJT 605. By applying a fixed potential V1 to the gate of the load FET 202, it is operated in the saturation region and the load FET 202 is made a constant current source. However, the relationship Vdd > V1 > ground potential (GND) is assumed to be satisfied.

[0475] In this state, an input signal is input to the input terminal connected to the base of the drive PNP type BJT801, and an output signal is output from the output terminal connected to the emitter of the drive PNP type BJT801.

[0476] Next, the small-signal operation of the amplifier circuit 1000 according to this embodiment will be described. Figure 42 shows an example of the small-signal equivalent circuit of the amplifier circuit 1000 of Figure 37. From Kirchhoff's current law at the collector and output terminals of the driving PNP type BJT801, equations (57) and (62) hold.

[0477]

number

[0478] V in If we set = 0, the output resistance can be calculated from equations (57) and (62) as shown in equation (63).

[0479]

number

[0480] In an ideal FET without channel length modulation, r ln →∞. Regarding BJT, r dp_c >>r fbn_b That is. Also, gm dp r dp_c >>1, gm fbn r fbn_c >>1, gm fbp r fbp >>1, and gm dp r dp_bSince >>1, equation (63) can be approximated as equation (64).

[0481]

number

[0482] Comparing equation (64) with equation (60), in the amplifier circuit 1000, the output resistance is A of the ID circuit 1020. 1000 / 1020 It can be seen that it is reduced by a factor of two. Here, A 1000 / 1020 The answer is given by equation (65) below.

[0483]

number

[0484] Therefore, the driving force of the output load in the amplification circuit 1000 is higher than that of the ID circuit 1020.

[0485] Next, we will return to Figure 37 and explain the small-signal operation of the amplifier circuit 1000.

[0486] When the voltage at the input terminals increases, the base voltage of the driving PNP type BJT801 increases, causing the emitter current of the driving PNP type BJT801 to decrease. As a result, the emitter voltage of the driving PNP type BJT801 increases, and the collector voltage decreases. The increase in the emitter voltage of the driving PNP type BJT801 is equivalent to an increase in the voltage at the output terminals.

[0487] Simultaneously, as the collector voltage of the driving PNP type BJT801 decreases, the gate voltage of the feedback P type FET104 decreases, increasing the source-drain current, and the base voltage of the feedback NPN type BJT605 decreases, reducing the collector current. Here, since the load FET202 is a constant current source, Kirchhoff's current law at the output terminal causes the emitter current of the driving PNP type BJT801 to increase. This suppresses the rise in the emitter voltage and the fall in the collector voltage of the driving PNP type BJT801. Suppressing the rise in the emitter voltage of the driving PNP type BJT801 is equivalent to suppressing the voltage rise at the output terminal.

[0488] Conversely, when the voltage at the input terminal decreases, the base voltage of the driving PNP type BJT801 decreases, causing the emitter current of the driving PNP type BJT801 to increase. As a result, the emitter voltage of the driving PNP type BJT801 decreases, and the collector voltage increases. A decrease in the emitter voltage of the driving PNP type BJT801 is equivalent to a decrease in the voltage at the output terminal.

[0489] Simultaneously, the collector voltage of the driving PNP type BJT801 rises, causing the gate voltage of the feedback P type FET104 to rise and the source-drain current to decrease, and the base voltage of the feedback NPN type BJT605 to rise and the collector current to increase. Here, since the load FET202 is a constant current source, Kirchhoff's current law at the output terminal causes the emitter current of the driving PNP type BJT801 to begin to decrease. This suppresses the decrease in the emitter voltage and the increase in the collector voltage of the driving PNP type BJT801. Suppression of the decrease in the emitter voltage of the driving PNP type BJT801 is equivalent to suppression of the voltage decrease at the output terminal.

[0490] From the above, in the amplifier circuit 1000 of this embodiment, the output feedback speed is increased compared to the ID circuit 1020 because a feedback P-type FET 104 is added, and the output fluctuation transitions quickly from a transient state to a steady state. In particular, the output feedback speed is greater during the falling edge than during the rising edge of the output waveform. Therefore, in the output waveform of the amplifier circuit 1000, the rising and falling edges are steep, while the rising and falling edge overshoots and undershoots are suppressed, and oscillation of the output waveform is also suppressed. As a result, the rising time t of the output waveform of the amplifier circuit 1000 r and fall time t f This shortens the rise time to t, allowing for an amplification circuit capable of transmitting faster clock signals. sr and fall settling time t sf This allows for a shorter circuit, resulting in an amplifier circuit capable of driving larger output loads.

[0491] Next, the method for driving the amplifier circuit 1000 will be explained.

[0492] The power supply potential Vdd is applied to the source of the load FET 202, and the ground potential is applied to the emitter of the feedback NPN type BJT 605. Furthermore, by applying a fixed potential V1 to the gate of the load FET 202, it is operated in the saturation region, making the load FET 202 a constant current source. By applying a fixed potential V3 to the source of the feedback P type FET 104, the gate-source voltage is lowered. However, Vdd > V1 > ground potential (GND), and Vdd ≥ V3 ≥ V A Assume that the following relationship is satisfied.

[0493] In this state, an input signal is input to the input terminal connected to the base of the drive PNP type BJT801, and an output signal is output from the output terminal connected to the emitter of the drive PNP type BJT801.

[0494] In this embodiment, the feedback P-type FET 104 cannot be changed to a feedback PNP-type BJT 504. This is because, in that case, the emitter-base current of the feedback PNP-type BJT 504 would become the base-emitter current of the feedback NPN-type BJT 605, resulting in a constant collector current flowing through both the feedback PNP-type BJT 504 and the feedback NPN-type BJT 605.

[0495] <Ninth Embodiment> The amplifier circuit according to this embodiment will now be described. In the following description, components similar to those described in the embodiments described above will be denoted by the same reference numerals, and their detailed descriptions will be omitted as appropriate.

[0496] <Regarding the configuration of the amplification circuit> Figure 43 shows an example of the configuration of the amplifier circuit 1100 according to this embodiment. The amplifier circuit 1100 is a form of source follower circuit.

[0497] The amplification circuit 1100 comprises a drive N-type FET 101, a load FET 102, a current source FET 103, and a feedback N-type FET 105. The drive N-type FET 101, load FET 102, and feedback N-type FET 105 are all composed of N-type FETs. The current source FET 103 is composed of a P-type FET.

[0498] The source of the load FET 102 is connected to GND, and the drain of the load FET 102 is connected to the source of the driver N-type FET 101. The drain of the current source FET 103 is connected to the drain of the driver N-type FET 101, and the source of the current source FET 103 is connected to the power supply.

[0499] In other words, the current source FET 103, the drive N-type FET 101, and the load FET 102 are arranged in series between the power supply and GND.

[0500] The gate of the drive N-type FET 101 is connected to the input terminal IN of the amplification circuit 1100. A fixed potential V1 is input to the gate of the load FET 102. As a result, the load FET 102 functions as a constant current source.

[0501] The connection point between the source of the drive N-type FET 101 and the drain of the load FET 102 is connected to the output terminal OUT.

[0502] The source of the feedback N-type FET 105 is connected to a fixed potential V3. The gate of the feedback N-type FET 105 is connected to the connection point between the drain of the current source FET 103 and the drain of the drive N-type FET 101. The drain of the feedback N-type FET 105 is connected to the output terminal OUT.

[0503] <About the operation of the amplifier circuit> Figure 44 shows an example of the small-signal equivalent circuit of the amplifier circuit 1100 in Figure 43. From Kirchhoff's current law at the drain and output terminals of the driving N-type FET 101, equations (4) and (67) hold.

[0504]

number

[0505] V in If we set = 0, the output resistance can be calculated from equations (4) and (67) as shown in equation (68).

[0506]

number

[0507] In an ideal FET without channel length modulation, r ln →∞, r cp →∞, gm dn r dn >>1, and gm fbn r fbn Since >>1, equation (68) can be approximated as equation (69).

[0508]

number

[0509] Comparing equation (69) with equation (3), in the amplifier circuit 1100, the output resistance is 1 / r of that of the source follower circuit 110. dn gm fbn It can be seen that the reduction is doubled. Therefore, the driving force of the output load in the amplification circuit 1100 is higher than that of the source follower circuit 110.

[0510] Next, we will return to Figure 43 and explain the small-signal operation of the amplifier circuit 1100.

[0511] When the voltage at the input terminal increases, the gate voltage of the drive N-type FET 101 increases, which in turn increases the source-drain current of the drive N-type FET 101. As a result, the source voltage of the drive N-type FET 101 increases, and the drain voltage decreases. An increase in the source voltage of the drive N-type FET 101 is equivalent to an increase in the voltage at the output terminal.

[0512] Simultaneously, as the drain voltage of the driving N-type FET 101 decreases, the gate voltage of the feedback N-type FET 105 decreases, reducing the source-drain current. Here, since the load FET 102 is a constant current source, Kirchhoff's current law at the output terminal causes the source-drain current of the driving N-type FET 101 to decrease. This suppresses the rise in the source voltage and the fall in the drain voltage of the driving N-type FET 101. Suppressing the rise in the source voltage of the driving N-type FET 101 is equivalent to suppressing the voltage rise at the output terminal.

[0513] Conversely, when the voltage at the input terminal decreases, the gate voltage of the driving N-type FET 101 decreases, thus reducing the source-drain current of the driving N-type FET 101. As a result, the source voltage of the driving N-type FET 101 decreases and the drain voltage increases. The decrease in the source voltage of the driving N-type FET 101 is equivalent to a decrease in the voltage at the output terminal. Simultaneously, the increase in the drain voltage of the driving N-type FET 101 causes the gate voltage of the feedback N-type FET 105 to increase, increasing the source-drain current. Since the load FET 102 is a constant current source, Kirchhoff's current law at the output terminal causes the source-drain current of the driving N-type FET 101 to increase. This suppresses the decrease in the source voltage and the increase in the drain voltage of the driving N-type FET 101. Suppression of the decrease in the source voltage of the driving N-type FET 101 is equivalent to suppression of the decrease in the voltage at the output terminal.

[0514] Based on the above, in the amplifier circuit 1100 of this embodiment, the output feedback speed is increased compared to the source follower circuit 110 because a feedback N-type FET 105 is added, and the output fluctuation transitions quickly from a transient state to a steady state.

[0515] In particular, the output feedback speed is greater during the falling edge of the output waveform than during the rising edge. As a result, in the output waveform of the amplifier circuit 1100, the falling edge is steeper compared to the source follower circuit 110, while rising and falling edge overshoot is suppressed, and oscillation of the output waveform is also suppressed.

[0516] As a result, the fall time t of the output waveform of the amplifier circuit 1100 shown in Figure 7 f This shortens the settling time t, allowing for an amplification circuit capable of transmitting faster clock signals. sf This allows for a shorter circuit, resulting in an amplifier circuit capable of driving larger output loads.

[0517] Furthermore, the amplifier circuit 1100 in this embodiment differs from the SSF circuit 120 in that it adds a feedback N-type FET 105 instead of a feedback P-type FET 104.

[0518] Therefore, similar to the SSF circuit 120, the output feedback speed increases, and the output fluctuation transitions quickly from a transient state to a steady state. However, compared to the source follower circuit 110, the SSF circuit 120 has a higher output feedback speed during the rising edge of the output waveform than during the falling edge, whereas in the amplifier circuit 1100 of this embodiment, the output feedback speed is higher during the falling edge of the output waveform than during the rising edge.

[0519] Here, the drive N-type FET 101 controls the rise time t of the output waveform. r and rise settling time t sr The method for shortening the fall time t of the output waveform is the same for both the amplifier circuit 1100 and the SSF circuit 120 in this embodiment, but in the amplifier circuit 1100 in this embodiment, the feedback N-type FET 105 mainly shortens the fall time t of the output waveform. f and fall settling time t sf To shorten the time, both the rise and fall times can be shortened, resulting in a large overall reduction.

[0520] In contrast, in the SSF circuit 120, the feedback P-type FET 104 mainly controls the rise time t of the output waveform. r and rise settling time t sr In order to shorten the rise time, although the rise time is shortened more than in the amplification circuit 1100 in this embodiment, the fall time cannot be shortened, resulting in a small total shortening amount.

[0521] Therefore, in the output waveform of the amplification circuit 1100, compared to the SSF circuit 120, the rising edge is slightly slower but the falling edge is steeper, shortening the rising and falling edges of the output waveform. At the same time, the suppression of undershoot during rising and falling edges is slightly weaker, but the suppression of overshoot is stronger, and oscillation of the output waveform is also suppressed.

[0522] As a result, the rise time t of the output waveform of the amplifier circuit 1100 shown in Figure 7 r Even if it increases slightly, the fall time t f This shortens the rise time to t, allowing for an amplification circuit capable of transmitting faster clock signals. sr Even if it increases slightly, the fall-off settling time t sf This allows for a shorter circuit, resulting in an amplifier circuit capable of driving larger output loads.

[0523] Next, the method for driving the amplification circuit 1100 will be explained.

[0524] The ground potential is applied to the source of the load FET 102, and the power supply potential Vdd is applied to the source of the current source FET 103. By applying a fixed potential V1 to the gate of the load FET 102, it is operated in the saturation region, making the load FET 102 a constant current source. By applying a fixed potential V2 to the gate of the current source FET 103, it is operated in the saturation region, making the current source FET 103 a constant current source. By applying a fixed potential V3 to the source of the feedback N-type FET 105, the gate-source voltage is lowered. However, Vdd > V2 > V1 > ground potential (GND), and V A Assume that the relationship ≥V3 ≥ ground potential (GND) is satisfied.

[0525] In this state, an input signal is input to the input terminal connected to the gate of the drive N-type FET 101, and an output signal is output from the output terminal connected to the source of the drive N-type FET 101.

[0526] <Tenth Embodiment> The amplifier circuit according to this embodiment will now be described. In the following description, components similar to those described in the embodiments described above will be denoted by the same reference numerals, and their detailed descriptions will be omitted as appropriate.

[0527] <Regarding the configuration of the amplification circuit> Figure 45 shows an example of the configuration of the amplifier circuit 1200 according to this embodiment. The amplifier circuit 1200 is a form of source follower circuit. In the amplifier circuit 1200 according to this embodiment, unlike the amplifier circuit 1100 of the ninth embodiment, the driving FET is a P-type FET.

[0528] The amplification circuit 1200 comprises a drive P-type FET 201, a load FET 202, a current source FET 203, and a feedback P-type FET 104. The drive P-type FET 201, load FET 202, and feedback P-type FET 104 are all P-type FETs. The current source FET 203 is an N-type FET.

[0529] The source of the load FET 202 is connected to the power supply, and the drain of the load FET 202 is connected to the source of the driver P-type FET 201. The drain of the current source FET 203 is connected to the drain of the driver P-type FET 201, and the source of the current source FET 203 is connected to GND. In other words, the current source FET 203, the driver P-type FET 201, and the load FET 202 are arranged in series between the power supply and GND.

[0530] The gate of the drive P-type FET 201 is connected to the input terminal IN of the amplification circuit 1200. A fixed potential V1 is input to the gate of the load FET 202. As a result, the load FET 202 functions as a constant current source.

[0531] The connection point between the source of the drive P-type FET201 and the drain of the load FET202 is connected to the output terminal OUT.

[0532] The source of the feedback P-type FET 104 is connected to a fixed potential V3. The gate of the feedback P-type FET 104 is connected to the connection point between the drain of the current source FET 203 and the drain of the drive P-type FET 201. The drain of the feedback P-type FET 104 is connected to the output terminal OUT.

[0533] <About the operation of the amplifier circuit> Figure 46 shows an example of the small-signal equivalent circuit of the amplifier circuit 1200 in Figure 45. From Kirchhoff's current law at the drain and output terminals of the driving P-type FET 201, equations (13) and (70) hold.

[0534]

number

[0535] V in If we set = 0, the output resistance can be calculated from equations (13) and (70) as shown in equation (71).

[0536]

number

[0537] In an ideal FET without channel length modulation, r lp →∞, r cn →∞, gm dp r dp >>1, and gm fbp r fbp Since >>1, equation (71) can be approximated as equation (72).

[0538]

number

[0539] Comparing equation (72) with equation (12), in the amplifier circuit 1200, the output resistance is 1 / r of the source follower circuit 210. dp gm fbp It can be seen that the reduction is doubled. Therefore, the driving force of the output load in the amplification circuit 1200 is higher than that of the source follower circuit 210.

[0540] Next, we will return to Figure 45 and explain the small-signal operation of the amplifier circuit 1200.

[0541] When the voltage at the input terminal increases, the gate voltage of the drive P-type FET 201 increases, causing the source-drain current of the drive P-type FET 201 to decrease. As a result, the source voltage of the drive P-type FET 201 increases and the drain voltage decreases. An increase in the source voltage of the drive P-type FET 201 is equivalent to an increase in the voltage at the output terminal.

[0542] Simultaneously, as the drain voltage of the driving P-type FET 201 decreases, the gate voltage of the feedback N-type FET 105 decreases, reducing the source-drain current. Here, since the load FET 202 is a constant current source, Kirchhoff's current law at the output terminal causes the source-drain current of the driving P-type FET 201 to increase. This suppresses the rise in the source voltage and the fall in the drain voltage of the driving P-type FET 201. Suppressing the rise in the source voltage of the driving P-type FET 201 is equivalent to suppressing the voltage rise at the output terminal.

[0543] Conversely, when the voltage at the input terminal decreases, the gate voltage of the drive P-type FET 201 decreases, causing the source-drain current of the drive P-type FET 201 to increase. As a result, the source voltage of the drive P-type FET 201 decreases and the drain voltage increases. A decrease in the source voltage of the drive P-type FET 201 is equivalent to a decrease in the voltage at the output terminal.

[0544] Simultaneously, the increase in the drain voltage of the driving P-type FET 201 causes the gate voltage of the feedback N-type FET 105 to rise, increasing the source-drain current. Since the load FET 202 is a constant current source, Kirchhoff's current law at the output terminal causes the source-drain current of the driving P-type FET 201 to decrease. This suppresses the decrease in the source voltage and the increase in the drain voltage of the driving P-type FET 201. Suppressing the decrease in the source voltage of the driving P-type FET 201 is equivalent to suppressing the decrease in the voltage at the output terminal.

[0545] From the above, in the amplifier circuit 1200 of this embodiment, the output feedback speed is increased compared to the source follower circuit 210 because a feedback P-type FET 104 is added, and the output fluctuation transitions quickly from the transient state to the steady state. In particular, the output feedback speed is greater during the rising edge than during the falling edge of the output waveform. Therefore, in the output waveform of the amplifier circuit 1200, the rising edge is steeper compared to the source follower circuit 210, while the rising and falling edge undershoots are suppressed, and oscillation of the output waveform is also suppressed. As a result, as shown in Figure 7, the rising edge time t of the output waveform of the amplifier circuit 1200 r This shortens the rise time to t, allowing for an amplification circuit capable of transmitting faster clock signals. sr This allows for a shorter circuit, resulting in an amplifier circuit capable of driving larger output loads.

[0546] Furthermore, the amplifier circuit 1200 in this embodiment differs from the SSF circuit 220 in that it adds a feedback P-type FET 104 instead of a feedback N-type FET 105.

[0547] Therefore, similar to the SSF circuit 220, the output feedback speed increases, and the output fluctuation transitions quickly from a transient state to a steady state. However, compared to the source follower circuit 210, the SSF circuit 220 has a higher output feedback speed during the falling edge of the output waveform than during the rising edge, whereas in the amplifier circuit 1200 of this embodiment, the output feedback speed is higher during the rising edge of the output waveform than during the falling edge.

[0548] Here, the driving P-type FET201 controls the fall time t of the output waveform. f and fall settling time t sf The method for shortening the rise time t is the same for both the amplifier circuit 1200 and the SSF circuit 220 in this embodiment, but in the amplifier circuit 1200 in this embodiment, the feedback P-type FET 104 mainly shortens the rise time t of the output waveform. r and rise settling time t srTo shorten the time, both the rise and fall times can be shortened, resulting in a large overall reduction.

[0549] In contrast, in the SSF circuit 220, the feedback N-type FET 105 mainly controls the fall time t of the output waveform. f and fall settling time t sf In order to shorten the fall time, although the fall time is shortened more than that of the amplification circuit 1200 in this embodiment, the fall time cannot be shortened, and the total shortening amount is small.

[0550] Therefore, in the output waveform of the amplification circuit 1200, the rising edge is steeper, even though the falling edge is slightly slower, compared to the SSF circuit 220. This shortens the rise and fall times of the output waveform, while the suppression of rise and fall overshoot is slightly weaker, but the suppression of undershoot is stronger, thus suppressing oscillation of the output waveform.

[0551] As a result, the fall time t of the output waveform of the amplifier circuit 1200 shown in Figure 7 f Even if it increases slightly, the rise time t r This shortens the settling time t, allowing for an amplification circuit capable of transmitting faster clock signals. sf Even if it increases slightly, the startup and settling time t sr This allows for a shorter circuit, resulting in an amplifier circuit capable of driving larger output loads.

[0552] Next, the method for driving the amplifier circuit 1200 will be explained.

[0553] The power supply potential Vdd is applied to the source of the load FET 202, and the ground potential is applied to the source of the current source FET 203. By applying a fixed potential V1 to the gate of the load FET 202, it is operated in the saturation region, making the load FET 202 a constant current source. By applying a fixed potential V2 to the gate of the current source FET 203, it is operated in the saturation region, making the current source FET 203 a constant current source. By applying a fixed potential V3 to the source of the feedback P-type FET 104, the gate-source voltage is lowered. However, Vdd > V1 > V2 > ground potential (GND), and Vdd ≥ V3 ≥ V A Assume that the following relationship is satisfied.

[0554] In this state, the input signal is input to the input terminal connected to the gate of the drive P-type FET 201, and the output signal is output from the output terminal connected to the source of the drive P-type FET 201.

[0555] <Embodiment 11> The amplifier circuit according to this embodiment will now be described. In the following description, components similar to those described in the embodiments described above will be denoted by the same reference numerals, and their detailed descriptions will be omitted as appropriate.

[0556] <Regarding the configuration of the amplification circuit> Figure 47 shows an example of the configuration of the amplifier circuit 1300 according to this embodiment. The amplifier circuit 1300 has the same configuration as the amplifier circuit 1100 shown in Figure 43, except for the connection of the gate of the current source FET 103. That is, the gate of the current source FET 103 is connected to a fixed potential V2 in the amplifier circuit 1100, but in the amplifier circuit 1300 it is connected to the input terminal. As a result, the drive N-type FET 101 and the current source FET 103 constitute an inverter circuit.

[0557] <About the operation of the amplifier circuit> Figure 48 shows an example of the small-signal equivalent circuit of the amplifier circuit 1300 in Figure 47. From Kirchhoff's current law at the drain and output terminals of the driving N-type FET 101, equations (20) and (73) hold.

[0558]

number

[0559] V in If we set = 0, the output resistance can be calculated from equations (20) and (73) as shown in equation (74).

[0560]

number

[0561] Equation (74) is identical to equation (68), which shows the output resistance of the amplifier circuit 1100 in the ninth embodiment. Therefore, it can be seen that the output resistance of the amplifier circuit 1100 in the ninth embodiment and the amplifier circuit 1300 in this embodiment are the same, and the driving force of the output load is also the same.

[0562] Next, we will return to Figure 47 and explain the small-signal operation of the amplifier circuit 1300.

[0563] As the voltage at the input terminal increases, the gate voltages of the drive N-type FET 101 and the current source FET 103 increase, causing the source-drain current of the drive N-type FET 101 to increase and the source-drain current of the current source FET 103 to decrease. As a result, the source voltage of the drive N-type FET 101 increases and the drain voltage decreases more rapidly than in the amplification circuit 1100 of the ninth embodiment. The increase in the source voltage of the drive N-type FET 101 is equivalent to an increase in the voltage at the output terminal.

[0564] Simultaneously, as the drain voltage of the driving N-type FET 101 decreases, the gate voltage of the feedback N-type FET 105 decreases, reducing the source-drain current. Here, since the load FET 102 is a constant current source, Kirchhoff's current law at the output terminal causes the source-drain current of the driving N-type FET 101 to decrease. This suppresses the rise in the source voltage and the fall in the drain voltage of the driving N-type FET 101. Suppressing the rise in the source voltage of the driving N-type FET 101 is equivalent to suppressing the voltage rise at the output terminal.

[0565] Conversely, when the voltage at the input terminal decreases, the gate voltages of the drive N-type FET 101 and the current source FET 103 decrease, causing the source-drain current of the drive N-type FET 101 to decrease and the source-drain current of the current source FET 103 to increase. As a result, the source voltage of the drive N-type FET 101 decreases and the drain voltage increases more rapidly than in the amplification circuit 1100 of the ninth embodiment. The decrease in the source voltage of the drive N-type FET 101 is equivalent to a decrease in the voltage at the output terminal.

[0566] Simultaneously, the increase in the drain voltage of the driving N-type FET 101 causes the gate voltage of the feedback N-type FET 105 to rise, increasing the source-drain current. Since the load FET 102 is a constant current source, Kirchhoff's current law at the output terminal causes the source-drain current of the driving N-type FET 101 to increase. This suppresses the decrease in the source voltage and the increase in the drain voltage of the driving N-type FET 101. Suppression of the decrease in the source voltage of the driving N-type FET 101 is equivalent to suppression of the voltage decrease at the output terminal.

[0567] From the above, in the amplifier circuit 1300 of this embodiment, unlike the amplifier circuit 1100 of the ninth embodiment, the gate of the current source FET 103 is connected to the input terminal, so the voltage change at node A becomes faster, and the output fluctuation transitions quickly from the transient state to the steady state. In particular, the output feedback speed is greater during the falling edge than during the rising edge of the output waveform. Therefore, in the output waveform of the amplifier circuit 1300, the rising and falling edges become steep, while rising and falling edge overshoots and undershoots are suppressed, and oscillation of the output waveform is also suppressed. As a result, the rising time t of the output waveform of the amplifier circuit 1300 r and fall time t f This shortens the rise time to t, allowing for an amplification circuit capable of transmitting faster clock signals. sr and fall settling time t sf This allows for a shorter circuit, resulting in an amplifier circuit capable of driving larger output loads.

[0568] Next, the method for driving the amplification circuit 1300 will be explained.

[0569] The ground potential is applied to the source of the load FET 102, and the power supply potential Vdd is applied to the source of the current source FET 103. By applying a fixed potential V1 to the gate of the load FET 102, it is operated in the saturation region, making the load FET 102 a constant current source, and by applying a fixed potential V3 to the source of the feedback N-type FET 105, the gate-source voltage is lowered. However, Vdd > V1 > ground potential (GND), and V A Assume that the relationship ≥V3 ≥ ground potential (GND) is satisfied.

[0570] In this state, an input signal is input to the input terminal connected to the gate of the drive N-type FET 101 and the gate of the current source FET 103, and an output signal is output from the output terminal connected to the source of the drive N-type FET 101.

[0571] <Twelfth Embodiment> The amplifier circuit according to this embodiment will now be described. In the following description, components similar to those described in the embodiments described above will be denoted by the same reference numerals, and their detailed descriptions will be omitted as appropriate.

[0572] <Regarding the configuration of the amplification circuit> Figure 49 shows an example of the configuration of the amplifier circuit 1400 according to this embodiment. The amplifier circuit 1400 has the same configuration as the amplifier circuit 1200 shown in Figure 45, except for the connection of the gate of the current source FET 203. That is, the gate of the current source FET 203 is connected to a fixed potential V2 in the amplifier circuit 1200, but in the amplifier circuit 1400 it is connected to the input terminal. As a result, the drive P-type FET 201 and the current source FET 203 constitute an inverter circuit.

[0573] <About the operation of the amplifier circuit> Figure 50 shows an example of the small-signal equivalent circuit of the amplifier circuit 1400 in Figure 49. From Kirchhoff's current law at the drain and output terminals of the driving P-type FET 201, equations (23) and (75) hold.

[0574]

number

[0575] V in If we set = 0, the output resistance can be calculated from equations (23) and (75) as shown in equation (76).

[0576]

number

[0577] Equation (76) is identical to equation (71), which shows the output resistance of the amplifier circuit 1200 in the tenth embodiment. Therefore, it can be seen that the output resistance of the amplifier circuit 1200 in the tenth embodiment and the amplifier circuit 1400 in this embodiment are the same, and the driving force of the output load is also the same.

[0578] Next, we will return to Figure 49 and explain the small-signal operation of the amplifier circuit 1400.

[0579] As the voltage at the input terminal increases, the gate voltages of the drive P-type FET 201 and the current source FET 203 increase, causing the source-drain current of the drive P-type FET 201 to decrease and the source-drain current of the current source FET 203 to increase. As a result, the source voltage of the drive P-type FET 201 increases and the drain voltage decreases more rapidly than in the amplification circuit 1200 of the tenth embodiment. The increase in the source voltage of the drive P-type FET 201 is equivalent to an increase in the voltage at the output terminal.

[0580] Simultaneously, as the drain voltage of the driving P-type FET 201 decreases, the gate voltage of the feedback P-type FET 104 decreases, increasing the source-drain current. Here, since the load FET 202 is a constant current source, Kirchhoff's current law at the output terminal causes the source-drain current of the driving P-type FET 201 to increase. This suppresses the rise in the source voltage and the fall in the drain voltage of the driving P-type FET 201. Suppressing the rise in the source voltage of the driving P-type FET 201 is equivalent to suppressing the voltage rise at the output terminal.

[0581] Conversely, when the voltage at the input terminal decreases, the gate voltages of the drive P-type FET 201 and the current source FET 203 decrease, causing the source-drain current of the drive P-type FET 201 to increase and the source-drain current of the current source FET 203 to decrease. As a result, the source voltage of the drive P-type FET 201 decreases and the drain voltage increases more rapidly than in the amplification circuit 1200 of the tenth embodiment. The decrease in the source voltage of the drive P-type FET 201 is equivalent to a decrease in the voltage at the output terminal.

[0582] Simultaneously, the increase in the drain voltage of the drive P-type FET 201 causes the gate voltage of the feedback P-type FET 104 to rise, reducing the source-drain current. Since the load FET 202 is a constant current source, Kirchhoff's current law at the output terminal causes the source-drain current of the drive P-type FET 201 to decrease. This suppresses the decrease in the source voltage and the increase in the drain voltage of the drive P-type FET 201. Suppressing the decrease in the source voltage of the drive P-type FET 201 is equivalent to suppressing the decrease in the voltage at the output terminal.

[0583] From the above, in the amplifier circuit 1400 of this embodiment, unlike the amplifier circuit 1200 of the tenth embodiment, the gate of the current source FET 203 is connected to the input terminal, so the voltage change at node A becomes faster, and the output fluctuation transitions quickly from the transient state to the steady state. In particular, the output feedback speed is greater during the rising edge than during the falling edge of the output waveform. Therefore, in the output waveform of the amplifier circuit 1400, the rising and falling edges become steep, while rising and falling edge overshoots and undershoots are suppressed, and oscillation of the output waveform is also suppressed. As a result, the rising time t of the output waveform of the amplifier circuit 1400 r and fall time t f This shortens the rise time to t, allowing for an amplification circuit capable of transmitting faster clock signals. sr and fall settling time t sf This allows for a shorter circuit, resulting in an amplifier circuit capable of driving larger output loads.

[0584] Next, the method for driving the amplifier circuit 1400 will be explained.

[0585] The power supply potential Vdd is applied to the source of the load FET 202, and the ground potential is applied to the source of the current source FET 203. By applying a fixed potential V1 to the gate of the load FET 202, it is operated in the saturation region to become a constant current source, and by applying a fixed potential V3 to the source of the feedback P-type FET 104, the gate-source voltage is lowered. However, Vdd > V1 > ground potential (GND), and Vdd ≥ V3 ≥ VA Assume that the following relationship is satisfied.

[0586] In this state, an input signal is input to the input terminal connected to the gate of the drive P-type FET 201 and the gate of the current source FET 203, and an output signal is output from the output terminal connected to the source of the drive P-type FET 201.

[0587] In addition, in any of the first to twelfth embodiments described above, the fixed potential V3 and the ground potential (or power supply potential) may be equal. However, in that case, the gate-source voltage of either the feedback N-type FET or the feedback P-type FET will not decrease.

[0588] Furthermore, in any of the first to twelfth embodiments described above, the fixed potentials V1 and V3 may be equal. That is, the terminal that was previously set to fixed potential V3 may be connected to fixed potential V1. In that case, the number of power supply terminals is reduced by one, which improves the convenience of the circuit.

[0589] Figure 51 shows a modified configuration of the one shown in Figure 1. As illustrated in the example in the figure, the fixed potential V3 may be omitted, and the corresponding points may be connected in common to the fixed potential V1.

[0590] Figure 52 shows a modified configuration of the one shown in Figure 2. As illustrated in the example in the figure, the fixed potential V3 may be omitted, and the corresponding points may be connected in common to the fixed potential V1.

[0591] Figure 53 shows a modified configuration of the one shown in Figure 3. As shown in the example in the figure, the fixed potential V3 may be omitted, and the corresponding points may be connected in common to the fixed potential V1.

[0592] Figure 54 shows a modified configuration of the one shown in Figure 11. As illustrated in the example in the figure, the fixed potential V3 may be omitted, and the corresponding points may be connected in common to the fixed potential V1.

[0593] Figure 55 shows a modified example of the configuration shown in Figure 17. As illustrated in the example in the figure, the fixed potential V3 may be omitted, and the corresponding points may be connected in common to the fixed potential V1.

[0594] Figure 56 shows a modified example of the configuration shown in Figure 18. As illustrated in the example in the figure, the fixed potential V3 may be omitted, and the corresponding points may be connected in common to the fixed potential V1.

[0595] Figure 57 shows a modified example of the configuration shown in Figure 19. As illustrated in the example in the figure, the fixed potential V3 may be omitted, and the corresponding points may be connected in common to the fixed potential V1.

[0596] Figure 58 shows a modified example of the configuration shown in Figure 21. As illustrated in the example in the figure, the fixed potential V3 may be omitted, and the corresponding points may be connected in common to the fixed potential V1.

[0597] Figure 59 shows a modified configuration of the one shown in Figure 23. As illustrated in the example in the figure, the fixed potential V3 may be omitted, and the corresponding points may be connected in common to the fixed potential V1.

[0598] Figure 60 shows a modified version of the configuration shown in Figure 27. As shown in the example in the figure, the fixed potential V3 may be omitted, and the corresponding points may be connected in common to the fixed potential V1.

[0599] Figure 61 shows a modified configuration of the one shown in Figure 31. As illustrated in the example in the figure, the fixed potential V3 may be omitted, and the corresponding points may be connected in common to the fixed potential V1.

[0600] Figure 62 shows a modified example of the configuration shown in Figure 37. As illustrated in the example in the figure, the fixed potential V3 may be omitted, and the corresponding points may be connected in common to the fixed potential V1.

[0601] Figure 63 shows a modified configuration of the one shown in Figure 43. As illustrated in the example in the figure, the fixed potential V3 may be omitted, and the corresponding points may be connected in common to the fixed potential V1.

[0602] Figure 64 shows another modification of the configuration shown in Figure 43. As illustrated in the example in this figure, the fixed potential V3 may be omitted, and the source of the feedback N-type FET 105 may be connected to the source of the load FET 102.

[0603] Figure 65 shows a modified configuration of the one shown in Figure 45. As illustrated in the example in the figure, the fixed potential V3 may be omitted, and the corresponding points may be connected in common to the fixed potential V1.

[0604] Figure 66 shows another modification of the configuration shown in Figure 45. As illustrated in the example in the figure, the fixed potential V3 may be omitted, and the source of the feedback P-type FET 104 may be connected to the source of the load FET 202.

[0605] Figure 67 shows a modified configuration of the one shown in Figure 47. As illustrated in the example in the figure, the fixed potential V3 may be omitted, and the corresponding points may be connected in common to the fixed potential V1.

[0606] Figure 68 shows another modification of the configuration shown in Figure 47. As illustrated in the example in the figure, the fixed potential V3 may be omitted, and the source of the feedback N-type FET 105 may be connected to the source of the load FET 102.

[0607] Figure 69 shows a modified configuration of the one shown in Figure 49. As illustrated in the example in the figure, the fixed potential V3 may be omitted, and the corresponding points may be connected in common to the fixed potential V1.

[0608] Figure 70 shows another modification of the configuration shown in Figure 49. As illustrated in the example in this figure, the fixed potential V3 may be omitted and the source of the feedback P-type FET 104 may be connected to the source of the load FET 202.

[0609] <Regarding the effects produced by the embodiments described above> Next, examples of the effects produced by the embodiments described above will be shown. In the following description, the effects will be described based on the specific configurations illustrated in the embodiments described above, but they may be replaced with other specific configurations illustrated in this specification to the extent that similar effects are produced. That is, for convenience, one of the corresponding specific configurations may be described below, but it may be replaced with another corresponding specific configuration.

[0610] Furthermore, such substitutions may be made across multiple embodiments. That is, the configurations exemplified in different embodiments may be combined to produce similar effects.

[0611] According to the embodiment described above, the amplification circuit is an amplification circuit that amplifies a signal input to the input terminal IN and outputs it to the output terminal OUT. The amplification circuit comprises a first transistor of a first conductivity type (e.g., P-type), a second transistor of a second conductivity type different from the first conductivity type (e.g., N-type), a third transistor which is a field-effect transistor of a third conductivity type, and a fourth transistor which is a field-effect transistor of a fourth conductivity type different from the first conductivity type. Here, the first transistor corresponds to one of the following, for example, a feedback P-type FET 104, a feedback N-type FET 105, a feedback PNP-type BJT 504, a feedback NPN-type BJT 605, etc. The second transistor corresponds to at least one of the following, for example, a drive N-type FET 101, a drive P-type FET 201, a drive PNP-type BJT 801, etc. The third transistor corresponds to at least one of the following, for example, a load FET 102, a load FET 202, etc. Furthermore, the fourth transistor corresponds to at least one of the following: for example, a feedback N-type FET 105, a feedback P-type FET 104, etc. The feedback P-type FET 104 has a first control terminal, a first current terminal connected to a first potential, and a second current terminal connected to the output terminal OUT. Here, the first potential corresponds to at least one of the following: for example, the power supply potential Vdd, the ground potential, etc. The drive N-type FET 101 has a second control terminal connected to the input terminal IN, a third current terminal connected to the output terminal OUT, and a fourth current terminal connected to the first control terminal of the feedback P-type FET 104. The load FET 102 has a third control terminal which is the gate terminal connected to a first fixed potential, a fifth current terminal which is the source terminal connected to a second potential, and a sixth current terminal which is the drain terminal connected to the output terminal OUT. Here, the first fixed potential corresponds to, for example, a fixed potential V1, etc. Furthermore, the second potential corresponds to at least one of the following: for example, the ground potential, the power supply potential Vdd, etc.The feedback N-type FET 105 has a fourth control terminal, which is the gate terminal connected at the same potential as the first control terminal of the feedback P-type FET 104; a seventh current terminal, which is the source terminal connected to the third fixed potential; and an eighth current terminal, which is the drain terminal connected to the output terminal OUT. Here, the third fixed potential corresponds to, for example, a fixed potential V3.

[0612] This configuration reduces excess steady-state current in the amplification circuit, thereby shortening the rise (settling time) and fall (settling time) of the output waveform. Furthermore, the through-current flowing through the CMOS inverter, consisting of the feedback P-type FET 104 and feedback N-type FET 105, is reduced, resulting in lower power consumption. Additionally, the range in which the input / output characteristics are linear is shifted overall, reducing the power consumption of the amplification circuit and suppressing hot carrier generation. Moreover, because the gate-source voltages of the two feedback transistors are aligned, an inverter can be constructed using feedback transistors with symmetrical design parameters (threshold voltage, gate length-to-gate width ratio, gate oxide capacitance, etc.), increasing design flexibility and versatility.

[0613] Furthermore, the same effect can be achieved even if other configurations exemplified in this specification are appropriately added to the above configuration, that is, if other configurations in this specification that are not mentioned as the above configuration are appropriately added.

[0614] Furthermore, according to the embodiments described above, the feedback PNP type BJT504 is a bipolar transistor. The first control terminal of the feedback PNP type BJT504 is the base terminal, the first current terminal of the feedback PNP type BJT504 is the emitter terminal, and the second current terminal of the feedback PNP type BJT504 is the collector terminal. With this configuration, the rise time (settling time) and fall time (settling time) of the output waveform can be shortened by reducing the excess steady-state current in the amplification circuit.

[0615] Furthermore, according to the embodiment described above, the driving PNP type BJT801 is a bipolar transistor. The second control terminal of the driving PNP type BJT801 is the base terminal, the third current terminal of the driving PNP type BJT801 is the emitter terminal, and the fourth current terminal of the driving PNP type BJT801 is the collector terminal. With this configuration, the rise time (settling time) and fall time (settling time) of the output waveform can be shortened by reducing the excess steady-state current in the amplification circuit.

[0616] Furthermore, according to the embodiment described above, the driving N-type FET 101 is a field-effect transistor. The second control terminal of the driving N-type FET 101 is the gate terminal, the third current terminal of the driving N-type FET 101 is the source terminal, and the fourth current terminal of the driving N-type FET 101 is the drain terminal. With this configuration, the rise time (settling time) and fall time (settling time) of the output waveform can be shortened by reducing the excess steady-state current in the amplification circuit.

[0617] Furthermore, according to the embodiment described above, the feedback P-type FET 104 is a field-effect transistor. The first control terminal of the feedback P-type FET 104 is the gate terminal, the first current terminal of the feedback P-type FET 104 is the source terminal, and the second current terminal of the feedback P-type FET 104 is the drain terminal. The driving N-type FET 101 is also a field-effect transistor. The second control terminal of the driving N-type FET 101 is the gate terminal, the third current terminal of the driving N-type FET 101 is the source terminal, and the fourth current terminal of the driving N-type FET 101 is the drain terminal. Furthermore, the amplification circuit includes a current source element that supplies current to the fourth current terminal of the driving N-type FET 101. Here, the current source element corresponds to at least one of, for example, a current source FET 103, a current source FET 203, etc. With such a configuration, the rise time (settling time) and fall time (settling time) of the output waveform can be shortened by reducing the excess steady-state current in the amplification circuit.

[0618] Furthermore, according to the embodiment described above, the current source FET 103 has a fifth control terminal which is a gate terminal connected to a second fixed potential, a ninth current terminal which is a source terminal connected to the power supply potential Vdd, and a tenth current terminal which is a drain terminal connected to the fourth current terminal of the drive N-type FET 101. The current source FET 103 is also a fifth transistor as a field-effect transistor of the first conductivity type (for example, P-type). Here, the second fixed potential corresponds to, for example, a fixed potential V2. With such a configuration, the rise time (settling time) and fall time (settling time) of the output waveform can be shortened by reducing the excess steady-state current in the amplification circuit.

[0619] Furthermore, according to the embodiment described above, the fixed potential V2 is connected to the input terminal IN. With this configuration, since the gate of the current source FET 103 is connected to the input terminal, the voltage change at node A becomes faster, and the output fluctuation transitions quickly from a transient state to a steady state. In particular, the output feedback speed is greater during the falling edge than during the rising edge of the output waveform. As a result, in the output waveform of the amplifier circuit 1300, the rising and falling edges become steep, while the rising and falling edge overshoots and undershoots are suppressed, and oscillation of the output waveform is also suppressed. As a result, the rising time t of the output waveform of the amplifier circuit 1300 r and fall time t f This shortens the circuit and allows for the creation of an amplification circuit capable of transmitting faster clock signals.

[0620] Furthermore, according to the embodiment described above, in a steady state, no current flows between the connection point (node ​​X) between the third current terminal of the drive N-type FET 101 and the sixth current terminal, which is the drain terminal of the load FET 102, and the output terminal OUT. With such a configuration, in a steady state I outWhen I0 = 0, the source-drain currents of the feedback P-type FET 104 and the feedback N-type FET 105 become equivalent. Therefore, the input-output characteristics of the CMOS inverter consisting of the feedback P-type FET 104 and the feedback N-type FET 105 become symmetrical, and the excess steady-state current in the amplification circuit is reduced.

[0621] Furthermore, according to the embodiment described above, when the first potential is the power supply potential Vdd and the second potential is the ground potential, the relationship in equation (114) is satisfied in the steady state. With such a configuration, the steady state I out When I0 = 0, the source-drain currents of the feedback P-type FET 104 and the feedback N-type FET 105 become equivalent. Therefore, the input-output characteristics of the CMOS inverter consisting of the feedback P-type FET 104 and the feedback N-type FET 105 become symmetrical, and the excess steady-state current in the amplification circuit is reduced.

[0622] Furthermore, according to the embodiment described above, when the first potential is the power supply potential Vdd and the second potential is the ground potential, the relationship in equation (115) is satisfied in the steady state. With such a configuration, the steady state I out When I0 = 0, the source-drain currents of the feedback P-type FET 104 and the feedback N-type FET 105 become equivalent. Therefore, the input-output characteristics of the CMOS inverter consisting of the feedback P-type FET 104 and the feedback N-type FET 105 become symmetrical, and the excess steady-state current in the amplification circuit is reduced.

[0623] Furthermore, according to the embodiment described above, when the first potential is the ground potential and the second potential is the power supply potential Vdd, the relationship in equation (214) is satisfied in the steady state. With such a configuration, the steady state I out When I0 = 0, the source-drain currents of the feedback P-type FET 104 and the feedback N-type FET 105 become equivalent. Therefore, the input-output characteristics of the CMOS inverter consisting of the feedback P-type FET 104 and the feedback N-type FET 105 become symmetrical, and the excess steady-state current in the amplification circuit is reduced.

[0624] Furthermore, according to the embodiment described above, when the first potential is the ground potential and the second potential is the power supply potential Vdd, the relationship in equation (215) is satisfied in the steady state. With such a configuration, the steady state I out When I0 = 0, the source-drain currents of the feedback P-type FET 104 and the feedback N-type FET 105 become equivalent. Therefore, the input-output characteristics of the CMOS inverter consisting of the feedback P-type FET 104 and the feedback N-type FET 105 become symmetrical, and the excess steady-state current in the amplification circuit is reduced.

[0625] Furthermore, according to the embodiment described above, the sum of the fixed potential V1 and the fixed potential V2 is equal to the power supply potential Vdd. With such a configuration, steady state I out When I0 = 0, the source-drain currents of the feedback P-type FET 104 and the feedback N-type FET 105 become equivalent. Therefore, the input-output characteristics of the CMOS inverter consisting of the feedback P-type FET 104 and the feedback N-type FET 105 become symmetrical, and the excess steady-state current in the amplification circuit is reduced.

[0626] Furthermore, according to the embodiments described above, -Vthfbp = Vthfbn and βfbp = βfbn. With such a configuration, steady state I out When I0 = 0, the source-drain currents of the feedback P-type FET 104 and the feedback N-type FET 105 become equivalent. Therefore, the input-output characteristics of the CMOS inverter consisting of the feedback P-type FET 104 and the feedback N-type FET 105 become symmetrical, and the excess steady-state current in the amplification circuit is reduced.

[0627] According to the embodiment described above, the amplification circuit comprises a feedback P-type FET 104 which is a field-effect transistor of a first conductivity type, a drive N-type FET 101 which is a field-effect transistor of a second conductivity type different from the first conductivity type, a load FET 102 which is a field-effect transistor of a second conductivity type, a feedback N-type FET 105 which is a field-effect transistor of a second conductivity type, a current source FET 103, a differential amplifier 162 (or differential amplifier 262), and a switch. Here, the switch corresponds to at least one of, for example, a switch 161, a switch 261, etc. The feedback P-type FET 104 has a first control terminal which is the gate terminal, a first current terminal which is the source terminal connected to the power supply potential Vdd, and a second current terminal which is the drain terminal connected to the output terminal OUT. The drive N-type FET 101 has a second control terminal, which is the gate terminal connected to the input terminal IN, a third current terminal, which is the source terminal, and a fourth current terminal, which is the drain terminal connected to the first control terminal, which is the gate terminal of the feedback P-type FET 104. The load FET 102 has a third control terminal, which is the gate terminal connected to a fixed potential V1, a fifth current terminal, which is the source terminal connected to ground potential, and a sixth current terminal, which is the drain terminal connected to the third current terminal, which is the source terminal of the drive N-type FET 101. The feedback N-type FET 105 has a fourth control terminal, which is the gate terminal connected at the same potential as the first control terminal, which is the gate terminal of the feedback P-type FET 104, a seventh current terminal, which is the source terminal connected to a fixed potential V3, and an eighth current terminal, which is the drain terminal connected to the output terminal OUT. The current source FET 103 supplies current to the fourth current terminal, which is the drain terminal of the drive N-type FET 101. The differential amplifier 162 has its first differential input terminal connected to the connection point (node ​​X) between the third current terminal, which is the source terminal of the drive N-type FET 101, and the sixth current terminal, which is the drain terminal of the load FET 102. The differential amplifier 162 also has its second differential input terminal connected to the output terminal OUT. Switch 161 can switch between connecting the first differential input terminal and the second differential input terminal of the differential amplifier 162.

[0628] With this configuration, the rise time (settling time) and fall time (settling time) of the output waveform can be shortened by reducing the excess steady-state current in the amplification circuit. In addition, power consumption is reduced because the through-current flowing through the CMOS inverter consisting of the feedback P-type FET 104 and feedback N-type FET 105 is reduced. Furthermore, since the range in which the input / output characteristics are linear is shifted overall, the power consumption of the amplification circuit can be reduced and hot carrier generation can be suppressed. In addition, since the gate-source voltages of the two feedback transistors are aligned, an inverter consisting of feedback transistors with symmetrical design parameters (threshold voltage, ratio of gate length to gate width, gate oxide capacitance, etc.) can be constructed, increasing design flexibility and versatility. Furthermore, by adjusting V1 or V2 so that the output voltage of the differential amplifier 162 becomes 0V, the steady state I out When I0 = 0, the source-drain currents of the feedback P-type FET 104 and the feedback N-type FET 105 become equivalent. Therefore, the input-output characteristics of the CMOS inverter consisting of the feedback P-type FET 104 and the feedback N-type FET 105 become symmetrical, and the excess steady-state current in the amplification circuit is reduced.

[0629] Furthermore, the same effect can be achieved even if at least one of the other configurations illustrated in the present specification is appropriately added to the above configuration, that is, if other configurations illustrated in the present specification that are not mentioned as the above configuration are appropriately added.

[0630] Furthermore, according to the embodiments described above, the feedback P-type FET 104 and the feedback N-type FET 105 are enhancement-type transistors. With such a configuration, the threshold voltage Vth = -Vth fbp =Vth fbn This value becomes greater than 0. As a result, the through-current of the CMOS inverter consisting of the feedback P-type FET 104 and the feedback N-type FET 105 is reduced, and the power consumption of the amplification circuit 100 is reduced.

[0631] Furthermore, according to the embodiment described above, the current source FET 103, the drive N-type FET 101, and the load FET 102 are depletion-type transistors. With such a configuration, the threshold voltage Vth = -Vth cp =Vth ln =Vth dn This becomes 0 or less. Therefore, the input voltage of the amplification circuit 100 can be reduced, and the power consumption of the amplification circuit 100 and the generation of hot carriers can be suppressed.

[0632] According to the embodiment described above, the composite circuit comprises an amplification circuit and an evaluation circuit. The evaluation circuit is used to determine fixed potentials V1 and V2 to satisfy the condition that no current flows between the connection point between the third current terminal of the driving N-type FET 101 and the sixth current terminal, which is the drain terminal of the load FET 102, and the output terminal OUT. The evaluation circuit comprises a sixth transistor which is a field-effect transistor of a first conductivity type, a seventh transistor which is a field-effect transistor of a second conductivity type different from the first conductivity type, an eighth transistor which is a field-effect transistor of a second conductivity type different from the first conductivity type, a ninth transistor which is a field-effect transistor of a second conductivity type, and a current source FET 103. Here, the sixth transistor corresponds to at least one of, for example, a feedback P-type FET 104, a feedback N-type FET 105, etc. Also, the seventh transistor corresponds to at least one of, for example, a driving N-type FET 101, a driving P-type FET 201, etc. Furthermore, the eighth transistor corresponds to at least one of the following: load FET 102, load FET 202, etc. Also, the ninth transistor corresponds to at least one of the following: feedback N-type FET 105, feedback P-type FET 104, etc. The feedback P-type FET 104 has a sixth control terminal which is the gate terminal, an eleventh current terminal which is the source terminal connected to the power supply potential Vdd, and a twelfth current terminal which is the drain terminal connected to the output terminal OUT. The drive N-type FET 101 has a seventh control terminal which is the gate terminal connected to the input terminal IN, a thirteenth current terminal which is the source terminal, and a fourteenth current terminal which is the drain terminal connected to the sixth control terminal which is the gate terminal of the feedback P-type FET 104. The load FET 102 has an eighth control terminal which is the gate terminal connected to the fixed potential V1, a fifteenth current terminal which is the source terminal connected to the ground potential, and a sixteenth current terminal which is the drain terminal connected to the thirteenth current terminal which is the source terminal of the drive N-type FET 101.The feedback N-type FET 105 has a 9th control terminal, which is a gate terminal connected at the same potential as the 6th control terminal, which is the gate terminal of the feedback P-type FET 104; a 17th current terminal, which is a source terminal connected to a fixed potential V3; and a 18th current terminal, which is a drain terminal connected to the output terminal OUT. The current source FET 103 supplies current to the 14th current terminal, which is the drain terminal of the drive N-type FET 101.

[0633] With this configuration, the rise time (settling time) and fall time (settling time) of the output waveform can be shortened by reducing the excess steady-state current in the amplification circuit. In addition, power consumption is reduced because the through-current flowing through the CMOS inverter consisting of the feedback P-type FET 104 and feedback N-type FET 105 is reduced. Furthermore, since the range in which the input / output characteristics are linear is shifted overall, the power consumption of the amplification circuit can be reduced and hot carrier generation can be suppressed. Also, since the gate-source voltages of the two feedback transistors are aligned, an inverter consisting of feedback transistors with symmetrical design parameters (threshold voltage, ratio of gate length to gate width, gate oxide capacitance, etc.) can be constructed, increasing design flexibility and versatility. In addition, by adjusting V1 or V2 so that the potential difference between the source of the driving N-type FET 101 and the drain of the load FET 102 (for example, node X in Figure 8) and the drain of the feedback P-type FET 104 and the drain of the feedback N-type FET 105 (output terminal OUT) is 0V, the steady state I out When I0 = 0, the source-drain currents of the feedback P-type FET 104 and the feedback N-type FET 105 become equivalent. Therefore, the input-output characteristics of the CMOS inverter consisting of the feedback P-type FET 104 and the feedback N-type FET 105 become symmetrical, and the excess steady-state current in the amplification circuit is reduced.

[0634] Unless otherwise specified, the order in which each process is performed can be changed.

[0635] Furthermore, the same effect can be achieved even if other configurations exemplified in this specification are appropriately added to the above configuration, that is, if other configurations in this specification that are not mentioned as above configurations are appropriately added.

[0636] Furthermore, according to the embodiment described above, the connection point between the 13th current terminal, which is the source terminal of the drive N-type FET 101, and the 16th current terminal, which is the drain terminal of the load FET 102, and the output terminal OUT can be selectively short-circuited. With such a configuration, the steady state I can also be controlled by adjusting V1 or V2 so that the potential difference between the source of the drive N-type FET 101 and the drain of the load FET 102 (for example, node X in Figure 8) and the drain of the feedback P-type FET 104 and the drain of the feedback N-type FET 105 (output terminal OUT) becomes 0V. out When I0 = 0, the source-drain currents of the feedback P-type FET 104 and the feedback N-type FET 105 become equivalent. Therefore, the input-output characteristics of the CMOS inverter consisting of the feedback P-type FET 104 and the feedback N-type FET 105 become symmetrical, and the excess steady-state current in the amplification circuit is reduced.

[0637] Furthermore, according to the embodiment described above, the amplification circuit comprises a first transistor of the first conductivity type, a drive N-type FET 101 of the first conductivity type, and a load FET 102 which is a field-effect transistor of the third conductivity type. Here, the first transistor corresponds to, for example, one of the following: a feedback N-type FET 105, a feedback P-type FET 104, etc. The feedback N-type FET 105 has a first control terminal, a first current terminal connected to a fixed potential V3, and a second current terminal connected to the output terminal OUT. The drive N-type FET 101 has a second control terminal connected to the input terminal IN, a third current terminal connected to the output terminal OUT, and a fourth current terminal connected to the first control terminal of the feedback N-type FET 105. The load FET 102 has a third control terminal which is the gate terminal connected to a fixed potential V1, a fifth current terminal which is the source terminal connected to the ground potential, and a sixth current terminal which is the drain terminal connected to the output terminal OUT.

[0638] With this configuration, the excess steady-state current in the amplification circuit is reduced, thereby shortening the rise time (settling time) and fall time (settling time) of the output waveform. Furthermore, the reduced number of transistors reduces noise. Here, the N-type drive transistor can handle the rise time of the output waveform, and the P-type feedback transistor can handle the fall time. Alternatively, the P-type drive transistor can handle the fall time, and the N-type feedback transistor can handle the rise time. Therefore, the rise-to-settling time or fall-to-settling time can be shortened.

[0639] Furthermore, according to the embodiment described above, the feedback N-type FET 105 is a field-effect transistor. The first control terminal of the feedback N-type FET 105 is the gate terminal, the first current terminal of the feedback N-type FET 105 is the source terminal, and the second current terminal of the feedback N-type FET 105 is the drain terminal. The driving N-type FET 101 is also a field-effect transistor. The second control terminal of the driving N-type FET 101 is the gate terminal, the third current terminal of the driving N-type FET 101 is the source terminal, and the fourth current terminal of the driving N-type FET 101 is the drain terminal. Furthermore, the amplification circuit includes a current source FET 103 that supplies current to the fourth current terminal of the driving N-type FET 101. With this configuration, the rise time (settling time) and fall time (settling time) of the output waveform can be shortened by reducing the excess steady-state current in the amplification circuit. In addition, noise can be reduced because the number of transistors is small.

[0640] Furthermore, according to the embodiment described above, the current source FET 103 is a field-effect transistor of a fourth conductivity type different from the first conductivity type, having a fourth control terminal which is a gate terminal connected to a fixed potential V2, a seventh current terminal which is a source terminal connected to the power supply potential Vdd, and an eighth current terminal which is a drain terminal connected to the fourth current terminal of the drive N-type FET 101. With this configuration, the rise time (settling time) and fall time (settling time) of the output waveform can be shortened by reducing the excess steady-state current in the amplification circuit. In addition, noise can be reduced because the number of transistors is small.

[0641] Furthermore, according to the embodiment described above, the fixed potential V2 is connected to the input terminal IN. With this configuration, since the gate of the current source FET 103 is connected to the input terminal, the voltage change at node A becomes faster, and the output fluctuation transitions quickly from a transient state to a steady state. In particular, the output feedback speed is greater during the falling edge than during the rising edge of the output waveform. As a result, in the output waveform of the amplifier circuit 1300, the rising and falling edges become steep, while the rising and falling edge overshoots and undershoots are suppressed, and oscillation of the output waveform is also suppressed. As a result, the rising time t of the output waveform of the amplifier circuit 1300 r and fall time t f This shortens the circuit and allows for the creation of an amplification circuit capable of transmitting faster clock signals.

[0642] Furthermore, according to the embodiment described above, the amplification circuit comprises a first field-effect transistor of a first conductivity type, a second field-effect transistor of a first conductivity type, a third field-effect transistor of a third conductivity type, and a fourth field-effect transistor of a fourth conductivity type different from the first conductivity type. Here, the first field-effect transistor corresponds to at least one of, for example, a feedback N-type FET 105, a feedback P-type FET 104, etc. The second field-effect transistor corresponds to at least one of, for example, a driving N-type FET 101, a driving P-type FET 201, etc. The third field-effect transistor corresponds to at least one of, for example, a load FET 102, a load FET 202, etc. The fourth field-effect transistor corresponds to at least one of, for example, a current source FET 103, a current source FET 203, etc. The feedback N-type FET 105 has a first gate terminal, a first source terminal connected to a fixed potential V3, and a first drain terminal connected to the output terminal OUT. The drive N-type FET 101 has a second gate terminal connected to the input terminal IN, a second source terminal connected to the output terminal OUT, and a second drain terminal connected to the first gate terminal of the feedback N-type FET 105. The load FET 102 has a third gate terminal connected to a fixed potential V1, a third source terminal connected to ground potential, and a third drain terminal connected to the output terminal OUT. The current source FET 103 has a fourth gate terminal connected to the input terminal IN, a fourth source terminal connected to the power supply potential Vdd, and a fourth drain terminal connected to the second drain terminal of the drive N-type FET 101.

[0643] With this configuration, the excess steady-state current in the amplification circuit is reduced, thereby shortening the rise time (settling time) and fall time (settling time) of the output waveform. Furthermore, the reduced number of transistors reduces noise. Here, the N-type drive transistor can handle the rise time of the output waveform, and the P-type feedback transistor can handle the fall time. Alternatively, the P-type drive transistor can handle the fall time, and the N-type feedback transistor can handle the rise time. Therefore, the rise-to-settling time or fall-to-settling time can be shortened. Also, because the gate of the current source FET 103 is connected to the input terminal, the voltage change at node A becomes faster, and the output fluctuation transitions quickly from a transient state to a steady state. In particular, the output feedback speed is greater during the fall time than during the rise time of the output waveform. Therefore, in the output waveform of the amplification circuit 1300, the rise and fall times become steep, while rise and fall overshoot and undershoot are suppressed, and oscillation of the output waveform is also suppressed. As a result, the rise time t of the output waveform of the amplification circuit 1300 is shortened. r and fall time t f This shortens the circuit and allows for the creation of an amplification circuit capable of transmitting faster clock signals.

[0644] Furthermore, according to the embodiments described above, the fixed potential V3 is equal to the ground potential. Such a configuration increases the degree of freedom of the circuit.

[0645] Furthermore, according to the embodiment described above, the fixed potential V3 is equal to the fixed potential V1. With this configuration, the number of power supply terminals is reduced by one, thus improving the convenience of the circuit.

[0646] <Modifications of the embodiments described above> In the embodiments described above, the material, dimensions, shape, relative arrangement, or implementation conditions of each component may also be described, but these are all examples and not limiting.

[0647] Accordingly, countless variations and equivalents not shown are envisioned within the scope of the art disclosed herein. For example, these include modifying, adding or omitting at least one component, or even extracting at least one component from at least one embodiment and combining it with a component from another embodiment.

[0648] Furthermore, in the embodiments described above, if a material name or the like is mentioned without further specification, it is assumed that the material includes other additives, such as alloys, unless otherwise specified, as long as it does not create a contradiction.

[0649] Furthermore, unless contradictory, any component described as being provided as "one" in the embodiments described above may be provided as "one or more".

[0650] Furthermore, each component in the embodiments described above is a conceptual unit, and the scope of the technology disclosed in this specification includes cases where one component consists of multiple structures, where one component corresponds to a part of a structure, and where multiple components are provided in a single structure.

[0651] Furthermore, each component in the embodiments described above shall include structures having other structures or shapes, as long as they perform the same function.

[0652] Furthermore, the descriptions in this specification are referenced for all purposes related to the present technology and are not considered to be prior art. [Explanation of symbols]

[0653] 100, 150, 160, 200, 250, 260, 300, 500, 600, 700, 800, 900, 1000, 1100, 1200, 1300, 1400 Amplifier circuit, 101 Drive N-type FET, 102, 202 Load FET, 103, 203 Current source FET, 104 Feedback P-type FET, 105 Feedback N-type FET, 110, 210 Source follower circuit, 120, 220 SSF circuit, 161, 261 Switch, 162, 262 Differential amplifier, 201 Drive P-type FET, 504 Feedback PNP-type BJT, 605 Feedback NPN-type BJT, 701 Drive NPN-type BJT, 720, 820 FET input ID circuit, 801 Driver PNP type BJT, 910, 1010 emitter follower circuit, 920, 1020 ID circuit.

Claims

1. This is an amplification circuit that amplifies the signal input to the input terminal and outputs it to the output terminal. A first transistor, which is a field-effect transistor of a first conductivity type, has a first control terminal that is a gate terminal, a first current terminal that is a source terminal connected to a first potential, and a second current terminal that is a drain terminal connected to the output terminal. A second transistor is a field-effect transistor of a second conductivity type different from that of a first transistor, having a second control terminal which is a gate terminal connected to the input terminal, a third current terminal which is a source terminal, and a fourth current terminal which is a drain terminal connected to the first control terminal which is the gate terminal of the first transistor. A third transistor, which is a field-effect transistor of second conductivity type, has a third control terminal which is a gate terminal connected to a first fixed potential, a fifth current terminal which is a source terminal connected to a second potential, and a sixth current terminal which is a drain terminal connected to the third current terminal which is the source terminal of the second transistor. A fourth transistor, which is a field-effect transistor of the second conductivity type, has a fourth control terminal, which is a gate terminal connected at the same potential as the first control terminal, which is the gate terminal of the first transistor; a seventh current terminal, which is a source terminal connected to a third fixed potential; and an eighth current terminal, which is a drain terminal connected to the output terminal. A current source element that supplies current to the fourth current terminal, which is the drain terminal of the second transistor, The first differential input terminal is connected to the connection point between the third current terminal, which is the source terminal of the second transistor, and the sixth current terminal, which is the drain terminal of the third transistor, and the second differential input terminal is connected to the differential amplifier connected to the output terminal, The differential amplifier is equipped with a switch that can switch whether or not to connect the first differential input terminal and the second differential input terminal of the differential amplifier. Amplifier circuit.

2. An amplification circuit that amplifies a signal input to an input terminal and outputs it to an output terminal, A first transistor of a first conductivity type having a first control terminal, a first current terminal connected to a third fixed potential, and a second current terminal connected to the output terminal, A second transistor of a first conductivity type having a second control terminal connected to the input terminal, a third current terminal connected to the output terminal, and a fourth current terminal connected to the first control terminal of the first transistor, The third transistor is an N-type or P-type field-effect transistor having a third control terminal which is a gate terminal connected to a first fixed potential, a fifth current terminal which is a source terminal connected to a second potential, and a sixth current terminal which is a drain terminal connected to the output terminal. The first transistor is a field-effect transistor, The first control terminal of the first transistor is the gate terminal. The first current terminal of the first transistor is the source terminal, The second current terminal of the first transistor is the drain terminal. The second transistor described above is a field-effect transistor, The second control terminal of the second transistor is the gate terminal. The third current terminal of the second transistor is the source terminal. The fourth current terminal of the second transistor is the drain terminal. The amplification circuit further comprises a current source element that supplies current to the fourth current terminal of the second transistor. Amplifier circuit.

3. The amplification circuit is as described in claim 2, The current source element is an N-type or P-type field-effect transistor of a different conductivity type than the first, having a fourth control terminal which is a gate terminal connected to a second fixed potential, a seventh current terminal which is a source terminal connected to a first potential, and an eighth current terminal which is a drain terminal connected to the fourth current terminal of the second transistor. Amplifier circuit.

4. This is an amplification circuit that amplifies the signal input to the input terminal and outputs it to the output terminal. A first field-effect transistor of a first conductivity type having a first gate terminal, a first source terminal connected to a third fixed potential, and a first drain terminal connected to the output terminal, A second field-effect transistor of a first conductivity type, having a second gate terminal connected to the input terminal, a second source terminal connected to the output terminal, and a second drain terminal connected to the first gate terminal of the first field-effect transistor, A third field-effect transistor of type N or P, having a third gate terminal connected to a first fixed potential, a third source terminal connected to a second potential, and a third drain terminal connected to the output terminal, The system comprises a fourth field-effect transistor of N-type or P-type, which has a fourth gate terminal connected to the input terminal, a fourth source terminal connected to the first potential, and a fourth drain terminal connected to the second drain terminal of the second field-effect transistor, and which has a conductivity type different from that of the first field-effect transistor. Amplifier circuit.

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