Semiconductor devices and equipment

Abstract

In the present invention, a first element included in a semiconductor layer 11 differs from a second element included in a semiconductor layer 21, and a third element included in a source electrode 13 is the same as a fourth element included in a gate electrode 22.

Description

Technical Field

[0001] The present invention relates to a semiconductor device. Background Art

[0002] There is a technique in which constituent elements of semiconductor layers of transistors provided on the same substrate are made different from each other. Patent Document 1 discloses a semiconductor device using a TFT including polysilicon and a TFT including an oxide semiconductor layer. Patent Document 2 discloses a semiconductor device including a first top-gate thin film transistor having a polycrystalline silicon layer as a channel and a second top-gate thin film transistor having an oxide semiconductor layer as a channel. In the semiconductor device of Patent Document 2, it is disclosed that the source and drain of the first top-gate thin film transistor and the gate of the second top-gate thin film transistor are a common metal layer. Prior Art Documents Patent Documents

[0003] Patent Document 1 Japanese Unexamined Patent Application Publication No. 2020-202223 Patent Document 2 Japanese Unexamined Patent Application Publication No. 2018-50030 Summary of the Invention Problems to be Solved by the Invention

[0004] The technique of Patent Document 1 does not sufficiently study cost reduction. The technique of Patent Document 2 can only obtain effects with a limited structure. Therefore, an object of the present invention is to provide a technique that is advantageous for reducing the cost of a semiconductor device. Means for Solving the Problems

[0005] A first aspect of the semiconductor device according to the present invention is: a substrate; a first semiconductor layer of a first transistor provided on the substrate; A first conductive layer is provided on the substrate and overlaps the first semiconductor layer, A second semiconductor layer of the second transistor is provided on the aforementioned substrate, A second conductive layer is provided on the substrate and overlaps the second semiconductor layer, Equipped with, Among the elements of groups 12 to 16 contained in the first semiconductor layer, the first element having the highest concentration in the first semiconductor layer is different from the second element having the highest concentration in the second semiconductor layer among the elements of groups 12 to 16 contained in the second semiconductor layer. The third element, which has the highest concentration in the first conductive layer among the metallic or metalloid elements contained in the first conductive layer, is the same as the fourth element, which has the highest concentration in the second conductive layer among the metallic or metalloid elements contained in the second conductive layer. The first conductive layer is in contact with the first semiconductor layer. The second conductive layer is insulated from the second semiconductor layer. It is characterized by the following:

[0006] A second aspect of the semiconductor device according to the present invention is that the second conductive layer is provided between the second semiconductor layer and the substrate; a third aspect is that the third conductive layer, provided on the substrate and overlapping the second conductive layer, does not contact the second semiconductor layer and is insulated from the second conductive layer; and a fourth aspect is that the first transistor is P-type and the second transistor is N-type. [Effects of the Invention]

[0007] According to the present invention, it is possible to provide a technology that is advantageous in reducing the cost of semiconductor devices. [Brief explanation of the drawing]

[0008] [Figure 1A] A schematic diagram illustrating a semiconductor device. [Figure 1B] A schematic diagram illustrating a semiconductor device. [Figure 1C] A schematic diagram illustrating a semiconductor device. [Figure 1D] Schematic diagram illustrating a semiconductor device. [Figure 2A] Schematic diagram illustrating types of transistors. [Figure 2B] Schematic diagram illustrating types of transistors. [Figure 2C] Schematic diagram illustrating types of transistors. [Figure 2D] Schematic diagram illustrating types of transistors. [Figure 3A] Schematic diagram illustrating a semiconductor device. [Figure 3B] Schematic diagram illustrating a semiconductor device. [Figure 4A] Schematic diagram illustrating a semiconductor device. [Figure 4B] Schematic diagram illustrating a semiconductor device. [Figure 5A] Schematic diagram illustrating a semiconductor device. [Figure 5B] Schematic diagram illustrating a semiconductor device. [Figure 6A] Schematic diagram illustrating a semiconductor device. [Figure 6B] Schematic diagram illustrating a semiconductor device. [Figure 7A] Schematic diagram illustrating a method for manufacturing a semiconductor device. [Figure 7B] Schematic diagram illustrating a method for manufacturing a semiconductor device. [Figure 7C] Schematic diagram illustrating a method for manufacturing a semiconductor device. [Figure 7D] Schematic diagram illustrating a method for manufacturing a semiconductor device. [Figure 8] Schematic diagram illustrating a semiconductor device. [Figure 9A] Schematic diagram illustrating a semiconductor device. [Figure 9B] Schematic diagram illustrating a semiconductor device. [Figure 10A] Schematic diagram illustrating an apparatus. [Figure 10B] Schematic diagram illustrating an apparatus. MODE FOR CARRYING OUT THE INVENTION

[0009] Hereinafter, embodiments for carrying out the present invention will be described with reference to the drawings. In the following description and drawings, components common to multiple drawings are denoted by the same reference numeral. In some cases, common components will be described by referring to multiple drawings without further explanation. Also, the description of components denoted by the same reference numeral may be omitted. Different items with the same name can be distinguished by adding "the ○" or "the ○" (where ○ is a number), such as the first item (or item 1) and the second item (or item 2). In this specification, when A and B are either C or D, it means that A and B are either C, or A and B are either D, or A is C and B is D, or A is D and B is C.

[0010] Figure 1A is a schematic plan view of a semiconductor device AP. A semiconductor device AP suitable for this embodiment may include a pixel region 2 in which a plurality of pixel circuits PX are arranged, and a peripheral region 3 surrounding the pixel region 2. In Figure 1A, the pixel region 2 is the region enclosed by the dashed-dotted line, and the peripheral region 3 is the region sandwiched between the dashed-dotted line and the double-dotted line. A semiconductor device AP having a pixel region 2 can be used as a display device or an imaging device. This embodiment is also applicable to semiconductor device APs that do not have a pixel region 2 or a peripheral region 3, and may be, for example, an arithmetic unit, a memory device, or a communication device.

[0011] Figure 1B is a schematic cross-sectional view of a semiconductor device AP. The semiconductor device AP comprises a substrate 1, a transistor 10 provided on the substrate 1, and a transistor 20 provided on the substrate 1. Figures 2A to 2D are schematic cross-sectional views showing the configuration of transistor 10 or transistor 20. Transistor 10 includes a semiconductor layer 11 provided on the substrate 1, and transistor 20 includes a semiconductor layer 21 provided on the substrate 1. Each of the semiconductor layers 11 and 21 is composed of at least one element from groups 12 to 16. Note that semiconductor layers 11 and 21 may also contain elements other than those from groups 12 to 16 (e.g., hydrogen).

[0012] Transistor 10 may be provided in at least one of the pixel region 2 and the peripheral region 3. Transistor 20 may be provided in at least one of the pixel region 2 and the peripheral region 3. Here, an example is shown in which transistor 10 is provided in both the pixel region 2 and the peripheral region 3, and transistor 20 is provided in the pixel region 2. Also, transistor 30 is provided in the peripheral region 3 together with transistor 10. Transistor 10 in the peripheral region 3 and transistor 30 in the peripheral region 3 can both constitute a complementary integrated circuit such as a CMOS circuit. In a complementary integrated circuit, transistor 10 may be a P-type transistor and transistor 30 may be an N-type transistor. Alternatively, in a complementary integrated circuit, transistor 10 may be an N-type transistor and transistor 30 may be a P-type transistor. Transistor 10 may be an N-type transistor or a P-type transistor, but generally, it is preferable that transistor 10 be an N-type transistor because electron mobility is generally higher than hole mobility. Transistor 20 may be an N-type transistor or a P-type transistor, but since electron mobility is generally higher than hole mobility, it is preferable that transistor 20 be an N-type transistor.

[0013] In the pixel region 2, a functional element 200 may be provided on top of transistor 20 (and transistor 10). The functional element 200 is an element that can generally constitute a pixel, such as a liquid crystal element, a light-emitting element, or a photoelectric conversion element. The functional element 200 is connected to a transistor included in the pixel circuit PX, and the transistor to which the functional element 200 is connected is, for example, transistor 20 or transistor 10.

[0014] As shown in Figure 1B, an insulator 40 is provided on the substrate 1. This insulator 40 is a laminate of insulating films with various functions, including gate insulating films for transistors 10, 20, and 30, as well as interlayer insulating films, planarization films, diffusion prevention films, protective films, and sealing films around transistors 10, 20, and 30.

[0015] Figure 1C shows one pixel circuit PX when the semiconductor device AP is an imaging device. The pixel circuit PX includes a functional element 200 which is a photoelectric conversion element and an amplifying transistor 104 which amplifies the signal generated by the functional element 200. The functional element 200 which is a photoelectric conversion element includes a first electrode 201, a second electrode 209, a functional layer 205 disposed between the first electrode 201 and the second electrode 209, and an insulating layer 207 disposed between the functional layer 205 and the second electrode 209. The functional layer 205 is a photoelectric conversion layer made of an organic material, an inorganic material, or a hybrid material of an organic material and an inorganic material. The hybrid material may be a quantum dot material. The functional element 200 which is a photoelectric conversion element may include a blocking layer 203 disposed between the functional layer 205 and the first electrode 201. The blocking layer 203 is provided to prevent charges of the same conductivity type as the signal charges accumulated in the functional layer 205 from being injected from the first electrode 201 into the functional layer 205. The blocking layer 203 and the insulating layer 207 are optional. With this configuration, the photoelectric conversion unit can accumulate the charge generated by the incident light as signal charge. Furthermore, by controlling the voltage supplied to the pixel circuit PX, the signal from the photoelectric conversion element (functional element 200) can be read out.

[0016] Pixel PX includes a reset transistor 102, a capacitor 103, an amplification transistor 104, and a selection transistor 105. The drain of the reset transistor 102 is connected to a node supplied with a reset voltage Vres. A power supply voltage Vs is supplied to node A, which includes the first electrode 201 of the functional element 200. The source of the reset transistor 102 is connected to the second electrode 209 of the functional element 200 and the gate of the amplification transistor 104. With this configuration, the reset transistor 102 can reset the voltage at node B to the reset voltage Vres. In other words, the reset transistor 102 is the reset unit that supplies the reset voltage Vres to the second electrode 209. When the reset transistor 102 is turned off, node B, which includes the second electrode 209 of the functional element 200 (photoelectric conversion element), becomes electrically floating. Node C is capacitively coupled to node B via the capacitor 103. The first terminal of the capacitor 103 is connected to node B. The voltage Vd from the voltage supply unit 410 is supplied to node C, to which the second terminal of capacitor 103 is connected. Node B contains the gate of the amplification transistor 104. Amplification transistor 104 is the amplification unit, and the gate of amplification transistor 104 is the input node of the amplification unit. In other words, the second electrode 209 of the functional element 200 is electrically connected to the amplification unit. With this configuration, the amplification unit can amplify and output the signal generated by the functional element 200 (photoelectric conversion element). The drain of amplification transistor 104 is connected to the node to which the power supply voltage is supplied. The source of amplification transistor 104 is connected to the output line 130 via selection transistor 105. A current source 160 is connected to the output line 130. Amplification transistor 104 and the current source 160 form a source follower circuit and output a signal based on the charge generated by the functional element 200 to the output line 130. A column circuit 140 is further connected to the output line 130. The signal from the pixel circuit PX output to output line 130 is input to column circuit 140.

[0017] Figure 1D shows one pixel circuit PX when the semiconductor device AP is a display device. The pixel PX includes a functional element 200 which is an organic EL element, and the functional element 200 may include a first electrode 201, a second electrode 209, and a functional layer 205 disposed between the first electrode 201 and the second electrode 209. The functional layer 205 is an emissive layer made of an organic or inorganic material. The first electrode 201 is, for example, a cathode, and the second electrode 209 is, for example, an anode. The emissive color of the emissive layer of the functional element 200 which is an organic EL element may differ for each subpixel, being red, green, and blue, or each subpixel may be set to white and spectrally separated using a color filter.

[0018] The pixel circuit PX includes a select transistor 107, a drive transistor 106, and a capacitor 108. The power supply voltage Vd is supplied to the drive transistor 106 from the power line PL, and the power supply voltage Vs is supplied to the first electrode 201. The power supply voltage Vs may be lower than the power supply voltage Vd. The select transistor 107 outputs a data signal applied to the data line DL in response to a scan signal applied to the scan line GL. The capacitor 108 charges with a voltage corresponding to the data signal received via the select transistor 107. The source or drain of the select transistor 107 is connected to node D. The gate of the drive transistor 106 is also connected to node D. The drive transistor 106 is connected to node E. The drive transistor 106 is connected to the second electrode 209 of the functional element 200. One of the source and drain of the drive transistor 106 is connected to node E, and the other of the source and drain of the drive transistor 106 is connected to the second electrode 209. A voltage Vd is supplied to node E from the voltage supply unit. The first terminal of capacitor 108 is connected to node D. In this example, the second terminal of capacitor 108 is connected to node E, and node E is capacitively coupled to node D via capacitor 108. However, capacitor 108 may be connected to a node to which the second electrode 209 is connected, instead of node E. The drive transistor 106 controls the drive current flowing to the functional element 200 according to the amount of charge stored in the capacitor. As a result, the functional element 200, as a light-emitting element, emits light with a brightness corresponding to the data level of the data signal.

[0019] The pixel circuit PX described in Figures 1C and 1D is merely one example and is not limited thereto. The pixel PX can further include multiple transistors and thus contain a larger number of capacitors. Capacitors 103 and 108 may be of the MIS type, with a dielectric layer sandwiched between a conductive layer and a semiconductor layer; they may be of the MIM type, with a dielectric layer sandwiched between two conductive layers; or they may have a structure with a dielectric layer sandwiched between two semiconductor layers.

[0020] In the pixel circuit PX described above, for example, the selection transistor 105, reset transistor 102, and selection transistor 107 can be switch transistors. These switch transistors can be the transistor 20 described above. In the pixel circuit PX described above, for example, the amplification transistor 104 and the drive transistor 106 differ from switch transistors in that they output a potential correlated with the potential input to the gate, and these transistors can be the transistor 10 described above. Capacitors 103 and 108 have a common function in that they hold an amount of charge corresponding to the signal level of the pixel. It is preferable that the reset transistor 102 and the selection transistor 107 directly connected to capacitors 103 and 108 be transistors 10. It is also possible that the amplification transistor 104 and the drive transistor 106 directly connected to capacitors 103 and 108 be transistors 20.

[0021] Figures 2A to 2D are schematic cross-sectional diagrams showing the configuration of transistor 10 or transistor 20. Figures 2A to 2D show four different configurations of transistor 10 or transistor 20, but first, we will explain the common features of each configuration.

[0022] The transistor 10 includes a semiconductor layer 11, a gate electrode 12, a source electrode 13, a drain electrode 14, and a gate insulating film 15, all provided on a substrate 1. The gate electrode 12, source electrode 13, and drain electrode 14 overlap the semiconductor layer 11. The gate electrode 12 is insulated from the semiconductor layer 11 by the gate insulating film 15, while the source electrode 13 and drain electrode 14 are in contact with the semiconductor layer 11. In the transistor 10, the gate electrode 12 is provided on the channel of the semiconductor layer 11, and the gate insulating film 15 is provided between the semiconductor layer 11 and the gate electrode 12. In the transistor 10, the source electrode 13 is provided on the source of the semiconductor layer 11, and the drain electrode 14 is provided on the drain of the semiconductor layer 11.

[0023] The transistor 20 includes a semiconductor layer 21, a gate electrode 22, a source electrode 23, a drain electrode 24, and a gate insulating film 25, all provided on a substrate 1. The gate electrode 22, source electrode 23, and drain electrode 24 overlap the semiconductor layer 21. The gate electrode 22 is insulated from the semiconductor layer 21 by the gate insulating film 25, while the source electrode 23 and drain electrode 24 are in contact with the semiconductor layer 21. In the transistor 20, the gate electrode 22 is provided on the semiconductor layer 21, and the gate insulating film 25 is provided between the semiconductor layer 21 and the gate electrode 22. In the transistor 20, the source electrode 23 is provided on the source of the semiconductor layer 21, and the drain electrode 24 is provided on the drain of the semiconductor layer 21.

[0024] Among the elements of groups 12 to 16 contained in semiconductor layer 11, the element with the highest concentration in semiconductor layer 11 is designated as element S1. Among the elements of groups 12 to 16 contained in semiconductor layer 21, the element with the highest concentration in semiconductor layer 21 is designated as element S2. In this embodiment, element S1 is different from element S2.

[0025] The semiconductor layers 11 and 21 may be group IV semiconductors such as Si, Ge, fullerene, and carbon nanotubes, in which case elements S1 and S2 in the semiconductor layers 11 and 21 may be group 14 elements. The semiconductor layers 11 and 21 may be group II-VI compound semiconductors such as ZnSe, CdS, and ZnO, in which case elements S1 and S2 in the semiconductor layers 11 and 21 may be group 12 or group 16 elements. The semiconductor layers 11 and 21 may be oxide semiconductors such as InGaZnO and InSnZnO, in which case elements S1 and S2 in the semiconductor layers 11 and 21 may be oxygen (group 16 element) or elements from groups 12 to 14. The oxygen concentration in the oxide semiconductor is, for example, 50 at% or more, 70 at% or less, 67 at% or less, and 60 at%. The semiconductor layers 11 and 21 may be III-V compound semiconductors such as GaAs, InP, and GaN, in which case elements S1 and S2 in the semiconductor layers 11 and 21 may be group 13 or group 15 elements. The semiconductor layers 11 and 21 may be group IV compound semiconductors such as SiC and SiGe, in which case elements S1 and S2 in the semiconductor layers 11 and 21 may be group 14 elements. The semiconductor layers 11 and 21 may be organic semiconductors, in which case elements S1 and S2 in the semiconductor layers 11 and 21 may be carbon (group 14 element).

[0026] The semiconductor layers 11 and 21 are at least one of a single crystal layer, a polycrystalline layer, and an amorphous layer. The semiconductor layers 11 and 21 may also be a composite of multiple types of layers among the single crystal layer, polycrystalline layer, and amorphous layer. For increasing the area of ​​the semiconductor device AP, it is preferable that the semiconductor layers 11 and 21 are thin-film transistors (TFTs) using polycrystalline or amorphous layers.

[0027] Each of the gate electrodes 12, 22, source electrodes 13, 23, and drain electrodes 14, 24 consists of at least one conductive layer. When the gate electrodes 12, 22 have a multilayer structure consisting of multiple conductive layers, the bottom or top conductive layer of the gate electrodes 12, 22 contacts the gate insulating film 15, 25. When the source electrodes 13, 23 and drain electrodes 14, 24 have a multilayer structure consisting of multiple conductive layers, the bottom or top conductive layer of the source electrodes 13, 23 and drain electrodes 14, 24 contacts the semiconductor layers 11, 21. In the following description of the conductive layers of the gate electrodes 12, 22, source electrodes 13, 23, and drain electrodes 14, 24, the conductive layer in question may be the conductive layer closest to the semiconductor layers 11, 21.

[0028] On the substrate 1, a conductive member may be provided in addition to the gate electrode 12, overlapping the semiconductor layer 11 and insulated from the semiconductor layer 11. Furthermore, on the substrate 1, a conductive member 28 (described later) may be provided in addition to the gate electrode 22, overlapping the semiconductor layer 21 and insulated from the semiconductor layer 21. The conductive member 28 can be used as an auxiliary electrode for the transistor 20, wiring, a light-shielding member, a height difference adjustment member, etc. There may be other conductive layers between the conductive member 28 and the semiconductor layer 21, but there may be no other conductive layers between the conductive member 28 and the semiconductor layer 21.

[0029] Each conductive layer of the source electrode 13 and the drain electrode 14 is composed of at least one type of metallic or metalloid element. Among the metallic or metalloid elements contained in the conductive layers of the source electrode 13 and the drain electrode 14, the element with the highest concentration in the source electrode 13 and the drain electrode 14 is denoted as element M1.

[0030] The conductive layer of the gate electrode 22 is composed of at least one type of metallic element or metalloid element. Among the metallic elements or metalloid elements contained in the gate electrode 22, the element with the highest concentration in the gate electrode 22 is denoted as element M2.

[0031] The conductive layer of the gate electrode 12 is composed of at least one type of metallic element or metalloid element. Among the metallic elements or metalloid elements contained in the conductive layer of the gate electrode 12, the element with the highest concentration in the conductive layer of the gate electrode 12 is defined as element M3.

[0032] The conductive layers of the source electrode 23 and the drain electrode 24 are composed of at least one type of metallic or metalloid element. Among the metallic or metalloid elements contained in the conductive layers of the source electrode 23 and the drain electrode 24, the element with the highest concentration in the gate electrode 22 is designated as element M4.

[0033] The element M3, which is a metallic or metalloid element contained in the gate electrode 12, may be different from the element S2 contained in the semiconductor layer 21. Also, the element M4, which is a metallic or metalloid element contained in the gate electrode 22, may be different from the element S1 contained in the semiconductor layer 11.

[0034] The conductive layer of the conductive member 28 overlaps with the semiconductor layer 21 and is insulated from the semiconductor layer 21. The conductive layer of the conductive member 28 is composed of at least one metallic element or metalloid element other than the gate electrode 22. Among the metallic elements or metalloid elements contained in the conductive layer of the conductive member 28, the element with the highest concentration in the conductive member 28 is defined as element M5.

[0035] The element M1, which is a metallic or metalloid element contained in the source electrode 13 and the drain electrode 14, may be different from the element S2 contained in the semiconductor layer 21.

[0036] The element M2, which is a metallic or metalloid element contained in the gate electrode 22, may be different from the element S1 contained in the semiconductor layer 11.

[0037] The element M3, which is a metallic or metalloid element contained in the gate electrode 12, may be different from the element S2 contained in the semiconductor layer 21.

[0038] The element M4, which is a metallic or metalloid element contained in the gate electrode 22, may be different from the element S1 contained in the semiconductor layer 11.

[0039] The element M5, which is a metallic or metalloid element contained in the conductive member 28, may be different from the element S1 contained in the semiconductor layer 11.

[0040] Making the main constituent elements of one gate electrode of transistor 10 and transistor 20 different from the main constituent elements of the other semiconductor layer of transistor 10 and transistor 20 is advantageous in determining the electrode characteristics of transistors 10 and 20.

[0041] For example, elements M1 to M4 are elements from groups 3 to 13, and can also be elements from groups 3 to 9. Typically, elements M1 to M4 can be any of gold (Au), silver (Ag), copper (Cu), platinum (Pt), molybdenum (Mo), tungsten (W), tantalum (Ta), or titanium (Ti). In particular, it is preferable that they be any of copper (Cu), molybdenum (Mo), tungsten (W), or titanium (Ti).

[0042] In this embodiment, elements M1 and M2 may be the same. Having the same elements means that their atomic numbers are the same. Using the same elements for the source electrode 13, drain electrode 14, and gate electrode 22 can reduce design, procurement, and manufacturing costs.

[0043] In this embodiment, elements M1 and M5 may be the same. Having the same elements means that their atomic numbers are the same. Using the same elements for the source electrode 13, drain electrode 14, and conductive member 28 can reduce design, procurement, and manufacturing costs.

[0044] Although the insulator 40 on the substrate 1 shown in Figure 1B is omitted in Figures 2A to 2D, an insulating film such as a gate insulating film or an interlayer insulating film may be provided around the semiconductor layers 11 and 21 as at least a part of the insulator 40.

[0045] In the T-type transistor 10 shown in Figures 2A and 2D, the semiconductor layer 11 is provided between the substrate 1 and the gate electrode 12. In the T-type transistor 20, the semiconductor layer 21 is provided between the substrate 1 and the gate electrode 22.

[0046] In the C-type transistor 10 shown in Figures 1A and 1B, the gate electrode 12, source electrode 13, and drain electrode 14 of the transistor 10 are located on either the side of the semiconductor layer 11 facing the substrate 1 or the side opposite to the substrate 1. In the example in Figure 2A, the gate electrode 12, source electrode 13, and drain electrode 14 are located on the side of the semiconductor layer 11 facing the substrate 1. In the example in Figure 2B, the gate electrode 12, source electrode 13, and drain electrode 14 are located on the side of the semiconductor layer 11 facing the substrate 1. In the C-type transistor 10, the gate electrode 12 may be located between the source electrode 13 and the drain electrode 14.

[0047] In the C-type transistor 20 shown in Figures 1A and 1B, the gate electrode 22, source electrode 23, and drain electrode 24 of the transistor 20 are located on either the side of the substrate 1 relative to the semiconductor layer 21 or the side opposite to the substrate 1. In the example in Figure 2A, the gate electrode 22, source electrode 23, and drain electrode 24 are located on the side of the substrate 1 relative to the semiconductor layer 11. In the example in Figure 2B, the gate electrode 22, source electrode 23, and drain electrode 24 are located on the side of the substrate 1 relative to the semiconductor layer 21. In the C-type transistor 20, the gate electrode 22 may be located between the source electrode 23 and the drain electrode 24.

[0048] In the B-type transistor 10 shown in Figures 2B and 2C, the gate electrode 12 is provided between the substrate 1 and the semiconductor layer 11. In the B-type transistor 20, the gate electrode 22 is provided between the substrate 1 and the semiconductor layer 21.

[0049] In the S-type transistor 10 shown in Figures 2C and 2D, the semiconductor layer 11 is provided between the gate electrode 12 and the source electrode 13. In the S-type transistor 10, the semiconductor layer 11 is also provided between the gate electrode 12 and the drain electrode 14. In the S-type transistor 20, the semiconductor layer 21 is provided between the gate electrode 22 and the source electrode 23. In the S-type transistor 20, the semiconductor layer 21 is also provided between the gate electrode 22 and the drain electrode 24.

[0050] In the second embodiment, both transistor 10 and transistor 20, which are mounted on the same substrate 1, are T-type. In this case, it is preferable that both transistor 10 and transistor 20 are C-type, and it is also preferable that both transistor 10 and transistor 20 are S-type. However, transistor 10 may be either C-type or S-type, and transistor 20 may be the other of C-type or S-type.

[0051] In the third embodiment, both transistor 10 and transistor 20, which are mounted on the same substrate 1, are type B transistors. In this case, it is preferable that both transistor 10 and transistor 20 are type C, and it is also preferable that both transistor 10 and transistor 20 are type S. However, transistor 10 may be either type C or type S, and transistor 20 may be the other type C or type S.

[0052] In the fourth embodiment, both transistor 10 and transistor 20, which are mounted on the same substrate 1, are C-type transistors. In this case, it is preferable that both transistor 10 and transistor 20 are T-type, and it is also preferable that both transistor 10 and transistor 20 are B-type. However, transistor 10 may be either T-type or B-type, and transistor 20 may be the other of T-type or B-type.

[0053] In the fifth embodiment, both transistor 10 and transistor 20, which are mounted on the same substrate 1, are S-type transistors. In this case, it is preferable that both transistor 10 and transistor 20 are T-type, and it is also preferable that both transistor 10 and transistor 20 are B-type. However, transistor 10 may be either T-type or B-type, and transistor 20 may be the other of T-type or B-type.

[0054] As in the second to fifth embodiments, by making both transistors 10 and 20, which are provided on the same substrate 1, the configuration of the semiconductor device AP can be simplified, and the cost required for the design and manufacture of the semiconductor device AP can be reduced.

[0055] In the sixth embodiment, the element M2 contained in the gate electrode 22 is the same as the element M4 contained in the source electrode 23 and the drain electrode 24. Using the same element for the three electrodes of the transistor 20 can reduce costs.

[0056] In the seventh embodiment, the element M3 contained in the gate electrode 12 is the same as the element M1 contained in the source electrode 13 and the drain electrode 14. Using the same element for the three electrodes of the transistor 10 can reduce costs.

[0057] In the eighth embodiment, the gate electrode 22 has a conductive layer containing the same element M4 as the element M1 contained in the source electrode 13 and the drain electrode 14. The conductive layer of the gate electrode 22 may be continuous with the conductive layer of the source electrode 13 or the drain electrode 14. The conductive layer of the gate electrode 22 containing element M4 may be discontinuous with the conductive layer of the source electrode 13 or the drain electrode 14 containing element M1.

[0058] In the ninth embodiment, the conductive member 28 has a conductive layer containing the same element M5 as the element M1 contained in the source electrode 13 and the drain electrode 14. A semiconductor layer 21 is provided between the gate electrode 22 and the conductive member 28 (conductive layer containing element M5). In the ninth embodiment, the conductive layer containing the same element M5 as the element M1 is the conductive member 28. The conductive layer of the conductive member 28 containing element M5 may be continuous with the conductive layer of the source electrode 13 or the drain electrode 14 containing element M1. The conductive layer of the conductive member 28 may be discontinuous with the conductive layer of the source electrode 13 or the drain electrode 14 containing element M1.

[0059] The potential of the conductive member 28 (conductive layer containing element M5) may be the same as the potential of any of the gate electrode 12, source electrode 13, drain electrode 14, gate electrode 22, source electrode 23, and drain electrode 24. In particular, the potential of the conductive member 28 (conductive layer containing element M5) may be the same as the potential of the gate electrode 22. For this purpose, the gate electrode 22 and the conductive member 28 may be electrically connected to each other. The conductive layer containing element M2 of the gate electrode 22 and the conductive layer containing element M5 of the conductive member 28 may be in contact, or they may be electrically connected via another conductive layer (e.g., via). The electric field applied to the semiconductor layer 21 can be controlled by the gate electrode 22 and the conductive member 28 located on both sides of the semiconductor layer 21. The potential of the conductive member 28 (conductive layer containing element M5) may be different from the potential of any of the gate electrode 12, source electrode 13, drain electrode 14, gate electrode 22, source electrode 23, and drain electrode 24, or it may be a floating potential.

[0060] The element M3, which is a metallic or metalloid element contained in the gate electrode 12, may be different from the element M2, which is a metallic or metalloid element contained in the gate electrode 22. Differentiating the main metallic or metalloid elements contained in the gate electrodes 12 and 22 is advantageous in determining the characteristics of transistors 10 and 20.

[0061] Among the elements of groups 12-16 contained in semiconductor layer 11, element S3 is defined as the element whose concentration in semiconductor layer 11 is second only to element S1. If semiconductor layer 11 is a binary compound semiconductor, then semiconductor layer 11 is a compound of elements S1 and S3. Similarly, among the elements of groups 12-16 contained in semiconductor layer 21, element S4 is defined as the element whose concentration in semiconductor layer 21 is second only to element S2. If semiconductor layer 21 is a binary compound semiconductor, then semiconductor layer 21 is a compound of elements S2 and S4. Element S3 in semiconductor layer 21 may be different from element S4 in semiconductor layer 21.

[0062] In oxide semiconductors such as InGaZnO and InSnZnO, if elements S1 and S2 are oxygen (O), then elements S3 and S4 may be zinc (Zn). In oxide semiconductors such as InGaZnO and InSnZnO, the concentration of zinc may be 10-30 at%, 10-20 at%, for example, 16 at%. In oxide semiconductors such as InGaZnO and InSnZnO, if elements S1 and S2 are oxygen (O), then elements S3 and S4 may be indium (In). The concentration of indium may be 5-20 at%, for example, 14 at%. In oxide semiconductors such as InGaZnO and InSnZnO, the concentrations of gallium (Ga) and tin (Sn) may be lower than the concentration of zinc (Zn). In oxide semiconductors such as InGaZnO and InSnZnO, the concentrations of gallium (Ga) and tin (Sn) may be lower than the concentration of indium (In). In oxide semiconductors such as InGaZnO and InSnZnO, the concentrations of gallium (Ga) and tin (Sn) can range from 5 to 20 at%, for example, 10 at%. In InGaZnO, for example, In:Ga:Zn:O = 16:10:14:60.

[0063] In the tenth embodiment, a conductive layer containing the same element (e.g., element M2 or element M5) as element M1 in the conductive layer of the source electrode 13 or drain electrode 14 may be the same layer as the conductive layer of the source electrode 13 or drain electrode 14. "Same layer" means a layer formed from a single film. Even if they are the same layer, the heights of the two layers from the substrate 1 may differ due to differences in the height of the substrate during film formation. Furthermore, if they are the same layer, the two layers may have approximately the same thickness. Here, "approximately the same thickness" means that the thickness of one layer is 90-110% of the thickness of the other layer.

[0064] Table 1 will be used to explain the combinations of transistor types 10 and 20.

[0065] [Table 1]

[0066] Table 1 lists 32 possible combinations of transistor types 10 and 20. In Table 1, if transistors 10 and 20 are T-type, "T" is written in the TB column; if transistors 10 and 20 are B-type, "B" is written in the TB column. If transistors 10 and 20 are C-type, "C" is written in the CS column; if transistors 10 and 20 are S-type, "S" is written in the CS column. In Table 1, if the gate electrode 22 contains the same element as element M1 contained in the source electrode 13 and drain electrode 14, "G" is written in the M column. Also, if the conductive member 28 other than the gate electrode 22 contains the same element as element M1 contained in the source electrode 13 and drain electrode 14, "N" is written in the M column.

[0067] Nos. 01-04 and Nos. 09-12 correspond to the second embodiment. Nos. 21-24 and Nos. 29-32 correspond to the third embodiment. Nos. 01, 02, 05, 06 and Nos. 17, 18, 21, 22 correspond to the fourth embodiment. Nos. 11, 12, 15, 16 and Nos. 27, 28, 31, 32 correspond to the fifth embodiment. Examples of odd numbers with "G" in column M correspond to the eighth embodiment. Examples of odd numbers with "N" in column M correspond to the ninth embodiment.

[0068] Figure 3A illustrates a cross-sectional view of a semiconductor device AP having the configuration of No. 01 in Table 1, using dashed lines. In Figure 3A, the dashed lines indicate that the components connected by the dashed lines are on the same layer, that is, the source electrode 13 (and drain electrode 14) are on the same layer as the gate electrode 22.

[0069] Figure 3B illustrates a cross-sectional view of a semiconductor device AP having the configuration of No. 31 in Table 1, using dashed lines. In Figure 3B, the dashed lines indicate that the components connected by the dashed lines are on the same layer, that is, the source electrode 13 (and drain electrode 14) are on the same layer as the gate electrode 22.

[0070] Figure 4A illustrates a cross-sectional view of a semiconductor device AP having the configuration of No. 02 in Table 1, using dashed lines. In Figure 4A, the dashed lines indicate that the members connected by the dashed lines are in the same layer, that is, the source electrode 13 (and drain electrode 14) are in the same layer as the conductive member 28.

[0071] Figure 4A illustrates a cross-sectional view of a semiconductor device AP having the configuration of No. 01 in Table 1, using dashed lines. In Figure 4A, the dashed lines indicate that the components connected by the dashed lines are on the same layer, that is, the source electrode 13 (and drain electrode 14) are on the same layer as the gate electrode 22.

[0072] Figure 4B illustrates a cross-sectional view of a semiconductor device AP having the configuration of No. 32 in Table 1, using dashed lines. In Figure 4B, the dashed lines indicate that the members connected by the dashed lines are on the same layer, that is, the source electrode 13 (and drain electrode 14) are on the same layer as the conductive member 28.

[0073] Figure 4B illustrates a cross-sectional view of a semiconductor device AP having the configuration of No. 31 in Table 1, using dashed lines. In Figure 4B, the dashed lines indicate that the components connected by the dashed lines are in the same layer, that is, the source electrode 13 (and drain electrode 14) are in the same layer as the gate electrode 22.

[0074] Figure 5A illustrates a cross-sectional view of a semiconductor device AP having the configuration of No. 08 in Table 1, using dashed lines. In Figure 5A, the dashed lines indicate that the members connected by the dashed lines are on the same layer, that is, the source electrode 13 (and drain electrode 14) are on the same layer as the conductive member 28.

[0075] Figure 5A illustrates a cross-sectional view of a semiconductor device AP having the configuration of No. 07 in Table 1, using dashed lines. In Figure 5A, the dashed lines indicate that the components connected by the dashed lines are on the same layer, that is, the source electrode 13 (and drain electrode 14) are on the same layer as the gate electrode 22.

[0076] Figure 5B illustrates a cross-sectional view of a semiconductor device AP having the configuration of No. 27 in Table 1, using dashed lines as an example. In Figure 5B, the dashed lines indicate that the source electrode 13 (and drain electrode 14) are on the same layer as the gate electrode 22.

[0077] FIG. 6A exemplarily shows a cross-sectional view of the T / C transistor illustrated in FIG. 2A. FIG. 6A shows the magnitude relationship between the thicknesses of respective layers and distances. For example, in the transistor 20, the gate electrode 22, the source electrode 23, and the drain electrode 24 have a thickness T1. The semiconductor layer 21 has a thickness T2 smaller than the thickness T1 (T1>T2). The gate insulating film 25 has a thickness T3 smaller than the thickness T1 (T1>T3). As shown in FIG. 6A, the thickness T3 may be smaller than the thickness T2 (T3<T2), or may be larger than the thickness T2 (T2<T3). The distance between the conductive member 28 and the semiconductor layer 21 is larger than the distance between the gate electrode 22 and the semiconductor layer 21 (the thickness of the gate insulating film 25). An interlayer insulating film 26 is disposed between the conductive member 28 and the semiconductor layer 21. An interlayer insulating film 27 is disposed between the semiconductor layer 21 and the source electrode 23. The interlayer insulating film 27 is in the same layer as the gate insulating film 25. An interlayer insulating film 29 is provided to cover the transistor 20. The gate insulating film 25 has a portion extending outward from between the gate electrode 22 and the semiconductor layer 21 (a portion not overlapping the gate electrode 22), and the interlayer insulating film 29 is provided with a convex portion reflecting this extended portion (the portion not overlapping the gate electrode 22).

[0078] Such a structure of transistor 20 shown in Figure 6A can also be applied to transistor 10. For example, in transistor 10, the interlayer insulating film 16 is placed below the semiconductor layer 11, the interlayer insulating film 17 is placed above the semiconductor layer 11, and the semiconductor layer 11 is placed between the interlayer insulating film 16 and the interlayer insulating layer 17. The interlayer insulating film 19 is provided covering transistor 10. The conductive member 28 does not need to extend between the semiconductor layer 11 and the substrate 1. Any of the interlayer insulating films 16, 17, and 19 overlapping transistor 10 and any of the interlayer insulating films 26, 27, and 29 overlapping transistor 20 may be in the same layer. For example, the interlayer insulating film 19 and the interlayer insulating film 26 may be in the same layer. The interlayer insulating film 17 may be in the same layer as the gate insulating film 15. The conductive member 28 is provided between the semiconductor layer 21 and the substrate 1, and the interlayer insulating film provided between this conductive member 28 and the substrate 1 may be in the same layer as at least one of the interlayer insulating film 17 and the gate insulating film 15.

[0079] Figure 6B illustrates a cross-sectional view of the B / S type transistor shown in Figure 2A. Figure 6B shows the relative thicknesses and distances of each layer. This example differs from Figure 6B in that the gate insulating film 25 has a thickness T4 (T4 > T2) greater than the thickness T2. In addition, in transistor 10, the interlayer insulating film 16 is located below the semiconductor layer 11, the interlayer insulating film 17 is located above the semiconductor layer 11, and the semiconductor layer 11 is located between the interlayer insulating film 16 and the interlayer insulating layer 17.

[0080] The manufacturing method of the semiconductor device AP will be explained using Figures 7A to 7D.

[0081] Figure 7A shows a first example of the manufacturing method. In the first example, a semiconductor layer 11 is formed on a substrate 1 in step S11. In step S12, a conductive film 18 is deposited on the substrate 1 to cover the semiconductor layer 11. At this time, the conductive film 18 is in contact with the semiconductor layer 11. In step S13, the conductive film 18 is patterned. Patterning can be done by wet etching or dry etching, but wet etching is preferred to suppress damage to the semiconductor layer 11. A source electrode 13 and a drain electrode 14 are formed from the conductive film 18 by patterning. A gate electrode 22 or conductive member 28 is also formed from the conductive film 18 by patterning. In step S14, a semiconductor layer 21 is formed on the gate electrode 22 or conductive member 28, insulated from the gate electrode 22 or conductive member 28. In this way, the gate electrode 22 or conductive member 28 is formed in the same layer as the source electrode 13 and the drain electrode 14.

[0082] Figure 7B shows a second example of the manufacturing method. In the second example, in step S21, a conductive film 18 is deposited on the substrate 1. In step S22, the conductive film 18 is patterned. Patterning can be done by wet etching or dry etching. The source electrode 13 and drain electrode 14 are formed from the conductive film 18 by patterning. Also, the gate electrode 22 or conductive member 28 is formed from the conductive film 18 by patterning. In step S23, a semiconductor layer 11 is formed to cover the source electrode 13 and drain electrode 14. At this time, the semiconductor layer 11 is in contact with the source electrode 13 and drain electrode 14. In step S14, a semiconductor layer 21 is formed on the gate electrode 22 or conductive member 28, insulated from the gate electrode 22 or conductive member 28. In this way, the gate electrode 22 or conductive member 28 is formed in the same layer as the source electrode 13 and drain electrode 14.

[0083] Figure 7C shows a third example of the manufacturing method. In the second example, a semiconductor layer 11 is formed on the substrate 1 in step S31. A semiconductor layer 21 is formed on the substrate 1 in step S32. A conductive film 18 is formed on the substrate 1 to cover the semiconductor layers 11 and 21. At this time, the conductive film 18 is in contact with the semiconductor layer 11, and an insulating film is provided between a part of the conductive film 18 and the semiconductor layer 21. In step S34, the conductive film 18 is patterned. Patterning can be done by wet etching or dry etching, but wet etching is preferred to suppress damage to the semiconductor layers 11 and 21. A source electrode 13 and a drain electrode 14 are formed from the conductive film 18 by patterning. A gate electrode 22 or a conductive member 28 is also formed from the conductive film 18 by patterning. The gate electrode 22 or conductive member 28 is insulated from the semiconductor layer 21 by the insulating film provided in step S34. In this way, the gate electrode 22 or the conductive member 28 is formed in the same layer as the source electrode 13 and the drain electrode 14.

[0084] Figure 7D shows a fourth example of the manufacturing method. In the second example, a semiconductor layer 21 is formed on the substrate 1 in step S41. A semiconductor layer 11 is formed on the substrate 1 in step S42. A conductive film 18 is formed on the substrate 1 to cover the semiconductor layers 11 and 21. At this time, the conductive film 18 is in contact with the semiconductor layer 11, and an insulating film is provided between a part of the conductive film 18 and the semiconductor layer 21. In step S44, the conductive film 18 is patterned. Patterning can be done by wet etching or dry etching, but wet etching is preferred to suppress damage to the semiconductor layers 11 and 21. A source electrode 13 and a drain electrode 14 are formed from the conductive film 18 by patterning. A gate electrode 22 or a conductive member 28 is also formed from the conductive film 18 by patterning. The gate electrode 22 or conductive member 28 is insulated from the semiconductor layer 21 by the insulating film provided in step S44. In this way, the gate electrode 22 or the conductive member 28 is formed in the same layer as the source electrode 13 and the drain electrode 14.

[0085] In the first example in Figure 7A and the second example in Figure 7B, the conductive film 18 is deposited before the formation of the semiconductor layer 21. Compared to the third example in Figure 7C and the fourth example in Figure 7D, where the conductive film 18 is deposited after the formation of the semiconductor layer 21, the step height in the conductive film 18 can be reduced. Therefore, in the first example in Figure 7A and the second example in Figure 7B, the patterning of the conductive film 18 can be improved compared to the third example in Figure 7C and the fourth example in Figure 7D.

[0086] In Figures 7A to 7D, the semiconductor layer 11 can be formed by CVD, the semiconductor layer 21 by PVD, the conductive film 18 by PVD, and the insulating film by CVD.

[0087] In the 11th embodiment, the distance D1 between the semiconductor layer 11 and the substrate 1 may be different from the distance D2 between the semiconductor layer 21 and the substrate 1. By making the distances D1 and D2 different for transistors 10 and 20, the characteristics of transistors 10 and 20 can be made more appropriate compared to the case where the distances D1 and D2 are equal. There are influences from the substrate 1 on the semiconductor layers 11 and 21, and influences from components located on the opposite side of the semiconductor layers 11 and 21 from the substrate 1. By making the distances D1 and D2 different for transistors 10 and 20, the characteristics of transistors 10 and 20 can be made more appropriate.

[0088] In the twelfth embodiment, the distance D3 between the substrate 1 and the gate electrode 12 may be different from the distance D4 between the substrate 1 and the gate electrode 22. That is, the influence from the substrate 1 on the gate electrodes 12 and 22, and the influence from components on the opposite side of the gate electrodes 12 and 22 from the substrate 1, can be made more appropriate in the characteristics of the transistors 10 and 20.

[0089] The distance D3 between the substrate 1 and the gate electrode 12 may be different from the distance D2 between the substrate 1 and the semiconductor layer 21. Also, the distance D4 between the substrate 1 and the gate electrode 22 may be different from the distance D1 between the substrate 1 and the semiconductor layer 11.

[0090] In the 13th embodiment, the distance D5 between the semiconductor layer 11 and the gate electrode 12 may be different from the distance D6 between the semiconductor layer 21 and the gate electrode 22. The distance D5 between the semiconductor layer 11 and the gate electrode 12 corresponds to the thickness of the gate insulating film 15, and the distance D6 between the semiconductor layer 21 and the gate electrode 22 corresponds to the thickness of the gate insulating film 25. By making the distances D5 and D6 different in transistors 10 and 20, the characteristics of transistors 10 and 20 can be made more appropriate compared to the case where the distances D5 and D6 are equal.

[0091] As in the 11th to 13th embodiments, when the positional relationship between the substrate 1, the semiconductor layers 11 and 21, and the gate electrodes 12 and 22 differs for transistors 10 and 20, a step is likely to occur between transistor 10 and transistor 20. If the conductive layer of the same layer is continuous between transistor 10 and transistor 20, an unexpected break in the conductive layer may occur due to the step between transistor 10 and transistor 20. Therefore, it is preferable that the conductive layer of the same layer is discontinuous between transistor 10 and transistor 20. To electrically connect the discontinuous conductive layer of the same layer, it is sufficient to connect it with another conductive layer. For example, when the source electrode 13 (and drain electrode 14) and the gate electrode 22 are in the same layer, discontinuous, and electrically connected, they can be connected with a conductive layer included in at least one of the gate electrode 12 and source electrode 23 (drain electrode 24).

[0092] In the 14th embodiment, element S1 in semiconductor layer 11 is a group 14 element, and element S2 in semiconductor layer 21 may be a group 12, 13, 15, or 16 element. For example, element S1 in semiconductor layer 11 may be silicon (Si), and element S2 in semiconductor layer 21 may be oxygen (O). Semiconductor layer 11 may be a polycrystalline or amorphous layer, and semiconductor layer 21 may be an oxide semiconductor layer. Semiconductor layer 11 may be a polycrystalline silicon layer. In semiconductor layer 21, element S4 may be indium (In). By making element S4 indium (In), the mobility of semiconductor layer 21 can be increased. Semiconductor layer 21 may contain gallium (Ga). Semiconductor layer 21 may contain tin (Sn). By containing tin (Sn) in semiconductor layer 21, the mobility of semiconductor layer 21 can be increased.

[0093] Substrate 1 may be an insulating substrate such as glass or resin, but it may also be a semiconductor substrate such as silicon, or a conductive substrate such as metal. If substrate 1 is a resin substrate, a substrate is prepared by forming a resin film such as polyimide on a base material such as glass, and transistors 10 and 20 are formed on the resin film of the substrate. Then, the base material and the resin film are separated using a laser or the like, and this resin film can be used as substrate 1 (resin substrate). The resin substrate may also be a flexible substrate. If substrate 1 is a semiconductor substrate, at least one of the semiconductor layers 11 and 21 may be a single-crystal semiconductor layer epitaxially grown on a single-crystal semiconductor substrate 1 in accordance with the crystal structure of the substrate 1. Alternatively, if substrate 1 is a semiconductor substrate, at least one of the semiconductor layers 11 and 21 may have a structure (SOI (Semiconductor On Insulator) structure) formed on a single-crystal semiconductor substrate 1 via an insulating layer. If substrate 1 is a conductive substrate, an insulating layer may be provided between the semiconductor layers 11 and 21 and the substrate 1. Transistor 10 may be a P-type transistor or an N-type transistor. Preferably, transistor 10 forms a CMOS circuit with transistor 30, and preferably transistor 10 is a P-type transistor and transistor 30 is an N-type transistor. Alternatively, transistor 10 may be an N-type transistor and transistor 30 may be a P-type transistor. Among the elements of groups 12 to 16 contained in the semiconductor layer 31 of transistor 30, the element with the highest concentration in the semiconductor layer 31 is defined as element S5. Element S5 may be the same as element S1 contained in the semiconductor layer 11. Among the elements of groups 12 to 16 contained in the semiconductor layer 31 of transistor 30, the element with the second highest concentration in the semiconductor layer 31 after element S5 is defined as element S6. Element S6 may be different from element S3 contained in the semiconductor layer 11. For example, elements S1 and S5 may be silicon (Si), element S3 may be boron (B), and element S6 may be phosphorus (P).

[0094] If transistor 10 is an N-type transistor and transistor 30 is a P-type transistor, then element S3 may be phosphorus (P) and element S6 may be boron (B). If the semiconductor layer 11 of transistor 10 and the semiconductor layer 31 of transistor 30 are polycrystalline semiconductor layers, they are suitable for speeding up switching due to their high carrier mobility. If the semiconductor layer 11 of transistor 10 and the semiconductor layer 31 of transistor 30 are polycrystalline semiconductor layers, the gate voltage can be lowered due to their high carrier mobility compared to amorphous semiconductors, which is suitable for reducing the power consumption of the transistors.

[0095] Transistor 20 may be a P-type transistor or an N-type transistor. Generally, it is preferable that transistor 20 be an N-type transistor because electron mobility is higher than hole mobility. It is also preferable that transistor 20 be a switch transistor. If transistor 20 is an N-type switch transistor, high-speed switching is possible. If the semiconductor layer 21 of transistor 20 is an oxide semiconductor, the leakage current can be reduced due to the wide band gap, which is suitable for reducing the leakage current of the switching transistor.

[0096] The substrate 1 can be of various sizes, but its diagonal length is preferably 1 cm or more, and preferably 2.5 cm or more. If the diagonal length is less than 2.5 cm, the semiconductor layer 11 of the transistor 10 may be a single crystal layer. For example, a transistor 10 may be formed on a substrate 1 made of single crystal silicon, and a thin-film transistor 20 may be formed on that substrate 1. The diagonal length of the substrate 1 may be 5 cm or more. If the diagonal length of the substrate 1 is 5 cm or more, the transistor 10 is preferably a thin-film transistor, and the semiconductor layer 11 may be a polycrystalline layer or an amorphous layer. If the semiconductor layer 11 is a polycrystalline layer or an amorphous layer, sufficient uniformity of the characteristics of the transistor 10 can be ensured even if the diagonal length of the substrate 1 is 5 cm or more. If the diagonal length of the substrate 1 is less than 75 cm, the semiconductor layer 11 of the transistor 10 is preferably a polycrystalline layer. If the semiconductor layer 11 of the transistor 10 is a polycrystalline layer, the diagonal length of the substrate 1 may be 20 cm or more, 25 cm or more, or 30 cm or more. When the diagonal length of the substrate 1 is 20 cm or more, it is preferable to place the transistor 10, which has a polycrystalline layer for its semiconductor layer 11, in the pixel circuit PX. By using a polycrystalline layer with high charge mobility for the amplification transistor 104 and the driving transistor 106 of the pixel circuit PX, power consumption in the power line PL connected to the pixel circuit PX can be suppressed even on a substrate 1 with a large diagonal length. When the transistor 10 is placed in the pixel circuit PX, it is preferable that the diagonal length of the substrate 1 be less than 50 cm from the viewpoint of improving image quality. If the diagonal length of the substrate 1 is less than 50 cm, sufficient uniformity of the characteristics of the transistor 10 can be ensured. When the diagonal length of the substrate 1 is 75 cm or more, it is preferable that the semiconductor layer 11 of the transistor 10 is an amorphous layer. In any case of the diagonal length of the substrate 1, it is preferable that the semiconductor layer 21 of the transistor 20 is an oxide semiconductor layer.

[0097] Here, the diagonal length of substrate 1 has been described, but the same applies to the diagonal length of pixel area 2, and the diagonal length of substrate 1 may be read as the diagonal length of pixel area 2. For example, the diagonal length of pixel area 2 is preferably 1 cm or more, preferably 2.5 cm or more, preferably 5 cm or more, may be 20 cm or more, 25 cm or more, 30 cm or more, or less than 75 cm.

[0098] The 15th embodiment is a combination of the 11th and 14th embodiments, and it is preferable that the distance D1 between the semiconductor layer 11 and the substrate 1 is smaller than the distance D2 between the semiconductor layer 21 and the substrate 1. When the semiconductor layer 11 is a polycrystalline layer, controlling its crystallinity is important. By placing the semiconductor layer 11 closer to the substrate 1 than the semiconductor layer 21, the flatness of the semiconductor layer 11 can be improved, and the uniformity of its crystallinity can be improved. Furthermore, by forming the semiconductor layer 11 before the semiconductor layer 21, the influence of the heat treatment used to form the semiconductor layer 11 on the semiconductor layer 21 can be suppressed. In other words, appropriate heat treatment can be performed on the semiconductor layer 11 before the semiconductor layer 21 is formed. Therefore, it becomes easier to control the crystallinity of the semiconductor layer 11.

[0099] The 16th embodiment is a combination of the 12th and 14th embodiments, and it is preferable that the distance D3 between the substrate 1 and the gate electrode 12 is smaller than the distance D4 between the substrate 1 and the gate electrode 22.

[0100] The 17th embodiment is a combination of the 12th and 15th embodiments, and it is preferable that the distance D5 between the semiconductor layer 11 and the gate electrode 12 is smaller than the distance D6 between the semiconductor layer 21 and the gate electrode 22. The distance D5 between the semiconductor layer 11 and the gate electrode 12 corresponds to the thickness of the gate insulating film 15, and the distance D6 between the semiconductor layer 21 and the gate electrode 22 corresponds to the thickness of the gate insulating film 25. For example, the distance D5 may be 200 to 400 nm and the distance D6 may be 50 to 200 nm. By making the gate insulating film 15 thinner, the response characteristics of the transistor 10 can be improved and excellent driving force can be achieved. Also, by making the gate insulating film 25 thicker, the leakage current of the transistor 20 can be further reduced.

[0101] The 18th embodiment relates to a capacitance C provided on a substrate 1. Capacitor C can be applied to, for example, the capacitances 103 and 108 shown in Figures 1C and 1D, but is not limited to capacitances within the pixel circuit PX, and can also be applied to integrated circuits in the peripheral region 3. As shown in Figure 8, at least one of a lower gate electrode 221 and an upper gate electrode 222 is provided on the substrate 1 as a gate electrode 22 that overlaps the semiconductor layer 21. Both the lower gate electrode 221 and the upper gate electrode 222 are shown in Figure 8 for convenience, but one of them may be omitted.

[0102] The lower gate electrode 221 is located on the substrate 1 side relative to the semiconductor layer 21, and the lower gate electrode 221 is positioned between the semiconductor layer 21 and the substrate 1. The lower gate electrode 221 corresponds to the gate electrode 22 in the type B transistor 20 shown in Figures 2B, 2C, 3B, 4B, 5B, and 6B.

[0103] The upper gate electrode 222 is located on the side of the semiconductor layer 21 opposite to the substrate 1, with the semiconductor layer 21 situated between the upper gate electrode 222 and the substrate 1. The upper gate electrode 222 corresponds to the gate electrode 22 in the T-type transistor 20 shown in Figures 2A, 2D, 3A, 4A, 5A, and 6A. The lower gate electrode 221 and / or the upper gate electrode 222 overlap the semiconductor layer 21, and a gate insulating film 25 is provided between the lower gate electrode 221 and the semiconductor layer 21 and / or between the upper gate electrode 222 and the semiconductor layer 21.

[0104] The lower gate electrode 221 can overlap either the source electrode 23 or the drain electrode 24. Thus, the lower gate electrode 221 forms a capacitance Ce with either the source electrode 23 or the drain electrode 24. The upper gate electrode 222 can overlap either the source electrode 23 or the drain electrode 24. Thus, the lower gate electrode 221 forms a capacitance Ch with either the source electrode 23 or the drain electrode 24. In this way, the capacitances Ce and Ch are MIM-type capacitances, where a dielectric layer is sandwiched between two conductive layers.

[0105] Furthermore, when both a lower gate electrode 221 and an upper gate electrode 222 are provided, the potential of the lower gate electrode 221 may be the same as the potential of the upper gate electrode 222. For this purpose, the lower gate electrode 221 and the upper gate electrode 222 may be electrically connected to each other. The conductive layer of the lower gate electrode 221 and the conductive layer of the upper gate electrode 222 may be in contact, or they may be electrically connected via another conductive layer (e.g., via).

[0106] It is preferable that the element M2 in at least one of the conductive layers of the lower gate electrode 221 and the upper gate electrode 222 is the same as the element M1 in at least one of the conductive layers of the source electrode 13 and the drain electrode 14. It is also preferable that the conductive layer containing element M2 in either the lower gate electrode 221 or the upper gate electrode 222 is the same layer as the conductive layer containing element M1 in at least one of the source electrode 13 and the drain electrode 14.

[0107] The 19th embodiment also relates to a capacitance C provided on the substrate 1. Capacitance C can be applied to capacitances 103 and 108 shown in Figures 1C and 1D, for example, but is not limited to capacitances within the pixel circuit PX, and can also be applied to integrated circuits in the peripheral region 3. The points that are the same as in the 18th embodiment will not be explained. As shown in Figure 8, at least one of a lower capacitance electrode 281 and an upper capacitance electrode 282 may be provided on the substrate 1 as a conductive member 28. For convenience, both the lower capacitance electrode 281 and the upper capacitance electrode 282 are shown in Figure 8, but one of them may be omitted, or it may not be necessary to provide both the lower capacitance electrode 281 and the upper capacitance electrode 282.

[0108] The lower capacitive electrode 281 overlaps with at least one of the lower gate electrode 221, source electrode 23, drain electrode 24, upper gate electrode 222, and upper capacitive electrode 282. The lower capacitive electrode 281 is located between the electrode that overlaps it and the substrate 1.

[0109] The lower capacitance electrode 281 and at least one of the electrodes overlapping the lower capacitance electrode 281 constitute a MIM-type capacitance with a dielectric layer sandwiched between conductive layers. Here, the dielectric layer of the capacitance is an interlayer insulating film 26. For example, the lower capacitance electrode 281 constitutes capacitance Cf with the lower gate electrode 221. For example, the lower capacitance electrode 281 constitutes capacitance Ci with the source electrode 23 or the drain electrode 24. For example, the lower capacitance electrode 281 constitutes capacitance Cj with the upper gate electrode 222. For example, the lower capacitance electrode 281 constitutes capacitance Ca with the upper capacitance electrode 282.

[0110] The upper capacitive electrode 282 overlaps with at least one of the lower capacitive electrode 281, the lower gate electrode 221, the source electrode 23, the drain electrode 24, and the upper gate electrode 222. The electrode that overlaps with the upper capacitive electrode 282 is located between the upper capacitive electrode 282 and the substrate 1.

[0111] The upper capacitance electrode 282 and at least one of the electrodes overlapping the upper capacitance electrode 282 constitute a MIM-type capacitance with a dielectric layer sandwiched between conductive layers. Here, the dielectric layer of the capacitance is an interlayer insulating film 26. For example, the upper capacitance electrode 282 constitutes capacitance Ca with the lower capacitance electrode 281. For example, the upper capacitance electrode 282 constitutes capacitance Cb with the lower gate electrode 221. For example, the upper capacitance electrode 282 constitutes capacitance Cd with the source electrode 23 or drain electrode 24. For example, the upper capacitance electrode 282 constitutes capacitance Cg with the upper gate electrode 222.

[0112] In the example shown in Figure 8, the lower capacitance electrode 281 and the upper capacitance electrode 282 overlap the semiconductor layer 21. The lower capacitance electrode 281 is located between the semiconductor layer 21 and the substrate 1. The semiconductor layer 21 is located between the upper capacitance electrode 282 and the substrate 1. However, the lower capacitance electrode 281 and the upper capacitance electrode 282 only need to overlap with the other electrodes that constitute the capacitance; it is not necessary for them to overlap the semiconductor layer 21.

[0113] It is preferable that the element M5 in at least one of the conductive layers of the lower capacitive electrode 281 and the upper capacitive electrode 282 is the same as the element M1 in at least one of the conductive layers of the source electrode 13 and the drain electrode 14. It is also preferable that the conductive layer containing element M5 in either the lower capacitive electrode 281 or the upper capacitive electrode 282 is the same layer as the conductive layer containing element M1 in at least one of the source electrode 13 and the drain electrode 14.

[0114] In the 18th and 19th embodiments, at least one of the two electrodes constituting the capacitance C is a gate electrode 22 or a conductive member 28 (capacitive electrode) that does not contact the semiconductor layer 21. The other of the two electrodes constituting the capacitance C is either a gate electrode 22 or a conductive member 28 (capacitive electrode) that does not contact the semiconductor layer 21, or a source electrode 13 or drain electrode 14 that contacts the semiconductor layer 21. The electrode that does not contact the semiconductor layer 21 (gate electrode 22 or conductive member 28 (capacitive electrode)) of the two electrodes constituting the capacitance C is insulated from the other electrode of the two electrodes constituting the capacitance C by a dielectric layer (interlayer insulating film 26).

[0115] The capacitors 103 and 108 shown in Figures 1C and 1D are connected to the source or drain of the reset transistor 102, which becomes transistor 20, the source or drain of the selection transistor 107, and the source or drain of the drive transistor 106. In this case, the electrodes of the capacitors electrically connected to the semiconductor layers 11 and 21 of transistors 10 and 20 can be indirectly connected to the semiconductor layers 11 and 21 via other conductive layers (such as vias) so as not to come into contact with the semiconductor layers 11 and 21. This suppresses metal contamination of the semiconductor layers 11 and 21. In particular, when elements M1 to M5 are easily diffusive copper (Cu), it is preferable to suppress contact between the conductive layer made of copper (copper layer) and the semiconductor layers 11 and 21.

[0116] In the examples of Figures 4A, 5A, and 6A, the gate electrode 22 corresponds to the upper gate electrode 222 shown in Figure 8, and the conductive member 28 can correspond to the lower capacitive electrode 281 shown in Figure 8. The gate electrode 22 and the conductive member 28 can then form the capacitance Cj shown in Figure 8. This capacitance Cj can be used, for example, as capacitances 103 and 108 shown in Figures 1C and 1D.

[0117] In the example shown in Figure 4B, the gate electrode 22 corresponds to the lower gate electrode 221 shown in Figure 8, and the conductive member 28 can correspond to the upper capacitive electrode 282 shown in Figure 8. The gate electrode 22 and the conductive member 28 can then form the capacitance Cb shown in Figure 8. This capacitance Cb can be used, for example, as capacitances 103 and 108 shown in Figures 1C and 1D.

[0118] Figure 9A illustrates a cross-sectional view of a semiconductor device AP having the configuration of No. 01 in Table 1, using dashed lines. In Figure 9A, the dashed lines indicate that the components connected by the dashed lines are on the same layer, that is, the source electrode 13 (and drain electrode 14) are on the same layer as the gate electrode 22.

[0119] Figure 9A illustrates a cross-sectional view of a semiconductor device AP having the configuration of No. 02 in Table 1, using dashed lines. In Figure 9A, the dashed lines indicate that the members connected by the dashed lines are in the same layer, that is, the source electrode 13 (and drain electrode 14) are in the same layer as the conductive member 28.

[0120] In the example shown in Figure 9A, the gate electrode 22 corresponds to the upper gate electrode 222 shown in Figure 8, and the conductive member 28 corresponds to the upper capacitive electrode 282 shown in Figure 8. The gate electrode 22 and the conductive member 28 form the capacitance Cg shown in Figure 8. This capacitance Cg can be used, for example, as capacitances 103 and 108 shown in Figures 1C and 1D.

[0121] Figure 9B illustrates a cross-sectional view of a semiconductor device AP having the configuration of No. 17 in Table 1, using dashed lines. In Figure 9B, the dashed lines indicate that the components connected by the dashed lines are on the same layer, that is, the source electrode 13 (and drain electrode 14) are on the same layer as the gate electrode 22.

[0122] Figure 9B illustrates a cross-sectional view of a semiconductor device AP having the configuration of No. 18 in Table 1, using dashed lines. In Figure 9B, the dashed lines indicate that the members connected by the dashed lines are in the same layer, that is, the source electrode 13 (and drain electrode 14) are in the same layer as the conductive member 28.

[0123] In the example shown in Figure 9B, the gate electrode 22 corresponds to the lower gate electrode 221 shown in Figure 8, and the conductive member 28 corresponds to the lower capacitive electrode 281 shown in Figure 8. The gate electrode 22 and the conductive member 28 form the capacitance Cf shown in Figure 8. This capacitance Cf can be used, for example, as capacitances 103 and 108 shown in Figures 1C and 1D.

[0124] In Figures 3A to 9B, an insulator 40, as shown in Figure 1B, is provided on the substrate 1, and insulating films such as interlayer insulating films and gate insulating films contained in the insulator 40 are provided around the semiconductor layers 11 and 21. However, in Figures 3A to 9B, at least some of these insulators 40 are omitted from the description.

[0125] Figure 10A shows a device EQP equipped with a semiconductor device AP. The device EQP may include at least one of a display device DSPL, an imaging device IS, an acoustic device AUDIO, a control device CTRL, and a communication device IF. Typically, either the display device DSPL or the imaging device IS has the structure of the semiconductor device AP described above. The acoustic device AUDIO, the control device CTRL, and the communication device IF may also have the structure of the semiconductor device AP described above. The acoustic device AUDIO includes a microphone and a speaker. The communication device IF performs wired or wireless communication. The communication device IF may communicate in the 3.5 to 5.0 GHz frequency band or in the 24 to 53 GHz frequency band. The communication device IF may communicate using terahertz waves, not limited to microwaves or millimeter waves. The control device CTRL can consist of a wiring board and a plurality of components mounted on the wiring board. The control device CTRL may include semiconductor devices manufactured using a 65 to 5 nm process rule or may include semiconductor devices manufactured using a 1 to 4 nm process rule. For these manufacturing processes, EUV lithography equipment, electron beam lithography equipment, nanoimprint lithography equipment, etc., can be used.

[0126] The control device CTRL is connected to the display device DSPL. If the display device DSPL has a drive circuit for driving pixel circuits in the peripheral region 3, the control device CTRL can supply power and signals to the drive circuit. If the display device DSPL does not have a drive circuit for driving pixel circuits in the peripheral region 3, the control device CTRL has a drive circuit for driving pixel circuits.

[0127] The control unit CTRL is connected to the imaging device IS. The control unit CTRL controls the imaging mode of the imaging device IS and processes the signals output from the imaging device IS. The imaging device IS may be an image sensor, an infrared sensor, or a distance measuring sensor.

[0128] The EQP device may include an optical component OPT provided on a display device DSPL, which is a semiconductor device AP. The optical component OPT is a lens, cover, or filter. If the semiconductor device AP is a top-emission type display device DSPL, a semiconductor layer 21 may be provided between the substrate 1 of the semiconductor device AP and the optical component OPT. If the semiconductor device AP is a bottom-emission type display device DSPL, a substrate 1 may be provided between the semiconductor layer 21 of the semiconductor device AP and the optical component OPT.

[0129] The EQP system may include an imaging device (IS) and a display device (DSPL). The DSPL can display images captured by the IS.

[0130] The DSPL display device may be switchable between displaying at a low frame rate and displaying at a high frame rate higher than the low frame rate. For example, the low frame rate could be 10fps or less, or even 5fps or less, for example, 1fps, and the high frame rate could be 100fps or more, or even 200fps or more, for example, 240fps. The DSPL display device may also be switchable between displaying at a low refresh rate and displaying at a high refresh rate higher than the low refresh rate. For example, the low refresh rate could be 10Hz or less, or even 5Hz or less, for example, 1Hz, and the high refresh rate could be 100Hz or more, or even 200Hz or more, for example, 240Hz. Note that both the frame rate (fps) and the refresh rate (Hz) can be expressed as "frames per second" or "refreshes per second". The DSPL display device may also be switchable to display at an intermediate frame rate between the low and high frame rates. For example, a medium frame rate is 20-80 fps. The display device DSPL may also be switchable to display at a medium refresh rate between a low refresh rate and a high refresh rate. For example, a medium refresh rate is 20-80 Hz. Since oxide semiconductor layers have low leakage current, using an oxide semiconductor layer for the selection transistor 107 suppresses charge leakage from the capacitor 108, making it easy to drive at low frame rates. Also, since polycrystalline semiconductor layers have higher mobility than amorphous semiconductor layers, using a polycrystalline semiconductor layer for the selection transistor 107 allows for faster selection, making it easy to drive at high frame rates and refresh rates. Furthermore, since polycrystalline semiconductor layers have higher mobility than amorphous semiconductor layers, using a polycrystalline semiconductor layer for the drive transistor 106 allows for a lower gate voltage, making it easy to drive with low power consumption.

[0131] The imaging device IS can capture images at a medium frame rate between the low and high frame rates mentioned above. The imaging device IS can capture images at a medium frame rate between the low and high refresh rates mentioned above. For example, the imaging device IS can capture images at a frame rate of 20 to 80 fps. Here, "capture" is not limited to saving images, but also includes capture for temporary display purposes, such as live view. When displaying images captured by the imaging device IS at a medium frame rate, the frame rate of the display device DSPL is preferably a medium or high frame rate. When displaying images captured by the imaging device IS at a medium frame rate, the refresh rate of the display device DSPL is preferably a medium or high refresh rate. For example, when displaying images captured by the imaging device IS at a frame rate of 30 frames / second, the refresh rate of the display device DSPL is preferably 60 frames / second or 120 frames per second.

[0132] The EQP device can be an electronic device such as a smartphone, tablet, laptop computer, digital camera, or wearable device. The EQP device may be equipped with a battery such as a lithium-ion battery, solid-state battery, or fuel cell. Because the imaging device IS and display device DSPL can be powered by a low power source, the device can be operated for a long time by the battery. Figure 10B shows a head-mounted display (HMD) as a wearable device. The main unit, which has the display device DSPL and the imaging device IS, can be attached to the head by the attachment means WR. In addition to the electronic devices described above, the present invention can be applied to various devices such as transportation equipment, industrial equipment, medical equipment, and analytical instruments.

[0133] The embodiments described above can be modified as appropriate without departing from the technical concept. For example, multiple embodiments can be combined. Furthermore, some aspects of at least one embodiment can be deleted or replaced. Furthermore, new aspects can be added to at least one embodiment.

[0134] Furthermore, the disclosures in this specification include not only what is explicitly stated herein, but also all matters that can be understood from this specification and the drawings attached thereto. In addition, the disclosures in this specification include the complement of the individual concepts described herein. That is, if this specification states, for example, that "A is greater than B," then even if it omits the statement that "A is not greater than B," it can be said that this specification discloses that "A is not greater than B." This is because the statement that "A is greater than B" presupposes that the case where "A is not greater than B" is being considered.

[0135] The present invention is not limited to the embodiments described above, and various modifications and variations are possible without departing from the spirit and scope of the invention. Accordingly, the following claims are attached to make the scope of the invention public.

[0136] This application claims priority based on Japanese Patent Application No. 2021-036296 filed on March 8, 2021, and Japanese Patent Application No. 2021-109341 filed on June 30, 2021, and all of the contents of those applications are incorporated herein by reference.

Claims

1. circuit board and A first semiconductor layer of the first transistor is provided on the substrate, A first conductive layer is provided on the substrate and overlaps the first semiconductor layer, A second semiconductor layer of the second transistor is provided on the aforementioned substrate, A second conductive layer is provided on the substrate and overlaps the second semiconductor layer, Equipped with, Among the elements of groups 12 to 16 contained in the first semiconductor layer, the first element having the highest concentration in the first semiconductor layer is different from the second element having the highest concentration in the second semiconductor layer among the elements of groups 12 to 16 contained in the second semiconductor layer. The third element, which has the highest concentration among the metallic or metalloid elements contained in the first conductive layer, is the same as the fourth element, which has the highest concentration among the metallic or metalloid elements contained in the second conductive layer. The first conductive layer is in contact with the first semiconductor layer. The second conductive layer is insulated from the second semiconductor layer. The second conductive layer is provided between the second semiconductor layer and the substrate. The aforementioned second semiconductor layer is an oxide semiconductor layer, The second conductive layer is continuous with the first conductive layer. A semiconductor device characterized by the following features.

2. circuit board and A first semiconductor layer of the first transistor is provided on the substrate, A first conductive layer is provided on the substrate and overlaps the first semiconductor layer, A second semiconductor layer of the second transistor is provided on the aforementioned substrate, A second conductive layer is provided on the substrate and overlaps the second semiconductor layer, A third conductive layer is provided on the substrate and overlaps the second conductive layer, Equipped with, Among the elements of groups 12 to 16 contained in the first semiconductor layer, the first element having the highest concentration in the first semiconductor layer is different from the second element having the highest concentration in the second semiconductor layer among the elements of groups 12 to 16 contained in the second semiconductor layer. The third element, which has the highest concentration among the metallic or metalloid elements contained in the first conductive layer, is the same as the fourth element, which has the highest concentration among the metallic or metalloid elements contained in the second conductive layer. The first conductive layer is in contact with the first semiconductor layer. The second conductive layer is insulated from the second semiconductor layer. The third conductive layer does not contact the second semiconductor layer. The third conductive layer is provided between the second conductive layer and the substrate. The third conductive layer is insulated from the first semiconductor layer and the second conductive layer. A semiconductor device characterized by the following features.

3. circuit board and A first semiconductor layer of an N-type first transistor is provided on the substrate, A first conductive layer is provided on the substrate and overlaps the first semiconductor layer, A second semiconductor layer of a P-type second transistor is provided on the aforementioned substrate, A second conductive layer is provided on the substrate and overlaps the second semiconductor layer, Equipped with, Among the elements of groups 12 to 16 contained in the first semiconductor layer, the first element having the highest concentration in the first semiconductor layer is different from the second element having the highest concentration in the second semiconductor layer among the elements of groups 12 to 16 contained in the second semiconductor layer. The third element, which has the highest concentration among the metallic or metalloid elements contained in the first conductive layer, is the same as the fourth element, which has the highest concentration among the metallic or metalloid elements contained in the second conductive layer. The first conductive layer is in contact with the first semiconductor layer. The second conductive layer is insulated from the second semiconductor layer. The second transistor mentioned above is a switch transistor. A semiconductor device characterized by the following features.

4. circuit board and A first semiconductor layer of the first transistor is provided on the substrate, A first conductive layer is provided on the substrate and overlaps the first semiconductor layer, A second semiconductor layer of the second transistor is provided on the aforementioned substrate, A second conductive layer is provided on the substrate and overlaps the second semiconductor layer, Equipped with, Among the elements of groups 12 to 16 contained in the first semiconductor layer, the first element having the highest concentration in the first semiconductor layer is different from the second element having the highest concentration in the second semiconductor layer among the elements of groups 12 to 16 contained in the second semiconductor layer. The third element, which has the highest concentration among the metallic or metalloid elements contained in the first conductive layer, is the same as the fourth element, which has the highest concentration among the metallic or metalloid elements contained in the second conductive layer. The first conductive layer is in contact with the first semiconductor layer. The second conductive layer is insulated from the second semiconductor layer. The first conductive layer is provided between the first semiconductor layer and the substrate. The second semiconductor layer is provided between the second conductive layer and the substrate. A semiconductor device characterized by the following features.

5. circuit board and A first semiconductor layer of the first transistor is provided on the substrate, A first conductive layer is provided on the substrate and overlaps the first semiconductor layer, A second semiconductor layer of the second transistor is provided on the aforementioned substrate, A second conductive layer is provided on the substrate and overlaps the second semiconductor layer, Equipped with, Among the elements of groups 12 to 16 contained in the first semiconductor layer, the first element having the highest concentration in the first semiconductor layer is different from the second element having the highest concentration in the second semiconductor layer among the elements of groups 12 to 16 contained in the second semiconductor layer. The third element, which has the highest concentration among the metallic or metalloid elements contained in the first conductive layer, is the same as the fourth element, which has the highest concentration among the metallic or metalloid elements contained in the second conductive layer. The first conductive layer is in contact with the first semiconductor layer. The second conductive layer is insulated from the second semiconductor layer. The second semiconductor layer is provided between the second conductive layer and the substrate. The second conductive layer is continuous with the first conductive layer, The second transistor mentioned above is a switch transistor. A semiconductor device characterized by the following features.

6. circuit board and A first semiconductor layer of the first transistor is provided on the substrate, A first conductive layer is provided on the substrate and overlaps the first semiconductor layer, A second semiconductor layer of the second transistor is provided on the aforementioned substrate, A second conductive layer is provided on the substrate and overlaps the second semiconductor layer, Equipped with, Among the elements of groups 12 to 16 contained in the first semiconductor layer, the first element having the highest concentration in the first semiconductor layer is different from the second element having the highest concentration in the second semiconductor layer among the elements of groups 12 to 16 contained in the second semiconductor layer. The third element, which has the highest concentration among the metallic or metalloid elements contained in the first conductive layer, is the same as the fourth element, which has the highest concentration among the metallic or metalloid elements contained in the second conductive layer. The first conductive layer is in contact with the first semiconductor layer. The second conductive layer is insulated from the second semiconductor layer. The second semiconductor layer is provided between the second conductive layer and the substrate. The first semiconductor layer is an oxide semiconductor layer. A semiconductor device characterized by the following features.

7. The semiconductor device according to any one of claims 1 to 6, wherein the first conductive layer and the second conductive layer are the same layer.

8. The second semiconductor layer is provided between the substrate and the gate electrode of the second transistor. The semiconductor device according to any one of claims 1 to 7.

9. The gate electrode of the second transistor is provided between the substrate and the second semiconductor layer. The semiconductor device according to any one of claims 1 to 7.

10. The gate electrode of the second transistor includes the second conductive layer. The semiconductor device according to claim 8 or 9.

11. The second semiconductor layer is provided between the gate electrode of the second transistor and the second conductive layer. The semiconductor device according to claim 8 or 9.

12. The source electrode of the first transistor includes the first conductive layer, The source electrode and the gate electrode of the second transistor are provided on either the side of the second semiconductor layer facing the substrate or the side opposite to the substrate. The semiconductor device according to any one of claims 1 to 11.

13. The source electrode of the first transistor includes the first conductive layer, The second semiconductor layer is provided between the gate electrode of the second transistor and the source electrode of the second transistor. The semiconductor device according to any one of claims 1 to 12.

14. The semiconductor device according to any one of claims 1 to 13, wherein the second semiconductor layer is thinner than the gate electrode of the second transistor.

15. The semiconductor device according to any one of claims 1 to 14, wherein the third and fourth elements are copper (Cu) or titanium (Ti).

16. The semiconductor device according to any one of claims 1 to 15, wherein the drain electrode of the second transistor contains the same element as the fourth element.

17. The semiconductor device according to any one of claims 1 to 16, wherein the gate electrode of the first transistor contains the same element as the third element.

18. The distance between the first semiconductor layer and the substrate is different from the distance between the second semiconductor layer and the substrate. The distance between the first semiconductor layer and the first gate electrode of the first transistor is different from the distance between the second semiconductor layer and the second gate electrode of the second transistor. The distance between the substrate and the first gate electrode is different from the distance between the substrate and the second gate electrode. The second conductive layer is discontinuous with the first conductive layer. The semiconductor device according to any one of claims 2 to 6.

19. The semiconductor device according to any one of claims 1 to 15, characterized in that the first transistor and the second transistor are electrically connected.

20. The semiconductor device according to claim 2, having capacitance with a dielectric layer sandwiched between the second conductive layer and the third conductive layer.

21. The substrate is provided with an organic EL element, The first element is an element of Group 14, The semiconductor device according to any one of claims 1 to 5, wherein the second element is an element of group 12, group 13, group 15, or group 16.

22. The diagonal length of the aforementioned substrate is 5 cm or more. One of the first semiconductor layer and the second semiconductor layer is a polycrystalline layer. The other of the first semiconductor layer and the second semiconductor layer is an oxide semiconductor layer. The distance between the polycrystalline layer and the substrate is smaller than the distance between the oxide semiconductor layer and the substrate. The semiconductor device according to any one of claims 1 to 21.

23. The semiconductor device according to claim 1, 6, or 22, wherein the oxide semiconductor layer contains tin (Sn).

24. The semiconductor device according to any one of claims 1 to 23, wherein the third element is different from the second element, and the fourth element is different from the first element.

25. A semiconductor device according to any one of claims 1 to 24, A device characterized by comprising a control device connected to the aforementioned semiconductor device.

26. A semiconductor device according to any one of claims 1 to 24, The semiconductor device comprises an optical member provided on the semiconductor device, The apparatus is characterized in that the second semiconductor layer is provided between the substrate and the optical member.

27. A device comprising an imaging device and a display device, The display device includes the semiconductor device described in any one of claims 1 to 24. The display device can switch between displaying at a first rate and displaying at a second rate higher than the first rate. The imaging device is characterized by performing imaging at a third rate between the first rate and the second rate.

28. The apparatus according to claim 27, characterized in that the first rate is 10 fps or less, and the second rate is 100 fps or more.

29. The apparatus according to claim 27, characterized in that the first rate is 5 Hz or less, and the third rate is 20 to 80 fps.

30. A device comprising a semiconductor device according to any one of claims 1 to 24, Semiconductor devices manufactured using a 1-4 nm process rule, A communication device that communicates using terahertz waves, A device comprising at least one of the following: an all-solid-state battery.

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