Crystalline oxide thin films, laminates, and thin-film transistors

Abstract

Provided is a crystalline oxide thin film containing In as a main component. The crystalline oxide thin film has a low-resistance region A and a high-resistance region B which exhibit different spreading resistance values as measured by a scanning spreading resistance microscope (SSRM) in a plane direction of the crystalline oxide thin film, and the spreading resistance value in the high-resistance region B is at least 8 times the spreading resistance value in the low-resistance region A.

Description

[Technical Field]

[0001] This invention relates to crystalline oxide thin films, laminates, and thin-film transistors. [Background technology]

[0002] Thin-film transistors (TFTs) using crystalline oxide thin films as the channel layer are known to exhibit high mobility characteristics (see, for example, Patent Documents 1 to 7). In recent years, TFTs have tended to become smaller, making the characteristics of small TFTs important. Here, a small TFT refers to a TFT with a channel length L of 50 μm or less. Furthermore, for driving high-resolution displays, TFTs with high mobility and reduced parasitic capacitance are required. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Patent No. 5373212 [Patent Document 2] Japanese Patent Publication No. 2018-107316 [Patent Document 3] Patent No. 6097458 [Patent Document 4] Patent No. 6334598 [Patent Document 5] Patent No. 6289693 [Patent Document 6] International Publication No. 2018 / 043323 [Patent Document 7] International Publication No. 2020 / 196716 [Overview of the project]

[0004] To obtain a TFT with reduced parasitic capacitance by using an oxide thin film in the channel layer, a self-aligned TFT structure can be considered. Furthermore, to obtain a TFT exhibiting high mobility, it is necessary to use a crystalline oxide material in the channel layer rather than an amorphous material. However, when the crystalline oxide thin films described in Patent Documents 1 to 7 are applied to a self-aligned TFT structure, a sufficient energy barrier is not formed because there is no difference in resistivity between the region where the gate electrodes are stacked (region B) and the other regions (region A). This leads to a drain-induced barrier drop (DIBL) phenomenon where Vth tends to shift negative when a high drain voltage Vd is applied to drive the TFT, resulting in unstable TFT characteristics. Furthermore, because the average spacing (D) of the grain boundaries in region A is not controlled, there is a problem in that the stability of the TFT's mobility and threshold voltage (Vth) with respect to the device shape deteriorates. When such a TFT is incorporated into a circuit and used to drive a display, problems such as uneven brightness and burn-in may occur.

[0005] One of the objectives of the present invention is to provide a crystalline oxide thin film and a laminate that can form a region with a sufficiently large difference in resistivity. Another objective of the present invention is to provide a crystalline oxide thin film and a laminate in which the average spacing of the grain boundaries is controlled.

[0006] According to the present invention, the following crystalline oxide thin films and the like are provided. 1. A crystalline oxide thin film mainly composed of In, The aforementioned crystalline oxide thin film has a low-resistance region A and a high-resistance region B in the planar direction, with different spreading resistance values ​​measured by a scanning spreading resistance microscope (SSRM). A crystalline oxide thin film in which the spreading resistance value of the high-resistance region B is 8 times or more the spreading resistance value of the low-resistance region A. 2. The crystalline oxide thin film according to claim 1, wherein the spreading resistance value of the high-resistance region B is 10 times or more the spreading resistance value of the low-resistance region A. 3. The crystalline oxide thin film according to claim 1, wherein the spreading resistance value of the high-resistance region B is 15 times or more the spreading resistance value of the low-resistance region A. 4. A crystalline oxide thin film described in any of 1 to 3, with a film thickness of 80 nm or less. 5. A crystalline oxide thin film according to any one of 1 to 4, wherein, in the dC / dV values ​​measured by a scanning capacitance microscope (SCM), the dC / dV value at the boundary between the low-resistance region A and the high-resistance region B is greater than the dC / dV value of the high-resistance region B. 6. The average grain boundary angle θ between the lower surface of the crystalline oxide thin film and the grain boundaries within the thin film is 70° or more and 110° or less. A crystalline oxide thin film according to any one of 1 to 5, wherein the average spacing D between the grain boundaries is 0.01 μm or more and 2.0 μm or less. 7. The crystalline oxide thin film according to any one of 1 to 6, wherein the electron diffraction of the crystalline oxide thin film contains crystal grains having a bixbite structure. 8. The crystalline oxide thin film according to any one of 1 to 7, wherein the crystalline oxide thin film further contains one or more elements selected from the group consisting of H, B, C, N, O, F, Mg, Al, Si, O, S, Cl, Ar, Ca, Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zn, Ga, Ge, Y, Zr, Nb, Mo, Tc, Ru, Rh, Pd, Ag, Cd, Sn, Sb, Cs, Ba, Ln, Hf, Ta, W, Re, Os, Ir, Pt, Au, Pb, and Bi. A laminate containing a crystalline oxide thin film as described in any of sections 9.1 to 9.8. 10. The average grain boundary angle θ between the surface where the crystalline oxide thin film and the lower layer are in contact and the grain boundaries in the crystalline oxide thin film. sub The laminate described in 9, wherein the angle is 70° or more and 110° or less. 11. The laminate according to 9 or 10, wherein the lower layer is a substrate for a thin-film transistor or a constituent layer of a thin-film transistor. A thin-film transistor comprising a crystalline oxide thin film as described in any of sections 12.1 to 8 or a laminate as described in any of sections 9 to 11. 13. Channel layer and Source electrode and drain electrode connected to both ends of the channel layer, It has a gate electrode stacked on a channel layer via a gate insulating film. The channel layer is the crystalline oxide thin film, the gate insulating film is formed in the high-resistance region B, and the source electrode and drain electrode are formed in the low-resistance region A. The distance L from the ends of the source electrode and the drain electrode to the intersection of the perpendicular line drawn in the thickness direction from the end of the gate electrode and the crystalline oxide thin film off However, it is between 4 μm and 20 μm. The average spacing D between grain boundaries in the crystalline oxide thin film, and the distance L. off A thin-film transistor as described in 12, wherein the following equation (1) is satisfied. 2 ≤ L off / D≦100···(1) 14. The contact region length Ls between the source electrode and the drain electrode and the channel layer is 4 μm or more and 20 μm or less. The thin-film transistor according to 12 or 13, wherein the average spacing D between grain boundaries of the crystalline oxide thin film and the contact region length Ls satisfy the following formula (2). 1 ≤ Ls / D ≤ 100 ···(2) 15. A thin-film transistor according to any one of 12 to 14, wherein the horizontal gap ΔL between the low-resistance region A and the gate electrode is less than 1 μm. 16. A crystalline oxide thin film mainly composed of In, The film thickness is 80 nm or less. The crystalline oxide thin film has a high carrier concentration region A and a low carrier concentration region B in the plane direction, with different carrier concentrations. The carrier concentration in the aforementioned high carrier concentration region A is 10 19 cm -3 The above 10 22 cm -3 The following: A crystalline oxide thin film in which the carrier concentration in the high carrier concentration region A is eight times or more than the carrier concentration in the low carrier concentration region B. 17. The crystalline oxide thin film according to 16, wherein the carrier concentration in the high carrier concentration region A is 10 times or more than the carrier concentration in the low carrier concentration region B. 18. The crystalline oxide thin film according to 16, wherein a carrier concentration of the high carrier concentration region A is 15 times or more a carrier concentration of the low carrier concentration region B. 19. The carrier concentration of the low carrier concentration region B is 10 15 cm -3 or more, and 10 19 cm -3 or less, the crystalline oxide thin film according to any one of 16 to 18. 20. In the crystalline oxide thin film, an average grain boundary angle θ formed by a lower surface of the thin film and crystal grain boundaries in the thin film is 70° or more and 110° or less, the crystalline oxide thin film according to any one of 16 to 19, wherein an average interval D between the crystal grain boundaries is 0.01 μm or more and 2.0 μm or less. 21. The crystalline oxide thin film according to any one of 16 to 20, which, in electron diffraction of the crystalline oxide thin film, comprises crystal grains having a bixbyite structure. 22. The crystalline oxide thin film according to any one of 16 to 21, wherein the crystalline oxide thin film further comprises one or more elements selected from the group consisting of H, B, C, N, O, F, Mg, Al, Si, O, S, Cl, Ar, Ca, Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zn, Ga, Ge, Y, Zr, Nb, Mo, Tc, Ru, Rh, Pd, Ag, Cd, Sn, Sb, Cs, Ba, Ln, Hf, Ta, W, Re, Os, Ir, Pt, Au, Pb and Bi. 23. A laminate, comprising the crystalline oxide thin film according to any one of 16 to 22. 24. An average grain boundary angle θ formed by a surface where the crystalline oxide thin film is in contact with a lower layer and a crystal grain boundary in the crystalline oxide thin film sub is 70° or more and 110° or less, the laminate according to 23. 25. The laminate according to 23 or 24, wherein the lower layer is a substrate of a thin film transistor or a constituent layer of a thin film transistor. 26. A thin film transistor, comprising the crystalline oxide thin film according to any one of 16 to 22 or the laminate according to any one of 23 to 25. 27. a channel layer and a source electrode and a drain electrode respectively connected to both end sides of the channel layer, It has a gate electrode stacked on a channel layer via a gate insulating film. The channel layer is the crystalline oxide thin film, the gate insulating film is formed in the low carrier concentration region B, and the source electrode and drain electrode are formed in the high carrier concentration region A. The distance L from the ends of the source electrode and the drain electrode to the intersection of the perpendicular line drawn in the thickness direction from the end of the gate electrode and the crystalline oxide thin film is L. off However, it is between 4 μm and 20 μm. The average spacing D between grain boundaries in the crystalline oxide thin film, and the distance L. off A thin-film transistor as described in 26, wherein the following equation (1) is satisfied. 2 ≤ L off / D≦100···(1) 28. The contact region length Ls between the source electrode and the drain electrode and the channel layer is 4 μm or more and 20 μm or less. The thin-film transistor according to 26 or 27, wherein the average spacing D between grain boundaries of the crystalline oxide thin film and the contact region length Ls satisfy the following formula (2). 1 ≤ Ls / D ≤ 100 ···(2) 29. A thin-film transistor according to any one of 26 to 28, wherein the horizontal gap ΔL between the high-carrier concentration region A and the gate electrode is less than 1 μm. 30. A crystalline oxide thin film mainly composed of In, The film thickness is 80 nm or less. The average spacing D between grain boundaries in the aforementioned crystalline oxide thin film is 2 μm or less. Carrier concentration is 10 19 cm -3 The above 10 22 cm -3 The following are crystalline oxide thin films. A thin-film transistor comprising a crystalline oxide thin film as described in 31.30. An electronic circuit including a thin-film transistor as described in any of sections 32.12-15, 26-29, and 31. Electrical equipment, electronic equipment, vehicles, or power engines, including the electronic circuits described in 33.32.

[0007] According to the present invention, it is possible to provide a crystalline oxide thin film and a laminate that can form a region with a sufficiently large difference in resistivity. Furthermore, according to the present invention, it is possible to provide a crystalline oxide thin film and a laminate in which the average spacing of the grain boundaries is controlled. This allows for the provision of a self-matching TFT that does not exhibit the DIBL phenomenon, maintains high mobility, and offers high stability in terms of mobility and Vth relative to the element shape. [Brief explanation of the drawing]

[0008] [Figure 1] This is a schematic cross-sectional view of an example of a laminate according to this embodiment. [Figure 2] This is a schematic cross-sectional view of another example of the laminate according to this embodiment. [Figure 3A] This is a schematic cross-sectional view of a TFT according to an example of this embodiment. [Figure 3B] Figure 3A is a magnified view of the area around the source electrode. [Figure 4] This is a schematic cross-sectional view of another example of a TFT according to this embodiment. [Figure 5] This is a schematic cross-sectional view of another example of a TFT according to this embodiment. [Figure 6] This is a schematic cross-sectional view of another example of a TFT according to this embodiment. [Figure 7] This is a schematic cross-sectional view of another example of a TFT according to this embodiment. [Figure 8A] This is an example of a circuit diagram for the pixel section when using liquid crystal elements. [Figure 8B] This is an example of a circuit diagram for the pixel section when using organic EL elements. [Figure 8C] This is a top view of the display device according to this embodiment. [Figure 9] This is a schematic cross-sectional view of the TFT fabricated in the example. [Figure 10] These are the CL spectra measured in Example 217 and Comparative Example 20. [Modes for carrying out the invention]

[0009] The ordinal numbers "1st," "2nd," and "3rd" used in this specification are used to avoid confusion of constituent elements, and constituent elements that are not specified numerically are not limited to a specific number.

[0010] In this specification, the terms "film" or "thin film" and the term "layer" may be interchangeable in some cases.

[0011] In the sintered bodies and oxide thin films described herein, the terms "compound" and "crystalline phase" may, in some cases, be interchangeable.

[0012] In this specification, "oxide sintered body" may sometimes be simply referred to as "sintered body." In this specification, a "sputtering target" may sometimes be simply referred to as a "target."

[0013] In this specification, "electrically connected" includes cases where a connection is made via "something that has some electrical function." Here, "something that has some electrical function" is not particularly limited as long as it enables the exchange of electrical signals between the connected objects. For example, "something that has some electrical function" includes electrodes, wiring, switching elements (such as transistors), resistive elements, inductors, capacitors, and other elements with various functions.

[0014] In this specification, the source and drain functions of a transistor may be reversed when transistors of different polarities are used or when the direction of current changes during circuit operation. Therefore, in this specification, the terms source and drain may be used interchangeably.

[0015] In this specification, "x~y" represents a numerical range of "greater than or equal to x and less than or equal to y". The upper and lower limits specified for the numerical range can be combined in any way. Furthermore, forms that combine two or more of the individual embodiments of the present invention described below are also embodiments of the present invention.

[0016] 1. Crystalline oxide thin film (1) First embodiment of a crystalline oxide thin film The crystalline oxide thin film according to this embodiment is a crystalline oxide thin film mainly composed of In. The crystalline oxide thin film has a low-resistance region A and a high-resistance region B in the planar direction, with different spreading resistance values ​​measured by a scanning spreading resistance microscope (SSRM), and the spreading resistance value of the high-resistance region B is 8 times or more the spreading resistance value of the low-resistance region A.

[0017] The crystalline oxide thin film according to this embodiment is mainly composed of the element In. Being the main component means that the composition ratio (atomic %: at%) of In relative to the total metal elements of the crystalline oxide thin film is 50 at% or more. Preferably, the composition ratio of In is 70 at% or more, more preferably 80 at% or more, and even more preferably 85 at% or more. If 50 at% or more of the total number of atoms of the metal elements constituting the crystalline oxide thin film is the element In, then when the crystalline oxide thin film according to this embodiment is used in a TFT, it can exhibit sufficiently high mobility.

[0018] In addition to In, the crystalline oxide thin film may contain one or more elements selected from the group consisting of H, B, C, N, O, F, Mg, Al, Si, O, S, Cl, Ar, Ca, Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zn, Ga, Ge, Y, Zr, Nb, Mo, Tc, Ru, Rh, Pd, Ag, Cd, Sn, Sb, Cs, Ba, Ln, Hf, Ta, W, Re, Os, Ir, Pt, Au, Pb, and Bi.

[0019] In this embodiment, the crystalline oxide thin film may consist substantially of elements selected from In, Mg, Al, Si, Zn, Ga, Mo, Sn, Ln (lanthanide elements) and O. Here, "substantially" means that the crystalline oxide thin film according to this embodiment may contain other components to the extent that the effects of the present invention resulting from the above combination of In, Mg, Al, Si, Zn, Ga, Mo, Sn, Ln, and O occur.

[0020] In this embodiment, a more preferred first form of the crystalline oxide thin film is one in which the metallic elements consist of In and Ga, and the atomic ratio satisfies the following formula (11). [Ga] / ([In]+[Ga])<22at% (11) Furthermore, the metal elements may include unavoidable impurities, as well as F or H in addition to O. By keeping the composition within the above range, the In ratio increases, allowing Ga to substitute for In sites and crystallize into a bixbite structure even at low temperatures such as 300°C during annealing. Adding Ga, which has a strong bonding force with oxygen, further suppresses oxygen vacancies after annealing, enabling the formation of a stable semiconductor film.

[0021] In this embodiment, a more preferred second form of the crystalline oxide thin film consists of In as a metallic element and one or more elements X selected from B, Al, Sc, Mg, Zn, Ti, Y, Zr, Mo, Sn, Hf, W, Nb, Ta, Ge, Si, La, Ce, Pr, Nd, Sm, Dy, Ho, Er, Tm, Yb, and Lu, and satisfies the following formula (12) as an atomic ratio when X is a metallic element other than In. [X] / ([In]+[X])<15at% (12) Furthermore, the metal elements may include unavoidable impurities, as well as F or H in addition to O. By keeping the composition within the above range, the In ratio increases, allowing crystallization into a bixbite structure where X is substituted at the In site, even at low temperatures such as 300°C. Adding element X, which has a strong bonding force with oxygen, further suppresses oxygen vacancies after annealing, enabling the formation of a stable semiconductor film.

[0022] In this embodiment, a more preferred third form of the crystalline oxide thin film consists of In, Ga, and one or more elements X selected from B, Al, Sc, Mg, Zn, Ti, Y, Zr, Mo, Sn, Hf, W, Nb, Ta, Ge, Si, La, Ce, Pr, Nd, Sm, Dy, Ho, Er, Tm, Yb, and Lu as metal elements, and when metal elements other than In and Ga are added as elements X, the atomic ratios satisfy the following formulas (13) and (14). [Ga] / ([In]+[Ga]+[X])<22.5at% (13) [X] / ([In]+[Ga]+[X])<8.0at% (14) Furthermore, as a metallic element, it may contain unavoidable impurities, as well as F or H in addition to O. By using the above composition range, the In ratio increases, allowing crystallization into a bixbite structure with Ga substitution at the In sites, even at low temperatures such as 300°C. Furthermore, by adding element X, which has a strong bonding force with oxygen, oxygen vacancies after annealing are further suppressed, enabling the formation of a stable semiconductor film.

[0023] In this embodiment, a more preferred fourth form of the crystalline oxide thin film consists of In, Sn, and one or more elements X selected from B, Al, Sc, Mg, Zn, Ti, Y, Zr, Mo, Hf, W, Nb, Ta, Ge, Si, La, Ce, Pr, Nd, Sm, Dy, Ho, Er, Tm, Yb, and Lu as metal elements, and when element X is a metal element other than In and Sn, the atomic ratio satisfies the following formulas (15) and (16). [Sn] / ([In]+[Sn]+[X])<20at% (15) [X] / ([In]+[Sn]+[X])<8.0at% (16) Furthermore, as a metallic element, it may contain unavoidable impurities, as well as F or H in addition to O. By using this compositional range, the In ratio increases, allowing crystallization into a bixbite structure with Sn substitution at In sites, even at low temperatures such as 300°C. Sn has a large ionic radius and a large overlap of orbitals with In, thus maintaining high mobility. Furthermore, by adding an additive element X with strong oxygen bonding ability, oxygen vacancies after annealing are further suppressed, enabling the formation of a semiconductor-stable film.

[0024] In this embodiment, a more preferred fifth form of the crystalline oxide thin film consists of In, Zn, and one or more elements X selected from B, Al, Sc, Mg, Ti, Y, Zr, Mo, Hf, W, Nb, Ta, Ge, Si, La, Ce, Pr, Nd, Sm, Dy, Ho, Er, Tm, Yb, and Lu as metal elements, and when element X is a metal element other than In and Zn, the atomic ratios satisfy the following formulas (17) and (18). [Zn] / ([In]+[Zn]+[X])<12at% (17) [X] / ([In]+[Zn]+[X])<8.0at% (18) Furthermore, as a metallic element, it may contain unavoidable impurities, as well as F or H in addition to O. By using the above composition range, the In ratio increases, allowing crystallization into a bixbite structure with Zn substitution at In sites, even at low temperatures such as 300°C. Adding Zn allows the film to be in an amorphous state immediately after deposition, enabling processing without residue during semiconductor patterning with acid during TFT fabrication. Furthermore, by adding element X, which has a strong bonding force with oxygen, oxygen vacancies after annealing are suppressed, and a stable semiconductor film can be formed.

[0025] The content (atomic ratio) of each metal element in a crystalline oxide thin film can be determined by measuring the abundance of each element using ICP (Inductive Coupled Plasma) or XRF (X-ray Fluorescence) measurements. For ICP measurements, an inductively coupled plasma emission spectrometer (ICP-OES, manufactured by Agilent) can be used. For XRF measurements, a thin-film X-ray fluorescence spectrometer (AZX400, manufactured by Rigaku Corporation) can be used.

[0026] Furthermore, the content (atomic ratio) of each metal element in the crystalline oxide thin film can be analyzed with an error accuracy of less than 2 atomic percent by TEM-EDS measurement using an electron microscope, ICP measurement using an inductively coupled plasma emission spectrometer, and SIMS analysis using a sector-type dynamic secondary ion mass spectrometer. First, the metal elements in the crystalline oxide thin film are identified by cross-sectional TEM-EDS, and the composition ratio is identified with an error range of about 10 atomic percent by semi-quantitative analysis. Next, standard oxide thin films are prepared from 10 different composition ratios, each with known atomic ratios of metal elements within a range of 20 atomic percent from the semi-quantitative analysis results. For the standard oxide thin films, the absolute value of the composition ratio is taken from the value measured by an inductively coupled plasma emission spectrometer or a thin-film X-ray fluorescence spectrometer. Furthermore, source and drain electrodes formed on the upper surface of the standard oxide thin film using the same material and channel length as the TFT element are prepared, and these are used as standard materials. The oxide semiconductor layer is analyzed using a sector-type dynamic secondary ion mass spectrometer SIMS (IMS 7f-Auto, AMETEK), and the mass spectral intensity of each element is obtained, and a calibration curve of known element concentrations and mass spectral intensities is prepared. Next, the oxide thin film portion of the actual TFT element removed from the panel is analyzed using SIMS analysis with a sector-type dynamic secondary ion mass spectrometer to obtain spectral intensity. The atomic ratio is then calculated using the calibration curve described above, and the calculated atomic ratio can be confirmed with an accuracy of within 2 atomic percent of the atomic ratio of the oxide thin film measured separately using a thin-film X-ray fluorescence analyzer or an inductively coupled plasma emission spectrometer.

[0027] In the crystalline oxide thin film according to this embodiment, the crystalline oxide thin film has a low-resistance region A and a high-resistance region B in the planar direction of the crystalline oxide thin film, with different spreading resistance values ​​measured by scanning spreading resistance microscopy (SSRM), and the spreading resistance value R of the low-resistance region A A The extension of the high-resistance region B relative to the resistance value R B Ratio (R B / R A ) is more than 8 times. B / R A The ratio is preferably 10 times or more, and more preferably 15 times or more. B / R A The larger R is, the more sufficient an energy barrier is formed between the low-resistance region A and the high-resistance region B. Therefore, when a crystalline oxide thin film is used as the channel layer of a TFT, the DIBL phenomenon can be suppressed, and the TFT characteristics become more stable. B / R A There is no particular upper limit, but for example, it is 100,000 times or less, and may also be 10,000 times or less. B / R A If the voltage is too large, the energy barrier between the low-resistance region A and the high-resistance region B becomes too large, creating an electron injection barrier when a voltage Vd is applied between the source and drain electrodes, resulting in a decrease in the mobility of the TFT. Note that "high" and "low" in "resistance" refer to the relative levels of the spreading resistance values ​​between region A and region B. Expansion of low-resistance region A: Resistance value R A Ω is 1Ω or more, 1 × 10 6 A value of Ω or less is preferable.

[0028] The low-resistance region A can be formed by reducing the resistance of a target portion of a crystalline oxide thin film, for example, by heat treatment (annealing), plasma treatment, or ion implantation in the presence of indium tin oxide (ITO), indium zinc oxide (IZO), aluminum, etc. The region that is not subjected to the low-resistance treatment becomes the high-resistance region B.

[0029] In one embodiment, the thickness of the crystalline oxide thin film is preferably 80 nm or less. A thickness of 80 nm or less makes it easier for the low-resistance treatment to manifest, and the crystals of the crystalline oxide thin film tend to form columnar single-layer crystals. The thickness of the crystalline oxide thin film is preferably 60 nm or less, more preferably 50 nm or less, and particularly preferably 40 nm or less. On the other hand, the thickness of the crystalline oxide thin film is, for example, 3 nm or more, may be 5 nm or more, or 10 nm or more. By setting the thickness of the crystalline oxide thin film to 3 nm or more, high-quality crystals can be grown without being affected by the substrate during annealing crystallization. In this specification, film thickness is measured based on cross-sectional TEM observation images (sometimes referred to as "cross-sectional TEM images").

[0030] In one embodiment, the dC / dV value measured by a scanning capacitance microscope (SCM) is greater at the boundary between the low-resistance region A and the high-resistance region B than at the dC / dV value of the high-resistance region B. As a result, the carrier concentration changes continuously at the boundary between the low-resistance region A and the high-resistance region B, eliminating the existence of an electrical potential barrier between the source and drain during TFT operation (here, Vg > 0, meaning electrons are accumulated at the interface between the gate insulating film and the channel layer), thus enabling high mobility characteristics. The measurement conditions for SCM will be explained in detail in the examples.

[0031] In one embodiment, it is preferable that the average grain boundary angle θ between the bottom surface of the crystalline oxide thin film and the grain boundaries within the thin film is 70° or more and 110° or less. This prevents the grain boundaries from being too inclined with respect to the electrode surface, even in small TFTs with a short contact region length, and allows for a dense arrangement of grain boundaries along the length of the contact region. As a result, the TFT having the crystalline oxide thin film according to this embodiment exhibits better mobility.

[0032] The average grain boundary angle θ between the thin film surface and the grain boundaries within the thin film is measured based on cross-sectional TEM observation images (sometimes referred to as "cross-sectional TEM images"). Specifically, it is calculated by analyzing the angle between the grain boundaries observed by a cross-sectional TEM, which is observed under magnification using a transmission electron microscope, and the thin film surface.

[0033] In one embodiment, it is preferable that the average spacing D between grain boundaries in the crystalline oxide thin film is 0.01 μm or more and 2.0 μm or less. As a result, the small TFT having the crystalline oxide thin film according to this embodiment exhibits high mobility and uniform characteristics of mobility and threshold voltage (Vth) with respect to the device shape. Consequently, when the TFT is incorporated into a circuit and used to drive a display, a high-definition display can be realized without brightness unevenness or afterimages. The average spacing D between grain boundaries in a thin film is measured based on cross-sectional TEM observation images. The measurement conditions are described in detail in the examples.

[0034] In one embodiment, the crystalline oxide thin film contains crystal grains that have a bixbite structure in electron diffraction. Because the crystal grains with a bixbite structure have a well-symmetrical cubic crystal structure, the decrease in TFT properties (mobility) can be suppressed even when crossing crystal grain boundaries.

[0035] (2) Second embodiment of crystalline oxide thin film The crystalline oxide thin film of this embodiment is a crystalline oxide thin film mainly composed of In, with a film thickness of 80 nm or less. The crystalline oxide thin film has a high carrier concentration region A and a low carrier concentration region B in the plane direction, with the carrier concentration of the high carrier concentration region A being 10 19 cm -3 The above 10 22 cm -3The carrier concentration in the high-carrier concentration region A is 8 times or more than the carrier concentration in the low-carrier concentration region B. Preferably it is 10 times or more, more preferably 15 times or more, and even more preferably 100 times or more. By increasing the difference in carrier concentration, an energy barrier is formed between the low-resistivity region and the high-resistivity region, making the DIBL phenomenon less likely to occur when applied to and driven in the channel of a TFT, and resulting in stable TFT characteristics.

[0036] In this embodiment, the crystalline oxide thin film is defined by a high carrier concentration region A and a low carrier concentration region B, instead of the low-resistance region A and high-resistance region B of the crystalline oxide thin film in the first embodiment. The high carrier concentration region A corresponds to the low-resistance region A, and the low carrier concentration region B corresponds to the high-resistance region B.

[0037] In this embodiment, the thickness of the crystalline oxide thin film is 80 nm or less. A thickness of 80 nm or less makes it easier for the low-resistance treatment to manifest, and also tends to result in the crystalline oxide thin film forming columnar single-layer crystals. Similar to the first embodiment, the thickness of the crystalline oxide thin film is preferably 60 nm or less, more preferably 50 nm or less, and particularly preferably 40 nm or less. On the other hand, the thickness of the crystalline oxide thin film may be, for example, 3 nm or more, 5 nm or more, or 10 nm or more.

[0038] Furthermore, the carrier concentration in the high carrier concentration region A is 10 19 cm -3 The above 10 22 cm -3 The following is 10 19 cm -3 The above 10 21 cm -3 The following is preferable. This ensures that the conductivity in the low-resistance region is sufficiently high, and when used in a crystalline oxide thin film below the source and drain electrodes of a self-aligned TFT, and in a crystalline oxide thin film located between the intersection of a perpendicular line drawn in the thickness direction from the end of the gate electrode to the end of the gate electrode and the crystalline oxide thin film, it does not become a resistive component during TFT driving, enabling the realization of a high-mobility TFT.

[0039] In one embodiment, the carrier concentration in the low carrier concentration region B is 10 15 cm -3 The above 10 19 cm -3 It is preferable that it be less than [value]. As a result, when a low carrier concentration region B is used in the gate electrode and the crystalline oxide thin film region beneath the gate insulating film of a self-aligned TFT, Vth approaches 0V in the Id-Vg curve when Vd=0.1V is applied and the TFT is driven, showing good normally-off characteristics. The carrier concentration can be determined by Hall effect measurement, as described in the examples.

[0040] The constituent elements, manufacturing method, preferred range, etc., of the crystalline oxide thin film according to this embodiment are the same as those of the first embodiment. Furthermore, although the crystalline oxide thin film of the first embodiment is described for the laminates, TFTs, electronic circuits, electrical equipment, electronic equipment, vehicles, and power engines described later, these can also be applied to the second embodiment. Specifically, by replacing the low-resistance region A with the high-carrier-concentration region A and the high-resistance region B with the low-carrier-concentration region B, an example of application of the second embodiment can be obtained.

[0041] (3) Third embodiment of crystalline oxide thin film The crystalline oxide thin film of this embodiment is a crystalline oxide thin film mainly composed of In, with a film thickness of 80 nm or less, an average spacing D between grain boundaries of the crystalline oxide thin film of 2 μm or less, and a carrier concentration of 10 19 cm -3 The above 10 22 cm -3 The following applies: The crystalline oxide thin film of this embodiment has a high carrier concentration region A of the crystalline oxide thin film of the second embodiment. The constituent elements, manufacturing method, preferred range, etc. of the crystalline oxide thin film according to this embodiment are the same as those of the first and second embodiments.

[0042] 2. Laminate The laminate according to this embodiment comprises a crystalline oxide thin film according to the above-described embodiment and a lower layer supporting the crystalline oxide thin film. Figure 1 is a schematic cross-sectional view of an example of a laminate according to this embodiment. The laminate 10 has a crystalline oxide thin film 11 and a lower layer 12 that supports the crystalline oxide thin film 11. The crystalline oxide thin film 11 has one high-resistance region B (11B) in the planar direction and two low-resistance regions A (11A) that sandwich the high-resistance region B (11B).

[0043] In this embodiment, the crystalline oxide thin film and laminate only need to have a high-resistance region B and a low-resistance region A in the crystalline oxide thin film; other configurations are not limited. Figure 2 is a schematic cross-sectional view of another example of the laminate according to this embodiment. The laminate 20 has a crystalline oxide thin film 11 and a lower layer 12 that supports the crystalline oxide thin film 11. In the laminate 20, the crystalline oxide thin film 11 is formed with alternating high-resistance regions B (11B) and low-resistance regions A (11A) in the planar direction.

[0044] In laminates 10 and 20, the lower layer 12 is a single layer, but is not limited to this, and may be a laminate of two or more layers. Examples of the lower layer 12 include a substrate, buffer layer, insulating layer, electrode, light shield layer, etc. Each of these may be composed of two or more layers.

[0045] In the laminate according to this embodiment, the average grain boundary angle θ is formed between the surface of the lower layer and the grain boundaries in the crystalline oxide thin film. sub It is preferable that the angle is 70° or more and 110° or less. The average grain boundary angle θ is formed between the surface of the lower layer and the grain boundaries in the crystalline oxide thin film. sub By satisfying the above range, grain boundaries can be densely present on the surface of the lower layer in contact with the crystalline oxide thin film. As a result, when the crystalline oxide thin film is in contact with an electrode (e.g., a source electrode) as a lower layer, grain boundaries will be densely present on the electrode surface. Consequently, even when the contact area with the electrode is narrow (e.g., a small TFT), electron injection into the crystalline oxide thin film can be ensured, and a decrease in mobility can be suppressed.

[0046] (Method for manufacturing crystalline oxide thin films and laminates) The crystalline oxide thin film of this embodiment and the laminate containing the crystalline oxide thin film can be manufactured by depositing a thin film mainly composed of In oxide on a substrate, buffer layer, insulating layer, or other lower layer constituting a TFT, and then performing the low-resistance treatment described above on a desired portion. The film deposition method is not particularly limited, but examples include DC sputtering, AC sputtering, RF sputtering, ICP sputtering, reactive sputtering, ion plating, ALD, PLD, MO-CVD, ICP-CVD, sol-gel method, coating method, and mist CVD. When film deposition is performed by sputtering, the film deposition may be performed using a planar sputtering cathode apparatus or a rotary sputtering cathode apparatus.

[0047] One example of a film formation method is to form a film by DC sputtering using a sputtering target containing an oxide sintered body mainly composed of In oxide, and then to perform the low-resistance treatment described above on the desired portion. The atomic composition ratio of a crystalline oxide thin film obtained by sputtering reflects the atomic composition ratio of the oxide sintered body in the sputtering target. Therefore, it is preferable to deposit the film using a sputtering target containing an oxide sintered body having an atomic composition ratio similar to that of the desired oxide thin film.

[0048] Furthermore, heat treatment may be performed after the thin film is formed but before the resistance reduction treatment. The heat treatment process is not particularly limited, but a hot air furnace, IR furnace, lamp annealing apparatus, laser annealing apparatus, thermal plasma apparatus, etc., can be used. Furthermore, after annealing, plasma oxidation treatment with N2O or O2 may be performed before the resistance reduction treatment. The apparatus for plasma oxidation treatment is not particularly limited, but examples include PE-CVD.

[0049] The target used in the sputtering method preferably contains 500 ppm or less of impurity metals, and more preferably 100 ppm or less. The content of impurity metals in the target can be measured by ICP or SIMS, similar to crystalline oxide thin films. "Impurities" contained in the target refer to trace elements that are introduced during the raw material or manufacturing process, not intentionally added, and that do not substantially affect the performance of the target and semiconductor. "Impurity metals" refer to metallic elements among the elements considered as "impurities."

[0050] In this embodiment, the sputtering target may consist substantially of In and elements selected from Mg, Al, Si, Zn, Ga, Mo, Sn, Ln (lanthanide elements) and O. Here, "substantially" means that the sputtering target may contain other components in addition to In, to the extent that the effects of the present invention resulting from combinations of Mg, Al, Si, Zn, Ga, Mo, Sn, Ln, and O occur.

[0051] Similar to the crystalline oxide thin film of the present invention described above, in this embodiment, a more preferred first form of the sputtering target is an oxide in which the metallic elements are In and Ga, and the atomic ratio satisfies the following formula (11). [Ga] / ([In]+[Ga])<22at% (11)

[0052] A more preferred second form of the sputtering target is an oxide consisting of In as a metallic element and one or more elements X selected from B, Al, Sc, Mg, Zn, Ti, Y, Zr, Mo, Sn, Hf, W, Nb, Ta, Ge, Si, La, Ce, Pr, Nd, Sm, Dy, Ho, Er, Tm, Yb, and Lu, wherein the atomic ratio satisfies the following formula (12) when X is a metallic element other than In. [X] / ([In]+[X])<15at% (12)

[0053] A more preferred third form of the sputtering target is an oxide comprising In, Ga, and one or more elements X selected from B, Al, Sc, Mg, Zn, Ti, Y, Zr, Mo, Sn, Hf, W, Nb, Ta, Ge, Si, La, Ce, Pr, Nd, Sm, Dy, Ho, Er, Tm, Yb, and Lu as metallic elements, wherein when a metallic element other than In and Ga is used as the additive element X, the atomic ratio satisfies the following formulas (13) and (14). [Ga] / ([In]+[Ga]+[X])<22.5at% (13) [X] / ([In]+[Ga]+[X])<8.0at% (14)

[0054] A more preferred fourth form of the sputtering target is an oxide comprising In, Sn, and one or more elements X selected from B, Al, Sc, Mg, Zn, Ti, Y, Zr, Mo, Hf, W, Nb, Ta, Ge, Si, La, Ce, Pr, Nd, Sm, Dy, Ho, Er, Tm, Yb, and Lu as metallic elements, wherein the atomic ratios satisfy the following formulas (15) and (16) when element X is a metallic element other than In and Sn. [Sn] / ([In]+[Sn]+[X])<20at% (15) [X] / ([In]+[Sn]+[X])<8.0at% (16)

[0055] A more preferred fifth form of the sputtering target is an oxide comprising In, Zn, and one or more elements X selected from B, Al, Sc, Mg, Ti, Y, Zr, Mo, Hf, W, Nb, Ta, Ge, Si, La, Ce, Pr, Nd, Sm, Dy, Ho, Er, Tm, Yb, and Lu as metallic elements, wherein the atomic ratios satisfy the following formulas (17) and (18) when element X is a metallic element other than In and Zn. [Zn] / ([In]+[Zn]+[X])<12at% (17) [X] / ([In]+[Zn]+[X])<8.0at% (18)

[0056] An amorphous oxide thin film is obtained by sputtering using a sputtering target primarily composed of indium oxide. By patterning this oxide thin film in an island pattern using photolithography and then heating it to crystallize it before forming a protective film, a crystalline oxide thin film can be obtained in which the surface crystals have a single crystal orientation. The following describes each step.

[0057] (Oxide thin film formation process) In the oxide thin film deposition process, the oxide thin film is deposited by sputtering using the sputtering target described above and one or more gases selected from the group consisting of argon and oxygen that are substantially free of impurity gases. In this process, it is preferable to mount the sputtering target on an RF magnetron sputtering apparatus or a DC magnetron sputtering apparatus and perform sputtering.

[0058] The statement that a sputtering gas is "substantially free of impurity gases" means that, apart from the introduction of adsorbed water during gas insertion and unavoidable gases such as chamber leaks and adsorbed gases (unavoidable impurity gases), no impurity gases other than the sputtering gas are actively introduced. If possible, it is preferable to remove impurities from the gas introduced during sputtering film deposition (sputtering gas).

[0059] The proportion of impurity gas in the sputtering gas is preferably 0.1 volume% or less, and more preferably 0.05 volume% or less. If the proportion of impurity gas is 0.1 volume% or less, the crystallization of the oxide thin film proceeds without problems. The purity of high-purity argon and high-purity oxygen, which are examples of sputtered gases, is preferably 99% by volume or higher, more preferably 99.9% by volume or higher, and even more preferably 99.99% by volume or higher.

[0060] The gas introduced during sputtering deposition (sputtering gas) is not particularly limited, but examples include argon, nitrogen, oxygen, water, hydrogen, or a mixed gas containing two or more of these gases. As an example, when using argon and oxygen, the partial pressure of oxygen in the mixed gas is preferably greater than 0 vol% and 50 vol% or less, and more preferably greater than 0 vol% and 20 vol% or less. If the partial pressure of oxygen is greater than 0 vol% and 50 vol% or less, crystallization and semiconductor formation will occur easily upon heating. By changing the partial pressure of oxygen, the degree of oxidation of the oxide thin film, i.e., the degree of crystallization, can be adjusted. The partial pressure of oxygen should be selected as appropriate as needed. As an example, when using argon and water, the moisture content in the mixed gas is preferably more than 0.03% by volume and 10% by volume or less, and more preferably more than 0.03% by volume and 5% by volume or less. If the moisture content is more than 0.03% by volume and 5% by volume or less, crystallization and semiconductor formation will occur easily upon heating. Alternatively, a mixed gas of hydrogen and oxygen may be used instead of water.

[0061] The crystalline oxide thin film according to this embodiment preferably has In as its main component. By heating this oxide thin film in a heat treatment process described later, columnar crystals can be grown in the lower layer. By applying the oxide thin film formed as described above to a small TFT, excellent electron carrier injection is achieved during operation, resulting in high mobility, and uniform characteristics of mobility and threshold voltage (Vth) with respect to the device shape are obtained.

[0062] (Formation process of the constituent layers of a TFT) When forming a TFT constituent layer, such as an insulating layer, on a crystalline oxide thin film, it is preferable to heat-treat the obtained oxide thin film before forming the constituent layer on the oxide thin film. By performing annealing before forming the TFT constituent layer, oxygen and hydrogen diffuse during annealing, resulting in high-quality columnar crystals, and after the formation of the constituent layer, a compact TFT with fewer interfacial electron trap levels and high mobility can be obtained.

[0063] (Heat treatment process) After depositing the oxide thin film, a heat treatment is performed. This heat treatment is sometimes called annealing. The heat treatment temperature is preferably 250°C or higher and 500°C or lower, more preferably 280°C or higher and 470°C or lower, and even more preferably 300°C or higher and 450°C or lower. If the heat treatment temperature after deposition of an oxide thin film is 250°C or higher, the oxide thin film is more likely to crystallize. If the heat treatment temperature after deposition of an oxide thin film is 500°C or lower, abnormal crystal growth and enlarged grain size can be prevented, and the grain size can be controlled to be small.

[0064] The heating time in the heat treatment process is preferably 0.1 hours or more and 5 hours or less, more preferably 0.3 hours or more and 3 hours or less, and even more preferably 0.5 hours or more and 2 hours or less. If the heating time in the heat treatment process is 0.1 hours or longer, crystallization will not fail, and the oxide thin film is more likely to crystallize. If the heating time in the heat treatment process is 5 hours or less, it is more cost-effective. "Heating time" refers to the time (holding time) during which the predetermined maximum temperature is maintained during heat treatment.

[0065] The heating rate in the heat treatment process is preferably 2°C / min or more and 40°C / min or less, and more preferably 3°C / min or more and 20°C / min or less. If the heating rate in the heat treatment process is 2°C / min or higher, the manufacturing efficiency of oxide thin films is improved compared to when it is less than 1°C / min. If the heating rate in the heat treatment process is 40°C / min or less, the metal elements will diffuse uniformly during crystallization, and crystals will be formed without metal segregation at the grain boundaries. Furthermore, the heating rate during the heat treatment process differs from the value calculated from the furnace's set temperature and time; it is the actual temperature of the oxide thin film divided by time. The actual temperature of the oxide thin film can be determined, for example, by measuring the temperature of an area within 1 cm of the oxide thin film inside the furnace using a thermocouple.

[0066] The heat treatment process is preferably carried out in an atmospheric environment with a humidity of 10% or higher at 25°C. Maintaining an atmospheric environment with a humidity of 10% or higher during the heat treatment process allows hydrogen and oxygen to diffuse into the film during annealing, thereby promoting crystallization.

[0067] The heat treatment process is preferably carried out after patterning the oxide thin film. Performing the heat treatment after patterning allows for the removal of excess oxygen present in the film during deposition and organic matter that adheres during patterning, while promoting crystallization. As a result, a film can be formed that is free of organic matter and excess oxygen within the crystal grains and has few crystal defects, resulting in an oxide thin film with fewer electron traps and good conductivity.

[0068] Crystal defects in films after heat treatment can be evaluated by defect analysis, such as cathodoluminescence (CL). When there are many oxygen-derived defects, strong emission of light at 680 nm is detected. To obtain oxide thin films with few electron traps and good conductivity, it is necessary to adjust the film deposition method and annealing conditions so that the film quality is such that emission by CL is hardly detected.

[0069] The heat treatment process may be performed multiple times. For example, the heat treatment process described above (first heat treatment process) may be performed after patterning the oxide thin film, and then, after fabricating the TFT element, a final heat treatment process (second heat treatment process) may be performed. The second heat treatment process is preferably performed at a higher annealing temperature than the first heat treatment process.

[0070] (Resistance reduction process) Low-resistance region A and high-resistance region B are formed in the crystalline oxide thin film obtained in the heat treatment process. Low-resistance region A is not particularly limited, but can be formed by reducing the resistance of a target part of the crystalline oxide thin film by methods such as heat treatment (annealing) in the presence of indium tin oxide (ITO), aluminum, etc., plasma treatment, or ion implantation. The region that is not subjected to the low-resistance treatment becomes high-resistance region B.

[0071] When forming a low-resistance region A by annealing in the presence of ITO, an ITO layer is formed on the crystalline oxide thin film of the region to be made low-resistance by sputtering or the like, and then annealed at a temperature of 250°C or higher and 500°C or lower (preferably 280°C or higher and 470°C or lower, more preferably 300°C or higher and 450°C or lower) for a period of 0.1 hours or more and 5 hours or less. After annealing, the ITO layer may be removed by etching, or it may be left in place.

[0072] When forming a low-resistance region A by annealing in the presence of aluminum, an aluminum layer is formed on the crystalline oxide thin film of the region to be made low-resistance by sputtering or the like, and then annealed at a temperature of 250°C or higher and 500°C or lower (preferably 280°C or higher and 470°C or lower, more preferably 300°C or higher and 450°C or lower) for a period of 0.1 hours or more and 5 hours or less. After annealing, the material may remain as aluminum or as aluminum oxide. In either case, the aluminum or aluminum oxide layer may be removed by etching, or it may be left as is.

[0073] When forming a low-resistance region A by plasma treatment, the treatment is applied to a crystalline oxide thin film obtained in the heat treatment process. The gas used for plasma treatment is not particularly limited, but examples include H2, He, Ar, N2, and F-based gases. In general, elements with small ionic radii are preferred for use in plasma treatment. By performing plasma treatment using these elements, oxygen vacancies are created in the crystalline oxide thin film, increasing the carrier concentration and lowering the resistance.

[0074] When forming a low-resistance region A by ion implantation, there are two methods: directly implanting ions into the crystalline oxide thin film obtained in the heat treatment process, or implanting ions through gate insulating films or interlayer insulating films formed on the oxide thin film. The ions used for injection are not particularly limited, but H + He + , B + , N + , F +PHx + Ar + Examples include the following. Any element that causes oxygen vacancies through ion implantation, or an element that releases electrons and acts as a donor when left in the membrane, is acceptable. Furthermore, the element may or may not remain in the membrane.

[0075] In one embodiment, the low-resistance treatment step is preferably performed after the formation of the gate insulating film and / or gate electrode. Specifically, the gate insulating film and / or gate electrode can be used as a mask (self-alignment) to form a low-resistance region A and a high-resistance region B. For example, when using the ITO layer described above, the region where the ITO layer is directly stacked within the crystalline oxide thin film becomes the low-resistance region A, and the lower region of the gate insulating film and / or gate electrode becomes the high-resistance region B.

[0076] 3. Thin-film transistors (TFTs) The TFT according to this embodiment includes the crystalline oxide thin film or laminate of the present invention described above. Preferably, the crystalline oxide thin film of the present invention is used as the channel layer of the TFT. More preferably, the areas on both ends of the channel layer, i.e., the areas where the source electrode and drain electrode are connected, are low-resistance regions A of the crystalline oxide thin film, and the area in contact with the lower surface of the gate insulating film is a high-resistance region B.

[0077] In one embodiment, the TFT has a channel layer, source electrodes and drain electrodes connected to both ends of the channel layer, respectively, and a gate electrode laminated on the channel layer via a gate insulating film. The channel layer is a crystalline oxide thin film, with a gate insulating film formed in a high-resistance region B and source electrodes and drain electrodes formed in a low-resistance region A. The distance L is the distance from the ends of the source electrode and drain electrode to the intersection point of the crystalline oxide thin film with a perpendicular line drawn in the thickness direction from the end of the gate electrode. off However, the size is between 4 μm and 20 μm.

[0078] Furthermore, the average spacing D between grain boundaries in a crystalline oxide thin film and the distance L are also important. offThe following equation (1) is satisfied. 2 ≤ L off / D≦100···(1)

[0079] In one embodiment, the TFT has a contact region length Ls between the source electrode, drain electrode, and channel layer that is 4 μm or more and 20 μm or less. Furthermore, the average spacing D between grain boundaries of the crystalline oxide thin film and the contact region length Ls satisfy the following equation (2). 1 ≤ Ls / D ≤ 100 ···(2) This allows for excellent mobility even with a small contact area between the source electrode, drain electrode, and channel layer.

[0080] Conventional TFTs fabricated using conventional techniques employ crystalline oxide thin films to achieve high mobility. However, when source and drain electrodes were formed on the oxide thin film using a metal mask, the contact region length between the source electrode and the oxide thin film was, for example, about 100 μm. Therefore, even if the grain size of the oxide thin film was 1 μm or larger, there were approximately 100 grain boundaries in the contact region with the source electrode. This meant that a sufficient number of conductive grain boundaries were in contact with the source electrode, and this did not pose a major problem in terms of mobility.

[0081] Furthermore, in conventional technology, parasitic capacitance occurred in the overlapping region between the gate electrode and the source and drain electrodes. However, this was not a major problem because high resolution, high-speed driving, and large area were not required for displays. However, in recent years, displays such as OLEDs have been required to have high resolution, high-speed driving, and large area. In the trend towards higher resolution, the size of the TFT has decreased in order to increase the aperture ratio of the pixel circuit. Therefore, instead of deposition using metal masks as in the past, it is necessary to control the characteristics of small TFTs patterned by photolithography. Furthermore, in the trend towards higher resolution, high-speed driving, and large area displays, it is necessary to reduce parasitic capacitance in the backplane driving circuit to eliminate RC delay, which is the delay in the time from input to driving due to the influence of parasitic resistance and parasitic capacitance, and it is also necessary to minimize the variation in parasitic capacitance as much as possible in order to eliminate brightness unevenness of each pixel in OLEDs.

[0082] To solve these problems simultaneously, a self-aligned TFT structure is effective, in which a region where the semiconductor's resistance is selectively reduced by using the gate electrode as a mask is used as the source and drain regions. When an oxide thin film is applied to a self-aligned and compact TFT structure (self-aligned compact TFT structure), the contact region length between the source electrode and the crystalline oxide thin film is shortened. In addition, the intersection points between the perpendicular lines drawn in the thickness direction from the ends of the gate electrode and the ends of the drain electrode and the crystalline oxide thin film are shortened.

[0083] In order to apply a highly mobile crystalline oxide thin film to a self-aligned miniature TFT structure, achieve sufficient mobility, and stably control the threshold voltage (Vth), it is necessary to have a sufficient number of grain boundaries in the region from the ends of the source electrode and drain electrode to the intersection of the perpendicular line drawn in the thickness direction from the end of the gate electrode and the crystalline oxide thin film, and also to have a sufficient number of grain boundaries in the contact region with the source electrode. According to the TFT of this embodiment, the distance L off Since the contact area length Ls satisfies equations (1) and (2), it offers excellent mobility and can stably control Vth.

[0084] In one embodiment, the horizontal gap ΔL between the low-resistance region A and the gate electrode is less than 1 μm. Since the crystalline oxide thin film of the present invention is suitable for self-aligned TFTs, the gap ΔL can be made extremely small.

[0085] For example, a conventionally known configuration can be used for the TFT configuration according to this embodiment. The TFT according to this embodiment can be manufactured by employing the above-described method for manufacturing the crystalline oxide thin film and laminate. Specifically, the manufacturing method includes a step of depositing an oxide thin film by sputtering using a sputtering target and one or more gases selected from the group consisting of argon, nitrogen, hydrogen, water, and oxygen that are substantially free of impurity gases (sometimes referred to as the film deposition step), and a step of subjecting the oxide thin film to heat treatment (sometimes referred to as the heat treatment step). The conditions for the film deposition step and the heat treatment step are as described above. The source electrode, drain electrode, gate electrode, and gate insulating film can be formed using known materials and formation methods.

[0086] A crystalline oxide thin film according to one embodiment has high mobility in the direction parallel to the film surface. By using such a crystalline oxide thin film in the oxide semiconductor layer (channel layer) or conductive region of a self-aligned miniature TFT, high mobility and stable control of Vth can be achieved. Here, the mobility when Vd = 0.1V is applied is determined as linear mobility, and the mobility when Vd = 20V is applied is defined using saturation mobility as an indicator. Specifically, the mobility can be calculated by creating a transfer characteristic Id-Vg graph when each Vd is applied, calculating the transconductance (Gm) for each Vg, and then determining the mobility using the equations for the linear or saturation region. Current Id is the current between the source and drain electrodes, voltage Vd is the voltage applied between the source and drain electrodes (drain voltage), and voltage Vg is the voltage applied between the source and gate electrodes (gate voltage). Mobility is calculated over 20 cm². 2 It must be (V·s) or higher, and the higher the better.

[0087] Furthermore, in one embodiment of the crystalline oxide thin film, an ohmic electrode such as a metal, ITO, or IZO is placed on one side of the high-resistance region B, and a Schottky electrode such as a metal or oxide with a work function of 4.8 eV or more is placed on the other side, thereby enabling the construction of a Schottky barrier diode, MES-FET, etc.

[0088] The shape of the thin-film transistor according to this embodiment is not particularly limited as long as it is self-aligned, but top-gate transistors, back-channel etch transistors, or etch-stopper transistors are preferred.

[0089] The embodiments will be described below with reference to the drawings and other figures. However, it will be readily apparent to those skilled in the art that the embodiments can be implemented in many different ways, and their form and details can be modified in various ways without departing from the spirit and scope thereof. Accordingly, the present invention shall not be construed as being limited to the contents of the following embodiments.

[0090] In the drawings, the size, layer thickness, and area may be exaggerated for clarity. Therefore, the present invention is not limited to the size, layer thickness, and area shown in the drawings. Furthermore, the drawings schematically represent ideal examples, and the present invention is not limited to the shapes and values ​​shown in the drawings.

[0091] Figure 3A is a schematic cross-sectional view of an example of a TFT according to this embodiment. TFT50 is a top-gate type TFT and has a substrate 21, a buffer layer 22, a channel layer (crystalline oxide thin film) 11, an ITO layer 23, a gate insulating film 24, a gate electrode 25, an interlayer insulating film 26, a source electrode 27, a drain electrode 28, and a protective film 29.

[0092] The TFT50 has a structure in which a substrate 21, a buffer layer 22, and a channel layer (crystalline oxide thin film) 11 are stacked in this order. A high-resistance region 11B is located in the center of the channel layer 11, and a gate insulating film 24 and a gate electrode 25 are stacked on the high-resistance region 11B in this order. The gate insulating film 24 is an insulating film that blocks conductivity between the gate electrode 25 and the crystalline oxide thin film 11. On either side of the high-resistance region 11B are the low-resistance regions 11A-1 and 11A-2 of the channel layer 11. The low-resistance regions 11A-1 and 11A-2 and the gate electrode 25 are covered by an ITO layer 23 and an interlayer insulating film 26. The ITO layer 23 is used to form the low-resistance region of the channel layer 11. The source electrode 27 and drain electrode 28 are connected to low-resistance regions 11A-1 and 11A-2, respectively, via contact holes provided in the ITO layer 23 and the interlayer insulating film 26. The source electrode 27 and drain electrode 28 are conductive terminals for allowing source current and drain current to flow to the channel layer 11. A protective film 29 is provided so as to cover the TFT constituent layers, including the interlayer insulating film 26, the source electrode 27, and the drain electrode 28.

[0093] Figure 3B is a magnified view of the area near the source electrode in Figure 3A. Figure 3B shows the distance L from the end of the source electrode and the end of the drain electrode in the TFT50 to the intersection of the perpendicular line drawn in the thickness direction from the end of the gate electrode and the crystalline oxide thin film. off This diagram illustrates the contact region length Ls between the source electrode (drain electrode) and the channel layer, and the horizontal gap ΔL between the low-resistance region A and the gate electrode.

[0094] Figure 4 is a schematic cross-sectional view of another example of the TFT of this embodiment. TFT51 has the same configuration as TFT50, except that a light shield layer 31 is provided between the substrate 21 and the buffer layer 22. The light shield layer 31 is formed to suppress malfunctions of the TFT caused by light.

[0095] Figure 5 is a schematic cross-sectional view of another example of the TFT of this embodiment. TFT52 has the same configuration as TFT50, except that the ITO layer 23 is not formed. In this example, the low-resistance regions 11A-1 and 11A-2 are formed, for example, by ion implantation or a dry process such as plasma treatment.

[0096] Figure 6 is a schematic cross-sectional view of another example of the TFT of this embodiment. TFT60 has the same configuration as TFT50, except that the ITO layer 23 is not formed and the interlayer insulating film 26 has a two-layer structure (interlayer insulating films 26-1 and 26-2). In this example, the lower region of the gate electrode 25 of the interlayer insulating film 26-1 corresponds to the gate insulating film 24. In this example, the low-resistance regions 11A-1 and 11A-2 are formed, for example, by ion implantation.

[0097] Figure 7 is a schematic cross-sectional view of another example of the TFT of this embodiment. TFT70 is a bottom-gate type TFT and has a substrate 21, a gate electrode 25, a gate insulating film 24, a channel layer (crystalline oxide thin film) 11, an interlayer insulating film 26, a source electrode 27, a drain electrode 28, and a protective film 29.

[0098] In the TFT70, a gate electrode 25 is formed on a substrate 21, and a gate insulating film 24 is laminated on the substrate 21 and the gate electrode 25. A channel layer (crystalline oxide thin film) 11 is stacked on the gate insulating film 24, and the region corresponding to the gate electrode 25 is the high-resistance region 11B, with low-resistance regions 11A-1 and 11A-2 of the channel layer 11 on both sides of the high-resistance region 11B. An interlayer insulating film 26 covers the channel layer (crystalline oxide thin film) 11. The source electrode 27 and the drain electrode 28 are connected to the low-resistance regions 11A-1 and 11A-2, respectively, through contact holes provided in the interlayer insulating film 26. A protective film 29 is provided so as to cover the TFT constituent layers, including the interlayer insulating film 26, the source electrode 27, and the drain electrode 28.

[0099] The TFT in this embodiment can be improved using a known configuration.

[0100] There are no particular restrictions on the material used to form the substrate, and any commonly used material can be arbitrarily selected. For example, glass substrates, ceramic substrates, quartz substrates, and sapphire substrates can be used. It is also possible to use single-crystal semiconductor substrates such as silicon and silicon carbide, polycrystalline semiconductor substrates, compound semiconductor substrates such as silicon germanium, and SiO (Silicon Insulator) substrates, and substrates on which semiconductor elements are provided may also be used as substrates.

[0101] Furthermore, a flexible substrate may be used as the substrate. In addition to directly fabricating the TFT on the flexible substrate, another method for mounting the TFT on the flexible substrate is to fabricate the TFT on a non-flexible substrate, then peel it off and place it on the flexible substrate. In this case, it is preferable to provide a release layer between the non-flexible substrate and the TFT.

[0102] There are no particular restrictions on the material used to form the buffer layer 22; any commonly used material can be arbitrarily selected, and a multilayer film can also be used. For example, SiO2, SiNx, silicon oxynitride, Al2O3, Ta2O5, TiO2, MgO, ZrO2, Ga2O3, GeO2, Nd2O3, La2O3, CeO2, K2O, Li2O, Na2O, Rb2O, Sc2O3, Y2O3, HfO2, CaHfO3, PbTiO3, BaTa2O6, SrTiO3, Sm2O3, and AlN can be used. The oxidation state of each material may vary. The buffer layer 22 can be appropriately designed according to the type of substrate.

[0103] The light shield layer 31 may be connected to the source electrode 27, or it may be connected to the gate electrode 25. There are no particular restrictions on the material used to form the light shield layer; any commonly used material can be arbitrarily selected. Specifically, examples include metal electrodes made of Al, Ag, Cu, Cr, Ni, Co, Mo, Au, Ti, Zr, Ru, Y, Nb, Ta, W, etc., and metal electrodes made of alloys containing two or more of these metals. Furthermore, multilayer electrodes with two or more layers can also be used.

[0104] A second buffer layer may be placed between the light shield layer 31 and the substrate 21. There are no particular restrictions on the material used to form the second buffer layer; any commonly used material can be arbitrarily selected, and a multilayer film can be used. For example, SiO2, SiNx, silicon oxynitride, Al2O3, Ta2O5, TiO2, MgO, ZrO2, Ga2O3, GeO2, Nd2O3, La2O3, CeO2, K2O, Li2O, Na2O, Rb2O, Sc2O3, Y2O3, HfO2, CaHfO3, PbTiO3, BaTa2O6, SrTiO3, Sm2O3, and AlN can be used. The oxidation state of each material may vary.

[0105] There are no particular restrictions on the material used to form the gate insulating film; any commonly used material can be arbitrarily selected, and multilayer films can also be used. For example, SiO2, SiNx, silicon oxynitride, Al2O3, Ta2O5, TiO2, MgO, ZrO2, Ga2O3, GeO2, Nd2O3, La2O3, CeO2, K2O, Li2O, Na2O, Rb2O, Sc2O3, Y2O3, HfO2, CaHfO3, PbTiO3, BaTa2O6, SrTiO3, Sm2O3, and AlN can be used. The oxidation state of each material may vary.

[0106] In this embodiment, when the TFT is a small TFT, the crystalline oxide thin film serving as a channel layer for the source electrode and drain electrode has a channel length (L) of 1 μm or more and 50 μm or less. The channel width is not particularly limited, but for example, the channel width (W) is 1 μm or more and 1000 μm or less.

[0107] There are no particular restrictions on the materials used to form the drain electrode, source electrode, and gate electrode; commonly used materials can be arbitrarily selected. Specifically, examples include transparent electrodes such as ITO, IZO, ZnO, and SnO2; metal electrodes such as Al, Ag, Cu, Cr, Ni, Co, Mo, Au, Ti, Zr, Ru, Y, Nb, Ta, and W; and metal electrodes made of alloys containing two or more of these metals. Furthermore, multilayer electrodes with two or more layers can also be used.

[0108] There are no particular restrictions on the materials used to form each interlayer insulating film; commonly used materials can be arbitrarily selected, and multilayer films can also be used. For example, SiO2, SiN x Silicon oxide nitride, Al2O3, Ta2O5, TiO2, MgO, ZrO2, Ga2O3, GeO2, Nd2O3, La2O3, CeO2, K2O, Li2O, Na2O, Rb2O, Sc2O3, Y2O3, HfO2, CaHfO3, PbTiO3, BaTa2O6, SrTiO3, Sm2O3, and AlN can be used. Note that the oxidation state of each material may vary.

[0109] Regardless of the TFT structure, it is preferable to provide an interlayer insulating film on the drain electrode, source electrode, and conductive region. Furthermore, in the case of a bottom-gate type, it is preferable to provide a protective film on the channel layer. Providing a protective film improves the durability of the TFT even when it is operated for a long time.

[0110] The method for fabricating the buffer layer, gate insulating film, interlayer insulating film, and protective insulating film is not particularly limited. Examples of fabrication methods include PE-CVD, ALD, PLD, MO-CVD, RF sputtering, ICP sputtering, reactive sputtering, ICP-CVD, ion plating, sol-gel method, coating method, and mist CVD. In addition to silane (SiH4), tetraethoxysilane (TEOS) can also be used as the gas species for PE-CVD.

[0111] For example, when forming by PE-CVD, the process may involve high temperatures. Furthermore, protective or insulating films often contain impurity gases immediately after deposition, making heat treatment (annealing) preferable. Removing impurity gases through heat treatment results in a stable protective or insulating film, making it easier to form highly durable TFTs. Additionally, annealing after gate insulating film formation allows hydrogen contained in the gate insulating film to diffuse into the oxide thin film, terminating crystal defects on the oxide thin film surface with hydroxyl groups. As a result, an oxide thin film with fewer electron traps and good conductivity can be formed.

[0112] By using the crystalline oxide thin film of the present invention, the effects of temperature in the PE-CVD process and subsequent heat treatment become less pronounced, thus improving the stability of TFT properties even when a protective film or insulating film is formed.

[0113] The threshold voltage (Vth) is preferably -3.0V or higher and 3.0V or lower, more preferably -2.0V or higher and 2.0V or lower, and even more preferably -1.0V or higher and 1.0V or lower. When the threshold voltage (Vth) is -3.0V or higher and 3.0V or lower, it is possible to correct Vth to 0V by equipping the TFT with a Vth correction circuit. When the resulting TFT is mounted on a panel, the display can be driven without brightness unevenness or burn-in.

[0114] The threshold voltage (Vth) is obtained from the transfer characteristic graph when Id = 10 -9 It can be defined by Vg at A. The on-off ratio is 10. 6 The above 10 12 The following is preferable: 10 7 The above 10 11 The following is more preferable: 10 8 The above 10 10 The following is even more preferable: an on-off ratio of 10 6 The above conditions allow the LCD display to be driven. The on-off ratio is 10. 12 The following conditions allow for the driving of high-contrast organic EL elements. Also, the on-off ratio is 10 12 If the following conditions are met, the off-current is 10 -12 It can be reduced to A or less, and when used in the transfer transistors or reset transistors of a CMOS image sensor, it can increase the image retention time and improve sensitivity.

[0115] The on-off ratio can be determined by setting the value of Id at Vg = -10V as the off current value and the value of Id at Vg = 20V as the on current value, and then determining the ratio [on current value / off current value]. The OFF current value is 10 -10A or less is preferable, 10 -11 A or less is more preferable, 10 -12 A or less is even more preferable. Off current value is 10 -10 A value of A or less allows for the driving of high-contrast organic EL displays. Furthermore, when used in the transfer transistors or reset transistors of a CMOS image sensor, it can extend the image retention time and improve sensitivity.

[0116] The TFT according to this embodiment can be suitably used in display elements such as solar cells, liquid crystal elements, organic electroluminescent elements, and inorganic electroluminescent elements, as well as in electronic devices such as power semiconductor elements and touch panels.

[0117] The thin-film transistor according to this embodiment can be applied to various integrated circuits such as field-effect transistors, logic circuits, memory circuits, and differential amplifier circuits, and these can be applied to electronic devices and the like. Furthermore, the thin-film transistor according to this embodiment can be applied not only to field-effect transistors but also to electrostatic-induced transistors and Schottky barrier transistors. The thin-film transistor according to this embodiment can be suitably used in display devices such as portable or in-vehicle display devices and solid-state image sensors. Furthermore, the thin-film transistor according to this embodiment can also be suitably used as a transistor for a flat panel detector for X-ray image sensors in medical applications. Furthermore, the crystalline oxide thin film according to this embodiment can also be used in Schottky diodes, resistive random-access memory, and resistive elements. The following describes the case in which the thin-film transistor according to this embodiment is used in a display device.

[0118] Figure 8A is an example of a pixel circuit diagram when liquid crystal elements are used. When this is used in a Mini LED display, Figure 8A can be used not only for the liquid crystal control circuit but also for the LED chip control circuit. Figure 8B is an example of a pixel circuit diagram when organic EL elements are used.

[0119] The pixel circuitry can be applied to configurations where a single pixel has multiple pixel electrodes. Each pixel electrode is connected to a different transistor, and each transistor is configured to be driven by a different gate signal. This allows for independent control of the signals applied to individual pixel electrodes in a multi-domain designed pixel.

[0120] At least one of the transistors in the circuit diagram must be a TFT according to this embodiment. This makes it possible to provide a highly reliable display device. The circuit diagram is not limited to the configuration shown in Figures 8A and 8B. For example, switches, resistors, capacitives, transistors, sensors, or logic circuits may be added. Furthermore, in a display device using the TFT according to this embodiment, both Si-based transistors and the TFT of this embodiment may be incorporated.

[0121] Figure 8C is a top view of the display device according to this embodiment. The transistors placed in the pixel section can be the thin-film transistors according to this embodiment. Since the thin-film transistors according to this embodiment can easily be made into n-channel type transistors, a part of the drive circuit, which can be made up of n-channel type transistors, is formed on the same substrate as the transistors in the pixel section. By using the thin-film transistors shown in this embodiment for the pixel section and the drive circuit, a highly reliable display device can be provided.

[0122] Figure 8C shows an example of a top view of an active-matrix display device. A pixel section 301, a first scan line drive circuit 302, a second scan line drive circuit 303, and a signal line drive circuit 304 are formed on the substrate 300 of the display device. Multiple signal lines are arranged in the pixel section 301, extending from the signal line drive circuit 304, and multiple scan lines are arranged extending from the first scan line drive circuit 302 and the second scan line drive circuit 303. Pixels, each having a display element, are arranged in a matrix at the intersection regions of the scan lines and signal lines. The substrate 300 of the display device is connected to a timing control circuit (also called a controller or control IC) via a connection part such as an FPC (Flexible Printed Circuit).

[0123] In Figure 8C, the first scan line drive circuit 302, the second scan line drive circuit 303, and the signal line drive circuit 304 are formed on the same substrate 300 as the pixel unit 301. Therefore, the number of externally provided drive circuits and other components is reduced, thus reducing costs. Furthermore, if the drive circuits are provided outside the substrate 300, it becomes necessary to extend the wiring, increasing the number of connections between the wires. By providing the drive circuits on the same substrate 300, the number of connections between the wires can be reduced, improving reliability or yield. [Examples]

[0124] The present invention will be described in detail below based on examples. The present invention is not limited to these examples.

[0125] [Manufacturing of self-aligned top-gate structured miniature TFTs] Example 1 The thin-film transistor (TFT) 53 shown in Figure 9 was manufactured by the following process. Note that TFT 53 has the same configuration as TFT 50 shown in Figure 3A, except that it lacks the protective layer 29. (1) Formation of buffer layer 22 A 300 nm thick SiOx layer (buffer layer 22) was formed by sputtering on a 4-inch diameter alkali-free glass substrate 21 (Corning EAGLE XG) using an SiO2 sputtering target. The sputtering conditions were as follows: Substrate temperature: 25℃ Ultimate pressure: 8.5×10 -5 Pa Atmospheric gas: Ar Sputtering pressure (total pressure): 0.4 Pa Input voltage: RF300W Distance between S (substrate) and T (target): 70mm

[0126] (2) Formation of oxide thin film Next, a channel layer was formed by sputtering using an oxide sputtering target obtained from a raw material mixture with the composition ratios shown in Table 1. The metal composition ratios (unit: at%) in the oxide sputtering target are shown in Table 1. Table 1 shows the film deposition conditions and channel layer thickness for sputtering. Sputtering conditions other than those listed in Table 1 are as follows: Substrate temperature: 25℃ Ultimate pressure: 1.0×10 -4 Pa Atmosphere gas: A mixture of Ar and H2O Sputtering pressure (total pressure): 0.5 Pa Input voltage: DC300W Distance between S (substrate) and T (target): 70mm

[0127] (3) Formation of channel layer 11 Next, the oxide thin film was patterned in an island pattern by photolithography to form a channel layer 11. First, a photoresist film was formed on the oxide thin film. AZ1500 (manufactured by AZ Electronic Materials) was used as the photoresist. (10+L) offExposure was performed through a photomask having a pattern formed with dimensions of (×2 + Ls×2 + 2 (both ends) ×2) μm in width × 20 μm in length. After exposure, development was performed with tetramethylammonium hydroxide (TMAH). After development, the oxide thin film was etched with oxalic acid (ITO-06N manufactured by Kanto Chemical Co., Inc.). After etching, the photoresist was peeled off to obtain a substrate 21 with a patterned oxide thin film (channel layer 11). The dimensions of the obtained channel layer 11 are width (10 + L off ×2 + Ls×2 + 2 (both ends) ×2) μm × 20 μm in length.

[0128] (4) Annealing Next, the substrate 21 with the channel layer 11 formed thereon was placed in a furnace, heated to 350°C at a rate of 10°C / min in the atmosphere, and then held for 1 hour. After holding the inside of the furnace at 350°C for 1 hour, it was allowed to cool naturally. After the internal temperature of the furnace returned to room temperature, the substrate 21 was taken out of the furnace.

[0129] (5) Film formation of gate insulating film 24 Next, sputtering was performed using a SiO2 sputtering target to form a SiOx layer (gate insulating film 24) with a thickness of 10 nm. The sputtering conditions are as follows. Substrate temperature: 25°C Ultimate pressure: 8.5×10 -5 Pa Atmosphere gas: mixed gas of Ar + O2 (O2 flow rate 30%) Sputtering pressure (total pressure): 0.4 Pa Applied power: RF 100 W Distance between S (substrate) and T (target): 70 mm

[0130] (6) Annealing of gate insulating film 24 Next, the substrate 21 was placed in a furnace, heated to 400°C at a rate of 10°C / min in the atmosphere, and then held for 1 hour. After holding the inside of the furnace at 400°C for 1 hour, it was allowed to cool naturally. After the temperature in the furnace returned to room temperature, the substrate 21 was taken out of the furnace.

[0131] (7) Film formation of gate insulating film 24 Next, a 100 nm thick SiOx layer (gate insulating film 24) was formed by sputtering using an SiO2 sputtering target. The sputtering conditions were as follows: Substrate temperature: 25℃ Ultimate pressure: 8.5×10 -5 Pa Atmosphere gas: Ar + O2 mixed gas (O2 flow rate 30%) Sputtering pressure (total pressure): 0.4 Pa Input voltage: RF100W Distance between S (substrate) and T (target): 70mm As a result, the total thickness of the gate insulating film 24 became 110 nm.

[0132] (8) Formation of gate electrode 25 Next, a 150 nm thick Mo film was deposited using a Mo sputtering target. The sputtering conditions were as follows: Substrate temperature: 25℃ Ultimate pressure: 8.5×10 -5 Pa Atmospheric gas: Ar Sputtering pressure (total pressure): 0.4 Pa Input voltage: DC100W Distance between S (substrate) and T (target): 70mm

[0133] (9) Patterning of gate electrode 25 and gate insulating film 24 Next, the Mo film and gate insulating film 24 were patterned in an island pattern by photolithography. First, a photoresist film was formed on the channel layer. AZ1500 (manufactured by AZ Electronic Materials) was used as the photoresist. Exposure was performed through a photomask with a pattern of 10 μm x 28 μm size. After exposure, development was performed with tetramethylammonium hydroxyl (TMAH). After development, the Mo film was etched with PAN (a mixed acid of phosphoric acid, nitric acid, and acetic acid) to form the gate electrode 25. Next, the gate insulating film 24 was etched with buffered hydrofluoric acid (BHF) and patterned in an island-like manner. Next, after removing the photoresist, the exposed channel layer 11 was etched to a thickness of 10 nm using oxalic acid (ITO-06N, manufactured by Kanto Chemical Co., Ltd.) and then cleaned. The dimensions of the obtained gate electrode layer 25 and gate insulating film 24 were 10 μm in width and 28 μm in height.

[0134] (9) Resistance reduction treatment Low-resistance regions A (11A-1, 11A-2) were formed in the channel layer 11 by self-alignment using the gate electrode 25. A 2nm thick ITO layer 23 was formed using an ITO sputtering target. The sputtering conditions were as follows: Substrate temperature: 25℃ Ultimate pressure: 8.5×10 -5 Pa Atmosphere gas: Ar + O2 mixed gas (O2 flow rate 2%) Sputtering pressure (total pressure): 0.4 Pa Input voltage: DC100W Distance between S (substrate) and T (target): 70mm

[0135] Next, the substrate 21 was placed in a furnace and heated to 350°C in air at a rate of 10°C / min, then held for 1 hour for annealing. After maintaining the furnace temperature at 350°C for 1 hour, it was allowed to cool naturally. After the furnace temperature returned to room temperature, the substrate 21 was removed from the furnace.

[0136] (10) Formation of interlayer insulating film 26 Next, a 150 nm thick SiOx layer (interlayer insulating film 26) was formed by sputtering using an SiO2 sputtering target. The sputtering conditions were as follows: Substrate temperature: 25℃ Ultimate pressure: 8.5×10 -5 Pa Atmosphere gas: Ar + O2 mixed gas (O2 flow rate 30%) Sputtering pressure (total pressure): 0.4 Pa Input voltage: RF100W Distance between S (substrate) and T (target): 70mm

[0137] (11) Formation of contact holes in the interlayer insulating film 26 A substrate on which an interlayer insulating film 26 was formed was exposed using photoresist AZ1500 (manufactured by AZ Electronic Materials) via a photomask, and then developed with tetramethylammonium hydroxyl (TMAH). After development, buffered hydrofluoric acid (BHF) was used to form contact holes with a horizontal length of Ls (contact region length between source electrode 27 and drain electrode 28 and channel layer 11, Figure 3(B)) and a vertical length of 18 μm, as shown in Table 1.

[0138] (12) Formation of source electrode 27 and drain electrode 28 The source electrode 27 and drain electrode 28 were patterned using an image reversal resist AZ5214 and a photomask in a lift-off process. The image reversal resist AZ5214 was exposed through a photomask formed to pattern the final element shape shown in Table 1, and after an inversion bake process, the entire surface was exposed and developed with TMAH. A 150 nm thick Mo layer was deposited on the patterned resist-coated substrate under the following sputtering conditions. Substrate temperature: 25℃ Ultimate pressure: 8.5×10 -5 Pa Atmospheric gas: Ar Sputtering pressure (total pressure): 0.4 Pa Input voltage: DC100W Distance between S (substrate) and T (target): 70mm Subsequently, the source electrode 27 and drain electrode 28 were patterned by lifting off the substrate on which the Mo layer was deposited in acetone.

[0139] (13) Final Annealing Finally, a self-aligned top-gate structure miniature TFT was obtained by annealing in an N2 atmosphere at 300°C for 1 hour. Tables 1 and 2 summarize the TFT fabrication conditions.

[0140] Comparative Example 1 The TFT was fabricated in the same manner as in Example 1, except that the low-resistance treatment (9) in Example 1 was not performed.

[0141] Comparative Example 2 In Example 1, the TFT was fabricated in the same manner as in Example 1, except that the ITO layer 23 was formed and annealing was not performed, as in (9) the low-resistance treatment.

[0142] [Table 1]

[0143] [Table 2]

[0144] Example 2 In Example 1, the TFT was fabricated in the same manner as in Example 1, except that in (2) formation of the oxide thin film, an oxide sputtering target obtained from a raw material mixture with the composition ratio shown in Table 1 was used. In the following examples and comparative examples, the gate insulating film deposition in step (7) of Example 1 was not performed, and a 100 nm thick gate insulating film was formed in step (5).

[0145] Example 3 In Example 1 (2) Formation of an oxide thin film, an oxide sputtering target obtained from a raw material mixture with the composition ratio shown in Table 3 was used, the atmospheric gas during film formation was a mixed gas of Ar + O2, and the formation conditions for each constituent layer were changed as shown in Tables 3 and 4. Otherwise, the TFT was fabricated in the same manner as in Example 1. Tables 3 and 4 summarize the TFT fabrication conditions.

[0146] Comparative Examples 3-5 The TFT was fabricated in the same manner as in Example 3, except that the thickness of the oxide thin film in Example 3 was changed as shown in Table 3, and (9) the resistance reduction treatment was changed as shown in Table 4.

[0147] [Table 3]

[0148]

Table 4

[0149] Example 4, Comparative Examples 6 to 9 In the step (2) of forming an oxide thin film in Example 1, a TFT was produced in the same manner as in Example 1, except that an oxide sputtering target obtained from a raw material mixture having the charging composition ratio shown in Table 5 was used, and the formation conditions for each constituent layer were changed as shown in Tables 5 and 6. Tables 5 and 6 show a summary of TFT production conditions.

[0150]

Table 5

[0151]

Table 6

[0152] The following evaluations were performed on the TFTs obtained in the Examples and Comparative Examples. The results are shown in Tables 7 to 9. In the tables, "E+XX" represents "×10 XX " (A) Evaluation of the channel layer (crystalline oxide thin film) of the TFT (1) State of the channel layer after TFT production Regarding the crystalline state of the cross-section of the channel layer in the TFT, pretreatment was performed on the channel layer using a focused ion beam apparatus (FIB: Focused Ion Beam), and the cross-section of the channel layer was observed with a transmission electron microscope (TEM: Transmission Electron Microscope) to evaluate (a) the average grain boundary angle θ with respect to the thin film surface, (b) the average grain boundary angle θ with respect to the lower layer sub , (c) the average spacing D of grain boundaries and (d) the crystalline state.

[0153] Specifically, first, an ion beam was introduced perpendicular to the surface of the channel layer using a FIB (FIB "FB2100" manufactured by Hitachi High-Technologies Corporation) device, and a 16 μm × 4 μm test specimen was sampled. Then, from the sampled test specimen, two samples were extracted from a 3 μm region, starting from the edge of the region where the source electrode or drain electrode and the channel layer overlapped in the channel length direction (horizontal direction in the drawing) and moving towards the region where they did not overlap. For the two extracted samples, Ar ion milling was performed in the channel width direction (depth direction in the drawing), perpendicular to the channel length direction and film thickness direction, until the thickness of the thin film was approximately 100 nm, thereby reducing the thickness of the two extracted samples. If crystal grains could not be confirmed due to ion sputtering damage during FIB processing, etching was repeatedly performed using Ar ion milling (Gatan "Model 691" manufactured by Gatan Corporation) at an ion gun voltage of 4 keV until crystal grains could be confirmed. Cross-sectional TEM images were obtained using a transmission electron microscope (JEOL JEM-2800 model) with an acceleration voltage of 200kV, and an observation magnification of 100,000x (an area of ​​approximately 4μm square) was observed.

[0154] (a) Mean grain boundary angle θ with respect to the thin film surface The average grain boundary angle θ with respect to the thin film surface when observing the cross-section of the channel layer (crystalline oxide thin film) can be calculated by analyzing the angle between the grain boundary and the thin film surface observed by cross-sectional TEM. In the image observed at a magnification of 100,000x (channel length direction × thickness direction = 4 μm angle), Ls and L in the channel length direction in the TFT off Three arbitrary fields of view were extracted and observed so as to include the crystalline oxide film in each area. Furthermore, in cases where the crystal grains were large and grain boundaries could not be observed, multiple fields of view were extracted so that the observation points did not overlap in the channel length direction, within a 4 μm square range in the channel length direction × thickness direction, allowing observation of the entire channel layer in the TFT. Cross-sectional TEM images were then observed. The angles between the thin film surface and the grain boundaries were calculated by performing image analysis on the cross-sectional TEM images of each obtained field of view using "SPIP, Version 4.3.2.0" from Image Metrology Inc. Details are as follows. For the cross-sectional TEM images, lines with color codes H0, S0, and V10 were drawn at the grain boundaries in the observed images of crystalline oxide thin films. Furthermore, contrast was quantified using image analysis software, and a threshold height of (maximum density - minimum density) × 1 / 4 was set. Next, the region showing contrast below the threshold was defined as a grain boundary, and the angle between each thin film surface and the grain boundary was determined. The sum of the angles between each thin film surface and the grain boundary obtained was divided by the number of particles, and the average value of the angles obtained in all obtained fields was defined as the average grain boundary angle θ with respect to the thin film surface.

[0155] (b) Mean grain boundary angle θ with respect to the lower layer sub The grain boundaries were extracted using the same cross-sectional TEM image and analysis method as for the average grain boundary angle θ with respect to the thin film surface, and the angle they make with respect to the lower layer was determined. The sum of the angles between each lower layer surface and the grain boundaries was divided by the number of particles, and the average of the angles obtained in all obtained fields was used to determine the average grain boundary angle θ with respect to the lower layer surface. sub That's what I decided.

[0156] (c) Average spacing of grain boundaries D The average spacing D when observing the cross-section of an oxide thin film can be calculated by analyzing the spacing of crystal grains observed by cross-sectional TEM. At an observation magnification of 100,000x (channel length direction × thickness direction = 4 μm square), Ls and L in the channel length direction in the TFT are calculated. off Three arbitrary fields of view were extracted and observed so as to include the crystalline oxide film in each area. Furthermore, in cases where the crystal grains were large and grain boundaries could not be observed, multiple fields of view were extracted so that the observation points did not overlap in the channel length direction, allowing observation of the entire channel layer in the thin-film transistor within a 4 μm square range in the channel length direction × thickness direction, and cross-sectional TEM images were observed. The average grain boundary spacing D was calculated by performing image analysis on the cross-sectional TEM images of each obtained field of view using "SPIP, Version 4.3.2.0" from Image Metrology Inc. Details are as follows. For the cross-sectional TEM images, lines with color codes H0, S0, and V10 were drawn at the grain boundaries. Furthermore, contrast was quantified using image analysis software, and a threshold height of (maximum density - minimum density) × 1 / 4 was set. Next, regions showing contrast below the threshold were defined as grain boundaries, and the distance between each grain boundary and the nearest neighbor particle was determined and used as the grain boundary distance. The sum of the obtained distances for each grain boundary was divided by the number of locations where the distance was measured to obtain the average grain boundary distance, and the average of the average grain boundary distances obtained for all fields of view was calculated as D.

[0157] (d) Crystallized state The crystalline state was determined by observing the electron diffraction pattern of a sample obtained by observing a cross-sectional TEM image. Specifically, using an electron microscope (JEOL JEM-2800), an electron beam was irradiated onto the oxide thin film area observed in the cross-sectional TEM image with an irradiation area of ​​approximately 100 nmφ using a limiting aperture and an acceleration voltage of 200 kV. The camera length was set to 2 m, and the diffraction pattern was measured. Oxide thin films in which no clear diffraction spots were obtained in any three arbitrary fields extracted so that the observation points did not overlap in the channel length direction of the cross-sectional TEM image sample were judged to be "amorphous." On the other hand, oxide thin films in which symmetrical diffraction spots were observed from the diffraction pattern were judged to be "crystalline," and oxide thin films in which similar diffraction patterns were observed in any three arbitrary fields extracted so that the observation points did not overlap in the film thickness direction were judged to be "columnar crystals."

[0158] (2) Method for measuring the spreading resistance of oxide thin film cross-sections using SSRM The spreading resistance of the low-resistance region A and the high-resistance region B of the channel layer can be determined by scanning spread resistance microscopy (SSRM) measurements. The apparatus and measurement conditions are shown below. Equipment: NanoScope IVa AFM Dimension 3100 Stage AFM System + SSRM option, manufactured by Bruker AXS (formerly Veeco) Digital Instruments division. SSRM scanning mode: Simultaneous measurement of contact mode and spreading resistance. SSRM probe (Tip): p-type semiconductor diamond-coated silicon cantilever Sample preparation: After preparing the cross-section by mechanical polishing, each layer was short-circuited to allow the application of a bias voltage. Furthermore, a DC bias voltage of -3.0V was applied to the sample and measurements were performed. Measurement environment: Room temperature, in ambient air

[0159] (a) Spreading resistance R A and R B A cross-section of the channel layer, measuring 1 μm in the thickness direction and 4 μm in the channel length direction, was extracted to include the gate electrode layer, gate insulating film layer, low-resistance region A, and high-resistance region B. The observation cross-section was obtained by mechanical polishing underwater. Subsequently, the spreading resistance of this cross-section was measured using SSRM. The line profile of the spreading resistance was measured while moving the cantilever in 7.8 nm increments parallel to the channel length direction relative to the channel region, and the minimum value of the spreading resistance in low-resistance region A was defined as the "spreading resistance value R of low-resistance region A". A "The maximum value of the spreading resistance in the high-resistance region B is "Spreading resistance value R in the high-resistance region B" B " he said.

[0160] (b) Spreading resistance Rs(L), Rs(L) off ), and Rs(Ls) Regarding the channel layer of the TFT, L off The region and the region L in contact with the lower surface of the gate insulating film were extracted, and an observation cross-section was obtained by mechanical polishing underwater. Subsequently, the spreading resistance of the cross-section was measured by SSRM. The line profile of the spreading resistance was measured while moving the cantilever in 7.8 nm increments parallel to the channel length direction with respect to region L. off The minimum value of the spreading resistance in the region is "Rs(L off)1", and the maximum value of the spreading resistance at L was defined as "Rs(L)". Also, L off A region including the region and the region Ls in contact with the source electrode or drain electrode was extracted, and an observation cross-section was obtained by mechanical polishing underwater. The line profile of the spreading resistance was measured while moving the cantilever in 7.8 nm increments relative to region L. off The minimum value of the spreading resistance in the region is "Rs(L off )2", the minimum value of the spreading resistance at Ls was defined as "Rs(Ls)". Rs(L off ) is Rs(L off )1 and Rs(L off The average of 2 was used.

[0161] (c) Measurement of the horizontal gap ΔL between the low-resistance region A and the gate electrode. Using the same apparatus as that used for SSRM, the height image of the AFM mode cross-section was measured for the cross-section obtained by underwater mechanical polishing. The line profile of the height image was measured while moving the cantilever horizontally in 7.8 nm increments relative to the gate electrode surface, including the gate electrode layer and the adjacent interlayer insulating film layer. The location where the height changed abruptly was identified as the horizontal end of the gate electrode. Next, the spreading resistance R evaluated by SSRM was measured. A The channel lengthwise profile of the gate electrode and the horizontal profile of the gate electrode relative to the gate electrode surface were compared, and the difference between the ends of each was defined as ΔL. A positive ΔL indicates a horizontal gap between the low-resistance region A and the gate electrode; a ΔL of 0 indicates no gap; and a negative ΔL indicates that the gate electrode end and the low-resistance region A overlap horizontally.

[0162] (3) Scanning Capacitive Microscopy (SCM) Measurement The voltage change (dC / dV) of the capacitance in the low-resistance region A and high-resistance region B of the channel layer can be determined by scanning capacitance microscopy (SCM) measurements. The equipment and measurement conditions used are shown below. Observation device: NanoScope IVa AFM Dimension 3100 stage AFM system + SCM option manufactured by Digital Instruments Division, Bruker AXS (formerly Veeco) SCM scanning mode: Simultaneous measurement of dC / dV signals in contact mode and X-Y mode SCM probe (Tip): PtIr-coated silicon cantilever Sample processing: After preparing a cross-section by mechanical polishing, each layer was short-circuited to enable application of a bias voltage. Measurement was further performed by applying a modulation voltage of 4.0 V and a DC bias voltage of 0 V to the sample. Measurement environment: Room temperature, in the atmosphere

[0163] (a) Magnitude relationship between dC / dV(A-B) and dC / dV(B) A cross-section of 1.25 µm in the thickness direction of the channel layer × 10 µm in the plane direction was extracted to include a low-resistance region A and a high-resistance region B, and an observation cross-section was obtained by mechanical polishing in water. Subsequently, a signal of voltage change in capacitance (dC / dV) was obtained for the cross-section by SCM. For the channel region, a line profile of dC / dV was measured while moving the cantilever by 19.6 nm each step, and the magnitude relationship between the minimum value of dC / dV(B) in the high-resistance region B and dC / dV(A-B) at the boundary between the low-resistance region A and the high-resistance region B was evaluated.

[0164] (4) Identification of crystal structure by electron diffraction It was evaluated whether the crystal structure of the oxide thin film is a bixbyite structure by observing the electron diffraction pattern of the sample obtained from cross-sectional TEM image observation. Specifically, using an electron microscope ("JEM-2800 model" manufactured by JEOL Ltd.), an electron beam was irradiated to the oxide thin film area observed in a cross-sectional TEM image with an irradiation area of about 100 nmφ and an acceleration voltage of 200 kV via a selected area aperture, and the diffraction pattern was measured with the camera length set to 2 m. Furthermore, to identify the crystal structure, we performed a simulation of the electron diffraction pattern of the Bixbite structure of In2O3 using the electron diffraction simulation software ReciPro (free software ver4.641 (2019 / 03 / 04)). For the simulation, we used crystal structure data 14388 from the ICSD (Inorganic Crystal Structure Database: Japan Chemical Information Association), with space group: Ia-3, lattice constant: a=10.17700 Å, and atomic coordinates In site (0.250,0.250,0.250), In site (0.466,0.000,0.250), and O site (0.391,0.156,0.380). Furthermore, with a camera length of 2m, simulations were performed using 11 types of reciprocal lattice vectors (1 0 0), (1 1 1), (1 1 0), (2 1 1), (3 1 1), (2 2 1), (3 3 1), (2 1 0), (3 1 0), (3 2 1), and (2 3 0) as the direction of the incident electron beam. The electron diffraction pattern of the oxide thin film and the obtained simulation pattern were compared to the diffraction spot results. If the results matched any of the 11 simulation patterns, it was determined that the oxide thin film contained crystal grains with a bixbite structure.

[0165] (B) Evaluation of TFT performance The obtained TFTs were measured using a semiconductor parameter analyzer (Agilent Corporation "B1500") at room temperature and in a light-shielded environment (inside a shielded box). The drain voltage (Vd) was applied at 0.1V or 20V. For each applied Vd, the Id-Vg characteristics were obtained by measuring the current value Id in 0.2V steps from -5V to 20V using the gate voltage (Vg). Tables 7, 8, and 9 show the various parameters calculated from the Id-Vg characteristics. The calculation methods for each parameter are as follows.

[0166] (a) Maximum value of linear mobility (μlin Max) The maximum value of the linear mobility when Vd = 0.1V is applied was determined by creating an Id-Vg characteristic graph, calculating the transconductance (Gm) for each Vg, and deriving the linear mobility (μlin) using the equation for the linear region. Specifically, Gm was calculated using ∂(Id) / ∂(Vg). Furthermore, μlin was calculated using equation (b) for the linear region. μlin=(Gm L) / (W Ci Vd) (b) In equation (b), Ci is the capacitance of the gate insulating film, and is based on the gate insulating film thickness of the final shape described in Tables 2, 4, and 6, the relative permittivity of SiO2 is 3.9, and the permittivity of vacuum is 8.85 × 10⁻⁶. -14 Ci[F / cm] calculated based on [F / cm] 2 The value of ] was used. In equation (b), L is the channel length (L length) and W is the channel width (W length).

[0167] From the graphs of Vg-μlin, the maximum value of μlin for Vg = 0 to 20V was calculated and defined as the maximum value of linear mobility, "μlin Max". Tables 7-9 show L off The values ​​for a TFT with a width of 4 μm and an Ls of 2 μm are shown.

[0168] (b) Linear mobility variability of TFT (Δμlin) L prepared in each example and comparative example off and TFT36 elements with different Ls (condition: L off For the [μm]6 conditions × Ls[μm]6 conditions), the maximum value of the linear mobility was calculated using the method shown in (a) above. The range of variation in the maximum value of the linear mobility of the 36 elements was defined as "linear mobility variation of 36 elements (Δμlin)".

[0169] (c) Maximum saturation mobility (μsat Max) The maximum saturation mobility when Vd = 20V is applied was determined by creating an Id-Vg characteristic graph, calculating the transconductance (Gm) for each Vg, and deriving the saturation mobility (μsat) using the equation for the saturation region. Specifically, Gm was calculated using the following formula (c1).

number

[0170] (d) Linear mobility variation of TFT Δμsat L prepared in each example and comparative example off For each of the 36 TFTs with different Ls values, the maximum saturation mobility was calculated using the method described in (c) above. The range of variation in the maximum linear mobility of the 36 elements was defined as the "variation in saturation mobility of the 36 elements (Δμsat)".

[0171] (e) S value and Vth The S value and threshold voltage (Vth) were evaluated from the graphs of each Id-Vg characteristic. Specifically, the current value Id = 10 -11 ~10 -10 In region [A], the value obtained by the following formula (d) was calculated as the S value. Furthermore, the current value Id = 10 -8 The value of Vg in [A] was calculated as the threshold voltage (Vth). Tables 7-9 show L off The values ​​for a TFT with a width of 4 μm and an Ls of 2 μm are shown.

number

[0172] (f) Vth variation ΔVth L prepared in each example and comparative example off For each of the 36 TFTs with different Ls values, Vth was calculated using the method described in (e) above. The range of variation in the maximum linear mobility of the 36 elements was defined as the "linear mobility variation of the 36 elements (ΔVth)".

[0173] [Table 7]

[0174] [Table 8]

[0175] [Table 9]

[0176] [Formation of crystalline oxide thin films] In Examples 5-8, laminates were fabricated and evaluated in which only crystalline oxide thin films were formed on the substrate under the same conditions as the channel layers of the TFTs prepared in Examples 1-4. Example 5 (1) Formation of oxide thin film A 10 nm thick oxide thin film was formed on a 4-inch diameter alkali-free glass substrate (Corning EAGLE XG) by sputtering using a sputtering target obtained from a raw material mixture with the composition ratios shown in Table 10. Table 10 shows the metal composition ratio (unit: at%) of the sputtering target and the sputtering conditions. The sputtering conditions not listed in Table 10 are as follows: Substrate temperature: 25℃ Ultimate pressure: 1.0×10 -4 Pa Atmosphere gas: A mixture of Ar and H2O Sputtering pressure (total pressure): 0.5 Pa Input voltage: DC300W Distance between S (substrate) and T (target): 70mm

[0177] (2) Annealing of oxide thin films A substrate with an oxide thin film formed on it was placed in a furnace and heated to 350°C at a rate of 10°C / min in air, then held for 1 hour. After maintaining the furnace temperature at 350°C for 1 hour, it was allowed to cool naturally. After the furnace temperature returned to room temperature, the substrate was removed from the furnace.

[0178] (3) Treatment to reduce resistivity (high carrier concentration) (3-1) Formation of ITO film A 2nm thick ITO layer was formed using an ITO sputtering target. The sputtering conditions were as follows: Substrate temperature: 25℃ Ultimate pressure: 8.5×10 -5 Pa Atmosphere gas: Ar + O2 mixed gas (O2 flow rate 2%) Sputtering pressure (total pressure): 0.4 Pa Input voltage: DC100W Distance between S (substrate) and T (target): 70mm

[0179] (3-2) Patterning of the ITO layer An ITO layer was patterned into 1 cm square island shapes by photolithography. First, a photoresist film was formed on the ITO layer. AZ1500 (manufactured by AZ Electronic Materials) was used as the photoresist. The photoresist film was exposed to light through a photomask with numerous 1 cm square patterns. After exposure, it was developed with tetramethylammonium hydroxyl (TMAH). After development, the ITO layer was etched with oxalic acid (ITO-06N, manufactured by Kanto Chemical). After etching, the photoresist was removed to obtain a substrate on which 1 cm square ITO layers were formed at equal intervals on an oxide thin film.

[0180] (3-3) Annealing A substrate with an ITO layer patterned on it was placed in a furnace and heated to 350°C at a rate of 10°C / min in air, then held for 1 hour. After maintaining the furnace temperature at 350°C for 1 hour, it was allowed to cool naturally. After the furnace temperature returned to room temperature, the substrate was removed from the furnace. Here, the oxide thin film in the region annealed without being coated with the ITO layer becomes a high-resistance region B. On the other hand, the oxide thin film in the region annealed while being coated with the ITO layer becomes a low-resistance region A.

[0181] (3-4) Removal of the ITO layer The ITO layer of the annealed substrate was removed by etching with oxalic acid (ITO-06N, manufactured by Kanto Chemical). As a result, a crystalline oxide thin film having alternating 1 cm square high-resistance regions B and 1 cm square low-resistance regions A was obtained on the substrate.

[0182] Comparative Example 10 A crystalline oxide thin film was formed in the same manner as in Example 5, except that the low-resistance treatment (3) in Example 5 was not performed.

[0183] Comparative Example 11 In Example 5 (3) Resistance Reduction Treatment, a crystalline oxide thin film was formed in the same manner as in Example 5, except that an ITO layer was formed and annealing was not performed.

[0184] Example 6 In Example 5 (1), the formation of the oxide thin film was carried out in the same manner as in Example 5, except that an oxide sputtering target obtained from a raw material mixture with the composition ratios shown in Table 10 was used.

[0185] Example 7 In Example 5 (1) Formation of the oxide thin film, an oxide sputtering target obtained from a raw material mixture with the composition ratio shown in Table 11 was used, and the formation conditions for each constituent layer were changed as shown in Table 11, except that a crystalline oxide thin film was formed in the same manner as in Example 5.

[0186] Comparative Examples 12-14 A crystalline oxide thin film was formed in the same manner as in Example 5, except that the (3) low-resistance treatment or the thickness of the oxide thin film was changed as shown in Table 11.

[0187] Example 8, Comparative Examples 15-18 In Example 5 (1) Formation of the oxide thin film, an oxide sputtering target obtained from a raw material mixture with the composition ratio shown in Table 12 was used, and the formation conditions for each constituent layer were changed as shown in Table 12, except that a crystalline oxide thin film was formed in the same manner as in Example 5.

[0188] The crystalline oxide thin films obtained in the examples and comparative examples were evaluated in the same manner as the channel layer in Example 1. In addition, the carrier concentration of the crystalline oxide thin films was measured. The results are shown in Tables 10-12. (1) Carrier concentration Low-resistance region A and high-resistance region B of a crystalline oxide thin film were each cut into 1 cm squares, and electrodes were attached to the four corners using In-solder to create elements for Hall effect measurement, and the carrier concentration was measured. The carrier concentration was determined by AC Hall effect measurement using a ResiTest8400 (manufactured by Toyo Technica Co., Ltd.) at room temperature. The measurement conditions were as follows: For measurement accuracy, the value of the electron carrier concentration when the F value was 0.9 or higher and the absolute value of the Hall voltage phase was 170° to 180° was adopted. Current value: 1 × 10 -12 ~1 × 10 -3 A Magnetic field strength: 0.36T

[0189] (2) Measurement of SSRM and SCM A 1 cm square section was cut from the crystalline oxide thin film, containing both the low-resistance region A and the high-resistance region B, to obtain a cross-section. This cross-section was evaluated in the same manner as the channel layer of a TFT.

[0190] (3) Measurement of cross-sectional TEM and electron diffraction A cross-section was obtained by cutting an arbitrary region of the crystalline oxide thin film into a 1 cm square. The target position of this cross-section was evaluated in the same way as the channel layer of a TFT.

[0191] [Table 10]

[0192] [Table 11]

[0193] [Table 12]

[0194] [Manufacturing of self-aligned top-gate structured miniature TFTs] Examples 9-11, Comparative Example 19 In Example 1 (2) Formation of the oxide thin film, an oxide sputtering target obtained from a raw material mixture with the composition ratio shown in Table 13 was used, and the formation conditions for each constituent layer were changed as shown in Tables 13 and 14, except that the TFT was fabricated in the same manner as in Example 1. Tables 13 and 14 summarize the TFT fabrication conditions. Table 15 shows the TFT evaluation results.

[0195] [Table 13]

[0196] [Table 14]

[0197] [Table 15]

[0198] Examples 12-20 A TFT was fabricated in the same manner as in Example 1, except that, during the formation of the oxide thin film (2) in Example 1, an oxide sputtering target obtained from a raw material mixture with the composition ratios shown in Tables 16 and 17 was used, and a channel layer was formed using the sputtering conditions shown in Tables 16 to 19. Tables 16-19 summarize the TFT fabrication conditions. Tables 20 and 21 show the TFT evaluation results.

[0199] [Table 16]

[0200] [Table 17]

[0201] [Table 18]

[0202] [Table 19]

[0203] [Table 20]

[0204] [Table 21]

[0205] Examples 21-34B In Example 1 (2) Formation of the oxide thin film, an oxide sputtering target obtained from a raw material mixture with the composition ratios shown in Tables 22-24 was used, and the formation conditions for each constituent layer were changed as shown in Tables 22-27. Otherwise, the TFT was fabricated in the same manner as in Example 1. Tables 22-27 summarize the TFT fabrication conditions. Tables 28-30 show the TFT evaluation results.

[0206] [Table 22]

[0207] [Table 23]

[0208] [Table 24]

[0209] [Table 25]

[0210] [Table 26]

[0211] [Table 27]

[0212] [Table 28]

[0213] [Table 29]

[0214] [Table 30]

[0215] Examples 35-216 In Example 1 (2) Formation of the oxide thin film, an oxide sputtering target obtained from a raw material mixture with the composition ratios shown in Tables 31 to 55 was used, and the sputtering conditions for the oxide thin film were changed as shown in Tables 31 to 55. Otherwise, the TFT was fabricated in the same manner as in Example 1. Tables 31-55 show the evaluation results of the channel layer and the TFT performance obtained.

[0216] [Table 31]

[0217] [Table 32]

[0218] [Table 33]

[0219] Table 34

[0220] Table 35

[0221] Table 36

[0222] Table 37

[0223] Table 38

[0224] Table 39

[0225] Table 40

[0226] Table 41

[0227] Table 42

[0228] Table 43

[0229] Table 44

[0230] Table 45

[0231] Table 46

[0232] Table 47

[0233] Table 48

[0234] Table 49

[0235] Table 50

[0236] Table 51

[0237] Table 52

[0238] Table 53

[0239] Table 54

[0240] [Table 55]

[0241] Example 217, Comparative Example 20 (1) Formation of oxide thin film A 50 nm thick oxide thin film was formed on a 4-inch diameter alkali-free glass substrate (Corning EAGLE XG) by sputtering using a sputtering target obtained from a raw material mixture with the composition ratios shown in Table 56. Table 56 shows the metal composition ratio (unit: at%) of the sputtering target and the sputtering conditions. In Table 56, X represents metal elements other than In and Ga. The sputtering conditions not listed in Table 56 are as follows: Substrate temperature: 25℃ Ultimate pressure: 1.0×10 -4 Pa Atmospheric gas: O2 Sputtering pressure (total pressure): 0.5 Pa Input voltage: DC400W Distance between S (substrate) and T (target): 70mm

[0242] (2) Annealing of oxide thin films A substrate with an oxide thin film formed on it was placed in a furnace and heated to 350°C at a rate of 10°C / min in air, then held for 1 hour. After maintaining the furnace temperature at 350°C for 1 hour, it was allowed to cool naturally. After the furnace temperature returned to room temperature, the substrate was removed from the furnace.

[0243] (3) Electron diffraction measurement A cross-section was obtained by cutting an arbitrary region of the oxide thin film into a 1 cm square. The target position of this cross-section was evaluated in the same way as the channel layer of a TFT. As a result, Example 217 had a Bixbite structure, while Comparative Example 41 was amorphous.

[0244] (4) CL (Cathodoluminescence spectroscopy) measurement CL measurements were performed using the following measuring equipment and conditions. [Measuring device] • Equipment: Cathodoluminescence spectrometer • Spectrometer: Manufactured by Horiba, Ltd. • SEM: JEOL Schottky emission type SEM JSM-7100F / TTLS • Spectrometer: iHR-320 Diffraction grating (100 gr / mm, blaze wavelength 450 nm) • Detector: CCD: Jobin Yvon [Measurement conditions] ·Temperature: Room temperature • Slit: 500 μm • Acceleration voltage: 1kV ·Irradiation current: 0.7nA (1kV) WD: 10.3mm • Spectrum integration time: 60-180s The intensity of the obtained spectra was converted to counts per second. The CL spectra of the oxide thin films obtained in Example 217 and Comparative Example 20 are shown in Figure 10, respectively.

[0245] Furthermore, for each spectrum, the ratio I(640nm) / I(380nm) of the emission intensity I(640nm) originating from crystal defects such as oxygen vacancies and the emission intensity I(380nm) due to interband transition emission was calculated and compared to compare the amount of defects in the oxide thin film. The results are shown in Table 52. Example 217, which crystallized into a bixbite structure, exhibited lower luminescence and a film quality with fewer defects compared to Comparative Example 20, which was amorphous.

[0246] [Table 56] [Industrial applicability]

[0247] The crystalline oxide thin film of the present invention can be suitably used as a component of a thin-film transistor, for example, as a channel layer. Furthermore, the thin-film transistor of the present invention can be used in electronic circuits used in electrical equipment, electronic devices, vehicles, and power engines.

[0248] Although several embodiments and / or examples of the present invention have been described in detail above, those skilled in the art will find it easy to make many modifications to these exemplary embodiments and / or examples without substantially departing from the novel teachings and effects of the present invention. Accordingly, many of these modifications fall within the scope of the present invention. All references made in this specification and to the application on which the priority claim of this application under the Paris Convention rest with respect to this specification.

Claims

1. A crystalline oxide thin film mainly composed of In, The crystalline oxide thin film has a low-resistance region A and a high-resistance region B in the planar direction, with different spreading resistance values ​​as measured by a scanning spreading resistance microscope (SSRM). The expansion resistance value of the high-resistance region B is 8 times or more the expansion resistance value of the low-resistance region A. A crystalline oxide thin film in which, as measured by a scanning capacitance microscope (SCM), the dC / dV value at the boundary between the low-resistance region A and the high-resistance region B is greater than the dC / dV value of the high-resistance region B.

2. The crystalline oxide thin film according to claim 1, wherein the spreading resistance value of the high-resistance region B is 10 times or more the spreading resistance value of the low-resistance region A.

3. The crystalline oxide thin film according to claim 1, wherein the spreading resistance value of the high-resistance region B is 15 times or more the spreading resistance value of the low-resistance region A.

4. The crystalline oxide thin film according to claim 1, wherein the film thickness is 80 nm or less.

5. The average grain boundary angle θ between the lower surface of the crystalline oxide thin film and the grain boundaries within the thin film is 70° or more and 110° or less. The crystalline oxide thin film according to claim 1, wherein the average spacing D between the grain boundaries is 0.01 μm or more and 2.0 μm or less.

6. The crystalline oxide thin film according to claim 1, wherein the electron diffraction of the crystalline oxide thin film includes crystal grains having a bixbite structure.

7. The crystalline oxide thin film according to claim 1, further comprising one or more elements selected from the group consisting of H, B, C, N, O, F, Mg, Al, Si, O, S, Cl, Ar, Ca, Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zn, Ga, Ge, Y, Zr, Nb, Mo, Tc, Ru, Rh, Pd, Ag, Cd, Sn, Sb, Cs, Ba, Ln, Hf, Ta, W, Re, Os, Ir, Pt, Au, Pb, and Bi.

8. A laminate comprising the crystalline oxide thin film described in claim 1.

9. The laminate according to claim 8, wherein the average grain boundary angle θsub formed between the surface in contact with the crystalline oxide thin film and the lower layer and the grain boundaries in the crystalline oxide thin film is 70° or more and 110° or less.

10. The laminate according to claim 9, wherein the lower layer is a substrate for a thin-film transistor or a constituent layer of a thin-film transistor.

11. A thin-film transistor comprising a crystalline oxide thin film as described in claim 1.

12. channel layer and Source electrode and drain electrode connected to both ends of the channel layer, It has a gate electrode stacked on a channel layer via a gate insulating film. The channel layer is the crystalline oxide thin film, the gate insulating film is formed in the high-resistance region B, and the source electrode and drain electrode are formed in the low-resistance region A. The distance L from the ends of the source electrode and the drain electrode to the intersection of the perpendicular line drawn in the thickness direction from the end of the gate electrode and the crystalline oxide thin film ｏｆｆ However, it is between 4 μm and 20 μm. The average spacing D between grain boundaries in the crystalline oxide thin film and the distance L ｏｆｆ The thin-film transistor according to claim 11, wherein the following formula (1) is satisfied. 2≦L ｏｆｆ / D≦100・・・(1)

13. The contact region length Ls between the source electrode, the drain electrode, and the channel layer is 4 μm or more and 20 μm or less. The thin-film transistor according to claim 12, wherein the average spacing D between grain boundaries of the crystalline oxide thin film and the contact region length Ls satisfy the following formula (2). 1 ≤ Ls / D ≤ 100 ... (2)

14. The thin-film transistor according to claim 12, wherein the horizontal gap ΔL between the low-resistance region A and the gate electrode is less than 1 μm.

15. A crystalline oxide thin film mainly composed of In, The film thickness is 80 nm or less. The crystalline oxide thin film has a high carrier concentration region A and a low carrier concentration region B in the plane direction, with different carrier concentrations. The carrier concentration in the aforementioned high carrier concentration region A is 10 １９ cm －３ The above 10 ２２ cm －３ The following: The carrier concentration in the high carrier concentration region A is 8 times or more than the carrier concentration in the low carrier concentration region B. A crystalline oxide thin film in which, as measured by a scanning capacitance microscope (SCM), the dC / dV value at the boundary between the high carrier concentration region A and the low carrier concentration region B is greater than the dC / dV value of the low carrier concentration region B.

16. The crystalline oxide thin film according to claim 15, wherein the carrier concentration in the high carrier concentration region A is 10 times or more than the carrier concentration in the low carrier concentration region B.

17. The crystalline oxide thin film according to claim 15, wherein the carrier concentration in the high carrier concentration region A is 15 times or more than the carrier concentration in the low carrier concentration region B.

18. The carrier concentration of the low carrier concentration region B is 10 １５ cm －３ or more, and 10 １９ cm －３ or less, the crystalline oxide thin film according to claim 15.

19. The average grain boundary angle θ between the lower surface of the crystalline oxide thin film and the grain boundaries within the thin film is 70° or more and 110° or less. The crystalline oxide thin film according to claim 15, wherein the average spacing D between the grain boundaries is 0.01 μm or more and 2.0 μm or less.

20. The crystalline oxide thin film according to claim 15, wherein the electron diffraction of the crystalline oxide thin film includes crystal grains having a bixbite structure.

21. The crystalline oxide thin film according to claim 15, further comprising one or more elements selected from the group consisting of H, B, C, N, O, F, Mg, Al, Si, O, S, Cl, Ar, Ca, Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zn, Ga, Ge, Y, Zr, Nb, Mo, Tc, Ru, Rh, Pd, Ag, Cd, Sn, Sb, Cs, Ba, Ln, Hf, Ta, W, Re, Os, Ir, Pt, Au, Pb, and Bi.

22. A laminate comprising the crystalline oxide thin film described in claim 15.

23. The laminate according to claim 22, wherein the average grain boundary angle θsub formed between the surface in contact with the crystalline oxide thin film and the lower layer and the grain boundaries in the crystalline oxide thin film is 70° or more and 110° or less.

24. The laminate according to claim 23, wherein the lower layer is a substrate for a thin-film transistor or a constituent layer of a thin-film transistor.

25. A thin-film transistor comprising a crystalline oxide thin film according to claim 15.

26. channel layer and Source electrode and drain electrode connected to both ends of the channel layer, It has a gate electrode stacked on a channel layer via a gate insulating film. The channel layer is the crystalline oxide thin film, the gate insulating film is formed in the low carrier concentration region B, and the source electrode and drain electrode are formed in the high carrier concentration region A. The distance L from the ends of the source electrode and the drain electrode to the intersection of the perpendicular line drawn in the thickness direction from the end of the gate electrode and the crystalline oxide thin film ｏｆｆ However, it is between 4 μm and 20 μm. The average spacing D between grain boundaries in the crystalline oxide thin film and the distance L ｏｆｆ The thin-film transistor according to claim 25, wherein the following formula (1) is satisfied. 2≦L ｏｆｆ / D≦100・・・(1)

27. The contact region length Ls between the source electrode, the drain electrode, and the channel layer is 4 μm or more and 20 μm or less. The thin-film transistor according to claim 26, wherein the average spacing D between grain boundaries of the crystalline oxide thin film and the contact region length Ls satisfy the following formula (2). 1 ≤ Ls / D ≤ 100 ... (2)

28. The thin-film transistor according to claim 26, wherein the horizontal gap ΔL between the high carrier concentration region A and the gate electrode is less than 1 μm.

29. A thin-film transistor according to any one of claims 11 to 14 or 25 to 28, electronic circuit.

30. An electrical device, electronic device, vehicle, or power engine, including the electronic circuit described in claim 29.

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