Multi-rate burst mode receiver

Abstract

To provide a device and a method for managing a burst mode receiver within an optical line terminal (OLT) in a passive optical network.SOLUTION: An OLT includes a burst mode receiver 111 that decodes an optical burst signal 210 from an optical network unit (ONU) into a decoded output signal 220 by one or more digital signal processing (DSP) circuits 201-204 that process the signal at respective configurable processing speeds. The burst mode receiver includes means 205 for performing obtaining a symbol rate 240 of a next optical burst signal 215, and adjusting 234 configurable processing speeds 230 of the one or more DSP circuits based on the symbol rate 240 of the next optical burst signal 215 during an interval between reception of a valuable symbol in a preceding optical burst signal 211 and reception of a valuable symbol in the next optical burst signal 215.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] Various exemplary embodiments relate to an apparatus and method for managing a burst mode receiver in an optical line terminal (OLT) in a passive optical network.

Background Art

[0002] In a passive optical network (PON), at least one optical line terminal (OLT) on the network side is connected to one or more optical network units (ONUs) on the user side. Upstream optical burst signals received by the OLT are typically decoded by a burst mode receiver comprising one or more burst mode receiver components. For example, burst mode receivers in new PON systems such as 50G-PON according to the ITU-T G.9804 standard typically comprise more complex digital burst mode receiver components with digital signal processing functions, such as equalizers.

[0003] In such new PON systems, ONUs may be enabled to transmit optical burst signals to the OLT at a plurality of different symbol rates. In other words, the symbol rate of the optical burst signal received by the OLT may vary. Therefore, it is desirable to enable efficient reception of optical burst signals with different symbol rates.

Summary of the Invention

Problem to be Solved by the Invention

[0004] The scope of protection sought for various embodiments of the present invention is defined by the independent claims. If any of the embodiments and features described herein are not within the scope of the independent claims, they are to be construed as examples useful for understanding various embodiments of the present invention.

[0005] In particular, an objective of the embodiments of the present invention is to enable efficient reception and decoding of optical burst signals with different symbol rates by optical line termination equipment (OLT) within a passive optical network (PON). [Means for solving the problem]

[0006] This objective is achieved, according to a first exemplary aspect of the present disclosure, by an optical line termination device (OLT) configured to communicate with one or more optical network units (ONUs) in a passive optical network; the optical burst signals transmitted by the one or more ONUs each have their own symbol rate; and the optical line termination device includes a burst-mode receiver configured to decode the optical burst signals from the ONUs into decoded output signals by one or more digital signal processing circuits that process the signals at their respective configurable processing speeds. The optical line termination device includes means configured to acquire the symbol rate of the next optical burst signal; and to adjust the configurable processing speed of the one or more digital signal processing circuits based on the symbol rate of the next optical burst signal during the interval between the reception of valuable symbols in the preceding optical burst signal and the next optical burst signal.

[0007] Therefore, the optical burst signals received by the OLT can have different symbol rates. Each of the one or more ONUs in the network may transmit the optical burst signal at its own predetermined symbol rate, i.e., the symbol rate of each ONU may be fixed. Alternatively, the ONUs may transmit the optical burst signal at different symbol rates. The burst-mode receiver in the OLT is configured to receive and decode the optical burst signal, thereby generating a decoded output signal. In other words, the burst-mode receiver processes or converts the optical burst signal into a decoded output signal. For this purpose, the burst-mode receiver comprises one or more digital signal processing circuits that process the signal at their respective configurable processing speeds. A digital signal processing circuit may refer to a burst-mode receiver component in the burst-mode receiver that includes at least one digital signal processing function. The configurable processing speed of a digital signal processing circuit refers to the speed at which input samples are processed by the digital signal processing circuit and / or the speed at which output samples are generated by the digital signal processing circuit.

[0008] One or more digital signal processing circuits are interconnected to form a sequence, pipeline, or combination, and each processing performed by each interconnected digital signal processing circuit contributes to the decoding of the optical burst signal into a decoded output signal. In other words, one or more digital signal processing circuits form a processing data path for decoding the optical burst signal into a decoded output signal. Thus, each digital signal processing circuit processes the input signal into an output signal at its respective configurable processing speed. The input and / or output signals of the digital signal processing circuits are digital signals. The burst-mode receiver may further include one or more burst-mode receiver components without configurable processing speeds, such as fixed-speed analog burst-mode receiver components, within the data path for decoding the optical burst signal.

[0009] The next optical burst signal is the next optical burst signal in time received by the OLT, i.e., the first subsequent optical burst signal. The preceding optical burst signal is the last optical burst signal received by the OLT. In other words, the preceding optical burst signal and the next optical burst signal are temporally continuous.

[0010] Valuable symbols within an optical burst signal are those associated with valuable burst data. Valuable symbols may include symbols corresponding to the payload of the optical burst signal, such as data, error correction data, parity data, control data, and idle data. In addition, valuable symbols may further include some symbols in the preamble, some symbols in the header, or symbols in the delimiter of the optical burst signal. The location of symbols considered valuable within an optical burst signal may be predetermined or provisioned, for example, according to network requirements or network protocols.

[0011] By adjusting the configurable processing speed of one or more digital signal processing circuits based on the symbol rate of the next optical burst signal, the digital signal processing circuits can be optimized for the symbol rate of the next optical burst signal. This has the advantage of improving the energy efficiency of the burst-mode receiver, and thus the OLT, because the digital signal processing circuits can operate at the optimal processing speed for the received optical burst signal. In other words, it avoids the wasteful consumption of energy due to oversampling of the optical burst signal by the digital signal processing circuits. A further advantage is that the configurable processing speed of one or more digital signal processing circuits can be adjusted in real time, i.e., between incoming optical burst signals.

[0012] Since bits in the decoded output signal may be invalid during the period following adjustment of the configurable processing speed, it is further possible to avoid the misdecoding of these valuable symbols by adjusting the configurable processing speed of one or more digital signal processing circuits during the interval between the reception of valuable symbols in a series of optical burst signals. This has the advantage that data loss and data modification can be avoided when switching between configurable processing speeds.

[0013] According to one exemplary embodiment, the interval may include a guard time between a preceding optical burst signal and a subsequent optical burst signal; and / or a portion of the preamble within the subsequent optical burst signal.

[0014] Therefore, the interval between the reception of a valuable symbol in a preceding optical burst signal and the reception of a valuable symbol in the next optical burst signal may include a guard time between two consecutive optical burst signals. The guard time is a period that provides a safety margin against interference between consecutive optical burst signals. Thus, no valuable burst data is received by the OLT during the guard time. Alternatively, or complementaryly, a portion of the preamble within an optical burst signal may contain virtually no valuable burst data; for example, the beginning of the preamble may contain samples for tuning the burst-mode receiver.

[0015] According to one exemplary embodiment, adjusting the configurable processing speed of one or more digital signal processing circuits may include adjusting the clock frequencies of one or more digital signal processing circuits.

[0016] Each of the one or more digital signal processing circuits can be fitted with a clock signal that causes them to operate at their respective clock frequencies, i.e., a clock signal that causes the digital signal processing circuits to process signals at their respective clock frequencies or clock speeds. In other words, the digital clock of one or more digital signal processing circuits can determine the configurable processing speed of the digital signal processing circuits. Therefore, by adjusting the clock frequency of the digital signal processing circuits, the configurable processing speed of each digital signal processing circuit can be adjusted. This can be achieved by modifying the clock signal applied to each of the one or more digital signal processing circuits, for example, using a clock divisor circuit.

[0017] According to one exemplary embodiment, adjusting the configurable processing speed of each digital signal processing circuit may include enabling and / or disabling one or more parallel circuit instances of each digital signal processing circuit.

[0018] In other words, each digital signal processing circuit within a burst-mode receiver may include one or more parallel circuit instances of the digital signal processing circuit. These parallel circuit instances can operate at a nominal clock speed or frequency, i.e., a fixed processing speed. Therefore, by enabling or disabling these parallel circuit instances in the signal data path, the configurable processing speed of each digital signal processing circuit can be increased or decreased, i.e., the configurable processing speed of the digital signal processing circuits can be adjusted.

[0019] According to one exemplary embodiment, the burst-mode receiver further comprises at least one downsampling circuit configured to downsample a signal.

[0020] Therefore, at least one downsampling circuit may be included in the processing data path of a burst-mode receiver for decoding the optical burst signal into a decoded output signal. Downsampling can refer to converting a digital signal at one sample rate to a digital signal at a lower sample rate. The signal being downsampled may be the output signal of a preceding interconnected digital signal processing circuit. This allows the signal rate to be matched to the configurable processing speed of the subsequent digital signal processing circuit.

[0021] The downsampling circuit may be located, for example, within the processing data path of a burst-mode receiver, following a burst-mode receiver component having a fixed processing speed. The OLT means may be further configured to control the downsampling circuit according to a desired rate of the signal, for example, by enabling the downsampling circuit, disabling the downsampling circuit, or modulating the downsampling amount. In other words, the downsampling circuit may be configurable.

[0022] According to one exemplary embodiment, the burst-mode receiver further comprises at least one upsampling circuit configured to upsample a signal.

[0023] Therefore, at least one upsampling circuit may be included in the processing data path of a burst-mode receiver for decoding the optical burst signal into a decoded output signal. Upsampling can refer to converting a digital signal of one sample rate to a digital signal of a higher sample rate. The signal being upsampled may be the output signal of a preceding interconnected digital signal processing circuit. This allows the signal rate to be matched to the configurable processing speed of the subsequent digital signal processing circuit.

[0024] The upsampling circuit may be provided at the end of a processing data path or pipeline, whereby the decoded output signal can be upsampled to an appropriate rate for further circuits in the OLT connected to the burst mode receiver, for example, upper layer processing circuits and / or interface circuits in the OLT. Alternatively or additionally, the upsampling circuit may be provided before a burst mode receiver component that requires an input signal having a predetermined sampling rate. The means of the OLT may be further configured to control the upsampling circuit according to a desired rate of the signal to be upsampled, for example, by enabling the upsampling circuit, disabling the upsampling circuit, or modulating an upsampling amount. In other words, the upsampling circuit may be configurable.

[0025] According to an exemplary embodiment, the burst mode receiver further comprises at least one latency compensator circuit configured to adjust signal latency.

[0026] When adjusting the configurable processing speed of a digital signal processing circuit, the latency or processing delay of the digital signal processing circuit may change. For this purpose, at least one latency compensator circuit may be included in the processing data path of the burst mode receiver. The signal to which latency adjustment is applied may be an output signal of preceding interconnected digital signal processing circuits, or may be an output signal of preceding interconnected burst mode receiver components. The latency compensator circuit can compensate for changes in latency when adjusting the configurable processing speed of one or more digital signal processing circuits.

[0027] At least one latency compensator circuit can further compensate for changes in the end-to-end latency of a burst mode receiver. The end-to-end latency of a burst mode receiver may refer to the processing time for decoding symbols in an optical burst signal into one or more bits or samples in a decoded output signal. This has the advantage that the latency or processing delay of the burst mode receiver can be controlled. This further has the advantage that when adjusting the configurable processing speed of one or more digital signal processing circuits, the latency or processing delay of the burst mode receiver can be made substantially stable over time, that is, can be kept constant.

[0028] The OLT means may be further configured to control the latency compensator circuit in accordance with a desired latency, for example by enabling the latency compensator circuit, disabling the latency compensator circuit, or modulating the amount of latency adjustment. In other words, the latency compensator circuit may be configurable.

[0029] According to an exemplary embodiment, the latency compensator circuit may insert one or more dummy samples into a signal during the interval between reception of valid symbols in a preceding optical burst signal and a subsequent optical burst signal, or may be further configured to drop one or more non-payload samples from the signal.

[0030] Dummy samples and non-payload samples can be any data units, such as dummy bits and non-payload bits, or dummy symbols and non-payload symbols, depending on the signal being adjusted for latency. By inserting dummy samples or dropping non-payload samples, changes in end-to-end latency can be compensated without significantly impacting the system, for example, without affecting further circuitry in the OLT connected to a burst-mode receiver. A further advantage is that data loss and data modification can be avoided during latency adjustment, since the insertion of dummy samples or dropping of non-payload samples occurs during intervals in which no valuable burst data is substantially present.

[0031] According to one exemplary embodiment, the means may be further configured to control at least one downsampling circuit, at least one upsampling circuit, and / or at least one latency compensator circuit based on the symbol rate of the following optical burst signal.

[0032] According to one exemplary embodiment, the optical line termination device may be further configured to schedule guard times between consecutive optical burst signals for the shortest possible duration, so that the decoded output signal includes at least sufficient non-payload bits to compensate for changes in the end-to-end latency of the burst-mode receiver associated with adjusting a configurable processing speed between the highest and lowest processing speeds supported by the OLT.

[0033] According to one exemplary embodiment, the upsampling circuit may be further configured to upsample the signal to a predetermined data rate, or the latency compensator circuit may be further configured to adjust the latency of the signal to a predetermined latency.

[0034] The predetermined data rate or latency may be determined by the circuit or processing block receiving the upsampled or latency-adjusted signal, such as the next analog burst-mode receiver component in the data path, the next digital signal processing circuit in the data path, or further circuitry in the OLT such as a higher-layer processing circuit, or an interface circuit between the burst-mode receiver and the higher-layer processing circuit.

[0035] According to one exemplary embodiment, one or more digital signal processing circuits are selected from the group consisting of analog-to-digital converters, clock data recovery devices, equalizers, and / or decoders.

[0036] According to one exemplary embodiment, the means of the OLT may be further configured to determine the interval between the reception of a value symbol in a preceding optical burst signal and in a subsequent optical burst signal, based on burst timing information of the optical burst signal.

[0037] The burst timing information may be, for example, an upstream transmission schedule that includes time slots in which each ONU is permitted to transmit optical burst signals to the OLT.

[0038] According to one embodiment of the examples, obtaining the symbol rate of the following optical burst signal may further include determining the symbol rate based on the upstream transmission schedule.

[0039] The upstream transmission schedule may be determined by the OLT. The OLT can assign a symbol rate to the upstream transmission by each ONU in the passive optical network. Alternatively, or complementaryly, the OLT can assign the received upstream transmission, i.e., optical burst signals, to each ONU as part of the upstream transmission schedule. The OLT can recognize the symbol rate assigned to each ONU. This allows it to obtain the symbol rate for the next optical burst signal.

[0040] A second exemplary embodiment discloses a method comprising: acquiring the symbol rate of the next optical burst signal; and adjusting the configurable processing speed of one or more digital signal processing circuits in an optical line termination (OLT) based on the symbol rate of the next optical burst signal during the interval between receiving valuable symbols in the preceding optical burst signal and the next optical burst signal. The OLT is configured to communicate with one or more optical network units (ONUs) in a passive optical network; optical burst signals transmitted by the one or more ONUs each have their own symbol rate; and a burst-mode receiver is configured to decode the optical burst signals from the ONUs into decoded output signals by one or more digital signal processing circuits that process the signals at their respective configurable processing speeds.

[0041] A computer-implemented method is disclosed, according to a third exemplary embodiment, which includes acquiring the symbol rate of the next optical burst signal and adjusting the configurable processing speed of one or more digital signal processing circuits in an optical line termination (OLT) based on the symbol rate of the next optical burst signal during the interval between receiving valuable symbols in the preceding optical burst signal and the next optical burst signal. The OLT is configured to communicate with one or more optical network units (ONUs) in a passive optical network; optical burst signals transmitted by the one or more ONUs each have their own symbol rate; and a burst-mode receiver is configured to decode the optical burst signals from the ONUs into decoded output signals by one or more digital signal processing circuits that process the signals at their respective configurable processing speeds.

[0042] According to the fourth exemplary embodiment, a computer program product is disclosed which, when the computer program is run on a computer, includes computer executable instructions for performing the steps according to the third exemplary embodiment.

[0043] According to the fifth exemplary embodiment, a data processing system is disclosed that is configured to perform the computer-implemented method according to the third exemplary embodiment. [Brief explanation of the drawing]

[0044] [Figure 1] This is a schematic block diagram of the example passive optical network. [Figure 2] This figure illustrates an exemplary embodiment of a burst-mode receiver configured to decode an optical burst signal into a decoded output signal by one or more digital signal processing circuits that process the signal at their respective configurable processing speeds. [Figure 3A] This figure illustrates an exemplary embodiment of a burst-mode receiver in an OLT, in which adjusting the configurable processing speed includes adjusting the clock frequency of one or more digital signal processing circuits. [Figure 3B]This is a diagram illustrating an exemplary embodiment of a burst-mode receiver equipped with a downsampling circuit configured to downsample a signal. [Figure 4A] This is a diagram illustrating an exemplary embodiment of a burst-mode receiver equipped with an upsampling circuit configured to upsample a signal. [Figure 4B] This figure illustrates an exemplary embodiment of a burst-mode receiver in which adjusting the configurable processing speed includes enabling and / or disabling one or more parallel circuit instances of one or more digital signal processing circuits. [Figure 5A] This diagram illustrates an example of how the end-to-end latency of a burst-mode receiver can be changed by adjusting the configurable processing speed of one or more digital signal processing circuits within the burst-mode receiver. [Figure 5B] This figure illustrates an example of end-to-end latency adjustment performed by a latency compensator circuit within a burst-mode receiver, according to an embodiment. [Figure 6] This figure illustrates an exemplary embodiment of a suitable computing system for performing one or more steps in an embodiment of the present invention. [Modes for carrying out the invention]

[0045] Figure 1 shows a schematic block diagram of an exemplary point-to-multipoint optical network 100, in particular a passive optical network PON. The optical network 100 comprises an optical line termination device 110OLT and several optical network units ONUs 131, 132, 133 connected via an optical distribution network ODN 120. In this example, OLT 110 is connected to four ONUs 131, 132, 133, and 134, but OLT 110 may be connected to fewer or more endpoints. ODN 120 has a tree structure comprising optical feeder fibers 121, one or more passive optical splitters / multiplexers 123, and several optical distribution fibers or drop fibers 124, 125, 126, 127 connecting the splitters / multiplexers 123 to their respective ONUs 131, 132, 133, and 134. Downstream, the passive optical splitter / multiplexer 123 splits the optical signal coming from OLT 110 into lower-power optical signals for the connected ONUs 131, 132, 133, and 134, and upstream, the passive optical splitter / multiplexer 123 multiplexes the optical signals coming from the connected ONUs 131, 132, 133, and 134 into burst signals for OLT 110.

[0046] The passive optical network 100 may be a gigabit passive optical network GPON conforming to the ITU-T G.984 standard, a 10x gigabit passive optical network 10G-PON conforming to the ITU-T G.987 standard, a 10G symmetric XGS-PON conforming to the ITU-T G.9807 standard, a 4-channel 10G symmetric NG-PON2 conforming to the ITU-T G.989 standard, a 25GS-PON conforming to the ITU-T G.9804 standard, a 50G-PON, or a next-generation passive optical network NG-PON. The passive optical network 100 can perform time-division multiplexing (TDM) or time-wavelength division multiplexing (TWDM).

[0047] The OLT110 further comprises a burst-mode receiver 111 configured to receive and decode upstream optical burst signals transmitted by connected ONUs 131, 132, 133, and 134. For this purpose, the burst-mode receiver 111 typically comprises burst-mode receiver components, which can be analog and / or digital circuits. The burst-mode receiver components are typically interconnected to form a sequence or pipeline, with each component contributing to the decoding of the optical burst signal. Thus, the burst-mode receiver 111 generates a decoded output signal, i.e., a digital signal. The decoded output signal may include, for example, bits, symbols, or log-likelihood ratio values ​​llr. This output signal may further be provided to one or more higher-layer circuits within the OLT110 configured to utilize or process the decoded burst data.

[0048] It may be desirable for the ONUs 131-134 in the PON 100 to be able to transmit optical burst signals to the OLT 110 at multiple different symbol rates. Therefore, the symbol rate of the optical burst signals received by the OLT 110, and consequently by the burst-mode receiver 111, may vary. Typically, the digital burst-mode receiver components within the burst-mode receiver 111 are configured to operate at a fixed processing speed. Processing speed refers to the rate at which input samples are processed by each burst-mode receiver component within the burst-mode receiver 111, and / or the rate at which output samples are generated by said components. Therefore, the processing speed of the burst-mode receiver components can determine the throughput of the burst-mode receiver 111, i.e., the sample rate of the decoded output signal.

[0049] Receiving multi-rate optical burst signals with a typical fixed-rate digital burst-mode receiver component presents the problem of oversampling of lower-rate optical burst signals. This limits the energy efficiency of the burst-mode receiver 111 because the burst-mode receiver component continues to operate at full processing speed even when the optical burst signal has a lower rate. A further problem is that some burst-mode receiver components may not be able to process multi-rate optical burst signals because they require an input signal of a predetermined rate. In addition, burst-mode receivers in newer PON systems, such as 50G-PON according to the ITU-T G.9804 standard, typically feature more complex digital burst-mode receiver components with digital signal processing functions, such as equalizers. Such digital burst-mode receiver components with digital signal processing functions are sometimes referred to as digital signal processing (DSP) circuits. A burst-mode receiver containing a DSP circuit, i.e., a digital burst-mode receiver component, is sometimes referred to as a digital burst-mode receiver.

[0050] Therefore, it is desirable to enable energy-efficient reception and decoding of optical burst signals having different symbol rates. The following description describes exemplary embodiments of optical line termination equipment (OLT) equipped with a burst-mode receiver capable of receiving and decoding multi-rate optical burst signals in an energy-efficient manner.

[0051] Figure 2 shows an exemplary embodiment of a burst-mode receiver 111 configured to decode an optical burst signal 210 transmitted from an ONU into a decoded output signal 220 by one or more analog circuits 200 and one or more digital signal processing circuits 201, 202, 203, 204 that process signals 210, 207, 208, 209 within the OLT at their respective configurable processing speeds. The optical burst signal 210 is first processed by circuit 200 so that the optical signal 210 can be converted into an analog signal such as a voltage or current. Circuit 200 may comprise, for example, a photodiode and a transimpedance amplifier. The digital signal processing DSP circuits 201, 202, 203, 204 are interconnected such that each processing performed by each DSP circuit 201, 202, 203, 204 contributes to the decoding of the optical burst signal 210 into the decoded output signal 220. In other words, the DSP circuits 201, 202, 203, and 204 form the data path of a functional unit for decoding the optical burst signal 210 into the decoded output signal 220.

[0052] Each DSP circuit 201, 202, 203, and 204 processes an input signal into an output signal at its respective configurable processing speed; for example, DSP circuit 202 processes input signal 207 into output signal 208. The configurable processing speeds of DSP circuits 201, 202, 203, and 204 refer to the speed at which the input sample is processed by the DSP circuit and / or the speed at which the output sample is generated. Since DSP circuits 201, 202, 203, and 204 form a sequence or pipeline, it is clear that the output of a DSP circuit, for example, the output signal 207 of DSP circuit 201, can become the input to the next DSP circuit in the data path, for example, 202.

[0053] The DSP circuits 201, 202, 203, and 204 may be, for example, an analog-to-digital converter 201, a clock data recovery device 202, an equalizer 203, and / or a decoder 204. It will be clear that the configurable processing speed of a DSP circuit receiving an analog input signal, such as the analog-to-digital converter 201, cannot be defined by the speed at which the input sample is processed by the DSP circuit, since the analog input signal does not contain digital samples. The burst-mode receiver 111 may further include one or more burst-mode receiver components without configurable processing speeds, such as fixed-speed analog burst-mode receiver components, within the data path for decoding the optical burst signal.

[0054] The burst-mode receiver 111 further comprises means 205 configured to acquire the symbol rate 240 of the next optical burst signal 215. The next optical burst signal 215 is the temporally next optical burst signal received by the OLT, i.e., the first subsequent optical burst signal. The optical burst signal 211 preceding the next optical burst signal 215 is referred to as the preceding optical burst signal 211. In other words, the preceding optical burst signal 211 is the last optical burst signal received. Thus, the preceding optical burst signal 211 and the next optical burst signal 215 are temporally consecutive.

[0055] The optical burst signals 211, 215 may include preambles 212, 216; delimiters 213, 217; and payloads 214, 218. Delimiters 213, 217 indicate the start of payloads 214, 218. Payloads 214, 218 may include, for example, message data, error correction data, parity data, control data, and idle data. The optical burst signals 211, 215 may have different symbol rates. For example, burst signal 211 may be a 25G non-zero-return NRZ signal; or burst signal 215 may be a 50G NRZ signal or a 100G PAM4 signal. Thus, means 205 is configured to acquire the symbol rate 240 of the next optical burst signal 215 expected to arrive at the OLT, i.e., the burst-mode receiver 111.

[0056] Obtaining this symbol rate 240 may include determining the symbol rate of the next optical burst signal 215 based on the upstream transmission schedule. The upstream transmission schedule can assign symbol rates to scheduled upstream transmissions, i.e., optical burst signals, originating from ONUs in the network. Since the upstream transmission schedule is usually determined by the OLT or by a scheduler within the OLT, the symbol rate 240 of the next optical burst signal 215 can simply be determined from this schedule. Alternatively, or complementaryly, the OLT can assign the transmission opportunity of the received optical burst signal 210 to the respective ONU associated with each symbol rate. In other words, the OLT can associate the optical burst signal 210 with a specific ONU based on the upstream transmission schedule, the OLT can recognize the symbol rate assigned to this ONU, and thereby obtain the symbol rate of the next optical burst signal.

[0057] Means 205 are further configured to adjust the configurable processing speed of one or more DSP circuits 201, 202, 203, 204 based on the symbol rate 240 of the next optical burst signal 215 during the interval 240 between the reception of valuable symbols in the preceding optical burst signal 211 and the next optical burst signal 215.

[0058] Valuable symbols within the optical burst signals 211, 215 are symbols associated with valuable burst data 222, 224, i.e., valuable or relevant decoded data. Valuable symbols may include symbols corresponding to the payloads 214, 218 and delimiters 213, 217 of the optical burst signals. In addition, valuable symbols may be included within part 242 of the preamble 216. The location of symbols considered valuable may be predetermined or provisioned, for example, according to network requirements or network protocols.

[0059] Figure 2 illustrates a temporal example of the configurable processing speed 230 of DSP circuits 201, 202, 203, and 204, where the symbol rate of the next optical burst signal 215 is higher than the symbol rate of the preceding optical burst signal 211. The configurable processing speed 230 is adjusted at time step 234 from a lower configurable processing speed 233 to a higher configurable processing speed 235 based on the symbol rate 240 of the next optical burst signal 215.

[0060] By adjusting the configurable processing speed of one or more DSP circuits 201, 202, 203, and 204 based on the symbol rate 240 of the next optical burst signal 215, the DSP circuits can be optimized for the symbol rate of the next optical burst signal. This has the advantage of improving the power consumption of the burst mode receiver 111 and, consequently, the OLT, because the DSP circuits can operate at an improved processing speed for the received optical burst signal 210. In other words, it prevents the optical burst signal 210 from being processed at an excessively high sampling rate by one or more DSP circuits 201, 202, 203, and 204, thus avoiding wasted power consumption. A further advantage is that the configurable processing speed of each DSP circuit 201, 202, 203, and 204 can be adjusted in real time, i.e., between incoming optical burst signals 210.

[0061] Adjusting the configurable processing speed is done during the interval 240 between the reception of valuable symbols in consecutive optical burst signals 211, 215. Therefore, no valuable symbols arrive or are not received by the OLT during interval 240, and thus, a portion of the decoded output signal 220 associated with interval 240 may substantially lack valuable burst data, as shown by periods 221 and 223 in Figure 2.

[0062] Since samples in the decoded output signal 220 may be invalid during the period following adjustment of the configurable processing speed 232, 234, it is possible to avoid the misdecoding of these valuable symbols by adjusting the configurable processing speed of one or more of the respective DSP circuits 201, 202, 203, 204 during the interval 240 between the reception of valuable symbols in consecutive optical burst signals 211, 215. This has the advantage that data loss and data modification can be avoided when switching between configurable processing speeds.

[0063] The interval 240 may include a guard time 241 between the preceding optical signal 211 and the following optical signal 215. The guard time 241 is a period that provides a safety margin against interference between consecutive optical burst signals 211, 215 arriving at the OLT. Therefore, no valuable burst data is received by the OLT during the guard time 241. Alternatively, or complementaryly, the interval 240 may include a portion of the preamble 216 of the following optical burst signal 215. For example, the beginning portion 242 of the preamble 216 of the optical burst signal 215 may include samples for tuning the burst-mode receiver 111, i.e., worthless symbols in which the burst data in the decoded output signal 220 is irrelevant or not needed.

[0064] Means 205 may be further configured to determine the interval 240 based on burst timing information 250 of the optical burst signal 210. The burst timing information 250 may be, for example, the start time and duration of the burst, and this burst timing information may be included in the upstream transmission schedule of the OLT. The burst timing information may be provided by another circuit within the OLT, such as a scheduler, or by an external circuit. This makes it possible to determine when adjustments to the configurable processing speed can be performed without data loss.

[0065] Means 205 may comprise at least one processor and at least one memory. Computer program code may be included in the memory, and according to the embodiment, if performed by the processor, means 205 may adjust the configurable processing speed of one or more DSP circuits based on the symbol rate of the next optical burst signal. Means 205 may be, for example, a controller circuit.

[0066] Figure 3A shows an exemplary embodiment of a burst-mode receiver 111 in an OLT where adjusting the configurable processing speed includes adjusting the clock frequency of one or more DSP circuits 201, 202, 203, and 204. Clock signals 302 can be applied to the DSP circuits 201, 202, 203, and 204 to operate them at their respective clock frequencies, i.e., to cause the DSP circuits to process signals at their respective clock frequencies. In other words, the clock signals 302 applied to the DSP circuits 201, 202, 203, and 204 can determine their configurable processing speeds. Therefore, adjusting the configurable processing speeds of the DSP circuits 201, 202, 203, and 204 may include adjusting the respective clock frequencies of each DSP circuit.

[0067] This can be achieved by modifying the 303 clock signal 302 applied to each of the DSP circuits 201, 202, 203, and 204, for example, using a clock divider circuit 301. In other words, the burst mode receiver 111 may include a clock divider circuit 301 configured to adjust or modify the clock signal 302 applied to one or more of the DSP circuits 201, 202, 203, and 204. Means 205 may be configured to control the clock divider circuit 301. This can be achieved by providing the clock divider circuit 301 with a control signal 305 including a configurable processing speed for processing the next optical burst signal.

[0068] Figure 3A shows an exemplary embodiment in which the clock signal 302 applied to all DSP circuits 201, 202, 203, and 204 is regulated; however, it will be clear that the regulated clock signal 303 can also be applied to any number of DSP circuits 201, 202, 203, and 204. For example, Figure 3B shows an exemplary embodiment in which the regulated clock signal 303 is applied only to DSP circuits 202, 203, and 204. The unmodified clock signal 302 is applied to DSP circuit 201, allowing this circuit to operate at a fixed processing speed.

[0069] Thus, the DSP circuit 201 outputs sample 312 at a fixed rate. To allow the other DSP circuits 202, 203, and 204 to operate at lower configurable processing speeds, the burst-mode receiver 111 may further include at least one downsampling circuit 311. The circuit 311 may be configured to downsample the signal 312, that is, to convert a signal 312 having a certain sampling rate into a signal 313 having a lower sampling rate to match the configurable processing speed of the subsequent DSP circuits 202, 203, and 204. The signal 312 to be downsampled may be the output of the preceding interconnected DSP circuit 201.

[0070] Means 205 may be further configured to control the downsampling circuit 311 according to a desired rate of signal 313 based on the configurable processing speeds of the DSP circuits 202, 203, and 204. This can be achieved by providing the downsampling circuit 311 with a control signal 305 that includes a configurable processing speed for processing the next optical burst signal. The downsampling circuit 311 can be controlled, for example, by enabling the downsampling circuit, disabling the downsampling circuit, or modulating the amount of downsampling. In other words, the downsampling circuit 311 may be configurable.

[0071] Figure 4A shows an exemplary embodiment of a burst-mode receiver 111 in an OLT, including at least one upsampling circuit 401. The upsampling circuit 401 may be configured to upsample a signal 402, i.e., to convert a signal 402 having a certain sampling rate to a signal 403 having a higher sampling rate. In the exemplary embodiment shown in Figure 4A, the upsampling circuit is located at the end of a processing data path or pipeline. This allows the signal 402 to be upsampled to an appropriate rate for further circuits 404 in the OLT connected to the burst-mode receiver 111, for example, for higher-layer processing circuits and / or interface circuits in the OLT. Alternatively, or complementaryly, the upsampling circuit 401 may be located before burst-mode receiver components or DSP circuits that require an input signal of a predetermined rate, for example, between DSP circuits 201 and 202. In other words, the upsampling circuit may be configured to upsample a signal to a predetermined sampling rate that depends on the receiving end of the upsampled signal, for example, further circuits 404, burst-mode receiver components, or DSP circuits.

[0072] Means 205 may be further configured to control the upsampling circuit 401 according to a desired rate of signal 403. This can be achieved by providing the upsampling circuit 401 with a control signal 305 including a configurable processing rate for processing the next optical burst signal. The upsampling circuit 401 can be controlled, for example, by enabling the upsampling circuit, disabling the upsampling circuit, or modulating the amount of upsampling. In other words, the upsampling circuit 401 may be configurable.

[0073] The upsampling circuit 401 may be further configured to upsample the signal to a predetermined sampling rate. The predetermined sampling rate may be determined by a circuit or processing block that receives the upsampled signal 403, such as the next burst-mode receiver component in the data path, the next DSP circuits 201, 202, 203, 204 in the data path, the upper-layer processing circuit 404 in the OLT, or the interface circuit 404 between the burst-mode receiver in the OLT and the upper-layer processing circuit.

[0074] Figure 4B shows an exemplary embodiment of a burst-mode receiver 111 in the OLT, where adjusting the configurable processing speed includes enabling and / or disabling one or more parallel circuit instances 201a, 201b, 201c, 202a, 202b, 202c, 203a, 203b, 203c, 204a, 204b, 204c of one or more DSP circuits 201, 202, 203, 204.

[0075] In other words, each of the DSP circuits 201, 202, 203, and 204 within the burst-mode receiver 111 may include one or more parallel circuit instances of the digital signal processing circuit. Each of the parallel circuit instances 201a, 201b, 201c, 202a, 202b, 202c, 203a, 203b, 203c, 204a, 204b, and 204c can operate at a nominal clock speed or frequency, i.e., a fixed processing speed. Therefore, by enabling or disabling the parallel circuit instances of each DSP circuit in the signal data path, the configurable processing speed of each digital signal processing circuit can be increased or decreased, respectively. That is, the configurable processing speed of the DSP circuits 201, 202, 203, and 204 can be adjusted.

[0076] For example, if all three parallel circuit instances 204a, 204b, and 204c of the DSP circuit 204 are enabled, the DSP circuit 204 will operate at its maximum configurable processing speed. Disabling one parallel circuit instance, for example 204a, can reduce the configurable processing speed by one-third, and disabling two parallel circuit instances, for example 204a and 204b, can reduce the configurable processing speed by two-thirds.

[0077] It will be apparent that the configurable processing speed of one or more DSP circuits 201, 202, 203, 204 in the burst-mode receiver 111 can be adjusted by adjusting the clock frequency as described in relation to Figures 3A and 3B; and the configurable processing speed of other DSP circuits 201, 202, 203, 204 in the receiver 111 can be adjusted by enabling and / or disabling parallel circuit instances as described in relation to Figure 4B. It will be even more apparent that the configurable processing speed of a DSP circuit, for example 202, can be adjusted by a combination of adjusting the clock frequency of that DSP circuit and enabling and / or disabling parallel circuit instances 202a, 202b, 202c of that DSP circuit.

[0078] When adjusting the configurable processing speed of DSP circuits 201, 202, 203, and 204, the latency or processing delay of those DSP circuits 201, 202, 203, and 204 may change. For example, increasing the configurable processing speed may decrease the latency. Therefore, the burst-mode receiver 111 may further include at least one latency compensator circuit 401, 410 configured to adjust the latency of signals 402, 411, i.e., to increase and / or decrease the latency of signals 402, 411. This allows for compensation of latency changes when adjusting the configurable processing speed of one or more DSP circuits 201, 202, 203, and 204. It will be clear that circuit 401 in Figure 4A may be a latency compensator circuit that replaces or is additional to an upsampling circuit.

[0079] In the exemplary embodiments shown in Figures 4A and 4B, latency compensator circuits 401, 410 are located at the end of the processing data path or pipeline of the burst-mode receiver 111. This allows for compensation of changes in the end-to-end latency of the burst-mode receiver 111 associated with adjusting the configurable processing speed of one or more DSP circuits 201, 202, 203, 204. The end-to-end latency of the digital burst-mode receiver 111 may refer to the processing time required to decode symbols in the optical burst signal 210 into one or more bits in the decoded output signal 220. This has the advantage that the latency or processing delay of the burst-mode receiver 111 can be controlled. This has the further advantage that when adjusting the configurable processing speed of one or more DSP circuits 201, 202, 203, 204, the latency or processing delay of the burst-mode receiver 111 can be made substantially stable in time, i.e., kept constant. The latency compensator circuits 401 and 410 may be further configured to adjust the latency of the signal to a predetermined latency based on the receiving side of the latency-adjusted signal, for example, a further circuit 404 or a DSP circuit.

[0080] Figure 5A shows an example of how the end-to-end latency 551a, 552a, and 553a of a burst-mode receiver can be changed by adjusting the configurable processing speeds 561, 562, and 563 of one or more DSP circuits in the burst-mode receiver without a latency compensator circuit. At time step 571, i.e., during the interval between receiving valuable symbols in the preceding optical burst signal 510 and the next optical burst signal 520, the configurable processing speed 230 of one or more DSP circuits can be reduced from processing speed 561 to processing speed 562. This results in a change in end-to-end latency from latency 551a to latency 552a, i.e., an increase in processing delay. Similarly, increasing the configurable processing speed 230 of one or more DSP circuits from processing speed 562 to processing speed 563 at time step 572 can result in a change in end-to-end latency from latency 552a to latency 553a, i.e., a decrease in processing delay.

[0081] Figure 5B shows an example of latency adjustment performed by the latency compensator circuit 410. The latency compensator circuit may be configured to drop one or more non-payload samples 543 from the decoded output signal 220 during the interval between receiving valuable symbols in the preceding optical burst signal 510 and the following optical burst signal 520. The non-payload samples 543 may be samples or bits included in a portion of the decoded output signal 220 associated with the interval, i.e., in portion 543. In this way, the end-to-end latency 551b, 552b can be maintained when adjusting the configurable processing speed. This allows changes in end-to-end latency to be compensated without significantly impacting the system, for example, without affecting further circuitry in the OLT connected to the burst-mode receiver 111.

[0082] The latency compensator circuit 410 may be further configured to insert one or more dummy samples 555 into the decoded output signal 220 during the interval between the reception of valuable symbols in the preceding optical burst signal 520 and the following optical burst signal 530. Thus, the dummy samples 555 may be inserted into a portion of the decoded output signal 220 associated with the interval, i.e., portion 545. In this way, the end-to-end latency 552b, 553b can be maintained when adjusting the configurable processing speed. This allows changes in end-to-end latency to be compensated without significantly impacting the system, for example, without affecting downstream circuitry in the OLT connected to the burst-mode receiver 111.

[0083] A further advantage is that data loss and data modification can be avoided during latency adjustments because the insertion of dummy sample 554 or the dropping of non-payload sample 555 is performed during intervals without valuable symbols.

[0084] The maximum change in the end-to-end latency of a burst-mode receiver may occur by adjusting the configurable processing speed of one or more DSP circuits between the highest and lowest processing speeds supported by the OLT. Therefore, the OLT may be further configured to schedule the guard time 580 between consecutive optical burst signals 510, 520 to the minimum length, such that the decoded output signal 220 includes at least sufficient non-payload bits 545 to compensate for the change in the end-to-end latency of the burst-mode receiver associated with the adjustment of the configurable processing speed between the highest and lowest processing speeds supported by the OLT. In other words, the guard time 580 may be scheduled to compensate for this maximum change in end-to-end latency by dropping all necessary samples within the guard time.

[0085] Returning to Figure 4B, it will become clear that the latency compensator circuit 410 may also be located at another point in the processing data path or pipeline of the burst-mode receiver 111, for example, between the DSP circuits 202 and 203.

[0086] Therefore, the dummy samples inserted by the latency compensator circuit 410 can be any data unit depending on the signal being adjusted for latency. For example, when inserting dummy samples into the decoded output signal 220, the dummy samples can be dummy bits or dummy symbols, depending on whether the decoded output signal contains bits or symbols. Similarly, the non-payload samples dropped by the latency compensator circuit 410 can be any data unit, such as non-payload bits or non-payload symbols, depending on the signal being adjusted for latency.

[0087] Means 205 may be further configured to control the latency compensator circuit 410 according to the latency of a desired signal, for example, by enabling the latency compensator circuit, disabling the latency compensator circuit, or modulating the amount of latency adjustment. In other words, the latency compensator circuit may be configurable.

[0088] Figure 6 shows a suitable computing system 600 that enables the implementation of an embodiment of a method for managing the coordination of one or more burst-mode receiver components in an optical line termination device. The computing system 600 may generally be formed as a suitable general-purpose computer and comprises a bus 610, a processor 602, local memory 604, one or more optional input interfaces 614, one or more optional output interfaces 616, a communication interface 612, a memory element interface 606, and one or more memory elements 608. The bus 610 may comprise one or more conductors enabling communication between components of the computing system 600. The processor 602 may include any type of conventional processor or microprocessor that interprets and executes program instructions. The local memory 604 may include random-access memory (RAM) or other type of dynamic memory device that stores information and instructions for execution by the processor 602, and / or read-only memory (ROM) or other type of static memory device that stores static information and instructions for use by the processor 602. The input interface 614 may include one or more conventional mechanisms that enable an operator or user to input information into the computing device 600, such as a keyboard 620, a mouse 630, a pen, a voice recognition and / or biometric mechanism, or a camera. The output interface 616 may include one or more conventional mechanisms that output information to an operator or user, such as a display 640. The communication interface 612 may include any transceiver mechanism, such as one or more Ethernet interfaces, that enables the computing system 500 to communicate with other devices and / or systems, such as one or more DSP circuits 201, 202, 203, 204. The communication interface 612 of the computing system 600 may be connected to such other computing systems by a local area network (LAN) or a wide area network (WAN), such as the Internet.The storage element interface 606 provides a storage interface, such as a SATA interface or a Small Computer System Interface (SCSI), for connecting the bus 610 to one or more local disks, such as one or more storage elements 608, such as Serial Advanced Technology Attachment (SATA) disk drives, and can control the writing of data to and / or reading of data from these storage elements 608. Although the storage elements 608 described above are local disks, any other suitable computer-readable media can be used, such as removable magnetic disks, optical storage media such as CDs or DVDs, ROM disks, solid-state drives, or flash memory cards. Thus, the computing system 600 may correspond to the controller circuit 205 in the embodiment shown in Figure 2.

[0089] As used in this application, the term “circuit” may refer to one or more, or all of the following: (a) Hardware-only circuit implementations, such as implementations in simple analog and / or digital circuits. (b) The following combinations of hardware circuits and software (if applicable): (i) A combination of analog and / or digital hardware circuits and software / firmware. (ii) Any part of a hardware processor (including a digital signal processor), software, and memory that work together to enable a device such as a mobile phone or server to perform various functions. (c) Hardware circuits and / or processors, such as a microprocessor or part of a microprocessor, that require software (e.g., firmware) to operate but may not be present when not required for operation.

[0090] This definition of circuit applies to all use of this term in this application, including in the claims. In further examples, as used in this application, the term circuit also covers a hardware circuit or processor (or more processors), or a part of a hardware circuit or processor and any accompanying software and / or firmware implementation. The term circuit also covers, for example, a baseband integrated circuit or processor integrated circuit for a mobile device, or a similar integrated circuit in a server, cellular network device, or other computing device or network device, as applicable to a particular claim element.

[0091] While the present invention has been described with reference to specific embodiments, it will be apparent to those skilled in the art that the invention is not limited to the details of the exemplary embodiments described herein, and that the invention can be embodied in various modified and altered forms without departing from its scope. Therefore, these embodiments are considered illustrative and non-limiting in all respects, and the scope of the invention is indicated not by the foregoing description but by the appended claims, and thus all modifications that fall within the meaning and scope of the claims and their equivalents are intended to be encompassed therein. In other words, it is intended to cover all modifications, alterations, or equivalents that fall within the scope of fundamental principles and whose essential attributes are claimed in this patent application.

[0092] Readers of this patent application will further understand that the phrases “comprising” or “comprises” do not exclude other elements or steps, that the phrases “a” or “an” do not exclude multiple things, and that a single element, such as a computer system, processor, or other integrated unit, may perform the functionality of several means described in the claims. No reference numeral in the claims shall be construed as limiting the respective claim to which it pertains. Terms such as “first,” “second,” “third,” “a,” “b,” and “c,” when used herein or in the claims, are introduced to distinguish similar elements or steps and do not necessarily describe a sequential or chronological order. Similarly, terms such as “top,” “bottom,” “over,” and “under” are introduced for descriptive purposes and do not necessarily indicate relative positions. In other words, the terms used herein are interchangeable under appropriate circumstances, and it should be understood that embodiments of the present invention may operate in a different sequence or direction than those described or illustrated above. [Explanation of Symbols]

[0093] 100 Passive Optical Networks 110 Optical Network Terminal (OLT) 111 Burst Mode Receiver 120 Optical Distribution Network ODN 121 Optical feeder fiber 123 Passive Optical Splitter / Multiplexer 124, 125, 126, 127 Optical distribution fiber or drop fiber 131, 132, 133, 134 Optical Network Unit (ONU) 200 Analog Circuits 201a, 201b, 201c, 202a, 202b, 202c, 203a, 203b, 203c, 204a, 204b, 204c Parallel Circuit Instances 205 means 207 Input signal 208 Output Signals 209, 312, 402 signals 210 Optical burst signal 211, 510 Leading optical burst signal 212, 216 Preamble 213, 217 Delimiters 214, 218 payloads 215, 520 Next optical burst signal 220 Decoded output signal 221, 223 period 222,224 Valuable burst data 230 configurable processing speeds 232 Adjust 233 Low configurable processing speed 234 Adjusting the time step 235 High configurable processing speed 241, 580 Guard Time 242 Part of the preamble 250 Burst Timing Information 301 Clock Divisor Circuit 302 Clock signal 303 Adjust the clock frequency 305 Control signal 311 Downsampling Circuit Signals with a sampling rate lower than 313 401 Upsampling circuit, latency compensator circuit Signals with a sampling rate higher than 403 404 Further circuits, higher-layer processing circuits, interface circuits 410 Latency Compensator Circuit 411 Signal 543 Non-payload samples 545 non-payload bits 551a, 552a, 553a, 551b, 552b, 553b End-to-end latency 561, 562, 563 Configurable processing speeds 571, 572 time step 600 Computing Systems 602 Processors 604 Local memory 606 Memory Element Interface 608 memory elements 610 Bus 612 Communication Interface 614 Input Interfaces 616 Output Interface 620 keyboards 630 mice

Claims

1. An optical line termination device (110) OLT configured to communicate with one or more optical network units (131-134) ONUs in a passive optical network (100), comprising a burst mode receiver (111) configured such that optical burst signals (210) transmitted by one or more ONUs have their respective symbol rates, and the optical line termination device decodes the optical burst signals from the ONUs into decoded output signals (220) by one or more digital signal processing circuits (201, 202, 203, 204) that process the signals at their respective configurable processing speeds, wherein the optical line termination device - To obtain the symbol rate (240) of the next optical burst signal (215), - During the interval (240) between the reception of valuable symbols in a preceding optical burst signal (211) and in the next optical burst signal (215), the configurable processing speed (230) of one or more digital signal processing circuits is adjusted (234) based on the symbol rate (240) of the next optical burst signal (215). The system includes means (205) configured to perform the following: Adjusting the configurable processing speed of one or more digital signal processing circuits includes adjusting the clock frequency of one or more digital signal processing circuits (303), or Optical line termination device (110) OLT, wherein adjusting the configurable processing speed of each digital signal processing circuit (202) includes enabling and / or disabling one or more parallel circuit instances (202a, 202b, 202c) of each digital signal processing circuit.

2. The optical line termination device (OLT) according to claim 1, wherein the interval (240) includes a guard time (241) between a preceding optical burst signal (211) and a subsequent optical burst signal (215), and / or a portion (242) of the preamble (216) period within the subsequent optical burst signal (215).

3. The optical line termination device (OLT) according to claim 1 or 2, further comprising a burst-mode receiver (111) further comprising at least one downsampling circuit (311) configured to downsample a signal (312).

4. The optical line termination device (OLT) according to claim 1 or 2, further comprising a burst-mode receiver (111) and at least one upsampling circuit (401) configured to upsample a signal (402).

5. The optical line termination (OLT) according to claim 1 or 2, further comprising at least one latency compensator circuit (410) configured to adjust the latency of a signal (411).

6. The optical line termination (OLT) according to claim 5, wherein the latency compensator circuit (410) is further configured to insert one or more dummy samples (554) into the signal (220) or drop one or more non-payload samples (545) from the signal (220) during the interval between the reception of valuable symbols in a preceding optical burst signal (510) and a subsequent optical burst signal (520).

7. The optical line termination device OLT according to claim 3, wherein the means (205) is further configured to control at least one downsampling circuit (311) based on the symbol rate (240) of the next optical burst signal.

8. The optical line termination device OLT according to claim 4, wherein the means (205) is further configured to control at least one upsampling circuit (401) based on the symbol rate (240) of the next optical burst signal.

9. The optical line termination (OLT) according to claim 5, wherein the means (205) is further configured to control at least one latency compensator circuit (410) based on the symbol rate (240) of the next optical burst signal.

10. The optical line termination device OLT according to claim 4, wherein the upsampling circuit (401) is further configured to upsample the signal (402) to a predetermined data rate.

11. The optical line termination device (OLT) according to claim 5, wherein a latency compensator circuit (410) is further configured to adjust the latency of a signal (411) to a predetermined latency.

12. The optical line termination device (OLT) according to claim 1 or 2, wherein one or more digital signal processing circuits are selected from the group consisting of an analog-to-digital converter (201), a clock data recovery device (202), an equalizer (203), and / or a decoder (204).

13. The optical line termination device (OLT) according to claim 1 or 2, wherein means (205) is further configured to determine an interval (240) between the reception of a value symbol in a preceding optical burst signal (211) and in a subsequent optical burst signal (215) based on burst timing information (250) of optical burst signals (211, 215).

14. The optical line termination (OLT) according to claim 1 or 2, further comprising obtaining the symbol rate (240) of the next optical burst signal, and determining the symbol rate based on the upstream transmission schedule.

15. - To obtain the symbol rate (240) of the next optical burst signal (215), - During the interval (240) between the reception of valuable symbols in the preceding optical burst signal (211) and the following optical burst signal (215), adjust (234) the configurable processing speed (230) of one or more digital signal processing circuits (201, 202, 203) in the optical line termination device (110) OLT based on the symbol rate of the following optical burst signal. Includes, The OLT is configured to communicate with one or more optical network units (131-134) ONUs in a passive optical network, and the optical burst signals (210) transmitted by one or more ONUs each have their own symbol rates, and the burst mode receiver is configured to decode the optical burst signals from the ONUs into decoded output signals (220) by one or more digital signal processing circuits that process the signals at their respective configurable processing speeds. Adjusting the configurable processing speed of one or more digital signal processing circuits includes adjusting the clock frequency of one or more digital signal processing circuits (303), or A method comprising adjusting the configurable processing speed of each digital signal processing circuit (202), which includes enabling and / or disabling one or more parallel circuit instances (202a, 202b, 202c) of each digital signal processing circuit.

16. A method implemented by a computer, - To obtain the symbol rate of the next optical burst signal, - During the interval (240) between the reception of valuable symbols in the preceding optical burst signal (211) and the following optical burst signal (215), adjust the configurable processing speed (230) of one or more digital signal processing circuits in the optical line termination device (110) OLT based on the symbol rate of the following optical burst signal (232, 234) Includes, The OLT is configured to communicate with one or more optical network units (131-134) ONUs in a point-to-multipoint optical network, and optical burst signals (210) transmitted by one or more ONUs each have their own symbol rate, and the burst mode receiver is configured to decode the optical burst signals from the ONUs into decoded output signals (220) by one or more digital signal processing circuits that process the signals at their respective configurable processing speeds. Adjusting the configurable processing speed of one or more digital signal processing circuits includes adjusting the clock frequency of one or more digital signal processing circuits (303), or A computer implementation method wherein adjusting the configurable processing speed of each digital signal processing circuit (202) includes enabling and / or disabling one or more parallel circuit instances (202a, 202b, 202c) of each digital signal processing circuit.

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