Radiation imaging device and radiation imaging system

Abstract

The present invention provides a radiography apparatus and system that can suppress the visibility of line noise caused by analog binning readout while maintaining a high frame rate. [Solution] A radiation imaging apparatus comprising: a plurality of pixels arranged in a matrix, each having a conversion element and a switch element that convert radiation or light into electric charge; a drive unit that outputs a drive signal to drive the switch element; and a readout unit that reads electric charge from the pixels to which the drive signal is supplied and generates an image data signal, wherein the output of a first drive signal to a first drive line and the output of a second drive signal to a second drive line adjacent to the first drive line are performed with a timing difference to reduce line noise along the drive line, and the first charge read from the pixel by the first drive signal and the second charge read from the pixel by the second drive signal are added together to generate an image data signal.

Description

Technical Field

[0001] The present invention relates to a radiation imaging apparatus and a radiation imaging system that acquire an intensity distribution of radiation transmitted through a subject as an image.

Background Art

[0002] In recent years, as imaging apparatuses used for medical image diagnosis and non-destructive inspection using X-rays, radiation imaging apparatuses using a flat panel detector (hereinafter abbreviated as FPD) formed of a semiconductor material have been put into practical use.

[0003] This FPD is composed of a photodiode mainly made of amorphous silicon and a switching element (TFT) arranged on an insulating substrate such as a glass substrate. Radiation such as X-rays transmitted through a subject such as a patient is converted into a charge signal by the FPD, the charge signal is subjected to analog-to-digital conversion, and a transmission image of the subject can be acquired as a digital image. In recent years, switching elements (TFTs) may instead of amorphous silicon, be configured mainly with IGZO as the main material in some cases.

[0004] Radiography using an FPD can perform not only still image capturing but also moving image capturing in which images are read out at high speed. In moving image capturing, it is required to read out images at high speed and achieve a high frame rate.

Prior Art Literature

Patent Literature

[0005]

Patent Literature 1

Summary of the Invention

Problem to be Solved by the Invention

[0006] In a radiation imaging device, multiple pixels arranged in a matrix are connected by wiring extending in the row direction (drive lines) and wiring extending in the column direction (signal lines). An ON signal is supplied from the drive circuit via the drive lines, and image data is read from the pixel to which the ON signal is supplied via the signal lines. By sequentially switching the drive lines in this operation, a radiation image is generated.

[0007] In such radiation imaging devices, a binning process that combines multiple pixels into one pixel has been disclosed as a means of achieving high-frame-rate video recording, and this is also described as a known technique in Patent Document 1. In the binning process, for example, the drive circuit 210 simultaneously applies an ON signal to the drive lines of the first and second rows, thereby simultaneously closing the switch elements of the pixels located in the first and second rows, and transferring the pixel signals for both rows together to the signal line. This is called analog binning, and it makes it possible to read out two rows of data at once, so the time required for reading can be halved, and a higher frame rate can be achieved compared to when analog binning is not performed. In addition, the radiation image read out in this way is reduced only in the column direction, so by applying digital binning, which adds or averages the pixel values ​​in the row direction to this image, an image with the correct reduction ratio can be generated.

[0008] However, it was found that when performing this binning, especially analog binning, line-shaped noise (hereinafter referred to as line noise) in the row direction can be visible depending on the state of the drive circuit and each drive line during readout. As a result, when attempting to achieve a high frame rate by reading out two or more rows using the conventional analog binning method, line noise becomes visible, resulting in the generation of images unsuitable for diagnostic purposes.

[0009] Therefore, in view of the above problems, the present invention aims to provide a radiographic imaging apparatus and system that can suppress the visibility of line noise caused by analog binning readout while maintaining a high frame rate. [Means for solving the problem]

[0010] The present invention, which solves the above problems, is a radiation imaging apparatus comprising: a plurality of pixels arranged in a matrix, each having a conversion element that converts radiation or light generated by radiation irradiation into electric charge and a switch element that controls the output of electric charge from the conversion element; a drive unit that outputs a drive signal to drive the switch element; a plurality of drive lines that connect the drive unit and the pixels row by row and supply the drive signal output by the drive unit to the switch element; and a readout unit that reads electric charge from the pixels to which the drive signal has been supplied and generates an image data signal, wherein The drive unit outputs a first drive signal to the first of the multiple drive lines after radiation irradiation, and a second drive signal to the second drive line adjacent to the first drive line, with the high-level period of the first drive signal and the high-level period of the second drive signal staggered to reduce line noise along the drive line. The readout unit is characterized by generating an image data signal by summing a first charge read from a pixel by the drive unit outputting a drive signal to a first drive line and a second charge read from a pixel by the drive unit outputting a drive signal to a second drive line. [Effects of the Invention]

[0011] The above means makes it possible to provide a radiographic imaging governance system that can suppress the visibility of line noise caused by binning readout while maintaining a high frame rate. [Brief explanation of the drawing]

[0012] [Figure 1] A diagram illustrating an example configuration of a radiation imaging system according to an embodiment of the present invention. [Figure 2] A diagram illustrating an example configuration of a radiation imaging device according to an embodiment of the present invention. [Figure 3] A diagram illustrating an example of the cross-sectional structure of a pixel according to an embodiment of the present invention. [Figure 4]A diagram for explaining an working example of Example 1 of the radiation imaging system according to an embodiment of the present invention. [Figure 5] A diagram for explaining an working example of Example 2 of the radiation imaging system according to an embodiment of the present invention. [Figure 6] A diagram for explaining an working example of Example 3 of the radiation imaging system according to an embodiment of the present invention. [Figure 7] A sequence diagram of even-row binning readout processing of the radiation imaging system according to an embodiment of the present invention. [Figure 8] A sequence diagram of odd-row binning readout processing of the radiation imaging system according to an embodiment of the present invention. [Figure 9] A diagram for explaining another working example of Example 1 of the radiation imaging system according to an embodiment of the present invention. [Figure 10] A diagram for explaining another working example of Example 2 of the radiation imaging system according to an embodiment of the present invention. [Figure 11] A diagram for explaining another working example of Example 3 of the radiation imaging system according to an embodiment of the present invention. [Figure 12] A diagram for explaining an example of a driving circuit of the radiation imaging system according to an embodiment of the present invention. [Figure 13] A diagram for explaining an operation example of a control circuit in the working example of Example 1 of the radiation imaging system according to an embodiment of the present invention. [Figure 14] A diagram for explaining a working example of the radiation imaging system according to an embodiment of the present invention. MODE FOR CARRYING OUT THE INVENTION

[0013] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. Note that the following embodiments do not limit the invention according to the claims. Although a plurality of features are described in the embodiments, not all of these plurality of features are essential to the invention, and the plurality of features may be arbitrarily combined. Furthermore, in the accompanying drawings, the same or similar configurations are denoted by the same reference numerals, and duplicate descriptions are omitted.

[0014] FIG. 1 shows a configuration example of a radiation imaging system 100 according to Embodiments 1 to 3 of the present invention. The radiation imaging system 100 is configured to electrically capture an optical image formed by radiation and obtain an electrical radiation image. Radiation is typically X-rays, but may also be α-rays, β-rays, γ-rays, or the like. The radiation imaging system 100 includes, for example, a radiation imaging apparatus 110, a computer 120 serving as a control apparatus, a display 114, an exposure control apparatus 130, and a radiation generator 140.

[0015] The radiation generator 140 starts irradiation of radiation 160 in accordance with an exposure command (radiation command) from the exposure control apparatus 130. The radiation 160 emitted from the radiation generator 140 passes through a subject 150 and enters the radiation imaging apparatus 110. The radiation generator 140 also stops irradiation of the radiation 160 in accordance with a stop command from the exposure control apparatus 130.

[0016] The radiation imaging device 110 includes a radiation detection panel 111, a control circuit 112, and an image generation circuit 113, which is an image signal generation unit. The radiation detection panel 111 generates image data signals corresponding to the radiation incident on the radiation imaging device 110. The image data signal is data for generating a radiation image and is a data signal based on the charge generated by a conversion element described later. The control circuit 112 controls the operation of the radiation detection panel 111. For example, the control circuit 112 generates a stop signal to stop the irradiation of radiation from the radiation source 140 based on the image data signal obtained from the radiation detection panel 111. The stop signal is supplied to the exposure control device 130. In response to the stop signal, the exposure control device 130 sends a stop command to the radiation generator 140. The control circuit 112 is composed of a PLD (Programmable Logic Device) such as an FPGA (Field Programmable Gate Array). Alternatively, it may be composed of a dedicated circuit such as an ASIC (Application Specific Integrated Circuit). Alternatively, the control circuit 112 may be composed of a combination of a general-purpose processing circuit, such as a processor, and a memory circuit, such as a memory. In this case, the functions of the control circuit 112 may be realized by the general-purpose processing circuit executing a program stored in the memory circuit.

[0017] The image generation circuit 113 stores the image data signal supplied from the radiation detection panel 111 in memory and generates a radiation image signal based on this signal. Details of the method for generating the radiation image signal will be described later. The image generation circuit 113 transmits the generated radiation image signal to the control device, computer 120. The control device, computer 120, processes the received image signal.

[0018] The computer 120 includes a control unit that controls the radiation imaging device 110 and the exposure control device 130, a receiving unit that receives image signals from the radiation imaging device 110, and a signal processing unit that processes the image signals obtained by the radiation imaging device 110. The control unit, receiving unit, and signal processing unit may each be configured by dedicated circuits, similar to the control circuit 112, or by a combination of general-purpose processing circuits and memory circuits. In one example, the exposure control device 130 has an exposure switch, and when the exposure switch is turned on by the user, it sends an exposure command to the radiation generator 140 and a start notification to the computer 120 indicating the start of radiation irradiation. Upon receiving the start notification, the computer 120 responds to the start notification by notifying the control circuit 112 of the radiation imaging device 110 of the start of radiation irradiation.

[0019] In cases where the exposure control device 130 and the computer 120 are not synchronously connected, the radiation detection panel 111 may continue the image readout operation and detect the start of radiation 160 irradiation from the output value of the image signal.

[0020] Figure 2 shows an example configuration of a radiation detection panel 111. The radiation detection panel 111 includes, for example, a pixel array 200, a drive circuit 210 which is a drive unit, a readout circuit 220 which is a readout unit, and an AD converter 240. The drive circuit 210 and the readout circuit 220 function as peripheral circuits of the pixel array 200. The pixel array 200 is composed of, for example, a plurality of pixels 201 arranged in a matrix (array), a plurality of drive lines Vg(1) to Vg(8), a plurality of signal lines Sig1 to Sig8, and a bias line Bs. The drive lines connect the drive circuit, which is the drive unit, to the pixels row by row and supply the drive signal output from the drive circuit to the switch element (the switch element of the pixel) as described. In Figure 2, for illustrative purposes, the pixel array 200 is composed of 8 rows x 8 columns of pixels 201. However, in reality, more pixels 201 may be arranged. In one example, the radiation detection panel 111 has dimensions of 17 inches and has approximately 3000 rows x 3000 columns of pixels 201. Each pixel 201 is composed of a conversion element and an output switch element.

[0021] The pixel array 200 includes multiple conversion elements C11 to C88 and multiple output switch elements S11 to S88. In the following description, the conversion elements C11 to C88 are collectively referred to as conversion element C. The description of conversion element C applies to each of the conversion elements C11 to C88. Similarly, the output switch elements S11 to S88, drive lines Vg(1) to Vg(8), and signal lines Sig1 to Sig8 are collectively referred to as output switch element S, drive line Vg, and signal line Sig, respectively. Each row of the pixel array 200 is referred to as row 1 to row 8 from the top of the drawing, and each column of the pixel array 200 is referred to as column 1 to column 8 from the left of the drawing. Each pixel 201 is composed of a combination of one conversion element C and one output switch element S. For example, pixel 201, located in the first row and second column, is formed by a combination of a conversion element C12 and an output switch element S12.

[0022] In each pixel 201, a conversion element C converts incident radiation into a charge signal, and an output switch element S is connected between the conversion element C and the signal line Sig corresponding to the conversion element C. For example, output switch elements S11, S21, S31, S41, S51, S61, S71, S81 are connected between multiple conversion elements C11, C21, C31, C41, C51, C61, C71, C81 and the signal line Sig1. When the output switch element S is turned on, conduction occurs between the conversion element C and the signal line Sig, and the charge signal obtained by the conversion element C (for example, the charge accumulated in the conversion element C) is transferred to the signal line Sig. The conversion element C may be, for example, an MIS type photodiode made mainly of amorphous silicon and placed on an insulating substrate such as a glass substrate. Alternatively, the conversion element C may be a PIN type photodiode. The conversion element C may be configured as a direct type that directly converts radiation into electric charge, or as an indirect type that converts radiation into light and then detects this light. In the indirect type, the scintillator may be shared by multiple pixels 201.

[0023] The output switching element S is composed of a transistor, such as a thin-film transistor (TFT) having a control terminal (gate) and two main terminals (source and drain). The conversion element C has two main electrodes, one of which is connected to one of the two main terminals of the output switching element S, and the other main electrode of the conversion element is connected to a bias power supply Vs via a common bias line Bs. The bias power supply Vs generates a bias voltage.

[0024] The control terminal of the output switch element S for pixel 201 in the first row is connected to the drive line Vg(1). The control terminal of the output switch element S for pixel 201 in the second row is connected to the drive line Vg(2). The same applies to rows 3 through 8.

[0025] The drive circuit 210 supplies drive signals to the control terminals of the output switch elements S of each pixel 201 connected to each drive line, via the drive line Vg, according to the control signals supplied from the control circuit 112. The control signals include an ON signal (high level in the following description) for turning on the output switch elements S and an OFF signal (low level in the following description) for turning off the output switch elements S. The drive circuit 210 includes, for example, a shift register, which performs a shift operation according to the control signals (for example, a clock signal) supplied from the control circuit 112.

[0026] The readout circuit 220 amplifies and reads the charge signal obtained by the conversion element C and appearing on the signal line Sig. The readout circuit 220 includes one amplification circuit 221 for each signal line Sig. In the example in Figure 2, the pixel array 200 has eight signal lines Sig, so the readout circuit 220 includes eight amplification circuits 221. The amplification circuit 221 includes, for example, an integrating amplifier 222, an LPF circuit 223S, an LPF circuit 223N, a signal sample-and-hold switch element 224S, and a noise sample-and-hold switch element 224N. Furthermore, it includes capacitors 225S, 225N, and buffer circuits 226S and 226N. The signal sample-and-hold switch element 224S and capacitor 225S constitute a signal sample-and-hold circuit, and the noise sample-and-hold switch element 224N and capacitor 225N constitute a noise sample-and-hold circuit. The integrating amplifier 222 includes, for example, an operational amplifier, an integrating capacitor connected in parallel between the inverting input terminal and the output terminal of the operational amplifier, and a reset switch. A reference voltage is supplied to the non-inverting input terminal of the operational amplifier from a reference power supply Vref. When the reset switch is turned on in response to the control signal RC (reset pulse) supplied from the control circuit 112, the integrating capacitor is reset and the potential of the signal line Sig is reset to the reference potential. The LPF circuits 223S and 223N remove noise from the signal from the integrating amplifier 222 with a set filter value. The sample-and-hold circuits sample and hold the signals from the LPF circuits 223S and 223N, respectively. The on / off switching of the signal sample-and-hold switch element 224S and the noise sample-and-hold switch element 224N, which constitute the sample-and-hold circuits, is controlled by the control signals SHS and SHN supplied from the control circuit 112. The buffer circuits 226S and 226N buffer (impedance conversion) the signals from the sample-and-hold circuits and output them.

[0027] The readout circuit 220 also includes a multiplexer 227 that selects and outputs signals from a plurality of amplifier circuits 221 in a predetermined order. The multiplexer 227 includes, for example, a shift register, which performs a shift operation according to a control signal (e.g., a clock signal) supplied from the control circuit 112. This shift operation sequentially selects the plurality of amplifier circuits 221, and outputs the output of the signal sample-and-hold circuit and the noise sample-and-hold circuit within the selected amplifier circuit 221.

[0028] The AD converter 240 converts the difference between the two analog signals output from the multiplexer 227 into a digital signal. The output of the AD converter 240, i.e., the image signal, is transmitted to the computer 120.

[0029] Figure 3 schematically shows an example of the cross-sectional structure of a single pixel 201. The pixel 201 is formed on an insulating substrate 301 such as a glass substrate. The pixel 201 has a conductive layer 302, an insulating layer 303, a semiconductor layer 304, an impurity semiconductor layer 305, and a conductive layer 306 on the insulating substrate 301. The conductive layer 302 constitutes the gate of a transistor (e.g., a TFT) that makes up the output switch element S. The insulating layer 303 is arranged to cover the conductive layer 302. The semiconductor layer 304 is arranged on the portion of the conductive layer 302 that makes up the gate, via the insulating layer 303. The impurity semiconductor layer 305 is arranged on the semiconductor layer 304 so as to constitute the two main terminals (source and drain) of the transistor that makes up the switch element S. The conductive layer 306 constitutes wiring patterns connected to the two main terminals (source and drain) of the transistor that makes up the switch element S. A portion of the conductive layer 306 constitutes a signal line Sig, while another portion constitutes a wiring pattern for connecting the output switch element S to the conversion element C.

[0030] Pixel 201 further has an interlayer insulating film 307 covering the insulating layer 303 and the conductive layer 306. The interlayer insulating film 307 is provided with a contact plug 308 for connecting to the conductive layer 306 (output switch element S). On top of the interlayer insulating film 307, pixel 201 further has a conductive layer 309, an insulating layer 310, a semiconductor layer 311, an impurity semiconductor layer 312, a conductive layer 313, a protective layer 314, an adhesive layer 315, and a scintillator 316 in this order. These layers constitute an indirect type conversion element C. The conductive layer 309 and the conductive layer 313 constitute the lower electrode and the upper electrode of the photoelectric conversion element that constitutes the conversion element C, respectively. The conductive layer 313 is made of, for example, a transparent material. The conductive layer 309, the insulating layer 310, the semiconductor layer 311, the impurity semiconductor layer 312, and the conductive layer 313 constitute an MIS type sensor as a photoelectric conversion element. The impurity semiconductor layer 312 is formed, for example, from an n-type impurity semiconductor layer. The scintillator 316 is composed of, for example, a gadolinium-based material or a CsI (cesium iodide) material, and converts radiation into light.

[0031] Alternatively, the conversion element C may be configured as a direct-type conversion element that directly converts incident radiation into an electric charge signal. Examples of direct-type conversion elements C include those primarily made of amorphous selenium, gallium arsenide, gallium phosphorus, lead iodide, mercury iodide, CdTe, CdZnTe, etc. The conversion element C is not limited to the MIS type; for example, it may also be a pn type or PIN type photodiode.

[0032] In the example shown in Figure 3, in the orthographic projection (plan view) of the plane on which the pixel array 200 is formed, each of the multiple signal lines Sig overlaps with a portion of the conversion element C. While this configuration has the advantage of a large area of ​​the conversion element C for each pixel 201, it has the disadvantage of increasing the capacitive coupling between the signal line Sig and the conversion element C.

[0033] <Example 1> An example of the operation of the radiation imaging system 100 will be explained with reference to Figure 4. The operation of the radiation imaging system 100 is controlled by the computer 120. The operation of the radiation imaging device 110 is controlled by the control circuit 112 under the control of the computer 120.

[0034] In Figure 4, the radiation timing chart "Vg(1)" to "Vg(8)" indicates the level of the drive signal supplied from the drive circuit 210 to each drive line Vg(1) to Vg(8). The output switch element S connected to the drive line Vg to which a low-level (off signal) drive signal is supplied is off, and the output switch element S connected to the drive line Vg to which a high-level (on signal) drive signal is supplied is on. Also in Figure 4, RC indicates the state of the control signal RC (reset pulse) of the readout circuit 220. When RC in Figure 4 is low level (off signal), the reset switch is in the off state, and when it is high level (on signal), the reset switch is in the on state. Also in Figure 4, SHS indicates the level of the switch signal to the signal sample-and-hold switch element 224S of the signal sample-and-hold circuit. SHN indicates the level of the switch signal to the noise sample-and-hold switch element 224N of the noise sample-and-hold circuit. In the case of SHS and SHN signals, when the level is low (off signal), the signal sample-and-hold switch element 224S or the noise sample-and-hold switch element 224N is off. In the case of SHS and SHN signals, when the level is high (on signal), the signal sample-and-hold switch element 224S or the noise sample-and-hold switch element 224N is on.

[0035] Figure 4 shows an example of controlling analog binning operation in two adjacent rows.

[0036] The control circuit 112 within the radiation imaging device 110 receives an instruction from the computer 120 to start two-row binning and initiates two-row binning control on the radiation detection panel 111. When initiating two-row binning control, the control circuit 112 causes the radiation detection panel 111 to perform an accumulation operation while radiation is being irradiated. During the accumulation period, RC, SHS, and SHN are all controlled to low levels, and the drive circuit 210 is controlled to set the drive lines Vg(1) to Vg(8) to low levels. This allows charge to accumulate on the conversion element C of each pixel 201 for a predetermined period. After radiation irradiation, the readout period begins, and the control circuit 112 first sets RC to a high level for a predetermined period. This enables a reset operation that resets the integral capacitance in the amplification circuit 221 connected to each signal line Sig1 to Sig8. After that, the control circuit 112 sets RC to a low level and turns off the reset switch. Subsequently, the control circuit 112 controls SHN to a high level, turning on the noise sample-and-hold switch element 224N of the noise sample-and-hold circuit connected to each signal line Sig1 to Sig8. This performs a noise sample-and-hold operation, sampling and holding the noise signal during the reset operation of the integrating amplifier 222 connected to each signal line Sig1 to Sig8. After a predetermined period, the control circuit 112 returns SHN to a low level. After this, the control circuit 112 controls the drive circuit 210 to set the drive line Vg(1) to a high level. This starts the transfer of charge accumulated in the conversion element C of each pixel 201 connected to the first row of the pixel array 200 to each signal line Sig1 to Sig8. After a predetermined period, the control circuit 112 returns Vg(1) to a low level and simultaneously controls the drive circuit 210 to set Vg(2) to a high level. This stops the transfer of charge accumulated in the conversion element C of each pixel 201 connected to the first row of the pixel array 200 to each signal line Sig1 to Sig8. At the same time, the transfer of charge accumulated in the conversion element C of each pixel 201 connected to the adjacent second row to each signal line Sig1 to Sig8 begins. The reason why line-shaped noise can be seen in the row direction when analog binning is performed is that a high level is applied to multiple adjacent drive lines simultaneously, closing the switches of the pixels connected to the drive lines.Therefore, in subsequent embodiments, including this embodiment, when performing analog binning, the period during which high levels are applied is staggered so as not to apply high levels to adjacent drive lines simultaneously.

[0037] After a predetermined period, the control circuit 112 controls the drive circuit 210 to return Vg(2) to a low level. Subsequently, it controls SHS to a high level, turning on the signal sample-and-hold switch element 224S of the signal sample-and-hold circuit connected to each signal line Sig1 to Sig8. As a result, the charge transferred from the conversion element C of each pixel 201 connected to the first and second rows is amplified by the integrating amplifier 222, and the signal sample-and-hold operation is performed on each signal line Sig1 to Sig8. After a predetermined period, the control circuit 112 returns SHS to a low level. As a result, the capacitor 225S of the amplification circuit 221 connected to each signal line Sig1 to Sig8 is filled with electrical signals based on the charge transferred from the conversion element C of each pixel 201 connected to the first and second rows of the pixel array 200. In addition, the electrical signal of the noise component of the integrating amplifier 222 is filled in the capacitor 225N. Subsequently, the control circuit 112 controls the readout circuit 220, sequentially outputting the output of the signal sample-and-hold circuit and the output of the noise sample-and-hold circuit of each amplifier circuit 221 connected to signal lines Sig1 to Sig8 from the multiplexer 227. As a result, the AD converter 240 converts the difference between the output of the signal sample-and-hold circuit and the output of the noise sample-and-hold circuit of each amplifier 221 from the multiplexer 227 into a digital signal, and sequentially generates the image data signal after analog binning of the pixels in the first and second rows. In this example, the image data signal is generated by summing the charges read from the pixels in the first and second rows.

[0038] Next, the control circuit 112 sets RC to a high level again for a predetermined period, performing a reset operation to reset the integral capacitance in the amplification circuit 221 connected to each signal line Sig1 to Sig8. After that, the control circuit 112 sets RC to a low level, turns off the reset switch, and then controls SHN to a high level to perform a noise sample-and-hold operation of the integral amplifier 222 connected to each signal line Sig1 to Sig8. After the predetermined period has elapsed, the control circuit 112 returns SHN to a low level and then controls the drive circuit 210 to perform the same control on drive lines Vg(3) and Vg(4) as the control performed on drive lines Vg(1) and Vg(2) earlier. In other words, the drive circuit 210 controls drive line Vg(3) to a high level for a predetermined period and then returns it to a low level, while simultaneously setting drive line Vg(4) to a high level and then returning it to a low level after the predetermined period has elapsed. As a result, the charge accumulated in the conversion element C of each pixel 201 in the third and fourth rows is sequentially transferred to the connected signal lines Sig1 to Sig8. Furthermore, the control circuit 112 controls the drive circuit 210 to return the drive line Vg(4) to a low level, and after returning the drive line Vg(4) to a low level, controls SHS to a high level. This turns on the signal sample-and-hold switch element 224S of the signal sample-and-hold circuit connected to each signal line Sig1 to Sig8. This causes the signal sample-and-hold operation of the transferred charge accumulated in the conversion element C of each pixel 201 in the third and fourth rows to be performed for each signal line Sig1 to Sig8. After a predetermined period of time has elapsed, the control circuit 112 returns SHS to a low level. As a result, the capacitor 225S of the amplification circuit 221 connected to each signal line Sig1 to Sig8 has accumulated electrical signals based on the charge transferred from the conversion element C of each pixel 201 connected to the third and fourth rows. Furthermore, the capacitor 225N accumulates electrical signals from the noise component of the integrating amplifier 222. Subsequently, the control circuit 112 controls the readout circuit 220, sequentially outputting the output of the signal sample-and-hold circuit and the output of the noise sample-and-hold circuit of each amplifier circuit 221 connected to signal lines Sig1 to Sig8 from the multiplexer 227.As a result, the AD converter 240 converts the difference between the output of the signal sample-and-hold circuit and the output of the noise sample-and-hold circuit of each amplifier 221 from the multiplexer 227 into a digital signal, and sequentially generates the image data signals after analog binning of the pixels in the third and fourth rows.

[0039] Subsequently, the same control is performed on drive lines Vg(5) to Vg(8) in sets, such as drive lines Vg(5) and Vg(6), and drive lines Vg(7) and Vg(8), to generate an analog-binned image with 2 pixels in the column direction, thereby ending the readout period. The image generation circuit 113 may perform row-direction digital binning to match the row-direction and column-direction reduction ratios, or known image correction processing, on the image data generated by the radiation detection panel from the radiation image data signal. The generated image signal is then transmitted to the computer 120, allowing the radiation image to be displayed on the display 114 connected to the computer 120. After the radiation detection panel 111 has finished its readout period, the control circuit 112 controls the radiation detection panel again, entering another storage period to accumulate charge in the conversion element C of each pixel 201. Then, the readout period begins, and the aforementioned series of readout processes are performed. By repeating this process, a moving image can be provided. By performing analog binning in this manner, when reading the nth and n+1th adjacent rows that are being analog-binned, the drive lines Vg(n) and Vg(n+1) are not simultaneously given a high level. Therefore, the deterioration of line noise due to analog binning can be reduced. On the other hand, although the readout time increases compared to the control method that simultaneously gives a high level to the drive lines Vg(n) and Vg(n+1), the number of sample-hold and AD conversion processes remains the same as in the conventional analog binning control method. Therefore, the increase can be kept to a minimum. This makes it possible to reduce the deterioration of line noise due to analog binning while achieving a high frame rate. In this embodiment, in order to minimize the increase in readout time, in the adjacent rows being analog-binned, Vg(2) was controlled from a low level to a high level at the same time that Vg(1) was controlled from a high level to a low level. In other words, the output of the drive signal to the drive lines was controlled so that the falling edge of the drive signal to drive line Vg(1) and the rising edge of the drive signal to drive line Vg(2) were synchronized.However, if the increased read time can still keep up with the achieved frame rate, the drive line Vg(1) may be controlled from high level to low level, and then Vg(2) may be controlled from low level to high level after a predetermined period of time has elapsed. Alternatively, as shown in Figure 9, for example, Vg(2) may be controlled from low level to high level before Vg(1) is controlled from high level to low level, so that the high-level periods of the drive lines Vg of adjacent rows are partially overlapped. Overlapping the high-level periods of the drive lines Vg has the advantage of allowing for a longer transfer time of the charge signal from the output switch element S.

[0040] In the explanation using Figure 4, the waveform of the drive signal output from the drive circuit to the drive line Vg was explained using a rectangle. However, depending on the configuration of the drive circuit, the actual waveform may have a smeared rising and falling edge. In this case, for example, Figure 14 shows the case where the falling edge of the drive signal output to drive line Vg(1) (the first drive signal) and the rising edge of the drive signal output to Vg(2) (the second x drive signal) are aligned. As shown in Figure 14, if the smeared falling edge (tail) of the first drive signal and the rising edge of the second drive signal overlap, then the falling edge of the first drive signal and the rising edge of the second drive signal are considered to be aligned. In this case as well, it is possible to reduce the deterioration of line noise due to analog binning while achieving a high frame rate.

[0041] <Example 2> Next, Figure 5 shows an example of controlling analog binning operation in four adjacent rows.

[0042] The control circuit 112 in the radiation imaging device 110 receives an instruction from the computer 120 to start the 4-row binning operation, and initiates 4-row binning control on the radiation detection panel 111. The differences from Example 1 are explained here. When the 4-row binning control is started, an accumulation period is entered and charge is accumulated on the conversion element C of each pixel 201 for a predetermined period, but the operations performed during this accumulation period are the same as those in Example 1. After that, a readout period is entered and the control circuit 112 first sets RC to a high level. This performs a reset operation that resets the integral capacitance in the amplifier circuit 221 connected to each signal line Sig1 to Sig8. After that, the control circuit 112 sets RC to a low level and turns off the reset switch. After that, the control circuit 112 controls SHN to a high level and turns on the noise sample-and-hold switch element 224N of the noise sample-and-hold circuit connected to each signal line Sig1 to Sig8. This performs the noise sample-and-hold operation in the integral amplifier 222 connected to each signal line Sig1 to Sig8. After a predetermined period, the control circuit 112 returns SHN to a low level. After this, the control circuit 112 controls the drive circuit 210 to raise the drive lines Vg(1) and Vg(3) to a high level. This starts the transfer of charge accumulated in the conversion elements C of each pixel 201 connected to the first and third rows of the pixel array 200 to the respective signal lines Sig1 to Sig8. After a predetermined period, the control circuit 112 returns Vg(1) and Vg(3) to a low level and simultaneously controls the drive circuit 210 to raise Vg(2) and Vg(4) to a high level. This stops the transfer of charge accumulated in the conversion elements C of each pixel 201 connected to the first and third rows to the respective signal lines Sig1 to Sig8. At the same time, the transfer of charge accumulated in the conversion elements C of each pixel 201 connected to the second and fourth rows adjacent to the first and third rows to the respective signal lines Sig1 to Sig8 begins. After a predetermined period of time has elapsed, the control circuit 112 controls the drive circuit 210 to return Vg(2) and Vg(4) to low levels, and then controls SHS to a high level. This turns on the signal sample-and-hold switch element 224S of the signal sample-and-hold circuit connected to each signal line Sig1 to Sig8.Then, a sample-and-hold operation for the signal, based on the charge transferred from the conversion element C of each pixel 201 connected to the first to fourth rows, is performed on each signal line Sig1 to Sig8. After a predetermined period, the control circuit 112 returns SHS to a low level. As a result, the capacitor 225S of the amplifier circuit 221 connected to each signal line Sig1 to Sig8 accumulates electrical signals based on the charge transferred from the conversion element C of each conversion pixel connected to the first to fourth rows. In addition, the electrical signal of the noise component of the integrating amplifier 222 accumulates in the capacitor 225N. Subsequently, the control circuit 112 controls the readout circuit 220, and the outputs of the signal sample-and-hold circuits and the noise sample-and-hold circuits of each amplifier circuit 221 connected to the signal lines Sig1 to Sig8 are output sequentially from the multiplexer 227. As a result, the AD converter 240 converts the difference between the output of the signal sample-and-hold circuit and the output of the noise sample-and-hold circuit of each amplifier 221 from the multiplexer 227 into a digital signal, and sequentially generates the image signals after analog binning of the pixels in the first to fourth rows.

[0043] Next, the control circuit 112 sets RC to a high level again for a predetermined period, performing a reset operation to reset the integral capacitance in the amplification circuit 221 connected to each signal line Sig1 to Sig8. After that, the control circuit 112 sets RC to a low level, turns off the reset switch, and then controls SHN to a high level to perform a noise sample-and-hold operation on the integral amplifier 222 connected to each signal line Sig1 to Sig8. After the predetermined period has elapsed, the control circuit 112 returns SHN to a low level, and then controls the drive circuit 210 to perform the same control on drive lines Vg(5) to Vg(8) as the control performed on drive lines Vg(1) to Vg(4) earlier. In other words, the control circuit 210 sets drive lines Vg(5) and Vg(7) to a high level for a predetermined period, then returns them to a low level, while simultaneously setting drive lines Vg(6) and Vg(8) to a high level, and after the predetermined period has elapsed, returns them to a low level. As a result, the charge accumulated in the conversion element C of each pixel 201 in rows 5 to 8 is sequentially transferred to the connected signal lines Sig1 to Sig8. Furthermore, when the control circuit 112 controls the drive circuit 210 to return the drive lines Vg(6) and Vg(8) to a low level, it controls SHS to a high level after the drive lines Vg(6) and Vg(8) have returned to a low level. This turns on the signal sample-and-hold switch element 224S of the signal sample-and-hold circuit connected to each signal line Sig1 to Sig8. Then, the signal sample-and-hold operation of the charge accumulated in the conversion element C of each pixel 201 in rows 5 to 8 is performed for each signal line Sig1 to Sig8. After a predetermined period of time has elapsed, the control circuit 112 returns SHS to a low level. As a result, the capacitor 225S of the amplifier circuit 221 connected to each signal line Sig1 to Sig8 accumulates electrical signals based on the charge transferred from the conversion elements C of each conversion pixel connected to the 5th to 8th rows. In addition, the electrical signals of the noise component of the integrating amplifier 222 accumulate in the capacitor 225N. Subsequently, the control circuit 112 controls the readout circuit 220, and the outputs of the signal sample-and-hold circuits and the noise sample-and-hold circuits of each amplifier circuit 221 connected to the signal lines Sig1 to Sig8 are output sequentially from the multiplexer 227.As a result, the AD converter 240 converts the difference between the output of the signal sample-and-hold circuit and the output of the noise sample-and-hold circuit of each amplifier 221 from the multiplexer 227 into a digital signal. This sequentially generates the analog-binned image signals of the pixels in rows 5 to 8. This generates an analog-binned image of 4 pixels in the column direction, and the readout period ends. After the radiation detection panel 111 finishes the readout period, the control circuit 112 controls the radiation detection panel again, and enters the accumulation period again to accumulate charge in the conversion element C of each pixel 201. Then it enters the readout period and performs the aforementioned series of readout processes. By repeating this, a moving image can be provided. By performing analog binning of rows in this way, when reading out the adjacent rows n and n+1 that are to be analog-binned, high levels are not simultaneously applied to the drive lines Vg(n) and Vg(n+1). Therefore, the deterioration of line noise due to analog binning can be reduced. On the other hand, in the non-adjacent 4n-th and 4n+2-th rows, and the 4n+1-th and 4n+3-th rows, the drive lines Vg(4n) and Vg(4n+2), and Vg(4n+1) and Vg(4n+3), respectively, are simultaneously given a high level, so the read time is halved compared to Example 1.

[0044] In this embodiment as well, in adjacent rows undergoing analog binning, Vg(1) and Vg(3) were controlled from high to low levels at the same time as Vg(2) and Vg(4) were controlled from low to high levels. This suppresses the increase in readout time. However, if the increased readout time is still sufficient to meet the achieved frame rate, Vg(1) and Vg(3) may be controlled from high to low levels, and then Vg(2) and Vg(4) may be controlled from low to high levels after a predetermined period has elapsed. Alternatively, as shown in Figure 10, for example, Vg(2) and Vg(4) may be controlled from low to high levels before Vg(1) and Vg(3) are controlled from high to low levels, thereby partially overlapping the high-level periods of the drive lines Vg in adjacent rows. Overlapping the high-level periods of the drive lines Vg has the advantage of allowing for a longer transfer time of the charge signal from the output switch element S.

[0045] <Example 3> Next, Figure 6 shows an example of controlling analog binning operation in three adjacent rows. Here, the pixel array 200 in Figure 2 is assumed to have a configuration of 9 rows and 8 columns, with each pixel 201 in the 9th row connected to a drive line Vg(9) and further connected to the signal lines Sig1 to Sig8 of each column, and the drive line Vg(9) connected to the drive circuit 210. In the case of 3-row binning, it is assumed that a drive line Vg(0), which is not used as a radiographic image, exists in the first row to the drive circuit 210. For example, drive line Vg0 is a dummy drive line to which no conversion element is connected. Accordingly, Vg(0) and Vg(9) in the timing chart of Figure 6 represent the levels of the drive signal supplied to the drive line Vg(0) and the drive line Vg(9) to which each pixel 201 in the 9th row of the pixel array 200 is connected, respectively.

[0046] The control circuit 112 in the radiation imaging device 110 receives an instruction from the computer 120 to start the 3-row binning operation, and initiates 3-row binning control on the radiation detection panel 111. The differences from Example 2 are explained here. When initiating the 3-row binning control, an accumulation period is entered, and charge is accumulated on the conversion element C of each pixel 201 for a predetermined period. The operations performed during this accumulation period are the same as those in Example 2. Subsequently, a readout period is entered, and the control circuit 112 first sets RC to a high level for a predetermined period. This performs a reset operation that resets the integral capacitance in the amplifier circuit 221 connected to each signal line Sig1 to Sig8. After that, the control circuit 112 sets RC to a low level and turns off the reset switch. Then the control circuit 112 controls SHN to a high level, turning on the noise sample-and-hold switch element 224N of the noise sample-and-hold circuit connected to each signal line Sig1 to Sig8. This performs a noise sample-and-hold operation in the integral amplifier 222 connected to each signal line Sig1 to Sig8. After a predetermined period, the control circuit 112 returns SHN to a low level. After this, the control circuit 112 controls the drive circuit 210 to raise the drive lines Vg0 and Vg2 to a high level. This starts the transfer of the charge accumulated in the conversion element C of each pixel 201 connected to the 0th and 2nd rows to the respective signal lines Sig1 to Sig8. However, as mentioned above, the drive line Vg(0) is a dummy drive line and is not used as a radiation image, so the charge of the conversion element C transferred at this time is only that of each pixel 201 connected to the 2nd row of the pixel array 200. After a predetermined period, the control circuit 112 returns Vg(0) and Vg(2) to a low level and simultaneously controls the drive circuit 210 to raise Vg(1) and Vg(3) to a high level. This stops the transfer of the charge accumulated in the conversion element C of each pixel 201 connected to the 2nd row to the respective signal lines Sig1 to Sig8. Simultaneously, the transfer of charge accumulated in the conversion elements C of each pixel 201 connected to the 1st and 3rd rows adjacent to the 0th and 2nd rows is started to the respective signal lines Sig1 to Sig8. After a predetermined period of time has elapsed, the control circuit 112 controls the drive circuit 210 to return Vg(1) and Vg(3) to low levels, and after returning Vg(1) and Vg(3) to low levels, controls SHS to a high level.This turns on the signal sample-and-hold switch element 224S of the signal sample-and-hold circuit connected to each signal line Sig1 to Sig8. Then, the signal sample-and-hold operation of the charge transferred from the conversion element C of each pixel 201 connected to the first to third rows is performed on each signal line Sig1 to Sig8. After a predetermined period of time, the control circuit 112 returns SHS to a low level. As a result, the capacitor 225S of the amplifier circuit 221 connected to each signal line Sig1 to Sig8 accumulates the charge transferred from the conversion element C of each conversion pixel connected to the first to third rows, and the capacitor 225N accumulates the charge of the noise component of the integrating amplifier 222. Subsequently, the control circuit 112 controls the readout circuit 220, and the outputs of the signal sample-and-hold circuit and the noise sample-and-hold circuit of each amplifier circuit 221 connected to the signal lines Sig1 to Sig8 are output sequentially from the multiplexer 227. As a result, the AD converter 240 converts the difference between the output of the signal sample-and-hold circuit and the output of the noise sample-and-hold circuit of each amplifier 221 from the multiplexer 227 into a digital signal, and sequentially generates the image signals after analog binning of the pixels in the first to third rows.

[0047] Next, the control circuit 112 sets RC to a high level again for a predetermined period, performing a reset operation to reset the integral capacitance in the amplifier circuit 221 connected to each signal line Sig1 to Sig8. After that, the control circuit 112 sets RC to a low level, turns off the reset switch, and then controls SHN to a high level to perform a noise sample-and-hold operation on the integral amplifier 222 connected to each signal line Sig1 to Sig8. After the predetermined period has elapsed, the control circuit 112 returns SHN to a low level, and then controls the drive circuit 210 to perform the same control on drive lines Vg(3) to Vg(6) as the control performed on drive lines Vg(0) to Vg(3) earlier. In other words, it sets drive lines Vg(3) and Vg(5) to a high level for a predetermined period, then returns them to a low level, while simultaneously setting drive lines Vg(4) and Vg(6) to a high level, and after the predetermined period has elapsed, controls the drive circuit 210 to return them to a low level. As a result, the charge accumulated in the conversion element C of each pixel 201 connected to the 3rd to 6th rows of the pixel array 200 is sequentially transferred to the connected signal lines Sig1 to Sig8. However, in the conversion element C of each pixel 201 connected to the 3rd row, the charge has already been transferred by the aforementioned control that sets Vg(1) and Vg(3) to high levels. Therefore, it is very small compared to the charge transferred from the conversion element C of each pixel 201 connected to the 4th to 6th rows. For this reason, the charge transferred here can be considered equivalent to the charge accumulated in the conversion element C of each pixel 201 connected to the 4th to 6th rows.

[0048] When the control circuit 112 controls the drive circuit 210 to return the drive lines Vg(4) and Vg(6) to a low level, it controls SHS to a high level after the drive lines Vg(4) and Vg(6) have returned to a low level. This turns on the signal sample-and-hold switch element 224S of the signal sample-and-hold circuit connected to each signal line Sig1 to Sig8. Then, the signal sample-and-hold operation is performed for each signal line Sig1 to Sig8 on the charge accumulated in the conversion element C of each pixel 201 connected to the 4th to 6th rows that has been transferred. After a predetermined period of time has elapsed, the control circuit 112 returns SHS to a low level, so that the capacitor 225S of the amplifier circuit 221 connected to each signal line Sig1 to Sig8 has accumulated the charge transferred from the conversion element C of each pixel 201 connected to the 4th to 6th rows. In addition, the capacitor 225N has accumulated the charge of the noise component of the integrating amplifier 222. Subsequently, the control circuit 112 controls the readout circuit 220, sequentially outputting the output of the signal sample-and-hold circuit and the output of the noise sample-and-hold circuit of each amplifier circuit 221 connected to signal lines Sig1 to Sig8 from the multiplexer 227. As a result, the AD converter 240 converts the difference between the output of the signal sample-and-hold circuit and the output of the noise sample-and-hold circuit of each amplifier 221 from the multiplexer 227 into a digital signal, and sequentially generates the image signals after analog binning of pixels in rows 4 to 6.

[0049] After this, the control circuit 112 again raises RC to a high level for a predetermined period, resetting the integral capacitance in the amplification circuit 221 connected to each signal line Sig1 to Sig8. Then, the control circuit 112 controls the drive circuit 210 to perform the same control on drive lines Vg(6) to Vg(9) as the control performed earlier on drive lines Vg(3) to Vg(6). As a result, the charge accumulated in the conversion element C of each pixel 201 connected to rows 6 to 9 of the pixel array 200 is sequentially transferred to each connected signal line Sig1 to Sig8. However, the conversion element C of each pixel 201 connected to row 6 has already finished transferring charge through the aforementioned control that raises Vg(4) and Vg(6). Therefore, it is very small compared to the charge transferred from the conversion element C of each pixel 201 connected to rows 7 to 9. For this reason, the charge transferred here can be considered equivalent to the charge accumulated in the conversion element C of each pixel 201 connected to rows 7 to 9. Subsequently, the control circuit 112 controls SHS to a high level. This turns on the signal sample-and-hold switch element 224S of the signal sample-and-hold circuit connected to each signal line Sig1 to Sig8. Then, the signal sample-and-hold operation is performed for each signal line Sig1 to Sig8 on the charge accumulated in the conversion element C of each pixel 201 in rows 7 to 9 that has been transferred. After a predetermined period of time, the control circuit 112 returns SHS to a low level, so that the capacitor 225S of the amplifier circuit 221 connected to each signal line Sig1 to Sig8 has accumulated the electrical signals transferred from the conversion element C of each pixel 201 connected to rows 7 to 9. Also, the electrical signal of the noise component of the integrating amplifier 222 has accumulated in the capacitor 225N. Subsequently, the control circuit 112 controls the readout circuit 220 and outputs the output of the signal sample-and-hold circuit and the output of the noise sample-and-hold circuit of each amplifier circuit 221 connected to signal lines Sig1 to Sig8 sequentially from the multiplexer 227. As a result, the AD converter 240 converts the difference between the output of the signal sample-and-hold circuit and the output of the noise sample-and-hold circuit of each amplifier 221 from the multiplexer 227 into a digital signal, and sequentially generates the analog binned image signals of the pixels in rows 7 to 9.

[0050] This generates an analog-binned image with 3 pixels in the column direction, and the readout period ends. After the radiation detection panel 111 finishes the readout period, the control circuit 112 controls the radiation detection panel again, and enters the accumulation period again to accumulate charge on the conversion element C of each pixel 201. Then enters the readout period and performs the aforementioned series of readout processes. By repeating this, a moving image can be provided. By performing analog binning of rows in this way, when reading the nth and n+1th adjacent rows that are being analog-binned, high levels are not simultaneously applied to the drive lines Vg(n) and Vg(n+1). Therefore, the deterioration of line noise due to analog binning can be reduced.

[0051] In this embodiment as well, in adjacent rows undergoing analog binning, Vg(1) and Vg(3) were controlled from low to high at the same time that Vg(0) and Vg(2) were controlled from high to low in the drive lines Vg(0) to Vg(2). This suppresses the increase in readout time. However, if the increased readout time is still sufficient to meet the achieved frame rate, the drive lines Vg(0) and Vg(2) may be controlled from high to low, and then Vg(1) and Vg(3) may be controlled from low to high after a predetermined period has elapsed. Alternatively, as shown in Figure 11, for example, Vg(1) and Vg(3) may be controlled from low to high before Vg(0) and Vg(2) are controlled from high to low, thereby partially overlapping the high-level periods of the drive lines Vg in adjacent rows. Overlapping the high-level periods of the drive lines Vg has the advantage of allowing for a longer transfer time of the charge signal from the output switch element S. In the above explanation, the dummy drive line Vg0 is assumed to be in a configuration where no conversion element is connected, but it is not limited to this configuration; a configuration with a dummy conversion element connected is also acceptable. The dummy conversion element may be implemented, for example, by covering the top of the conversion element with a light-shielding material to prevent the generation of charge by light generated by the scintillator.

[0052] Examples 1 and 2 described methods for 2-row and 4-row analog binning, respectively. However, the processing of the readout period when performing analog binning of an even number of rows (2 × L) can be generalized using the flowchart shown in Figure 7, which will be explained below. Here, we show an example of scanning pixels from lower row numbers to higher row numbers, but scanning from higher row numbers to lower row numbers is also possible.

[0053] When the radiation imaging device 110 enters the readout period and starts the readout process, it first resets the value of counter A, which has undergone a signal sample-and-hold operation in step S701, to 0. Then, proceeding to step S702, the control circuit 112 first sets RC to a high level for a predetermined period. This corresponds to the reset operation of the integral capacitance in the amplification circuit 221 connected to each signal line Sig1 to Sig8, as performed in the above embodiment. Next, in step S703, the control circuit 112 controls SHN to a high level for a predetermined period, performing a noise sample-and-hold operation in the integral amplifier 222 connected to each signal line Sig1 to Sig8. Then, in step S704, the control circuit 112 sets the drive line Vg(2×(L×A+B)-1) to high for a predetermined period. Here, B becomes a number from 1 to L, and the charge accumulated in the conversion element C of each pixel 201 connected to a total of L rows, skipping one row each, is simultaneously transferred to each signal line Sig1 to Sig8. For example, in the case of 4-row binning (L=2), A is 0 and B is 1 and 2, so here the drive lines Vg(1) and Vg(3) are controlled simultaneously to transfer the charge accumulated in the conversion elements C of each pixel 201 in the 1st and 3rd rows of the pixel array 200. Next, in step S705, the control circuit 112 sets the drive line Vg(2×(L×A+B)) high for a predetermined period of time. Here again B will be a number from 1 to L, and the charge accumulated in the conversion elements C of each pixel 201 connected to the row transferred in step S704 and adjacent to a total of L rows is simultaneously transferred to each signal line Sig1 to Sig8. For example, in the case of 4-row binning (L=2), A is 0 and B is 1 and 2, so here the drive lines Vg(2) and Vg(4) are controlled to transfer the charge accumulated in the conversion elements C of each pixel 201 in the 2nd and 4th rows of the pixel array 200. Subsequently, in step S706, the control circuit 112 controls the SHS to a high level for a predetermined period. This performs a sample-and-hold operation for the signal charge of each pixel 201 in the pixel array 200 connected to rows 2×L×A+1 to 2×L×(A+1) that have been transferred. For example, in the case of 4-row binning (L=2), a sample-and-hold operation for the signal charge of each pixel 201 connected to rows 1 through 4 will be performed here. After this, in step S707, the control circuit 112 controls the multiplexer 227 and the readout circuit 220.This sequentially performs AD conversion on the difference between the output of the signal sample-and-hold circuit and the output of the noise sample-and-hold circuit of each amplification circuit 221 connected to signal lines Sig1 to Sig8. For example, in the case of 4-row binning (L=2), this sequentially generates the analog binned image signals of each pixel 201 connected to the 1st to 4th rows of the pixel array 200. Then, in step S708, the value of counter A, which performed the signal sample-and-hold operation, is increased by 1, and the process moves to the determination in step S709. In step S709, it is determined whether 2 × L × A is greater than the number of rows that make up the pixel array 200. In other words, it is determined here whether the analog binning readout process for all rows has been completed, and if the analog binning readout process for all rows has not been completed, the process returns to step S702. Then, a second analog binning readout is performed. Here, in step S704, for example, in the case of 4-row binning (L=2), A is 1 and B is 1 and 2, so drive lines Vg(5) and Vg(7) are controlled here, and in step S705, drive lines Vg(6) and Vg(8) are controlled. Then, in step S706, in the case of 4-row binning (L=2), a signal sample-and-hold operation is performed on the charge of each pixel 201 connected to the 5th to 8th rows of the pixel array 200. Then, in step S707, these outputs are converted to AD, and the image signals after analog binning are sequentially generated. After that, in step S708, the value of counter A, which performed the signal sample-and-hold operation, is increased by 1, and in step S709, it is determined whether 2 × L × A (A is 2 here) is greater than the number of rows that make up the pixel array 200. If the number of rows that make up the pixel array 200 is 8, then the readout process by analog binning of all rows is completed here, and the readout process for the readout period is terminated.

[0054] Example 3 described a method for analog binning of 3 rows. However, the processing of the readout period when performing analog binning of an odd number of rows (2 × L + 1) can be generalized using the flowchart shown in Figure 8, which will be explained below. Here, we show an example of scanning pixels from rows with lower row numbers to rows with higher row numbers, but scanning from rows with higher row numbers to rows with lower row numbers is also possible.

[0055] When the radiation imaging device 110 enters the readout period and starts the readout process, it first resets the value of counter A, which has undergone a signal sample-and-hold operation in step S801, to 0. Then, proceeding to step S802, the control circuit 112 first sets RC to a high level for a predetermined period. This corresponds to the reset process of the integral capacitance in the amplification circuit 221 connected to each signal line Sig1 to Sig8, as performed in the above embodiment. Next, in step S803, the control circuit 112 controls SHN to a high level for a predetermined period, performing a noise sample-and-hold operation in the integral amplifier 222 connected to each signal line Sig1 to Sig8. Then, in step S804, the control circuit 112 controls the drive line Vg(A × (2 × L +1 The power line Vg(A × (2 × L)) is set to high for a predetermined period. Here, B is a number from (0 to L), and the charge accumulated in the conversion element C of each pixel 201 connected to a total of L+1 rows, skipping one row each, is simultaneously transferred to each signal line Sig1 to Sig8. For example, in the case of 3-row binning (L=1), A is 0, B is 0 and 1, so here the charge accumulated in the conversion element C of each pixel 201 in the 0th and 2nd rows of the pixel array 200 is transferred. Here, as shown in Example 3, the drive line Vg(0) of the 0th row becomes a dummy drive line that is not used for the radiation image at the beginning of the drive circuit 210. Next, in step S805, the control circuit 112 controls the drive line Vg(A × (2 × L)) +1 Set ) + 2 × B + 1) to high for a predetermined period. Here again, B will be a number from (0 to L), and step S 8In step 04, the charge accumulated in the conversion element C of each pixel 201 connected to the row transferred and the adjacent L+1 rows is simultaneously transferred to the respective signal lines Sig1 to Sig8. For example, in the case of 3-row binning (L=1), A is 0 and B is 0 and 1, so here the drive lines Vg(1) and Vg(3) are controlled to transfer the charge accumulated in the conversion element C of each pixel 201 in the 1st and 3rd rows of the pixel array 200. Then, in step S806, the control circuit 112 controls SHS to a high level for a predetermined period. This performs a signal sample-and-hold operation on the charge of each pixel 201 connected to the A×(2×L+1)th row to the (A+1)×(2×L+1)th row that has been transferred. For example, in the case of 3-row binning (L=1), a signal sample-and-hold operation is performed here on the charge of each pixel 201 connected to the 0th to 3rd row. As mentioned earlier, the 0th row of the pixel array 200 is a dummy row that is not used for the radiation image, so in reality, it is a signal sample-and-hold operation of the charge of each pixel 201 connected to the 1st to 3rd rows. After this, in step S807, the control circuit 112 controls the multiplexer 227 and the readout circuit 220. This sequentially performs AD conversion on the difference between the output of the signal sample-and-hold circuit and the output of the noise sample-and-hold circuit of each amplifier circuit 221 connected to the signal lines Sig1 to Sig8. As a result, for example, in the case of 3-row binning (L=1), the analog binned image signals of each pixel 201 connected to the 1st to 3rd rows are sequentially generated. After that, in step S808, the value of counter A, which performed the signal sample-and-hold operation, is increased by 1, and the process moves to the determination in step S809. In step S809, it is determined whether (2×L+1)×A is greater than the number of rows that make up the pixel array 200. In other words, here it is determined whether the analog binning readout process for all rows has been completed, and if the analog binning readout process for all rows has not been completed, the process returns to step S802. Then a second analog binning readout is performed. Here, in step S804, for example, in the case of 3-row binning (L=1), A is 1 and B is 0 and 1, so here the drive lines Vg(3) and Vg(5) are controlled to perform charge transfer of each pixel 201 connected to the 3rd and 5th rows of the pixel array 200.Here, since charge has already been transferred to each pixel 201 connected to the third row when the drive lines Vg(1) and Vg(3) were controlled, transferring empty charge is equivalent to performing charge transfer only on each pixel 201 connected to the fifth row. Subsequently, in step S805, in the case of 3-row binning (L=1), A is 1 and B is 0 and 1, so the drive lines Vg(4) and Vg(6) are controlled here. Then, in step S806, in the case of 3-row binning (L=1), a signal sample-and-hold operation is performed on the charge of each pixel 201 connected to the fourth to sixth rows. As a result, in step S807, these outputs are converted AD, and the image signals after analog binning are sequentially generated. Subsequently, in step S808, the value of counter A, which performed the signal sample-and-hold operation, is increased by 1, and in step S809, it is determined whether (2×L+1)×A (A is 2 here) is greater than the number of rows that make up the pixel array 200. If the pixel array 200 consists of 6 rows, the analog binning readout process for all rows is completed at this point, and the readout process for the readout period ends. If the pixel array 200 consists of 9 rows, the process returns to step S802, and in steps S802 to S807, image signals equivalent to those after analog binning of each pixel 201 connected to rows 7 to 9 of the pixel array 200 are sequentially generated. Then, in step S808, the value of counter A, which has undergone a signal sample-and-hold operation, is increased by 1. Finally, in step S809, when (2 × L + 1) × A (where A is 3) matches the number of rows in the pixel array 200, the analog binning readout process for all rows is completed, and the readout period process ends.

[0056] In all of the above embodiments, the drive circuit 210 that controls the drive line Vg can, for example, have a circuit configuration including a shift register 2101 and a plurality of level shifters 2102, as shown in Figure 12. The shift register 2101 may consist of a plurality of AND gates 2103 and a plurality of D flip-flop circuits 2104. The plurality of shift registers 2102, plurality of AND gates 2103, and plurality of D flip-flop circuits 2104 exist for the number of rows of pixels 201 that make up the pixel array 200. Each level shifter 2102 sets its output to VON (Hi) when the output of the shift register 2101 input to it is high level, and sets its output to VOFF (Lo) when the output of the input shift register 2101 is low level. This controls the drive line Vg connected to each level shifter 2102 to either a high level or a low level.

[0057] The shift register 2101 operates according to the signals XOE (output enable), STV (start pulse), and CPV (shift clock) supplied from the control circuit 210.

[0058] For example, in the control example of analog binning operation in two adjacent rows shown in Example 1, the control circuit 210 can be implemented by supplying signals XOE, STV, and CPV as shown in the timing chart in Figure 13. The control circuit 210 raises the signal STV to a high level for a predetermined period, and during that time, it applies a pulsed signal CPV, thereby raising the output Q of the D flip-flop circuit 2104 connected to the drive line Vg(1) to a high level. Subsequently, the control circuit 210 raises the signal XOE to a low level, causing both inputs of the AND circuit connected to the drive line Vg(1) to become high, and the output of the AND circuit 2103 to transition to a high level. This is input to the level shifter 2102 connected to Vg(1), and the drive line Vg(1) becomes high level. At this time, the control circuit 210 keeps the signal XOE at a low level and again applies a pulsed signal CPV. This shifts the output Q of the D flip-flop circuit 2104 connected to drive line Vg(1) to the output Q of the D flip-flop circuit 2104 connected to drive line Vg(2). As a result, the output Q of the D flip-flop circuit 2104 connected to drive line Vg(1) becomes low level. This causes the output of the AND circuit 2103 connected to drive line Vg(1) to become low level, and simultaneously the output of the AND circuit 2103 connected to drive line Vg(2) to become high level. In this way, it is possible to control drive line Vg(1) from high level to low level and simultaneously control drive line Vg(2) from low level to high level. Subsequently, by appropriately applying the signals CPV and XOE, the control of drive line Vg in Example 1 can be realized.

[0059] Furthermore, in Examples 2 and 3, by changing the way signals XOE, STV, and CPV are supplied, it is possible to stagger the period during which a high level is applied to the drive line Vg of an adjacent row, while simultaneously applying the same level to the drive line Vg of a non-adjacent row. Moreover, it is possible to control the drive line Vg of a certain row from a high level to a low level while simultaneously controlling the drive line Vg of an adjacent row from a low level to a high level.

[0060] The invention is not limited to the embodiments described above, and various modifications and variations are possible without departing from the spirit and scope of the invention. Accordingly, claims are attached to disclose the scope of the invention.

[0061] Furthermore, the disclosures herein include the following imaging devices, radiation imaging devices, and radiation imaging systems.

[0062] (Item 1) A radiation imaging apparatus comprising: a plurality of pixels arranged in a matrix, each having a conversion element that converts radiation or light into electric charge and a switch element that controls the output of electric charge from the conversion element; a drive unit that outputs a drive signal to drive the switch element; a plurality of drive lines that connect the drive unit and the pixels row by row and supply the drive signal output by the drive unit to the switch element; and a readout unit that reads electric charge from the pixels to which the drive signal has been supplied and generates an image data signal, The drive unit outputs a first drive signal to a first drive line among a plurality of drive lines after radiation irradiation, and outputs a second drive signal to a second drive line adjacent to the first drive line, with the timing staggered to reduce line noise along the drive line, and the readout unit generates an image data signal by summing a first charge read from a pixel by the drive unit outputting a drive signal to the first drive line and a second charge read from a pixel by the drive unit outputting a drive signal to the second drive line.

[0063] (Item 2) The radiation imaging apparatus according to item 1, characterized in that the drive unit outputs drive signals to the first drive line and the second drive line such that the falling edge of the first drive signal and the rising edge of the second drive signal coincide.

[0064] (Item 3) The radiation imaging apparatus according to item 1 or 2, further comprising a processing unit that processes the image data signal to generate an image signal, wherein the processing unit processes the image data signal to generate an image signal of a pixel connected to a first drive line and a pixel connected to a second drive line.

[0065] (Item 4) The radiation imaging apparatus according to any one of items 1 to 3, characterized in that the drive unit outputs a third drive signal to a third drive line adjacent to the second drive line, outputs a fourth drive signal to a fourth drive line adjacent to the third drive line, outputs the first drive signal and outputs the second drive signal with staggered timing to reduce line noise along the drive line, and the readout unit generates an image data signal by summing a third charge read out from a pixel by the drive unit outputting a drive signal to the third drive line, a fourth charge read out from a pixel by the drive unit outputting a drive signal to the fourth drive line, the first charge and the second charge.

[0066] (Item 5) The radiation imaging apparatus according to item 4, characterized in that, after outputting the first drive signal, the second drive signal, the third drive signal, and the fourth drive signal, the drive unit subsequently outputs a fifth drive signal to a fifth drive line adjacent to either the third or fourth drive line, a sixth drive signal to a sixth drive line adjacent to the fifth drive line, a seventh drive signal to a seventh drive line adjacent to the sixth drive line, and an eighth drive signal to one of the third or fourth drive lines, with the timing staggered to reduce line noise along the drive lines.

[0067] (Item 6) The radiation imaging apparatus according to item 5, characterized in that the fifth drive line is adjacent to the fourth drive line, and the eighth drive signal is output to the fourth drive line.

[0068] (Item 7) The radiation imaging apparatus according to any one of items 4 to 6, characterized in that the conversion element connected to the first drive line is a dummy conversion element.

[0069] (Item 8) A radiation imaging apparatus comprising: a plurality of pixels arranged in a matrix, each having a conversion element that converts radiation or light into electric charge and a switch element that controls the output of the electric charge from the conversion element; a drive unit that outputs a drive signal to drive the switch element; a plurality of drive lines that connect the drive unit and the pixels row by row and supply the drive signal output by the drive unit to the switch element; and a readout unit that reads the electric charge from the pixels to which the drive signal has been supplied and generates an image data signal, The radiation imaging apparatus is characterized in that the drive unit outputs a first drive signal to a first drive line among a plurality of drive lines after radiation irradiation, and outputs a second drive signal to a second drive line adjacent to the first drive line, with a timing difference, and the readout unit generates an image data signal by summing a first charge read out from a pixel by the drive unit outputting a drive signal to the first drive line and a second charge read out from a pixel by the drive unit outputting a drive signal to the second drive line.

[0070] (Item 9) A radiation imaging system comprising a radiation imaging device described in any one of items 1 to 8, and a control device that acquires an image signal from the radiation imaging device and processes the image signal. [Explanation of symbols]

[0071] 100 Radiation Imaging Systems 110 Radiation imaging device 201 pixels 210 Drive Circuit 220 Readout Circuit

Claims

1. A plurality of pixels arranged in a matrix, each having a conversion element that converts radiation or light generated by radiation irradiation into an electric charge, and a switch element that controls the output of the electric charge from the conversion element, A drive unit that outputs a drive signal to drive the switch element, Multiple drive lines connect the drive unit and the pixels row by row and supply the drive signals output by the drive unit to the switch element, A readout unit that reads charge from pixels to which a drive signal is supplied and generates image data signals, A radiation imaging device equipped with, The drive unit outputs a first drive signal to the first of the multiple drive lines after radiation irradiation, and a second drive signal to the second drive line adjacent to the first drive line, with the high-level period of the first drive signal and the high-level period of the second drive signal staggered to reduce line noise along the drive line. The reading unit is characterized in that it generates an image data signal by summing a first charge read from a pixel by the drive unit outputting a drive signal to a first drive line and a second charge read from a pixel by the drive unit outputting a drive signal to a second drive line.

2. The radiation imaging apparatus according to claim 1, characterized in that the drive unit outputs drive signals to the first drive line and the second drive line such that the falling edge of the first drive signal and the rising edge of the second drive signal coincide.

3. The radiation imaging apparatus according to claim 1, further comprising a processing unit that processes the image data signal to generate an image signal, wherein the processing unit processes the image data signal to generate an image signal of a pixel connected to a first drive line and a pixel connected to a second drive line.

4. The drive unit outputs a third drive signal to the second drive line, which is adjacent to the third drive line on the opposite side of the first drive line; a fourth drive signal to the third drive line, which is adjacent to the fourth drive line on the opposite side of the second drive line; the first drive signal; and the second drive signal, with the high-level period of the third drive signal and the high-level period of the fourth drive signal shifted, and the high-level period of the second drive signal and the high-level period of the third drive signal shifted, in order to reduce line noise along the drive line. The readout unit generates an image data signal by summing the third charge read from the pixel by the drive unit outputting a drive signal to the third drive line, the fourth charge read from the pixel by the drive unit outputting a drive signal to the fourth drive line, the first charge, and the second charge. The radiation imaging apparatus according to feature 1.

5. The radiation imaging apparatus according to claim 4, characterized in that the drive unit outputs the first drive signal, the second drive signal, the third drive signal, and the fourth drive signal, and then subsequently outputs a fifth drive signal to the fourth drive line adjacent to the fifth drive line on the opposite side of the third drive line, a sixth drive signal to the fifth drive line adjacent to the fifth drive line on the opposite side of the fourth drive line, a seventh drive signal to the sixth drive line adjacent to the sixth drive line on the opposite side of the fifth drive line, and an eighth drive signal to the fourth drive line, with the high-level period of the sixth drive signal and the high-level period of the seventh drive signal shifted, and the high-level period of the eighth drive signal and the high-level period of the fifth drive signal shifted, in order to reduce line noise along the drive line.

6. The radiation imaging apparatus according to claim 4, characterized in that the conversion element connected to the first drive line is a dummy conversion element.

7. A radiation imaging system comprising a radiation imaging device as described in claim 1, and a control device that acquires an image signal from the radiation imaging device and processes the image signal.

Images