Systems, methods, and computer devices for transistor-based neural networks

Abstract

A computer system, method and apparatus for operating an artificial neural network is provided. The system includes a neuron. The neuron includes a plurality of synapses including charge-trapping transistors (CTTs) for processing an input signal, a storage block for receiving drain currents from the plurality of synapses, a storage capacitor for storing charge from the drain currents and serving as a short-term memory for the stored signal, a discharge pulse generator for generating an output signal by discharging the stored charge during a discharge cycle, and a comparator for comparing the output signal as an input voltage with a reference voltage. The CTTs provide synaptic weights, and the drain currents are generated as an output of multiplication from the plurality of synapses. The comparator generates a first output if the input voltage is above the reference voltage and a second output if the input voltage is below the reference voltage.

Description

[Technical Field]

[0001] The present disclosure generally relates to neural networks and numerical computation, and more specifically to systems, methods, and computer apparatus for analog-based neural networks and computation. [Background Art]

[0002] A generalized artificial neural network (ANN) is sometimes described as a machine learning architecture that borrows from biological neural structures. In this architecture, the activation of neurons from a first input can cascade to subsequent layers, causing either excitatory or inhibitory behavior of neurons in the subsequent layers. Neural networks form the foundation of artificial intelligence systems and are being applied in almost every aspect of technical solutions. One of the most important challenges in applying neural networks and artificial intelligence to computer problems is the total cost of ownership of the solution, particularly the power consumption of the solution. In conventional data centers, power is not a constraint, and high-power-consumption processors such as CPUs and GPUs are used to execute neural network algorithms on various types of data. However, there is an urgent need to orient artificial intelligence toward real-world applications. For example, in specific cases where various types of sensors generate data, the power budget imposes a significant constraint. This constraint has increased the need for low-power consumption methods for processing neural network algorithms that are much more efficient than general-purpose CPUs and GPUs.

[0003] FIG. 1A shows a general conventional ANN 100. FIG. 1A shows a basic inference system architecture. The ANN 100 includes an input layer 102 that receives an input, a hidden layer 104 that performs computation, and an output layer 106 that provides an output. Each of the input layer 102, the hidden layer 104, and the output layer 106 includes one or more neurons 108.

[0004] ANN100 is a machine learning architecture that loosely borrows its morphology from biological neural structures. In biological neural structures, activation of neuron 108 from a first input signal (not shown) (e.g., in the input layer 102) cascades to subsequent layers (e.g., the hidden layer 104). This cascade triggers excitatory or inhibitory behavior in neurons in the subsequent layers.

[0005] Individual neurons 108 can perform any of the following actions, either individually or in combination. Neurons 108 in the layer of ANN100 receiving the cascade can combine the values ​​of neurons 108 in the previous layer with their associated synaptic weights (not shown). Neurons 108 may also be subjected to nonlinear scaling, which will be hereafter referred to as the "activation function." The aforementioned combinations of values ​​are achieved by multiplication and then summed with other products. The multiplication is performed according to the activation of neuron 108 multiplied by its synaptic weight.

[0006] As a result of the activation function, advantageously, the output of the progress layer (e.g., hidden layer 104) does not have to be linearly mapped to the preceding layer (e.g., input layer 102). Nonlinear scaling advantageously allows gradient descent during the learning phase. Neuron 108 can propagate values ​​to subsequent layers of the neuron (e.g., output layer 106).

[0007] The process described above is implemented in conventional neural networks (such as ANN100). Therefore, important computational tasks such as vector-matrix multiplication can be implemented in ANN100. In this case, the input or neuron activation vector xi is multiplied by the cumulative multiplication (MAC) function (Σw) to generate the activation. ij *x i Using ), the matrix of synaptic weights w ij It is multiplied by this.

[0008] In implementations, product and sum are based on absolute values ​​(numerical values ​​in the case of digital, or voltage or current in the case of analog). For example, in digital implementations, input signals and synaptic weights are represented in binary, multiplication is performed with a digital multiplier, and the results are accumulated or summed as digital numbers. This method is relatively inefficient in terms of energy and silicon area efficiency.

[0009] Figure 1B shows a box diagram of the various functions that a conventional ANN100 can perform. Individual neurons 108 can perform various actions individually or in combination. Neurons 108 in a specific layer of the ANN100 (such as the hidden layer 104) can perform any of the functions described in Figure 1A.

[0010] The input layer 102 receives an input signal (not shown). The input layer 102 further multiplies the input signal by the synaptic weights (not shown) of neuron 108. In 112, the ANN 100 accumulates, i.e., sums up, the results of all the multiplications performed. In 114, the ANN adds a bias to the accumulated output of the multiplications and applies the sum to the activation function 116. With the activation function 116, the ANN executes the activation function and cascades the output of the activation function to the subsequent layers of neurons.

[0011] Figure 2 shows a conventional digital multiplication array 200. Figure 2 shows a digital implementation of a multiplication-accumulation array 200 that can compute functions such as multiplication and accumulation of conventional ANNs, like ANN100 in Figure 1.

[0012] The array 200 includes an activation memory 202 that receives output signals from the previous neurons 108 of the previous layers 102, 104; a weight memory 204 that supplies synaptic weights; a multiplier accumulator (MACS) 205 that multiplies the input signals and sums the outputs of the multiplications; and an accumulator 206 that accumulates the output signals of the MACs 205 that are being added.

[0013] The array 200 further includes a MAC unit 208 illustrating one possible embodiment of the multiplication accumulator 205.

[0014] Figure 11 shows a conventional analog conduction-based inference system 1100 that uses resistors to store synaptic weights in order to perform ANN100 in Figure 1A.

[0015] In system 1100, memory elements are used to create resistance proportional to the desired synaptic weight. Memory elements may require special processing layers in semiconductor manufacturing. A voltage is applied to a resistor (not shown), and the resulting current is the product of the input signal and the weight, according to Ohm's law, I=V / R. The weight is stored as 1 / R. [Overview of the project] [Problems that the invention aims to solve]

[0016] This system is dependent on process, absolute voltage, and temperature. Time-dependent drift of these parameters and inductive noise can introduce errors in the current, potentially directly affecting the accuracy of calculations and the performance of neurons implemented using System 1100. Complex techniques may be carefully employed to compensate for such non-idealities, which are costly and limit achievable performance. This difficulty makes analog in-memory computing extremely challenging and commercially impractical. Examples of techniques used to implement such in-memory solutions include phase-change memory (PCM), resistive RAM (RRAM), flash memory, and capacitive memory. The systems, methods, and apparatus of this disclosure can advantageously overcome at least some of these difficulties.

[0017] The calculations between the input layer 102 and the output layer 106 may be performed according to the synaptic weights 105.

[0018] System 1100 further includes hardware 1110 that implements ANN100. Hardware 1110 includes transistor 1112. Transistor 1112 may be integrated to form conductance pair 1114. Hardware 1110 further includes non-volatile memory 1116. [Means for solving the problem]

[0019] This disclosure represents an efficient and elegant analog processing system applicable at minimal cost to a number of purposes, including neural network processing. This disclosure represents embodiments including analog memory and computing mechanisms, such as those utilizing charge trap transistor (CTT) technology to adjust the threshold of N-type metal-oxide-semiconductor (NMOS) transistors to offset thresholds in a calibration mechanism, when implemented in use and in computer systems, methods, and apparatus. Neurons that perform functions such as multiplication, accumulation, and nonlinear activation in a neural network can be calibrated using existing standard silicon processing techniques such as complementary metal-oxide-semiconductor (CMOS).

[0020] To overcome the power and cost barriers inherent in intelligent systems, silicon neural network architectures implemented using analog / mixed-signal design techniques are required. These analog solutions can be improved by stability mechanisms to ensure stability and reliability. Advantageously, the neural networks implemented in the aforementioned embodiments can be used routinely over long periods.

[0021] This disclosure employs a novel architectural approach to enable the use of a wide variety of memory types, including charge-trap transistors (CTTs), where absolute voltage, current, and device characteristics do not affect accuracy. Instead of appropriately scaling values ​​depending on absolute voltage (or current), time is used as the reference. All calculations are performed ratiometrically with respect to time. Since a stable time reference (e.g., a crystal oscillator) is generally easy and inexpensive to obtain, all calculations can be performed against this stable time reference to calibrate all other dependencies.

[0022] In one embodiment, the fundamental computational elements required for signal processing, including neural network processing, are implemented using time or phase as fundamental information elements. This embodiment differs significantly from conventional approaches because its performance does not directly depend on absolute physical criteria such as voltage, current, conductance, or inductance, which are commonly used in analog signal processing solutions. By appropriately utilizing time or phase, significant performance improvements can be achieved that are more advantageous than other analog computing approaches. Such advantageous performance improvements include greater sensitivity to environmental and manufacturing non-ideal conditions.

[0023] In one embodiment, information is encoded as a change in time or phase of a periodic signal. Other physical phenomena may only be relevant in relation to the instantaneous value of a physical phenomenon in a ratiometric sense.

[0024] In one embodiment, the input is converted into a time pulse, which is then weighted by the conductance of an element whose conductance can be programmed and periodically updated, such as a CTT memory structure, to generate a scaled current pulse. The charge resulting from the current pulse is stored in a storage capacitor and used as a control signal for a comparator, such as a TIQ comparator. It is then propagated to the next cascaded layer or to either temporary storage or an ephemeral memory device, such as ephemeral memory storage.

[0025] In one embodiment, a comparator such as a threshold inverter quantization (TIQ) comparator is provided. In one embodiment, the TIQ comparator performs comparison and quantization. In one embodiment, the TIQ comparator includes at least one inverter in which a part of transistors function as charge trap devices. Each inverter includes two pairs of CTTs, each pair including a p-channel metal oxide semiconductor (PMOS) transistor and an n-channel metal oxide semiconductor (NMOS) transistor. The threshold of the TIQ comparator of each inverter 1001 is set according to a ratio obtained by dividing the strength of the PMOS CTT of the inverter 1001 by the strength of the NMOS CTT of the inverter 1001. It is understood that the strength of each transistor is related to the width of each transistor, the length of each transistor, the mobility of each transistor, and / or other related parameters or factors of each transistor. The TIQ comparator device may be a CTT calibrated TIQ comparator.

[0026] In one embodiment, an ephemeral memory device that temporarily holds information used after a short time delay is provided. The ephemeral memory device may include a plurality of sub-threshold pass-transistor logic (PTL) delay line blocks forming an inner ring of asynchronously controllable delays. The inner ring may be supported by an outer ring of D flip-flops forming an asynchronous counter. This combination can operate in conjunction with each other to achieve efficient short-term accurate storage of delay states.

[0027] In one embodiment, a calibration method is provided. In an embodiment, all device operations can be calibrated according to one specified reference structure including weight block → current mirror → storage capacitor → comparator chain. Once the reference chain is calibrated to a unit scale time (e.g., calibrating the full-scale charge of a 1 pF capacitor in 1 μs), all current mirror / capacitor-comparator chains may be calibrated using the same reference signal chain.

[0028] A system for operating an artificial neural network (ANN) is provided. The system includes neurons. Each neuron comprises multiple synapses, each containing a charge-trap transistor (CTT) that processes an input signal; a storage block that receives drain current from the multiple synapses; a storage capacitor that stores charge from the drain current to function as a short-term memory of the stored signal; a discharge pulse generator that generates an output signal by discharging the stored charge during a discharge cycle; and a comparator that compares the output signal, as an input voltage, to a reference voltage. The CTT supplies synaptic weights. The drain current is generated as the output of the multiplication from the multiple synapses. The comparator generates a first output if the input voltage is above the reference voltage, and a second output if the input voltage is below the reference voltage.

[0029] In one embodiment, the cumulative block includes a memory device that receives drain current from multiple synapses, multiple multipliers that store synaptic weights and perform multiplication of synaptic weights by input signals, and a cumulative unit that sums the outputs of the multiplications from the multiple multipliers to obtain a cumulative signal.

[0030] In one embodiment, the comparator is a threshold inverter quantization (TIQ) comparator comprising a cascade of at least one complementary metal-oxide-semiconductor (CMOS) inverter. Each CMOS inverter comprises a p-channel metal-oxide-semiconductor (PMOS) transistor and an n-channel metal-oxide-semiconductor (NMOS) transistor. The reference voltage corresponds to the self-generated threshold of the TIQ comparator. The threshold of the TIQ comparator is tunable via the PMOS or NMOS transistors. The threshold of the TIQ comparator corresponds to the ratio of the intensity of the PMOS transistor to the intensity of the NMOS transistor.

[0031] The drain current may be generated as the output of a multiplication of multiple synapses, or it may generate a charge equal to the product of the input signal and the synaptic weight.

[0032] Before connecting to the storage block, the drain currents may be connected together, the storage block may sum the drain currents, and the sum of the drain currents may be transmitted to the storage capacitor as a storage signal for storage.

[0033] Each CTT may perform a multiplication of the drain current representing the synaptic weight and time as input, and all multiplications may be stored in a storage capacitor.

[0034] The storage block may also sum the drain currents as a wired OR function.

[0035] The threshold voltage of each CTT can be programmed to store the values ​​of the corresponding synaptic weights. Each CTT includes a gate to which a voltage pulse is applied. The source of the voltage pulse is grounded. The gate-source voltage is constant. The voltage pulse transmits information over time.

[0036] Resistance can be used to store synaptic weights.

[0037] This resistor may be provided by a CTT.

[0038] In such cases, synaptic weights are stored in the threshold voltage shift of the CTT.

[0039] The charge from the first scaled current pulse may be stored on a storage capacitor so that it can be used as a control signal.

[0040] The integrated charge in each neuron is proportional to the product of the input signal and the synaptic weight, and the value of the integrated charge remains constant until discharge.

[0041] The current flowing through the CTT may be mirrored by a current mirror so that charge can be effectively stored on the capacitor to generate a voltage proportional to the weighted sum of the inputs.

[0042] The discharge pulse generator may also be a discharge cycle cascode current source.

[0043] The discharge pulse generator may further transmit the accumulated signal during storage in order to achieve the subtraction function in ANN.

[0044] In addition to the reference voltage of the TIQ comparator, a second reference voltage may be provided.

[0045] A second reference voltage may be provided in addition to the reference voltage of the TIQ comparator.

[0046] An activation pulse may be further generated as an output signal.

[0047] Multiple synapses may receive an input signal, convert the voltage of the input signal into a current, and generate a second scaled current pulse as an output signal.

[0048] The system may further include an ephemeral memory device for temporarily holding information between layers of the ANN. This ephemeral memory device includes an inner ring containing an analog subthreshold delay block that provides an asynchronously controllable delay, and an outer ring containing a plurality of asynchronous counters that support the inner ring. The inner and outer rings work together to achieve efficient, short-term, and accurate storage of the delayed state.

[0049] An ANN may include an input layer that receives inputs with neurons, at least one hidden layer that multiplies the inputs by synaptic weights to produce a product, adds a bias to the product to produce a sum, applies the sum to an activation function, executes the activation function to produce an output signal, and cascades the output signal to subsequent layers of neurons, and an output layer that provides the output signal. Each of the input layer, at least one hidden layer, and the output layer contains at least one neuron.

[0050] A subset of CTT may also be NMOS CTT.

[0051] A subset of CTT may also be PMOS CTT.

[0052] Each CTT may include a high dielectric constant metal gate. A drain bias may be applied during the charge trapping process.

[0053] Each CTT may include a gate dielectric containing an interface layer of SiO2.

[0054] Each gate dielectric may include an SiO2 interface layer and cascaded HfSiON layers.

[0055] Each CTT can apply a drain bias during the charge trapping process to stably trap other carriers in the gate dielectric.

[0056] The threshold voltage of each CTT may be modulated by the amount of charge trapped in each gate dielectric. Each drain bias may enhance and stabilize the charge trapping process by an enhanced local heating effect. Each threshold voltage of each CTT may be shiftable by a controlled amount and may encode a parameter value.

[0057] The weight values ​​are programmed by applying gate pulses of different lengths with a set programming voltage bias. During positive programming, a positive gate voltage pulse may be applied, and the threshold voltage may be shifted in a first direction. During negative programming, a negative pulse is applied, and the threshold voltage is shifted in a second direction opposite to the first direction.

[0058] A constant amplitude pulse may be applied to the gate's source voltage.

[0059] Constant-amplitude pulses may propagate directly into subsequent layers of the ANN.

[0060] Constant-amplitude pulses can pass through a nonlinear function and propagate to subsequent layers of an ANN.

[0061] This nonlinear function may also be a rectifier-linear unit (ReLU).

[0062] The first output may be higher than the second output. In one embodiment, the first output may be a high output and the second output may be a low output.

[0063] The first output may be lower than the second output. In one embodiment, the first output may be a low output and the second output may be a high output.

[0064] A method is provided for an artificial neural network (ANN) including neurons. The method includes the steps of processing an input signal through a plurality of charge-trap transistors (CTTs), the CTTs supplying synaptic weights, generating drain currents from the plurality of CTTs as the output of a multiplication, receiving drain currents from the plurality of CTTs, accumulating charge from the drain currents to function as a short-term memory of the accumulated signal, generating an output signal by discharging the accumulated charge during a discharge cycle, and comparing an input voltage with a reference voltage using a comparator. The comparator generates a first output if the input voltage is greater than or equal to the reference voltage, and a second output if the input voltage is less than the reference voltage.

[0065] In one embodiment, the step of receiving drain current from multiple CTTs includes the steps of receiving drain current from multiple synapses, storing synaptic weights, performing synaptic weight multiplication by input signals, and summing the outputs of the multiplications to obtain a cumulative signal.

[0066] In one embodiment, the comparator is a threshold inverter quantization (TIQ) comparator. The TIQ comparator comprises a cascade of at least one complementary metal-oxide-semiconductor (CMOS) inverter, each cascade of CMOS inverters comprising a p-channel metal-oxide-semiconductor (PMOS) transistor and an n-channel metal-oxide-semiconductor (NMOS) transistor. The reference voltage corresponds to the self-generated threshold of the TIQ comparator. The threshold of the TIQ comparator is adjustable via the PMOS or NMOS transistor, and the threshold of the TIQ comparator corresponds to the ratio of the intensity of the PMOS transistor to the intensity of the NMOS transistor.

[0067] The input signal may be received by a CTT. The voltage of the input signal may be converted to a current. A second scaled current pulse may be generated as the output signal.

[0068] This method may include the steps of: an input layer receiving an input; a hidden layer multiplying the input by synaptic weights to generate a product; a hidden layer adding a bias to the product to generate a sum; a hidden layer applying the sum to an activation function; a hidden layer executing the activation function to generate an output signal; and a hidden layer cascading the output signal to subsequent layers of neurons.

[0069] The method may further include a step of calibrating the ANN. The step of calibrating the ANN may include a step of determining a specified reference weight block; a step of calibrating the current mirror according to the specified reference weight block; a step of calibrating the storage capacitor according to the specified reference weight block; a step of calibrating the TIQ comparator according to the specified reference weight block; and a step of calibrating each synaptic weight stored in the CTT within the specified reference weight block.

[0070] After calibration, the current mirror, storage capacitor, and comparator may each be synchronized with a designated reference weight block. Once the calibration of the current mirror, capacitor, and comparator is complete, the signal path of each neuron is aligned with the designated reference weight block, and all neurons are aligned proportionally with one another.

[0071] The first output may be higher than the second output. In one embodiment, the first output may be a high output and the second output may be a low output.

[0072] The first output may be lower than the second output. In one embodiment, the first output may be a low output and the second output may be a high output.

[0073] A threshold inverter quantization (TIQ) comparator is provided that compares an input voltage to a reference voltage. The TIQ comparator includes an input connection to receive an input signal and a cascade of at least one complementary metal-oxide-semiconductor (CMOS) inverter. Each CMOS inverter includes a p-channel metal-oxide-semiconductor (PMOS) transistor and an n-channel metal-oxide-semiconductor (NMOS) transistor. The TIQ comparator further includes an output connection to transmit an output signal, a power supply connection to receive power, and ground. The reference voltage corresponds to the self-generated threshold of the TIQ comparator. When the input voltage exceeds the threshold, the second output inverts to the first output. When the input voltage falls below the threshold, the first output inverts to the second output. The threshold of the TIQ comparator is adjustable via the PMOS or NMOS transistors. The threshold of the TIQ comparator corresponds to the ratio of the intensity of the PMOS transistors to the intensity of the NMOS transistors.

[0074] The PMOS transistor may be a PMOS CTT. The NMOS transistor may be an NMOS CTT. The TIQ comparator device may be configured to be calibrated by the CTT.

[0075] The CTT may be configured to provide an adjustable threshold to the TIQ comparator for calibrating a baseline on an artificial neural network (ANN) that includes further CTTs.

[0076] Further subsets of CTTs may be PMOS devices.

[0077] Further subsets of CTTs may be NMOS devices.

[0078] The threshold voltage of the TIQ comparator device may be maintained and recalibrated by reprogramming the threshold voltage recorded in the weight matrix.

[0079] Correlated double sampling may be used to achieve improved cancellation of threshold shift in TIQ comparator devices.

[0080] In this case, correlated double sampling can initialize the voltage across the capacitor.

[0081] The TIQ comparator may also be a dual-slope TIQ comparator.

[0082] The first output may be higher than the second output. In one embodiment, the first output may be a high output and the second output may be a low output.

[0083] The first output may be lower than the second output. In one embodiment, the first output may be a low output and the second output may be a high output.

[0084] An ephemeral memory device is provided for temporarily holding information between layers of an artificial neural network (ANN). This ephemeral memory device includes an inner ring containing analog subthreshold delay blocks that provide asynchronously controllable delays, and an outer ring containing multiple asynchronous counters that support the inner ring. The inner and outer rings work together to achieve efficient, short-term, and accurate storage of delayed states.

[0085] An analog subthreshold delay block can include multiple subthreshold-pass transistor logic (PTL) delay line elements.

[0086] An asynchronous counter may include a first asynchronous counter. The first asynchronous counter may be a 1-bit asynchronous subthreshold counter. The asynchronous counter may include a D flip-flop.

[0087] An ephemeral memory device may further include multiple asynchronous counters.

[0088] The asynchronous counter may be a cascaded subthreshold counter of 1 bit.

[0089] Ephemeral memory devices may operate asynchronously.

[0090] Time may be temporarily stored in a space for power consumption in nanowatts or picowatts.

[0091] The ephemeral memory device can receive a first activation pulse and store the width of the first activation pulse via a first asynchronous counter. The device can transmit the first activation pulse to a subsequent layer of the ANN by counting down the first asynchronous counter.

[0092] The analog subthreshold delay block and the first asynchronous counter can together form a positive feedback loop with an internal delay. This forms an oscillator.

[0093] The oscillator may be a self-timing oscillator that oscillates based on the frequency of the delay line element. The ephemeral memory device may further include a second counter, which is clocked by the self-timing oscillator and created by the delay line element and a first asynchronous counter.

[0094] The oscillator may be activated while the storage capacitor is discharging. When the oscillator is activated, it triggers a first asynchronous counter to count up. When the storage capacitor has finished discharging, the oscillator is deactivated, and the first asynchronous counter retains its value. The oscillator is then activated again, and the first asynchronous counter can count down to zero during a first time period. During this first time period, pulses may be generated as input to subsequent neurons.

[0095] While the storage capacitor is discharging, the neuron may generate a first activation pulse. When the first activation pulse is high, the first activation pulse may activate the oscillator. When the first activation pulse is low, the first activation pulse deactivates the oscillator, the first asynchronous counter stops, the first asynchronous counter stores a value representing the pulse width of the first activation pulse, and the first asynchronous counter may further retain the stored value for a certain period of time.

[0096] The duration of time can be as short as a few seconds.

[0097] In this case, when the first activation pulse is high, the first asynchronous counter counts up, and when the ephemeral memory device applies the first activation pulse to a subsequent neuron to activate the delay line element and generate a second activation pulse equal to the first activation pulse, the first asynchronous counter may count down.

[0098] In this case, the first asynchronous counter may be paired with a second counter configured inversely to the first asynchronous counter. That is, when the first asynchronous counter counts down, the second counter counts up and further stores the width of the first activation pulse.

[0099] Therefore, the second counter, which counts up, is activated by the discharge cycle of the storage capacitor and deactivated when the comparator reverses its state according to the threshold voltage. The first asynchronous counter, which counts down, may be activated by the inference start signal to the subsequent layers of the ANN.

[0100] This device can use dynamic logic to save space and power.

[0101] Ephemeral memory devices may include time ephemeral memory devices.

[0102] Time may be calculated as absolute time, elapsed time, delay time, or rate of change of time.

[0103] Time may be calculated as absolute time. All information may be processed quantitatively with respect to time.

[0104] Other aspects and features will become apparent to those skilled in the art by considering the following description relating to some exemplary embodiments. [Brief explanation of the drawing]

[0105] The drawings included in this specification illustrate various examples of the articles, methods, and apparatus described herein. Please refer to the drawings.

[0106] [Figure 1A] This diagram shows a typical, conventional artificial neural network (ANN).

[0107] [Figure 1B] Figure 1A is a box diagram showing the different functions that an ANN can conventionally perform.

[0108] [Figure 2] This diagram shows a conventional digital multiplication array.

[0109] [Figure 3] This figure shows a neuron including a threshold inverter quantization (TIQ) comparator according to an embodiment.

[0110] [Figure 4] This figure shows a simplified neuron structure that utilizes charge trap transistors (CTTs) not only for multiplication but also for weight storage, according to the embodiment.

[0111] [Figure 5] This is a diagram showing a neuron according to the embodiment.

[0112] [Figure 6] This figure shows additional details of the dual-slope pulse generation process in each neuron.

[0113] [Figure 7] This figure shows a charge trap transistor (CTT) suitable for use in the neurons shown in Figures 3, 4, and 5, according to the embodiment.

[0114] [Figure 8] This figure shows an exemplary layer of an ANN including multiple CTTs according to the embodiment.

[0115] [Figure 9A] This figure shows a cascoded current mirror according to an embodiment.

[0116] [Figure 9B] This figure shows a cascoded current mirror according to an embodiment.

[0117] [Figure 10] Figures 3 and 5 show the TIQ comparator according to the embodiment.

[0118] [Figure 11]This figure shows a conventional analog conduction-based inference system that uses resistance to store synaptic weights.

[0119] [Figure 12] This figure shows a convolutional neural network (CNN) according to an embodiment.

[0120] [Figure 13] This figure shows two 3x3 matrices to be processed.

[0121] [Figure 14] This figure shows an implementation of a 3x3 convolutional neuron via simplified synapses in the CNN of Figure 12, according to an embodiment.

[0122] [Figure 15] This is a flowchart of a method for calibrating a reference block according to an embodiment.

[0123] [Figure 16] This figure shows an ephemeral memory scheme according to an embodiment.

[0124] [Figure 17] This figure shows an ephemeral memory device implementing the ephemeral memory scheme of Figure 16 according to the embodiment.

[0125] [Figure 18] This figure shows the ephemeral memory device of Figure 17 in more detail, according to the embodiment.

[0126] [Figure 19] These figures further illustrate the ephemeral memory structure shown in Figures 17 and 18 according to the embodiment.

[0127] [Figure 20] This is a flowchart illustrating a method using ANN according to the embodiment. [Modes for carrying out the invention]

[0128] To provide examples of each claimed embodiment, various apparatuses or processes are described below. The embodiments described below are not limiting to the claimed embodiments, and the claimed embodiments may cover processes or apparatuses other than those described below. The claimed embodiments are not limited to apparatuses or processes having all the features of any one of the apparatuses or processes described below, or to features common to some or all of the apparatuses described below.

[0129] One or more systems described herein may be implemented in a computer program running on a programmable computer, each comprising at least one processor, a data storage system (including volatile and non-volatile memory and / or storage elements), at least one input device, and at least one output device. For example, but not limited to, the programmable computer may be a programmable logic unit, a mainframe computer, a server, and a personal computer, a cloud-based program or system, a laptop, a personal data assistant, a mobile phone, a smartphone, or a tablet device.

[0130] Each program is preferably implemented in a high-level procedural or object-oriented programming language and / or scripting language for communication with the computer system. However, the program may also be implemented in assembly language or machine code, if necessary. In any case, the language may be a compiled language or an interpreted language. Each such computer program is preferably stored in a storage medium or device readable by a general-purpose or special-purpose programmable computer in order to configure and operate the computer when the storage medium or device is read by the computer to perform the procedures described herein.

[0131] The description of embodiments having multiple components that communicate with each other does not mean that all such components are necessary. Rather, various optional components are described in order to illustrate the wide variety of possible embodiments of the present invention.

[0132] Furthermore, process steps, method steps, algorithms, etc., may be described in sequential order (in the disclosure and / or claims), but such processes, methods, and algorithms may be configured to operate in an alternative order. In other words, any order or sequence of steps that may be described does not necessarily imply that the steps must be performed in that order. The steps of the processes described herein may be performed in any order that is practical. Furthermore, some steps may be performed simultaneously.

[0133] Where a single device or molded article is described herein, it will be readily apparent that multiple devices / molded articles (whether they cooperate or not) may be used in place of the single device / molded article. Similarly, where multiple devices or articles (whether they cooperate or not) are described herein, it will be readily apparent that a single device / article may be used in place of multiple devices or articles.

[0134] This disclosure describes a method for implementing a silicon neural network architecture, more generally a neural network in algorithmic computing functions, using analog / mixed-signal design techniques and stabilization mechanisms. Advantageously, the neural networks disclosed herein can be fabricated for both everyday and long-term use.

[0135] Traditional computing engines can be categorized into several types, including traditional computing such as the von-Neuman architecture, GPU-based computing (similar to the von-Neuman architecture but tuned for heavy mathematical operations), dataflow architectures, and combinations of the above. Traditional solutions have been implemented using digital CMOS process technology with traditional digital design approaches. Traditional solutions require a combination of memory and computing power. Differences between implementations mainly focus on how memory and computing are implemented and how information is transferred between these elements.

[0136] This disclosure relates to integrating computational and memory elements into a single device. In embodiments, the modified dataflow architecture can be used to favorably handle large computational workloads such as neural networks, although the embodiments remain entirely analog and time-domain. Advantageously, this disclosure may lead to reduced power consumption and area utilization compared to existing approaches.

[0137] Similar to how the human brain processes data, the concepts in this disclosure are principles of time-related information. Time can be measured and utilized in multiple ways, including absolute time, elapsed time, time delay (known as phase), and rate of change of time (frequency). In this disclosure, time can be used as the absolute reference. When time is used as the absolute reference, information is processed relative to time. In embodiments utilizing analog signal processing, the system may be sensitive to and dependent on absolute physical properties or parameters such as voltage, current, resistance, storage capacitance, and inductance. Since physical parameters can change with time, temperature, and manufacturing processes, relying on the absolute values ​​of physical parameters as a reference may reduce calculation accuracy. In this disclosure, we focus on time as the absolute reference, at least for the reasons stated above. Advantageously, because the calculation is performed ratiometrically, even slow drifts over time may not affect accuracy.

[0138] In the context of the results, several neural networks, including fully connected neural networks (FCNNs), multiple convolutional neural networks (CNNs), and recurrent neural networks (RNNs), were modeled using the architectures described in this disclosure. Each device and block was simulated using detailed SPICE device models and MOSRA reliability models of transistors based on physical design kits from foundries at 28nm, 22nm, and 14nm process nodes. These results are advantageously applicable to any technology node using transistors. Furthermore, these results may be advantageously applicable to other technology nodes with devices performing similar functions. Table 1 below shows the results for several industry-standard networks and their associated applications. Table 1: Performance Benchmarks [Table 1]

[0139] In the fields of in-memory and analog computing, numerous foundational technologies have been developed and researched over the past decade. Table 2 lists several technologies applied to edge AI computing and exemplary companies that utilize these technologies. Table 2: Various technologies used for in-memory or analog computing targeting edge AI applications [Table 2]

[0140] This disclosure may have applications in one or more of the following: generalized artificial intelligence for applications such as natural language processing, image processing, and natural motion processing for robotics, as well as neuromorphic computing to enable unsupervised learning and autonomous robot assistance for homes, factories, or hospitals.

[0141] Throughout this detailed explanation, the terms "ANN" are understood to refer to artificial neural networks, "CNN" to convolutional neural networks, and "CTT" and "CTTs" to charge trap transistors. The terms "NMOS" are understood to refer to n-channel metal oxide semiconductors, "PMOS" to p-channel metal oxide semiconductors, and "CMOS" to complementary metal oxide semiconductors.

[0142] Through this disclosure, a CTT may be understood as a conventional transistor that satisfies the technical requirements expressed herein and performs a charge trapping function as further described herein. A CTT is any transistor that satisfies these technical requirements (for example, as expressed in the discussion of Figure 7) and performs a charge trapping function. Thus, unless expressly otherwise provided, references to transistors are understood to include embodiments in which the transistor so referred to is a CTT.

[0143] Next, referring to Figure 3, a neuron 300 according to an embodiment is shown. The neuron 300 includes a plurality of synapses 302 that receive and process input signals, a storage block 304 that stores input signals, a storage capacitor 306 that temporarily stores the stored signals, a discharge pulse generator 308 that generates an output signal, and a comparator 314 that compares voltages.

[0144] Neuron 300 may form part of an ANN (not shown). Neuron 300 further includes an activation pulse 312 generated for propagation to subsequent layers of the ANN.

[0145] Such synapses include a CTT (not shown) that supplies synaptic weights.

[0146] The storage block 304 includes a storage device (not shown) for receiving drain current (not shown) from multiple synapses 302. The storage device may be any storage device capable of receiving and storing current. The storage device may be a memory. The drain current is generated as the output of the multiplication from the multiple synapses 302. The drain current generates an amount of charge proportional to the period during which a fixed voltage is applied as input.

[0147] The storage block 304 further includes a plurality of multipliers (not shown) for storing synaptic weights and multiplying the synaptic weights by input signals processed by the CTT. The storage block 304 further includes a storage unit (not shown) for summing the outputs of the multiplications from the plurality of multipliers.

[0148] The storage capacitor 306 stores charge from the drain current in order to function as a short-term memory for the stored signal.

[0149] The discharge pulse generator 308 generates an output signal by discharging the accumulated charge during a discharge cycle.

[0150] Comparator 314 generates a first output when the received input signal is equal to or greater than a reference voltage. Comparator 314 generates a second output when the received input signal is less than the reference voltage. In one embodiment, the first output is higher than the second output, and the first output is called the "high" output, and the second output is called the "low" output. In another embodiment, the first output is lower than the second output, and the first output is called the "low" output, and the second output is called the "high" output.

[0151] In one embodiment, comparator 314 is a threshold inverter quantization (TIQ) comparator 314 for comparing an input voltage with a reference voltage. Advantageously, in embodiments where comparator 314 is a TIQ comparator, the reference voltage VREF is self-generated by the comparator 314 as the intrinsic threshold voltage of the TIQ comparator 314.

[0152] The TIQ comparator 314 includes a cascade of at least one CMOS inverter (not shown). Each CMOS inverter includes a PMOS transistor (not shown) and an NMOS transistor (not shown). According to the transfer curve of each CMOS inverter, as the input signal increases from 0 volts to a high voltage, a threshold is reached in each CMOS inverter, causing the output to invert from a second output to a first output. For example, in one embodiment, this includes the output inverting from a low output to a high output. Thus, the threshold acts as an implicit reference voltage. Furthermore, when the input voltage falls below the threshold, the high output inverts from a first output to a second output. For example, in one embodiment, this includes the output inverting from a high output to a low output.

[0153] When an odd number of inverters are used, the output inverts each time the threshold for the CMOS inverter cascade is reached. When an even number (greater than zero) of inverters are used, the output does not invert each time the threshold for the CMOS inverter cascade is reached (i.e., the output inverts back to its original state).

[0154] In one embodiment, the PMOS transistor and the NMOS transistor are CTTs, and the threshold of the TIQ comparator 314 is adjustable via at least one of the PMOS CTT or NMOS CTT according to charge trapping techniques.

[0155] The threshold value of the TIQ comparator 314 corresponds to the ratio obtained by dividing the intensity of the PMOS transistor by the intensity of the NMOS transistor.

[0156] The threshold of the TIQ comparator 314 is inherent and can be advantageously adjusted according to CTT technology. A CTT device (such as the one described in relation to Figure 7) may act to control, modify, or otherwise alter the threshold or reference voltage in order to make the operation of the neural network 300 effective.

[0157] Because the VREF or threshold voltage of a conventional comparator is generated individually, conventional comparators may not be able to perform the aforementioned functions. Advantageously, the aforementioned TIQ function represents a novel and inventive improvement over conventional comparators by minimizing the number of transistors used to perform the comparator function, eliminating the source of the reference voltage or threshold voltage, and providing a mechanism for calibrating the threshold voltage of the TIQ comparator 314.

[0158] In this disclosure, the aforementioned function of the TIQ comparator 314 further includes using threshold calibration to calibrate the neuron 300.

[0159] Multiple synapses 302 propagate the input signal received as input. The storage block 304 stores charge during the charging cycle. In one embodiment, the storage block 304 is a charging cycle cascode current mirror. The storage capacitor 306 stores the resulting charge from the current pulse and functions as a form of short-term memory for the stored input signal.

[0160] The discharge pulse generator 308 discharges charge during the discharge cycle. In one embodiment, the discharge pulse generator 308 is a discharge cycle cascade current source. In the embodiment, the discharge pulse generator 308 further transmits an input signal during the charge cycle to achieve a subtraction function.

[0161] Neuron 300 does not necessarily need to have an explicit Vref. Vref may be incorporated as the threshold of the TIQ comparator 314 itself. Neuron 300 may be tunable based on changing the built-in threshold of the TIQ comparator 314.

[0162] In one embodiment, the CTT can be used to provide a method for calibrating the adjustable threshold of the TIQ comparator 314, i.e., the threshold of the neuron 300.

[0163] In this embodiment, correlated double sampling may be advantageously employed to achieve improved cancellation of the threshold shift of the TIQ comparator 314. Correlated double sampling is further advantageous in initializing the voltage of the storage capacitor 306.

[0164] Referring now to Figure 4, a simplified structure of the neuron 400 of this disclosure is shown, which, according to the embodiment, utilizes CTT not only for multiplication but also for weight storage.

[0165] Neuron 400 includes synapses 402a, 402b, and 402c for performing analog conduction-based inference. In this embodiment, synapses 402a, 402b, and 402c are CTTs 402a, 402b, and 402c. Synaptic weights are stored in threshold voltage shifts of CTTs 402a, 402b, and / or 402c.

[0166] CTT402a, 402b, and 402c receive input signals 408a, 408b, and 408c, respectively. Input signals 408a, 408b, and 408c are applied to CTT402a, 402b, and 402c, respectively.

[0167] CTT402a, 402b, and 402c generate drain currents 403a, 403b, and 403c, respectively. Drain currents 403a, 403b, and 403c each generate an amount of charge equal to the product of the input signals 408a, 408b, and 408c and the synaptic weights stored in CTT402a, 402b, and 402c, respectively.

[0168] Neuron 400 further includes a storage capacitor 404 for accumulating the resulting charge from drain currents 403a, 403b, and 403c.

[0169] Neuron 400 further includes a comparator 406. The comparator 406 may be the TIQ comparator 314 shown in Figure 3. In embodiments where the comparator 406 is the TIQ comparator 314, during the discharge phase of the operation of the storage capacitor 404, if the received input voltage falls below the reference voltage of the comparator 406, the output of the comparator 406 inverts from the first output to the second output, and if the received input voltage rises above the reference voltage, the output inverts from the second output to the first output.

[0170] The comparator 406 may be a dual-slope TIQ comparator 406 and may generate an activation output. In the realization of the mixed signal, the input is converted into a time pulse, which is then weighted by the conductance of neuron 400 to generate a scaled current pulse (not shown). The charge from the scaled current pulse is stored in a storage capacitor 404 and then discharged at a constant rate to generate a timing pulse 408d.

[0171] In this embodiment, neuron 400 forms part of an ANN (not shown). The timing pulse 408d may be propagated directly to subsequent layers of the ANN. The timing pulse 408d may be propagated to subsequent layers of the ANN after passing through a nonlinear function such as a rectifier linear unit (ReLU). The timing pulse 408d may be stored in an ephemeral memory device (not shown) for future use. The ephemeral memory device may be a time ephemeral memory device. The ephemeral memory device and / or time ephemeral memory device may be a storage capacitor 404.

[0172] Neuron 400 further includes a ground 416 for functioning as an electrical ground.

[0173] Referring to Figure 5, a neuron 500 according to the embodiment is shown.

[0174] Neuron 500 contains synapses 502a, 502b, 502c, and 502d (collectively referred to as synapses 502 and commonly called synapses 502) for receiving input signals, and stores and supplies synaptic weights. Synapses 502 can contain any number of synapses.

[0175] The neuron 500 further includes a storage block 504 for storing input signals, a storage capacitor 506 for temporarily storing the stored signals, a discharge pulse generator 508 for generating output signals, a comparator 514 for comparing voltages, and drains 520a, 520b, 520c, and 520d (collectively referred to as drains 520 and commonly called drains 520) corresponding to each synapse 502 for transmitting current from the synapse 502 to the storage block 504.

[0176] Neuron 500 may form part of an ANN (not shown). Neuron 500 further includes an activation pulse 512 generated for propagation to subsequent layers of the ANN.

[0177] Synapse 502 performs a multiplication function based on the received input signal. Each synapse 502 generates a current for a certain period of time. The received input signal may also be a received activation pulse 512. The duration for which each current is generated is equal to the width of the received activation pulse 512 received at each synapse 502. Each such received activation pulse 512 may have a different width.

[0178] The drains 520 are connected to each other before being connected to the storage block 504. The storage block 504 sums the currents transmitted through the drains 520. In one embodiment, the summation is equivalent to a wired OR function. The result of the summation in the storage block 504 is further transmitted as a signal to the storage capacitor 506.

[0179] In one embodiment, the storage block 504 functions as a current mirror to mirror the current flowing through the synapse 502. Advantageously, the current mirror can be used when the power supply is low and the headroom of the circuit operation is limited.

[0180] The storage block 504 includes a memory device (not shown) for receiving transmitted currents from drains 520 from multiple synapses 502, and multiple multipliers (not shown) for storing synaptic weights and multiplying the transmitted currents by the synaptic weights. The storage block 504 further includes a accumulator (not shown) for summing the outputs of the multiplications from the multiple multipliers.

[0181] The storage capacitor 506 includes a bottom plate 516 for grounding the neuron 500. The storage capacitor 506 further includes a top plate 518 for storing charge from the synapse 502. In one embodiment, advantageously, there is no implementation of an active integrator circuit, and a single open-loop storage capacitor 506 can temporarily store the stored charge.

[0182] The voltage pulses applied to each of the synapses 502 can simultaneously begin to transmit as signals. Each such signal stops transmitting, or "turns off," according to the input signal received from the previous layer of the ANN.

[0183] Figure 5 further illustrates graph 510, showing the activation pulse 512 in the context of a changing reference voltage. The width of the activation pulse 512 is the information passed from one neuron (e.g., neuron 500) across the ANN layers to subsequent neurons. The dual-slope multiple accumulation function described uses time to transmit the activation information.

[0184] The first slope 522 in graph 510 represents the accumulation time, i.e., the time it takes for the received input signal to be added across drain 520. This represents the "accumulation" stage of the "multiply-accumulate" operation.

[0185] The second slope 524 in graph 510 represents the generation of the activation pulse 512, during which a constant reference current discharges the stored charge on the storage capacitor 506. The down current is related to the charge discharged from the storage capacitor 506 by the constant current. The generated activation pulse 512 starts at the beginning of the discharge phase and stops when the voltage on the top plate 518 of the storage capacitor 506 drops below the threshold voltage of the comparator 514.

[0186] Referring next to Figure 6, a graph 600 is shown illustrating additional details of the dual-slope multiple accumulation function for generating an activation pulse 512 in neuron 500. In graph 600, the integrated charge is proportional to the multiplication product, but the absolute value of the multiplication product is not important. In this embodiment, the activation pulse is successfully generated when the value of the multiplication product remains constant until a constant current discharge event occurs, such as the generation of the activation pulse 512 as described with respect to Figure 5.

[0187] Graph 600 depicts the dual-slope process used to combine the multiplier function to generate the activation pulse 512. Graph 600 includes a vertical axis 614 representing charge. Graph 600 further includes a horizontal axis 606 representing time.

[0188] Graph 600 includes a first region 602 where the MAC integral occurs. In the first region 602, the charge stored in the storage capacitor 506 is proportional to the multiplication product. Such a multiplication product is expressed by referring to a matrix as shown in Figure 13, Σ(W ij *X i ) or the first region 602 includes a first slope 608 corresponding to a charging cycle.

[0189] Graph 600 includes a second region 604 in which the discharge of the storage capacitor 506 occurs on a unit basis. The discharge rate of the storage capacitor 506 provides a time ratio fraction proportional to the normalized dot product of the received input signal received at synapse 502 and the synaptic weights stored at synapse 502, which is used to generate the activation pulse 512 of the subsequent layer of the ANN. The second region 604 includes a second slope 610 corresponding to the discharge cycle of the storage capacitor 506.

[0190] The first slope 608 and the second slope 610 represent the charge and discharge cycles of neuron 500, respectively. Graph 600 depicts the charge cycle in which a previously generated activation pulse 512 is applied to neuron 500. The signal is transmitted from synapse 502 to storage block 504 via drain current 520, and the resulting currents are summed, i.e., the "storage" stage of "multiplication and storage".

[0191] Graph 600 further illustrates the discharge cycle. The storage capacitor 506 is discharged using a known constant current to generate the pulse width (not shown) of the activation pulse 512 that propagates to the subsequent layer of the ANN. The time required for the storage capacitor 506 to discharge determines the pulse width propagating to the subsequent layer.

[0192] Figure 7 shows a CTT700 suitable for use in synapses 302, 402, and 502 of neurons 300, 400, and 500 in Figures 3, 4, and 5, according to an embodiment.

[0193] The CTT700 includes a gate 702 for receiving an input signal. The CTT700 includes a layer source 704 for receiving a negative reference for the input voltage (or activation). The CTT700 includes a layer body bias 706 to facilitate possible threshold adjustments to compensate for parameters such as temperature. The CTT700 includes a layer drain 708 for transmitting an output signal. The CTT700 includes a gate dielectric (not shown) for interposing between the gate 702 and the substrate to which the CTT700 is applied. The gate dielectric is used to accumulate trapped charge and adjust the threshold voltage of the CTT700.

[0194] In one embodiment, CTT700 is a charge-trap gravimetric transistor. In another embodiment, CTT700 is an NMOS CTT. In yet another embodiment, CTT700 is a PMOS CTT.

[0195] The CTT device 700 has been used as a multilevel non-volatile memory. By utilizing the charge trapping phenomenon in the transistor 700, which has a high dielectric constant metal gate 702, and applying a drain bias during the charge trapping process, the charge trapping process in the CTT 700 can be enhanced.

[0196] N-type CTT700, which has a cascaded HfSiON layer (not shown) following an SiO2 interface layer (not shown) as the gate dielectric, is a common device type at process nodes of CMOS technology smaller than 32 nm. N-type CTTs may also include a high-K material similar to the nitride HfSiON layer as the gate dielectric, following the SiO2 interface layer.

[0197] The threshold voltage Vt (not shown) of CTT700 is modulated by the amount of charge confined in the gate dielectric of transistor 700. The drain bias enhances and stabilizes the charge trapping process through an enhanced local heating effect.

[0198] Using the CTT700 for synaptic multiplication is done by encoding the strengths of neurons 300, 400, and 500 and transmitting the amplitude of the previous layer as a constant voltage pulse width applied to the gate 702 of the CTT700. Synaptic multiplication may also be weight multiplication. The resulting drain current (drain currents 403, 520, etc.) is a function of Vgs (applied input voltage) and the threshold voltage associated with the CTT700, since Id = f(Vgs - Vt). Since all CTT700s start with a nominal Vt inherent to the silicon manufacturing process, during programming of the CTT700, the nominal Vt is shifted by an amount proportional to the weight accumulated by the CTT700. This change in Vt, i.e., delta Vt, represents the weight value associated with a particular device 700 or synapse 302, 402, 502. By utilizing a MOSFET in the subthreshold region, a logarithmic relationship between Id and (Vgs - Vt) becomes possible. In circuits utilizing subthreshold MOSFETs, Vt is constant and Vgs changes. This works well when Vgs is a control signal. However, in this embodiment, Vt of the CTT700 is shifted, which in turn induces a change in Id, Vgs is applied as a pulse over time, and the absolute voltage remains constant.

[0199] In one embodiment, input information is transmitted by pulse width, so the above proceeds with a single voltage amplitude. The current flowing through CTTs700 is integrated by neurons 300, 400, or 500, and the charge stored in storage capacitors 306, 404, or 506 is equal to the weighted sum of the inputs.

[0200] Q = Σ(I*t)

[0201] The programming of synaptic weights (not shown) is achieved, depending on the technology, by applying gate pulses of varying lengths (e.g., 50 μs to 10 ms) with a set programming voltage bias (e.g., Vgs = 1.2 V to 2.0 V, Vds = 1.0 V to 1.8 V).

[0202] In embodiments where the CTT700 implements a neuron (such as neuron 500 in Figure 5), inputs such as neural network inputs are converted into time pulses (such as activation pulses 512), the duration of which is proportional to the magnitude of the received input signal (pulse width modulation). The time pulse is a pulse of constant amplitude applied to gate 702. The conductance of the charge trap transistor 700 is pre-tuned in proportion to the synaptic weight (not shown). Thus, the drain current pulse (not shown) in the drain current 520 from the CTT700 generates an amount of charge equal to the product of the time pulse received at gate 702 and the previously stored synaptic weight. The resulting charge from the time current pulse, such as that transmitted by the drain current pulse from the CTT700, is stored on the storage capacitor 506 during the first slope 608 of dual-slope operation, as shown in Figure 6. Subsequently, a fixed current is applied to the storage capacitor 506, discharging it during the second slope 610.

[0203] When the voltage exceeds a threshold, the comparator inverts its state. The comparator may be a threshold inverter quantization (TIQ) comparator 314 in Figure 3 or a TIQ comparator 514 in Figure 5, and in some embodiments, it may be CTT calibrated. A time pulse is generated for the duration of the second slope 610. The width of the time pulse represents the output of neuron 500.

[0204] In the architecture of the embodiment described above, the drain current I represents the synaptic weight, and time t represents the activation input. Thus, each CTT700 performs multiplication of the synaptic weight and the activation pulse 512. All synaptic multiplications are stored in a single storage capacitor, such as storage capacitor 306 or storage capacitor 506.

[0205] Figure 8 shows an exemplary layer 800 according to an embodiment, which includes a plurality of CTT700s, namely CTT700a, 700b, 700c, 700d, 700e, and 700f (collectively referred to as CTT700 and commonly called CTT700). Layer 800 may include any number of CTT700s. In one embodiment, layer 800 is neuron 300 in Figure 3, neuron 400 in Figure 4, or neuron 500 in Figure 5. In one embodiment, layer 800 is an exemplary layer of synaptic weights.

[0206] In Figure 8, the drain current (not shown) is the output of the multiplication from the synapses. Each CTT700 generates a certain amount of current over a certain period. The sum is represented as the drain current that is taken up together with the storage capacitor (not shown).

[0207] Figures 9A and 9B show current mirrors 900 and 902 according to the embodiment, respectively.

[0208] The current mirror 900 includes transistors 903a, 903b, 903c, and 903d. In one embodiment, transistors 903a, 903b, 903c, and 903d do not perform a charge trap function and are therefore not CTT700.

[0209] The current mirror 902 includes transistors 903e, 903f, 903g, 903h, 903i, 903j, 903k, 903l, and 903m. In some embodiments, transistors 903e, 903f, 903g, 903h, 903i, 903j, 903k, 903l, and 903m do not perform the charge trap function and are therefore not CTT700.

[0210] The design of current mirrors 900 and 902 is subject to several design constraints, including good matching, high output impedance, and fast transient response. To achieve good matching, it is advantageous for transistors 903a and 903b to match terminal voltages, specifically Vg and Vd. Such matching voltages are favorably achieved by using a cascode current mirror structure. The cascode current mirror structure provides excellent matching of Vg and Vd. Furthermore, the cascode current mirror structure exhibits high output impedance at nodes 914 and 908 in this case. The performance of cascode current mirrors 900 and 902 is further improved by utilizing a cascode current mirror structure with transistors 903a, 903b, 903c, 903d, 903e, 903f, 903g, 903h, 903i, 903j, 903k, 903l, and 903m biased to the subthreshold operating region.

[0211] In one embodiment, the cascode current mirror 900 in Figure 9A may be the accumulation block 304 of the neuron 300 in Figure 3. In another embodiment, the cascode current mirror 902 in Figure 9B may be the discharge pulse generator 308 of the neuron 300 in Figure 3.

[0212] The current flowing through CTTs700 can be mirrored by the cascoded current mirror 902, resulting in the accumulation of charge on the storage capacitor 306 and generating a voltage proportional to the weighted sum of the inputs: V = 1 / CΣ(I*t).

[0213] Figure 10 shows a threshold inverter quantization (TIQ) comparator 1000 for threshold inverter quantization comparison according to an embodiment. The TIQ comparator 1000 may be the TIQ comparator 314 shown in Figure 3.

[0214] The TIQ comparator 1000 includes a cascade of two CMOS inverters 1001a and 1001b (collectively referred to as inverter 1001, and commonly called inverter 1001) for generating a first output when the received input signal exceeds the reference voltage of the TIQ comparator, and a second output when the received input signal falls below the reference voltage. The TIQ comparator 1000 further includes an input connection 1006 for receiving input signals. The TIQ comparator 1000 further includes an output connection 1008 for transmitting output signals. The TIQ comparator 1000 further includes a power connection 1004 for receiving power. The TIQ comparator 1000 further includes a ground connection 1010 for grounding the TIQ comparator 1000.

[0215] In one embodiment, the first output is higher than the second output. In such an embodiment, the first output is called the "high" output, and the second output is called the "low" output.

[0216] In one embodiment, the first output is lower than the second output. In such an embodiment, the first output is called the "low" output, and the second output is called the "high" output.

[0217] Each inverter 1001a, 1001b contains PMOS transistors 1002a, 1002c and NMOS transistors 1002b, 1002d, respectively (transistors 1002a, 1002b, 1002c, 1002d are collectively called transistor 1002 and are generally referred to as transistor 1002). Each of transistors 1002 may be a CTT700. The threshold of the TIQ comparator 1000 for each inverter 1001 is set according to the ratio obtained by dividing the intensity of the PMOS transistor 1002 by the intensity of the NMOS transistor 1002. The intensity of each transistor 1002 is understood to be related to the width of each transistor 1002, the length of each transistor 1002, the mobility of each transistor 1002, and / or any other relevant parameters or factors of each transistor 1002. Furthermore, fine-tuning and calibration can be maintained by reprogramming the threshold voltage using the same method as in the weight matrix 1302 as shown in Figure 13. The TIQ comparator 1000 may also be a CTT calibrated TIQ comparator 1000.

[0218] In Figure 10, the threshold voltage of transistor 1002 may be adjusted to calibrate the TIQ offset.

[0219] Conveniently, the offset of the TIQ comparator 1000 can be calibrated by adjusting any one of the transistors 1002 within the TIQ comparator 1000.

[0220] The threshold voltage of the TIQ comparator 1000 is self-generated by the TIQ comparator 1000. When the input voltage received via input connection 1006 exceeds the threshold voltage, the first output of the TIQ comparator 1000 is inverted to the second output and transmitted via output connection 1008. When the input voltage received via input connection 1006 falls below the threshold voltage, the second output is inverted to the first output and transmitted via output connection 1008.

[0221] Figure 12 shows an example illustrating how a neural network can be constructed using the architecture of this disclosure with respect to a CNN1200 according to an embodiment. Figure 12 is a simplified diagram of a CNN1200 for image classification. The CNN1200 may be implemented by neurons arranged in layers (for example, neuron 500 in Figure 5).

[0222] CNN1200 includes a convolutional layer 1204, a pooling layer 1206, a fully connected layer 1208, a hidden layer (not shown), and an output layer 1210.

[0223] The CNN1200, with its convolutional layer 1204 and pooling layer 1206 combined, can be considered a feature extractor 1201 for extracting features from the input image 1202.

[0224] The fully connected layer 1208 and the output layer 1210 together can be considered a classifier 1209 for classifying the input image 1202. In this embodiment, the classifier 1209 can further transmit an output signal (not shown) corresponding to the classification of the input image 1202.

[0225] In Figure 12, each layer 1204, 1206, and 1208 contains neurons (not shown), such as neuron 500. Each neuron in Figure 12 contains synapses (not shown), such as synapse 502 in Figure 5. The synapses in Figure 12 contain CTTs, such as CTT700 in Figure 7. The threshold voltage of CTT700 is programmed to store the synaptic weight values ​​of synapse 502. A voltage pulse (not shown) is applied to the gate 702 of each CTT700. Advantageously, the source may be grounded. The gate-source voltage may be constant, but the voltage pulse transmits information for activation input over time.

[0226] In Figure 14, an exemplary calculation in the convolutional layer 1204 is examined. The input image 1202 is a two-dimensional array of pixel values ​​representing the image. Each convolutional layer 1204 performs a two-dimensional "dot" product on the received pixel values. The input image 1202 is decomposed into smaller computational units, such as a 3x3 or 5x5 matrix. A 3x3 matrix is ​​provided as an example, as shown in Figure 13.

[0227] In Figure 13, a portion of the input image 120 is represented by a 3x3 matrix 1302 of pixel values ​​(X1, X2, ..., X9) received as input to neurons such as neuron 500 in the convolutional layer 120. The feature weight parameters (W1, W2, ..., W9) associated with the feature filter are represented by a 3x3 matrix 1304. The dot product of the two matrices 1302 and 1304 is equal to the sum of the products of each cell in the two matrices 1302 and 1304, according to the following formula. x·w = X1*W1 + X2*W2 + ... + X9*W9

[0228] Figure 14 shows the implementation of a convolutional neuron 1220 in the convolutional layer 1204 of CNN1200. The convolutional neuron 1220 includes a synaptic matrix 1214 that utilizes a CTT 1215 to calculate the multiplication portion of the dot product. The convolutional neuron 1220 further includes a storage capacitor 1216 for storing the output of the synaptic matrix 1214 and a comparator 1218 for comparing the voltages. The comparator 1218 may be a TIQ comparator 314. An activation pulse (not shown) is generated at the output of the comparator 1218.

[0229] The convolutional neuron 1220 receives input data 1212. The input data 1212 may be in the form of a matrix.

[0230] In one embodiment, input data 1212 is an input signal.

[0231] In one embodiment, the input signal is propagated from a layer prior to the CNN1200.

[0232] In one embodiment, the convolutional neuron 1220 is located in the first layer of the CNN 1200, and the input data 1212 is an input to the CNN 1200 from outside the CNN 1200.

[0233] In one embodiment, the input data 1212 includes matrices 1302 and 1304 in Figure 13.

[0234] In one embodiment, the convolutional neuron 1220 may be neuron 300 in Figure 3 or neuron 500 in Figure 5.

[0235] In Figure 14, the product of the input data 1212 is passed to subsequent layers of the CNN 1200, such as the pooling layer 1206 (not shown), or stored as a signal in an ephemeral memory device (not shown).

[0236] In a fully connected feedforward neural network, multiple activation pulses (such as activation pulse 512 in Figure 5) do not need to be maintained for a single neuron (such as neuron 500 in Figure 5). However, in the case of an ANN that reuses activation pulses multiple times, such as a CNN, the activation pulse generated at the output of 1218 may be temporarily stored before being processed by subsequent layers of the ANN. In these ANNs, an ephemeral memory device is used to temporarily store the width of the activation pulse.

[0237] In one embodiment, the convolutional neuron 1220 is implemented by the CTT700 shown in Figure 7. During positive programming, a positive gate voltage pulse is applied to the gate 702 of the CTT, and the threshold voltage of each CTT700 may be shifted in the positive direction. During negative programming, a negative gate voltage pulse may be applied to the gate 702, and the threshold voltage of each CTT700 may be shifted in the opposite direction.

[0238] During synaptic multiplication, the absolute values ​​of the physical parameters of the hardware implementing the ANN are not important for the calibration applied to the ANN.

[0239] It should be noted that the product of the synaptic multiplication functions is charge (i.e., I*t), and the sum of the synaptic outputs (i.e., charge) may be stored in a storage capacitor (such as storage capacitor 306 or storage capacitor 506). In the memory architecture described herein, activation pulses (not shown) may be advantageously used directly by subsequent layers of the ANN and therefore do not need to be converted to digital for storage in memory. If the convolutional neuron 1220 is utilized to generate multiple activation pulses, each activation pulse is stored in an ephemeral memory device.

[0240] In one embodiment, in the context of calibration, the overall neural network algorithm implementing the ANN favorably depends only on the relative relationships between neuronal activation pulse widths (not shown), and not on absolute voltage, current, or charge. To ensure that all neurons in the ANN are relatively accurate, the entire pathway (e.g., synapse 302) of each neuron (e.g., neuron 300 in Figure 3) can be calibrated relative to a single “golden” neuron (not shown), including each of its synapses (e.g., synapse 302). Such calibration favorably ensures that all neurons maintain a constant relationship with the golden neuron, thus maintaining ratiometric accuracy. In one embodiment, there are several calibrations involved in the solution, including initial programming calibration, continuous temperature calibration, and periodic CTT drift calibration.

[0241] Figure 15 shows a method 1500 for calibrating a reference block according to an embodiment. Method 1500 may be performed to calibrate neuron 300 in Figure 3. In 1502, neuron 300 determines a designated reference weight block (not shown). The designated reference weight block may be a reference weight block calibrated according to a signal. The designated reference weight block, or "golden block" or "golden delay block," is the block from which all other delay blocks are calibrated.

[0242] At 1504, the current mirrors within neuron 300 (e.g., current mirrors 900 and / or 902 shown in Figures 9a and 9b) are calibrated according to a specified reference weight block. After calibration, current mirrors 900 or 902 are synchronized with the golden delay block. At 1506, the storage capacitor 306 is calibrated according to a specified reference weight block. After calibration, the storage capacitor 306 is synchronized with the golden delay block. At 1508, the comparator 314 is calibrated according to a specified reference weight block. After calibration, the comparator 314 is synchronized with the golden delay block. Once this process is complete, each neuron signal path is matched to a single golden delay block. Conveniently, all neurons 300 can be effectively matched to one another. At 1510, each synaptic weight stored in the CTT 700 is calibrated against a specified reference weight block.

[0243] If components are calibrated according to a single reference weight block, such as the golden delay block, each component can maintain the same relative time, which is advantageous in improving system functionality and efficiency.

[0244] A further advantage of this disclosure is that calibration at the neuron level is easy, and as a result, ratiometric matching among all 300 neurons in a complete neural network (not shown) is easy. Advantageously, to achieve good accuracy in the ANN, the relative ratios of all activation / weight products can be accurate through reference block calibration.

[0245] In one embodiment, all device operations and all neuron signal paths are calibrated according to a single designated reference weight block > current mirror → storage capacitor → comparator chain.

[0246] Once the reference chain is calibrated to a unit-scale time (e.g., full-scale charging of a 1pF storage capacitor in 1μs), all current mirror → storage capacitor > comparator chains are calibrated using the same reference weight (Iref). All chains may be calibrated periodically to ensure that slight drifts in device characteristics are compensated for. Advantageously, this calibration process efficiently calibrates all differences between all neuronal signaling pathways. Advantageously, calibration using the method described above may be successful even if only time is stable.

[0247] Temperature compensation can be applied in at least one of two ways. In one embodiment, back bias voltage modulation is applied. In another embodiment, the Vgs pulse voltage may be adjusted. In any of the embodiments described above, the reference chain is maintained in unit scale time. Temperature compensation may be global. Temperature compensation may be continuous. Advantageously, temperature compensation ensures that only small amounts of global drift occur due to temperature, and as a result, all relative errors between signal paths can be kept negligible.

[0248] Figure 16 shows an ephemeral memory system 1600 for temporarily holding information according to an embodiment. The ephemeral memory system 1600 is a simplified diagram of the implementation of the ephemeral memory device 1700 shown in Figure 17.

[0249] The ephemeral memory system 1600 includes an activation 1602 for generating an activation pulse (not shown), an ephemeral memory mixed signal counter 1604 for storing the activation pulse, and a regeneration activation 1606 for regenerating the activation pulse.

[0250] Next, referring to Figure 17, an ephemeral memory device 1700 for temporarily holding information according to an embodiment is shown. The ephemeral memory device 1700 represents a typical implementation of the ephemeral memory scheme 1600 of Figure 16. In one embodiment, the information to be held may be input signals received by neuron 300 or 500. In one embodiment, the ephemeral memory device 1700 may be an ephemeral memory device.

[0251] The ephemeral memory device 1700 includes an inner ring 1704 for providing asynchronously controllable delay. The inner ring 1704 is supported by an outer ring 1706 containing an asynchronous counter 1708. This combination works in conjunction to achieve efficient short-term accurate storage of delayed states.

[0252] A key advantage of the ephemeral memory device 1700 over existing devices, methods, and systems is that the device can function asynchronously. The device 1700 provides a solution for temporarily storing time using nanowatt / picowatt-order power consumption in a physically small space, thereby enabling functionality with lower power and a smaller silicon area.

[0253] Figure 18 shows an ephemeral memory device 1800 for temporarily holding information according to an embodiment. The ephemeral memory device 1800 is an implementation of the ephemeral memory device 1700 shown in more detail in Figure 17.

[0254] The device 1800 includes an inner ring 1804 containing multiple subthreshold-pass transistor logic (PTL) delay line blocks 1802 for providing asynchronously controllable delays. The outer ring 1806 includes D flip-flops (not shown) that form an asynchronous counter 1808.

[0255] In the context of ephemeral, mixed-signal, time-memory structures, many artificial neural networks use a particular set of filter weights multiple times within a layer to process multiple activation inputs. Intermediate activations may be stored until all values ​​are available for processing by the next layer. In some embodiments, a simple storage capacitor may be insufficient due to leakage current associated with transistors connected to the storage capacitor. Thus, the ephemeral memory device 1800 may be advantageously used to store the pulse width (or time) of each activation. The ephemeral memory device 1800 can store the pulse width or time in an asynchronous counter 1808 and then be used to drive a time input to the next neuron.

[0256] The inner ring 1804, when activated, functions as an oscillator (not shown) and is active only while the neuron storage capacitor (such as storage capacitor 306 in Figure 3) is discharging. When activated, the oscillator triggers counter 1808 to count up. When the neuron storage capacitor discharges, the oscillator is deactivated and counter 1808 holds its value. The oscillator is then reactivated, and counter 1808 counts down to zero, during which time a pulse is generated by an asynchronous counter (not shown) as input to the next neuron. The absolute frequency of the asynchronous counter generating the pulse is not important. In some embodiments, only the transient stability of the oscillation frequency is important for accuracy.

[0257] Figure 19 shows an ephemeral memory device 1900 for temporarily holding information according to an embodiment. The ephemeral memory device 1900 is an embodiment of the device 1700 shown in more detail in Figure 17 and the device 1800 shown in Figure 18. In this embodiment, the information to be held is an input signal received by neuron 300 or 500.

[0258] In one embodiment, the ephemeral memory device 1900 is an ephemeral memory device.

[0259] The ephemeral memory device 1900 includes an inner ring 1904 for providing an asynchronously controllable delay. The device 1900 further includes an outer ring 1906 for supporting the inner ring 1904. The outer ring 1906 includes an asynchronous counter 1908. The asynchronous counter 1908 includes a first asynchronous counter 1909. The inner ring 1904 and the outer ring 1906 work together to achieve efficient, short-term, and accurate storage of the delay state.

[0260] The inner ring 1904 includes an analog subthreshold delay block 1902 for providing asynchronously controllable delay.

[0261] The asynchronous counter 1908 may also consist of multiple D flip-flops.

[0262] Using the analog subthreshold delay block 1902, positive feedback, and the first asynchronous counter 1909, a self-timing oscillator (not shown) that oscillates based on the frequency of the delay element can be created. In the ephemeral memory device 1900, the first asynchronous counter 1909 is clocked by the self-timing oscillator.

[0263] During the discharge period, an activation pulse (not shown) is generated from a neuron such as neuron 300. When the activation pulse is high, the activation pulse activates the self-timing oscillator. When the activation pulse is low, the activation pulse deactivates the self-timing oscillator, and the asynchronous counter 1908 stops, storing a numerical value representing the pulse width of the activation pulse. The asynchronous counter 1908 can advantageously retain the stored numerical value for a certain period of time. In the embodiment, the asynchronous counter 1908 preferably retains the stored numerical value for several seconds.

[0264] Device 1900 can advantageously use dynamic logic to save space and power.

[0265] During the activation pulse, the asynchronous counter 1908 counts up during the count-up period. When the ephemeral memory device 1900 applies an activation pulse to a subsequent neuron (such as neuron 300), the asynchronous counter 1908 counts down, enabling the analog subthreshold delay block 1902 to regenerate the process and generate a subsequent activation pulse (not shown) equal to the previous activation pulse during the count-up period. The result is the dual-slope process shown in Figure 6.

[0266] When the asynchronous counter 1908 counts down again, the stored number may be lost. In one embodiment, the asynchronous counter 1908 may be paired with another version of a counter (not shown) that operates in the reverse direction; that is, it may count up when the asynchronous counter 1908 counts down, and vice versa.

[0267] In one embodiment, the asynchronous counter 1908 is a 1-bit asynchronous subthreshold counter.

[0268] Furthermore, Figure 19 shows an example of unit time and its variation. In device 1900, up-counting is enabled by the discharge cycle of the accumulation capacitor. Up-counting is disabled by the threshold of a neuron, such as neuron 300. In device 1900, down-counting is enabled by the inference start signal to the subsequent layer of the ANN.

[0269] The asynchronous counter 1908 is activated at the start of the discharge phase (corresponding to the slope 610 in Figure 6). The counter 1908 is deactivated when the TIQ comparator 314 reverses its state (i.e., when the voltage currently across the storage capacitor 306 becomes equal to the reference voltage Vref).

[0270] In one embodiment, the defect of absolute delay provided by the analog subthreshold delay block 1902 does not prevent the normal operation of the device 1900 as long as the device 1900 remains stable for a short period (measured in milliseconds) and the asynchronous counter 1908 has enough extra states to compensate for it.

[0271] In the device 1900, a significant advantage over existing apparatuses, devices, methods, and systems is that the device 1900 can operate asynchronously. A solution for temporarily storing time in the nanowatt / picowatt power consumption space is provided. An advantage of the present disclosure is functionality at lower power.

[0272] Figure 20 is a flow diagram of a method 2000 of using an ANN including a neuron (such as neuron 300) according to an embodiment.

[0273] In 2002, an input signal is processed through a plurality of CTTs 700.

[0274] In 2004, a drain current is generated as an output of multiplication from the CTTs 700. The drain current generates an amount of charge proportional to the period during which a fixed voltage is applied as an input.

[0275] In 2006, the drain current is received from the plurality of CTTs 700.

[0276] In 2008, charge from the drain current is accumulated, functioning as short-term memory for the accumulated signal.

[0277] In 2010, an output signal is generated by discharging the charge during an accumulated discharge cycle.

[0278] In 2012, an input voltage is compared with a reference voltage by a comparator 314. The comparator 314 may be a TIQ comparator 314.

[0279] In 2014, if the input voltage exceeds the reference voltage of comparator 314, the first output is generated.

[0280] In 2016, if the input voltage falls below the reference voltage of comparator 314, a second output is generated.

[0281] In one embodiment, the first output is higher than the second output. In such an embodiment, the first output is called the "high" output, and the second output is called the "low" output.

[0282] In one embodiment, the first output is lower than the second output. In such an embodiment, the first output is called the "low" output, and the second output is called the "high" output.

[0283] While the above description provides examples of one or more apparatuses, devices, methods, or systems, it will be understood that other apparatuses, devices, methods, or systems may also be included within the scope of the claims as interpreted by those skilled in the art.

Claims

1. A system for operating an artificial neural network (ANN), the system includes neurons, Each of the aforementioned neurons Multiple synapses, including charge trap transistors (CTTs) that process input signals, A storage block that receives drain current from the aforementioned multiple synapses, A storage capacitor that stores charge from the drain current and functions as a short-term memory for the stored signal, A discharge pulse generator that generates an output signal by discharging the accumulated charge during a discharge cycle, A comparator that compares the output signal, which is the input voltage, with a reference voltage, Equipped with, The aforementioned CTT supplies synaptic weights, The drain current is generated as the output of the multiplication of multiple synapses, The drain current generates an amount of charge equal to the product of the time pulse received at the synapse and the synaptic weight. The comparator generates a first output when the input voltage is above the reference voltage, and generates a second output when the input voltage is below the reference voltage. The comparator is a threshold inverter quantization (TIQ) comparator consisting of a cascade of at least one complementary metal-oxide-semiconductor (CMOS) inverter, Each of the CMOS inverters consists of a p-channel metal-oxide-semiconductor (PMOS) transistor and an n-channel metal-oxide-semiconductor (NMOS) transistor. The aforementioned reference voltage corresponds to the threshold value of the TIQ comparator that is self-generated by the TIQ comparator. The threshold value of the TIQ comparator is adjustable via the PMOS transistor or the NMOS transistor. The system is characterized in that the threshold value of the TIQ comparator corresponds to the ratio obtained by dividing the intensity of the PMOS transistor by the intensity of the NMOS transistor.

2. The aforementioned storage block is A memory device that receives drain current from the aforementioned multiple synapses, Multiple multipliers that store the synaptic weights and perform multiplication of the drain current and the synaptic weights, A accumulator that obtains a cumulative signal by summing the multiplication outputs from the aforementioned multiple multipliers, The system according to claim 1, characterized by including the following:

3. The system according to claim 2, characterized in that the drain current is generated as the output of a multiplication from multiple synapses, and generates an amount of charge equal to the product of the input signal and the synaptic weight.

4. The drain currents are connected to each other before being connected to the storage block. The storage block sums the drain currents, The system according to claim 2, characterized in that the sum of the drain currents is transmitted to a storage capacitor as a storage signal.

5. Each threshold voltage of the CTT is programmed to store the corresponding synaptic weight value. Each of the aforementioned CTTs is equipped with a gate to which a voltage pulse is applied. The source of the voltage pulse is ground. The gate-source voltage is constant. The system according to claim 2, characterized in that the voltage pulse transmits information using time.

6. The system according to claim 2, characterized in that the current flowing through the CTT is mirrored by a current mirror, charge is stored in the storage capacitor, and a voltage proportional to the weighted sum of the inputs is generated.

7. The system according to claim 1, characterized in that it comprises a second reference voltage in addition to, or instead of, the reference voltage of the TIQ comparator.

8. The system according to claim 1, characterized in that the subset of the CTT is an NMOS CTT.

9. The system according to claim 1, characterized in that the subset of the CTT is a PMOS CTT.

10. The system according to claim 1, wherein each of the CTTs includes a high dielectric constant metal gate, and a drain bias is applied during the charge trapping process.

11. Each of the aforementioned CTTs is SiO ２ The system according to claim 1, characterized in that it comprises a gate dielectric including an interface layer.

12. Each of the gate dielectrics is SiO ２ The system according to claim 11, characterized in that it comprises an interface layer and a cascaded HfSiON layer.

13. The system according to claim 11, characterized in that each of the CTTs applies a drain bias during the charge trapping process to stably trap other carriers in the gate dielectric.

14. The aforementioned weight values ​​are programmed by applying gate pulses of different lengths with a set programming voltage bias. During positive programming, a positive gate pulse is applied, and the threshold voltage shifts in the first direction. The system according to claim 1, characterized in that a negative gate pulse is applied during negative programming, causing the threshold voltage to shift in a second direction opposite to the first direction.

15. A method for operating an artificial neural network (ANN) that includes neurons, The process involves processing an input signal that is converted into a time pulse via multiple charge trap transistors (CTTs), The CTT provides synaptic weights, The steps include generating a drain current as the output of a multiplication of the multiple CTTs, The steps of receiving the drain current from the plurality of CTTs and The steps include: accumulating charge from the drain current so as to function as a short-term memory for the accumulated signal; The process involves generating an output signal by discharging the accumulated charge during a discharge cycle using a discharge pulse generator, and The steps include comparing the input voltage with a reference voltage using a comparator, Includes, The drain current generates a charge equal to the product of the time pulse received at the synapse and the synaptic weight. The comparator generates a first output if the input voltage is equal to or greater than the reference voltage, and generates a second output if the input voltage is less than the reference voltage. The aforementioned comparator is a threshold inverter quantization (TIQ) comparator, The TIQ comparator consists of a cascade of at least one complementary metal-oxide-semiconductor (CMOS) inverter. Each of the CMOS inverters consists of a p-channel metal-oxide-semiconductor (PMOS) transistor and an n-channel metal-oxide-semiconductor (NMOS) transistor. The aforementioned reference voltage corresponds to the threshold value of the TIQ comparator that is self-generated by the TIQ comparator. The threshold value of the TIQ comparator is adjustable via the PMOS transistor or the NMOS transistor. The method is characterized in that the threshold value of the TIQ comparator corresponds to the ratio obtained by dividing the intensity of the PMOS transistor by the intensity of the NMOS transistor.

16. The step of receiving the drain current from the plurality of CTTs is: The steps include receiving the drain current from the synapse, The steps include: storing the synaptic weights, The steps include performing the multiplication of the drain current and the synaptic weight, The steps include: obtaining a cumulative signal by summing the outputs of the multiplications; The method according to 15, characterized by including the following:

17. The step further includes calibrating the ANN, The step of calibrating the ANN is: The steps include determining a specified reference weight block, The steps include: calibrating the current mirror according to the specified reference weight block; The steps include calibrating the storage capacitor according to the specified reference weight block, The steps include: calibrating the TIQ comparator according to the designated reference weight block; and calibrating each synaptic weight stored in the CTT within the designated reference weight block. The method according to 15, characterized by including the following:

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