Multilayer capacitor device and method for manufacturing the same

Abstract

The manufacturing process is simple, and the device provides a multilayer capacitor that significantly increases capacitance. [Solution] The multilayer capacitor device includes at least one first die S1, at least one second die S2, and a plurality of through-via structures V1, V2, V1', V2'. A first capacitor element C1 is disposed on the first surface of the first die, a second capacitor element C2 is disposed on the first surface of the second die, and the first surface of the second die faces the first surface of the first die. The plurality of through-via structures extend from the second surface of the second die, penetrate the second die, and are coupled to the first capacitor element and the second capacitor element, respectively. The number of first dies is one or more. The number of second dies is one or more.

Description

Technical Field

[0001] The present invention relates to a semiconductor package structure, and in particular, to a multilayer capacitor device and a method of manufacturing the same. Background Art

[0002] As the economic benefits of Moore's Law decline, it has become impossible to achieve dramatic improvements in performance and complexity by relying only on a few directions such as processes and architectures. For this reason, the industry is shifting from merely relying on process improvements to increase the number of transistors per unit area on a single silicon wafer to a method of improving overall performance and functionality through complex system-level chip design with relatively controllable costs. Among these approaches, chiplets are highly regarded because they can achieve higher transistor density and performance at relatively low cost.

[0003] A chiplet is obtained by originally dividing a plurality of elements included in one chip into separate small units, redesigning and remanufacturing each unit to enhance its respective function, and forming the units into one system-on-chip using advanced packaging technology. Among these, a single capacitor element (Si Cap) was born accordingly.

[0004] However, since the area of the chip carrier is limited, the charge capacity can only be increased in the vertical direction when expanding, and excessively high capacitor elements often face the problem of collapse. Summary of the Invention Problem to be Solved by the Invention

[0005] The present invention provides a multilayer capacitor device that can increase capacitance by laminating and bonding a plurality of dies.

[0006] The present invention further provides a method for manufacturing a multilayer capacitor device that can increase capacitance without making the capacitor element excessively tall. [Means for solving the problem]

[0007] The multilayer capacitor device of the present invention includes at least one first die, a first capacitor element, at least one second die, a second capacitor element, and a plurality of through-hole structures. The first capacitor element is disposed on the first surface of the first die, the second capacitor element is disposed on the first surface of the second die, and the first surface of the second die faces the first surface of the first die. The plurality of through-via (TSV) structures extend from the second surface of the second die, penetrate the second die, and are coupled to the first capacitor element and the second capacitor element, respectively.

[0008] The second die includes a dielectric layer, and the second capacitor element described above is arranged on the surface of the dielectric layer. The second capacitor element includes a trench capacitor, and the trench capacitor is arranged within the dielectric layer described above. The first and second capacitor elements include a multilayer capacitor.

[0009] The multilayer capacitor device further includes a redistribution layer disposed on the second surface of the second die, the redistribution layer being coupled to a through-via structure. The first surface of the second die is bonded to the first surface of the first die described above. The first surface of the first die includes a BEOL structure formed above the first capacitor element, and the BEOL structure comprises an internal connection layer having a multilayer structure. A portion of the through-via structure penetrates the second die and connects to the internal connection layer of the BEOL structure described above. There are multiple first dies, and each first surface of the multiple first dies comprises a first capacitor element. There are multiple second dies, and each first surface of the multiple second dies comprises a second capacitor element.

[0010] The manufacturing method for the stacked capacitor device of the present invention includes the following steps: A step of manufacturing a first die, wherein a first capacitor element is formed on the first surface of the first die. A step of manufacturing a second die, wherein a second capacitor element is formed on the first surface of the second die. A step of stacking the second die on the first die, wherein the first surface of the second die faces the first surface of the first die. A step of thinning the second surface of the second die, wherein the second surface faces the first surface of the second die. A step of forming a plurality of through-via structures, wherein the through-via structures extend from the second surface of the second die through the second die and are coupled to the first capacitor element and the second capacitor element, respectively.

[0011] The step of fabricating the second die described above includes forming the second capacitor element described above on a semiconductor substrate. The step of manufacturing the second die described above includes first forming a dielectric layer on the semiconductor substrate, and then forming the second capacitor element described above on the dielectric layer. The step of thinning the second surface of the second die described above includes removing the semiconductor substrate described above. After forming the through-via structure described above, it may further include forming a redistribution layer on the second surface of the second die, and the redistribution layer is bonded to a plurality of through-via structures. The method of stacking the second die described above on the first die described above includes joining the first die and the second die by fusion bonding or hybrid bonding.

[0012] Prior to the step of forming the through-via structure described above, the following steps may be repeated at least once: the step of fabricating another second die; the step of stacking the other second die on the first die; the step of thinning the second surface of the other second die; and the step of forming a plurality of through-via structures, wherein another second capacitor element is formed on the first surface of the other second die.

[0013] In another embodiment of the present invention, the following steps may be further included after the step of forming the through-via structure described above: a step of manufacturing another first die; a step of manufacturing another second die; a step of stacking another second die on another first die; a step of thinning the second surface of another first die; a step of thinning the second surface of another second die; and a step of joining the second surfaces of the two dies to each other, wherein another first capacitor element is formed on the first surface of another first die and another second capacitor element is formed on the first surface of another second die.

[0014] In each embodiment of the present invention, the first portion of the through-via structure described above is coupled to the first capacitor electrode of the first capacitor element and the first capacitor electrode of the second capacitor element, and the second portion of the through-via structure described above is coupled to the second capacitor electrode of the first capacitor element and the second capacitor electrode of the second capacitor element. [Effects of the Invention]

[0015] Based on the above, the method of the present invention allows for stacking multiple dies, first fabricating a capacitor element on each die, and then connecting the capacitor elements of each die with multiple through-via structures. For this reason, the manufacturing process of the present invention is simple, the capacitance can be greatly increased, and the fabrication of capacitor elements with excessive height can be avoided.

[0016] To make the above features of the present invention easier to understand, embodiments are shown below and will be described in detail in conjunction with the accompanying drawings. [Brief explanation of the drawing]

[0017] [Figure 1] This is a cross-sectional view of a multilayer capacitor device according to a first embodiment of the present invention. [Figure 2] Figure 1 is a circuit diagram of the capacitors in the multilayer capacitor device. [Figure 3]It is a cross-sectional view of a multilayer capacitor device according to a second embodiment of the present invention. [Figure 4A] It is a cross-sectional view of an initial stage of a manufacturing flow for a multilayer capacitor device according to a third embodiment of the present invention. [Figure 4B] It is a cross-sectional view of an intermediate stage of the manufacturing flow of the third embodiment. [Figure 4C] It is a cross-sectional view of an intermediate stage of the manufacturing flow of the third embodiment. [Figure 4D] It is a cross-sectional view of an intermediate stage of the manufacturing flow of the third embodiment. [Figure 4E] It is a cross-sectional view of an intermediate stage of the manufacturing flow of the third embodiment. [Figure 4F] It is a cross-sectional view of an intermediate stage of the manufacturing flow of the third embodiment. [Figure 4G] It is a cross-sectional view of a late stage of the manufacturing flow of the third embodiment. [Figure 5A] It is a cross-sectional view of an initial stage of a manufacturing flow for a multilayer capacitor device according to a fourth embodiment of the present invention. [Figure 5B] It is a cross-sectional view of an intermediate stage of the manufacturing flow of the fourth embodiment. [Figure 5C] It is a cross-sectional view of an intermediate stage of the manufacturing flow of the fourth embodiment. [Figure 5D] It is a cross-sectional view of an intermediate stage of the manufacturing flow of the fourth embodiment. [Figure 5E] It is a cross-sectional view of a late stage of the manufacturing flow of the fourth embodiment. [Figure 6A] It is a cross-sectional view of an initial stage of a manufacturing flow for a multilayer capacitor device according to a fifth embodiment of the present invention. [Figure 6B] It is a cross-sectional view of an intermediate stage of the manufacturing flow of the fifth embodiment. [Figure 6C] It is a cross-sectional view of an intermediate stage of the manufacturing flow of the fifth embodiment. [Figure 6D] It is a cross-sectional view of a late stage of the manufacturing flow of the fifth embodiment. [Figure 7A] It is a cross-sectional view of an initial stage of a manufacturing flow for a multilayer capacitor device according to a sixth embodiment of the present invention. [Figure 7B]This is a cross-sectional view of an intermediate stage in the manufacturing flow of the sixth embodiment. [Figure 7C] This is a cross-sectional view of an intermediate stage in the manufacturing flow of the sixth embodiment. [Figure 7D] This is a cross-sectional view of a later stage in the manufacturing flow of the sixth embodiment. [Figure 8] This is a cross-sectional view of a multilayer capacitor device according to a seventh embodiment of the present invention. [Figure 9] This is a cross-sectional view of another stacked capacitor device according to the seventh embodiment. [Figure 10A] This is a cross-sectional view of the initial stage of the manufacturing flow of a multilayer capacitor device according to the eighth embodiment of the present invention. [Figure 10B] This is a cross-sectional view of an intermediate stage in the manufacturing flow of the eighth embodiment. [Figure 10C] This is a cross-sectional view of an intermediate stage in the manufacturing flow of the eighth embodiment. [Figure 10D] This is a cross-sectional view of an intermediate stage in the manufacturing flow of the eighth embodiment. [Figure 10E] This is a cross-sectional view of a later stage in the manufacturing flow of the eighth embodiment. [Figure 11] This is a cross-sectional view of a multilayer capacitor device according to the ninth embodiment of the present invention. [Figure 12] This is a cross-sectional view of a multilayer capacitor device according to a tenth embodiment of the present invention. [Figure 13A] This is a cross-sectional view of the initial stage of the manufacturing flow of a multilayer capacitor device according to the 11th embodiment of the present invention. [Figure 13B] This is a cross-sectional view of an intermediate stage in the manufacturing flow of the 11th embodiment. [Figure 13C] This is a cross-sectional view of an intermediate stage in the manufacturing flow of the 11th embodiment. [Figure 13D] This is a cross-sectional view of an intermediate stage in the manufacturing flow of the 11th embodiment. [Figure 13E] This is a cross-sectional view of a later stage in the manufacturing flow of the 11th embodiment. [Modes for carrying out the invention]

[0018] Figure 1 is a cross-sectional view of a multilayer capacitor device according to a first embodiment of the present invention.

[0019] Referring to Figure 1, the stacked capacitor device 100 of the first embodiment includes a first die S1, a second die S2, a first capacitor element C1, a second capacitor element C2, and a plurality of through-via structures V1, V2. The first capacitor element C1 is located on the first surface S11 of the first die S1. For example, the first capacitor element C1 is formed on a semiconductor substrate ss1. The second capacitor element C2 is located on the first surface S21 of the second die S2. This is similar to forming the first capacitor element C1 on another semiconductor substrate ss2. The first surface S21 of the second die S2 faces the first surface S11 of the first die S1. The number of second dies S2 is one, but is not limited to one. The number of second dies S2 may be more than one. The through-via structures V1 and V2 described above extend from the second surface S22 of the second die S2, penetrate the second die S2, and connect to the first capacitor element C1 and the second capacitor element C2, respectively. The detailed circuit connection method is shown in Figure 2.

[0020] Next, the first die S1 may have an oxide layer 102a formed on the first capacitor element C1, and its surface is planarized to facilitate the formation of subsequent wiring. The wiring is, for example, a BEOL structure disposed on a semiconductor substrate ss1 and the first capacitor element C1, and the BEOL structure comprises a BEOL insulating layer 104a and an internal connection layer W1 having a multilayer structure, and the BEOL insulating layer 104a is, for example, an oxide layer. The internal connection layer W1 includes a copper layer, an aluminum layer, or a combination thereof. Similarly, the second die S2 may have an oxide layer 102b formed on the second capacitor element C2, and its surface is planarized to facilitate the formation of subsequent wiring. The wiring is, for example, a BEOL structure disposed on a semiconductor substrate ss2 and the second capacitor element C2, and the BEOL structure comprises a BEOL insulating layer 104b and an internal connection layer W2 having a multilayer structure, and the BEOL insulating layer 104b is, for example, an oxide layer. The internal connection layer W2 includes a copper layer, an aluminum layer, or a combination thereof. The multilayer capacitor device 100 is obtained by joining the first surface S11 of the first die S1 and the first surface S21 of the second die S2. For example, an oxide layer 106a formed on the BEOL insulating layer 104a and an oxide layer 106b formed on the BEOL insulating layer 104b are joined to the second die S2 by fusion bonding or hybrid bonding. 2 The first die S1 may be bonded to the oxide layer 106a. A bonding surface BS is provided between the oxide layer 106a and the oxide layer 106b.

[0021] In Figure 1, through-via structures V1 and V2 are connected to internal connection layers W1 and W2, respectively, and a hard mask layer 108 may be placed on the second surface S22 of the second die S2 to facilitate the formation of through-via structures V1 and V2. The material of through-via structures V1 and V2 is, for example, copper, or another suitable metal or alloy, and a liner layer 110 may be placed uniformly on the sidewalls of through-via structure V1 and through-via structure V2, for example, a silicon oxide layer, or another suitable insulating material layer. In Figure 1, the liner layer 110 is not in contact with internal connection layers W1 and / or internal connection layers W2, but the liner layer 110 may be in direct contact with internal connection layers W1 and / or internal connection layers W2.

[0022] The multilayer capacitor device 100 of the first embodiment further includes a redistribution layer RDL disposed on the second surface S22 of the second die S2, and the redistribution layer RDL is coupled to through-via structures V1, V2. The redistribution layer RDL includes a redistribution insulating layer 112 and a conductive redistribution pattern extending within the redistribution insulating layer 112. For example, the redistribution insulating layer 112 may include polyimide (PI) or other suitable material. The redistribution pattern may include a plurality of conductive wires 114 and redistribution through-holes 116. The redistribution layer RDL may further include pads 118, and the lower conductive wires 114 and the upper pads 118 are connected by the redistribution through-holes 116.

[0023] The first capacitor element C1 is electrically connected to the internal connection layer W1, and therefore the through-via structure V1 can be coupled to the first capacitor element C1 by the internal connection layer W1. Similarly, the second capacitor element C2 is electrically connected to the internal connection layer W2, and therefore the through-via structure V2 can be coupled to the second capacitor element C2 by the internal connection layer W2. Detailed circuit connections are shown in Figure 2. In Figure 2, the same or similar components are represented by the same component reference numerals as in Figure 1, and the contents of similar or similar components can be found in the relevant descriptions in Figure 1, which will not be repeated here. Furthermore, although Figure 2 appears to be larger in area than Figure 1 because it shows the circuit connections in the same cross-section, the structures in Figure 2 (e.g., different through-via structures) can be distributed across different cross-sections, and therefore the overall area of ​​the multilayer capacitor device does not increase as a result.

[0024] Referring to Figure 2, the first capacitor element C1 includes a first capacitor electrode TE, a second capacitor electrode BE, and a dielectric layer SC between the first capacitor electrode TE and the second capacitor electrode BE. Similarly, the second capacitor element C2 includes a first capacitor electrode TE, a second capacitor electrode BE, and a dielectric layer SC between the first capacitor electrode TE and the second capacitor electrode BE. The first capacitor element C1 and the second capacitor element C2 in the figure are exemplary structures and may be planar capacitors, trench capacitors, cylindrical capacitors, or combinations thereof. Through-via structure V1 is coupled to the first capacitor electrode TE of the first capacitor element C1, and through-via structure V2 is coupled to the first capacitor electrode TE of the second capacitor element C2. Through-via structure V1' is coupled to the second capacitor electrode BE of the first capacitor element C1, and through-via structure V2' is coupled to the second capacitor electrode BE of the second capacitor element C2. Therefore, a portion of the through-via structures V1 and V2 is coupled to the first capacitor electrode TE of a different capacitor element, while the other portion of the through-via structures V1 and V2 is coupled to the second capacitor electrode BE of a different capacitor element. In Figure 2, both the through-via structures V1 and V2 are coupled to the power supply voltage (V DD ) is connected, and therefore the first capacitor electrode TE of both the first capacitor element C1 and the second capacitor element C2 is VDD The through-via structures V1 and V2 in Figure 1 can be electrically connected to the same pad 118 via conductive wiring 114 in the redistribution layer RDL. Similarly, both the through-via structure V1' and the through-via structure V2' can be connected to the ground voltage (V SS ) is electrically connected, and therefore the second capacitor electrode BE of both the first capacitor element C1 and the second capacitor element C2 is V SS It combines with this. The rest can be inferred based on this.

[0025] Figure 3 is a cross-sectional view of a multilayer capacitor device according to a second embodiment of the present invention.

[0026] Referring to Figure 3, the difference between the stacked capacitor device 300 and the first embodiment is that a third die S3 is further stacked on top of the second die S2. That is, two dies (which may be considered as two second dies) are stacked on top of the first die S1. A third capacitor element C3 is placed on the first surface S31 of the third die S3. For example, the third capacitor element C3 is formed on another semiconductor substrate ss3. The first surface S31 of the third die S3 may also have an oxide layer 302 covering the third capacitor element C3, and its surface is planarized to facilitate the formation of subsequent wiring. The wiring is, for example, a BEOL structure formed on the semiconductor substrate ss3 and the third capacitor element C3, and the BEOL structure includes a BEOL insulating layer 304 and an internal connection layer W4 having a multilayer structure, and the internal connection layer W4 is electrically coupled to the third capacitor element C3. Similar to the circuit connection method in Figure 2, the BEOL insulating layer 304 is, for example, an oxide layer. The internal connection layer W4 described above includes a copper layer, an aluminum layer, or a combination thereof. The internal connection layer W3 is connected to the through-via structure V4 in the third die S3 via a redistribution layer RDL. The third die S3 in the multilayer capacitor device 300 may be joined to the second die S2 by fusion bonding or hybrid bonding. For example, the oxide layer on the second surface S22 of the second die S2 and the oxide layer on the first surface S31 of the third die S3 may be joined to form an oxide layer 306 having a bonding surface BS, and have an internal connection layer W3 having a multilayer structure. The internal connection layer W3 may connect the through-via structures V1 and V2 in the second die S2 and the through-via structure V3 in the third die S3.

[0027] In Figure 3, a hard mask layer 308 may be placed on the second surface S32 of the third die S3 to facilitate the formation of through-via structures V3 and V4. The material of the through-via structures V3 and V4 is, for example, copper or other suitable metal or alloy, and a liner layer 310 may be placed on the sidewalls of both the through-via structure V3 and the through-via structure V4, for example, a silicon oxide layer or other suitable insulating material layer. In Figure 3, the liner layer 310 is not in contact with the internal connection layers W3 and / or W4, but is not limited to this. The liner layer 310 may be in direct contact with the internal connection layers W3 and / or W4. A redistribution layer RDL is placed on the second surface S32 of the third die S3, and the redistribution layer RDL is coupled to the through-via structures V3 and V4. The redistribution layer RDL may include a redistribution insulating layer 312 and a conductive redistribution pattern extending within the redistribution insulating layer 312. For example, the redistribution insulating layer 312 may contain polyimide (PI) or other suitable material. The redistribution pattern may include a plurality of conductive wires 314 and redistribution through-holes 316. The materials of the conductive wires 314 and redistribution through-holes 316 in the redistribution pattern may be, for example, copper, aluminum, tungsten, silver, gold, or other suitable metals or alloys. The redistribution layer RDL may further include pads 318, connecting the lower conductive wires 314 and the upper pads 318 via the redistribution through-holes 316. The material of the pads 318 may be, for example, aluminum, copper, or other suitable metals or alloys. The surface on which the pads 318 are exposed may further include conductive terminals (not shown), such as BGA balls or C4 bumps.

[0028] Based on the second embodiment disclosed, a structure can be achieved in which multiple dies are stacked and packaged into a single capacitor element (Si Cap), thereby increasing capacitance within a limited chip carrier area and avoiding the problem of capacitor elements of excessive height collapsing.

[0029] Figures 4A to 4G are cross-sectional views of the manufacturing flow of a multilayer capacitor device according to a third embodiment of the present invention. In these figures, the same or similar component reference numerals are used as in the first embodiment to represent the same or similar component, and the details of the same or similar component can be found in the relevant descriptions of the first embodiment described above, so they will not be repeated here.

[0030] Referring to Figure 4A, first, a first die S1 and a second die S2 are fabricated, and the method for fabricating the first die S1 may be the same as or different from the method for fabricating the second die S2. If the method for fabricating the first die S1 and the method for fabricating the second die S2 are the same, then the first die S1 and the second die S2 can be formed with the same or similar structure. First, a first capacitor element C1 is formed on the first surface S11 of the first die S1. This step involves, for example, first forming the first capacitor element C1 on a semiconductor substrate ss1, forming an oxide layer 102a on the first capacitor element C1 and performing a planarization process, and then forming a BEOL structure thereon that includes a BEOL insulating layer 104a and an internal connection layer W1 having a multilayer structure. The internal connection layer W1 is, for example, a copper layer. Next, another oxide layer 106a is formed on the BEOL structure described above. In some embodiments, a second capacitor element C2 is first formed on the first surface S21 of the second die S2. This step involves, for example, first forming the second capacitor element C2 on another semiconductor substrate ss2, forming an oxide layer 102b on the second capacitor element C2 and performing a planarization process, and then forming a BEOL structure thereon, which includes a BEOL insulating layer 104b and an internal connection layer W2 having a multilayer structure. The internal connection layer W2 is, for example, a copper layer. Next, another oxide layer 106b is formed on the BEOL structure described above. Next, the second die S2 is laminated on the first die S1, with the first surface S21 of the second die S2 facing the first surface S11 of the first die S1. The lamination method involves, for example, fusion bonding the first die S1 and the second die S2 to form a junction surface BS between the oxide layer 106a and the oxide layer 106b. However, the present invention is not limited thereto. One method for stacking a second die S2 on a first die S1 is, for example, a chip-level stacking process using hybrid bonding.

[0031] Subsequently, referring to Figure 4B, after the step of stacking the second die S2 on the first die S1, the second surface S22 of the second die S2 is thinned. Thinning of the second surface S22 of the second die S2 is, for example, thinning of the back surface of the semiconductor substrate ss2. Then, a hard mask layer 108 is first formed on the thinned second surface S22, and an opening VO1 is formed extending from the second surface S22 of the second die S2 and penetrating the second die S2 using a photolithography / etching method. Furthermore, in order to prevent oxidation of the internal connection layer W1 (for example, a copper layer), the opening VO1 is stopped within the oxide layer 106a above the internal connection layer W1 and does not expose the internal connection layer W1.

[0032] Subsequently, referring to Figure 4C, another photolithography / etching method is used to form an opening VO2 that extends from the second surface S22 of the second die S2 and penetrates the semiconductor substrate ss2. The opening VO2 remains within the oxide layer 102b above the internal connection layer W2, without exposing the internal connection layer W2.

[0033] Next, referring to Figure 4D, a liner layer 110 is formed on the inner surfaces of openings VO1 and VO2, for example, a silicon oxide layer or another suitable insulating material layer. The method for forming the liner layer 110 is, for example, to conformally deposit a layer of liner material onto the surface of the hard mask layer 108 and the inner surfaces of openings VO1 and VO2, and then remove the liner material other than that of openings VO1 and VO2, but is not limited to this.

[0034] Then, referring to Figure 4E, first remove the liner layer 110 at the bottom of opening VO1 and the bottom of opening VO2, and then further etch until the internal connecting layer W1 below opening VO1 and the internal connecting layer W2 below opening VO2 are exposed. Since the thickness of the liner layer 110 in openings VO1 and VO2 is similar, and the remaining portion of the oxide layer 106a below opening VO1 and the remaining portion of the oxide layer 106b below opening VO2 are of approximately the same thickness, this etching process may be performed simultaneously.

[0035] Subsequently, referring to Figure 4F, a through-via structure V1 is formed in opening VO1 and a through-via structure V2 is formed in opening VO2. The method for forming the through-via structures V1 and V2 is, for example, to first deposit a metal material to fill openings VO1 and VO2, and then to remove the metal material other than openings VO1 and VO2 by performing an etch-back or planarization process, but is not limited to this. In addition, a barrier layer (not shown) may be formed on the inner surfaces of openings VO1 and VO2 before depositing the metal material. The formed through-via structure V1 extends from the second surface S22, penetrates the second die S2, and connects to the internal connection layer W1, and the formed through-via structure V2 extends from the second surface S22, penetrates the semiconductor substrate ss2 in the second die S2, and connects to the internal connection layer W2. Detailed circuit connection methods can be found in Figure 2 and related explanations and will not be repeated here.

[0036] Referring to Figure 4G, a redistribution layer RDL may be formed on the second surface S22 of the second die S2, and the redistribution layer RDL is coupled to the through-via structures V1 and V2. A method for forming the redistribution layer RDL is, for example, to first form a plurality of conductive wirings 114 connected to the through-via structures V1 and V2, then deposit a redistribution insulating layer 112, and then form redistribution through-holes 116 and pads 118 in the redistribution insulating layer 112, and expose the pads 118, but is not limited to this. Subsequently, conductive terminals (not shown), such as BGA balls or C4 bumps, may be formed on the surface where the pads 118 are exposed.

[0037] Figures 5A to 5E are cross-sectional views of the manufacturing flow of a multilayer capacitor device according to a fourth embodiment of the present invention.

[0038] Refer to Figure 5A, and for the previous manufacturing flow, see Figures 4A to 4F. Subsequently, an oxide layer 500 and an internal connecting layer W3 are first formed on the second surface S22 of the second die S2. The internal connecting layer W3 is connected to through via structures V1 and V2.

[0039] Referring to Figure 5B, the third die S3 is fabricated, and the method for fabricating the third die S3 may be the same as the method for fabricating the second die S2; therefore, the third die S3 may be considered as another second die. First, a third capacitor element C3 is formed on the first surface S31 of the third die S3. This step involves, for example, forming the third capacitor element C3 on a semiconductor substrate ss3, forming an oxide layer 302 on the third capacitor element C3 and performing a planarization process, and then forming a BEOL structure on top of that, which includes a BEOL insulating layer 304 and an internal connection layer W4 having a multilayer structure. The internal connection layer W4 is, for example, a copper layer and is similar to the circuit connection method in Figure 2, and the internal connection layer W4 is electrically coupled to the third capacitor element C3. Next, another oxide layer 502 is formed on the BEOL structure described above. Next, a third die S3 is laminated on the second die S2, and the first surface S31 of the third die S3 faces the first surface S11 of the first die S1. The lamination method described above is, for example, fusion bonding or hybrid bonding, in which a bonding surface BS is formed between the oxide layer 500 and the oxide layer 502.

[0040] In Figure 5C, the methods in Figures 4B and 4C may be used as a reference. After thinning the third die S3, a hard mask layer 308 is formed on the second surface S32, and openings VO3 and VO4 are formed extending from the second surface S32 of the third die S3 and penetrating the semiconductor substrate ss3 of the third die S3. Of these, opening VO3 is stopped within the oxide layer 502 above the internal connection layer W3, but is not limited to this. Opening VO3 may also be stopped within the oxide layer 500 above the internal connection layer W3. Different photolithography / etching methods may be employed to form openings VO3 and VO4 at different depths and to prevent the internal connection layer W3 and internal connection layer W4 (e.g., copper layer) from being exposed and oxidized.

[0041] Subsequently, in Figure 5D, referring to the methods in Figures 4D to 4F, a liner layer 310 is formed on the inner surfaces of openings VO3 and VO4, exposing the internal connection layer W3 below opening VO3 and the internal connection layer W4 below opening VO4, and through via structures V3 and V4 are formed within them, respectively.

[0042] If additional dies are to be stacked, the steps shown in Figures 5A to 5D above may be repeated.

[0043] In Figure 5E, the method in Figure 4G may be used as a reference, and a redistribution layer RDL including a redistribution insulating layer 312, conductive wiring 314, redistribution through-holes 316, and pads 318 may be formed on the second surface S32 of the third die S3, and the redistribution layer RDL is coupled to through-via structures V3 and V4.

[0044] Figures 6A to 6D are cross-sectional views of the manufacturing flow of a multilayer capacitor device according to a fifth embodiment of the present invention.

[0045] Referring to Figure 6A, first a first die S1 and a second die S2 are fabricated, and the method for fabricating the first die S1 may be the same as or different from the method for fabricating the second die S2. If the method for fabricating the first die S1 and the method for fabricating the second die S2 are the same, then the first die S1 and the second die S2 can be formed with the same or similar structure. First, a first capacitor element C1 is formed on the first surface S11 of the first die S1. This step is, for example, to first form the first capacitor element C1 on a semiconductor substrate ss1, to form an oxide layer 102a on the first capacitor element C1 and perform a planarization process, and then to form a BEOL structure thereon that includes a BEOL insulating layer 104a and an internal connecting layer W1 having a multilayer structure, and then to form another oxide layer 106a and a metal layer ML1 located in the oxide layer 106a on the BEOL structure described above. In this process, the metal layer ML1 is electrically connected to the internal connection layer W1, and the metal layer ML1 is, for example, an aluminum layer or another metal material layer that is resistant to oxidation. First, a second capacitor element C2 is formed on the first surface S21 of the second die S2. This step involves, for example, first forming the second capacitor element C2 on another semiconductor substrate ss2, forming an oxide layer 102b on the second capacitor element C2 and performing a planarization process, and then forming a BEOL structure thereon, which includes a BEOL insulating layer 104b and an internal connection layer W2 having a multilayer structure. Next, another oxide layer 106b and a metal layer ML2 in the oxide layer 106b are formed on the BEOL structure described above. In this process, the metal layer ML2 is electrically connected to the internal connection layer W2, and the metal layer ML2 is, for example, an aluminum layer or another metal material layer that is resistant to oxidation. Next, the second die S2 is laminated onto the first die S1, with the first surface S21 of the second die S2 facing the first surface S11 of the first die S1. One method of lamination is, for example, fusion bonding of the first die S1 and the second die S2, forming a bonding surface BS between the oxide layer 106a and the oxide layer 106b. However, the present invention is not limited thereto. Another method of laminating the second die S2 onto the first die S1 is, for example, hybrid bonding.

[0046] Referring to Figure 6B, the second surface S22 of the second die S2 may be thinned, and openings VO1 and VO2 may be simultaneously formed using a photolithography / etching method, with the metal layer ML1 in the deeper opening VO1 being used as an etching stop layer.

[0047] Referring to Figure 6C, a through via structure V1 is formed in opening VO1, and a through via structure V2 is formed in opening VO2. The method for forming the through via structures V1 and V2 is, for example, to first deposit a metal material to fill openings VO1 and VO2, and then to remove the metal material other than openings VO1 and VO2 by performing an etch-back or planarization process, but is not limited to this. If necessary, before depositing the metal material, a film layer such as a liner layer (not shown) or a barrier layer (not shown) may be formed on the inner surface or sidewalls of openings VO1 and VO2.

[0048] In Figure 6D, a redistribution layer RDL may be formed on the second surface S22 of the second die S2, as can be seen from Figure 4G and related explanations, but this will not be explained again here.

[0049] Figures 7A to 7D are cross-sectional views of the manufacturing flow of a multilayer capacitor device according to the sixth embodiment of the present invention.

[0050] Refer to Figure 7A, and for the previous manufacturing flow, refer to Figures 6A to 6C. First, an oxide layer 700, an internal connecting layer W2 within it, and a metal layer ML3 are formed on the second surface S22 of the second die S2, and the internal connecting layer W2 is electrically connected to the metal layer ML3. The metal layer ML3 is, for example, an aluminum layer or another metal material layer that is difficult to oxidize.

[0051] Referring to Figure 7B, a third die S3 is fabricated, and the method for fabricating the third die S3 may be the same as the method for fabricating the second die S2; therefore, the third die S3 may be considered as another second die. First, a third capacitor element C3 is formed on the first surface S31 of the third die S3, an oxide layer 302 is formed on the third capacitor element C3 and a planarization process is performed, and then a BEOL structure including a BEOL insulating layer 304 and an internal connection layer W4 having a multilayer structure is formed thereon, and similar to the circuit connection method in Figure 2, the internal connection layer W4 is electrically coupled to the third capacitor element C3. Next, another oxide layer 702 and a metal layer ML4 within it are formed on the BEOL structure described above, and the internal connection layer W4 is electrically connected to the metal layer ML4. The metal layer ML4 is, for example, an aluminum layer or another metal material layer that is difficult to oxidize. Next, a third die S3 is laminated on the second die S2, and the first surface S31 of the third die S3 faces the first surface S11 of the first die S1. The lamination method described above is, for example, fusion bonding or hybrid bonding, in which a bonding surface BS is formed between the oxide layer 700 and the oxide layer 702.

[0052] In Figure 7C, the third die S3 is thinned, and through-via structures V3 and V4 are formed, referring to the methods in Figures 6B and 6C. Of these, through-via structure V3 is coupled to the first capacitor element C1 and the second capacitor element C2, respectively, via metal layer ML3. Through-via structure V4 is coupled to the third capacitor element C3 via metal layer ML4.

[0053] In Figure 7D, a redistribution layer RDL may be formed on the second surface S32 of the third die S3, as can be seen from Figure 5E and related explanations, but this will not be explained again here.

[0054] Figure 8 is a cross-sectional view of a multilayer capacitor device according to a seventh embodiment of the present invention.

[0055] Referring to Figure 8, the difference between the multilayer capacitor device 800 and the first embodiment is that, except for the first die S1 having a semiconductor substrate ss1, the remaining dies do not have a semiconductor substrate and instead use a dielectric layer D2, on which the second capacitor element C2 is formed. As a result, the total thickness of the multilayer capacitor device 800 can be significantly reduced. For example, the thickness of the thinned semiconductor substrate is more than 10 times the thickness of the dielectric layer D2, and therefore the semiconductor substrate-free design is more suitable for applications in mobile devices and devices requiring miniaturization. The dielectric layer D2, the second capacitor element C2 formed on the surface D2s of the dielectric layer D2, the oxide layer 102b, and the BEOL structure covering the second capacitor element C2 can be considered as the second die S2. In some embodiments, when the first die S1 and the second die S2 are manufactured using the same process, the first die S1 may include a semiconductor substrate ss1, a dielectric layer D1 thereon, a first capacitor element C1 formed on the surface D1s of the dielectric layer D1, an oxide layer 102a, and a BEOL structure covering the first capacitor element C1. In some embodiments, the materials of the dielectric layer D1 and dielectric layer D2 are, for example, silicon oxide or other suitable dielectric material.

[0056] In Figure 8, through-via structures V1 and V2 are connected to internal connection layers W1 and W2, respectively, and since etching of the semiconductor substrate is not required in the via process, the hard mask layer 108 in Figure 1 can be omitted, and the dielectric layer D2, oxide layer 102b, BEOL insulating layer 104b, oxide layer 106a, and oxide layer 106b, which have similar etching rates, can be directly etched and stopped at internal connection layers W1 and W2. Also, a design without a semiconductor substrate is possible. 800 multilayer capacitor devices To reduce the overall thickness, the depth of the through-via structure V1 (and through-via structure V2) is also reduced accordingly. As a result, the asbestos ratio between through-via structure V1 and through-via structure V2 naturally decreases, thus lowering the difficulty of the process.

[0057] Figure 9 is a cross-sectional view of another stacked capacitor device according to the seventh embodiment.

[0058] In Figure 9, the difference between the multilayer capacitor device 900 and the multilayer capacitor device 800 in Figure 8 is that a third die S3 is further stacked on top of the second die S2. That is, two dies (which may be considered as two second dies S2) are stacked on top of the first die S1. The first surface S31 of the third die S3 faces downward. For this reason, the third die S3 also does not contain a semiconductor substrate and may include a dielectric layer D3, a third capacitor element C3 formed on the dielectric layer D3, an oxide layer 302, and a BEOL structure covering the third capacitor element C3 (for example, a BEOL insulating layer 304 and an internal connection layer W4). The redistribution layer RDL is located on the back surface D3b of the dielectric layer D3, and the redistribution layer RDL is coupled to through-via structures V3 and V4. The redistribution layer RDL may include, but is not limited to, a redistribution insulating layer 312 and a conductive redistribution pattern extending within the redistribution insulating layer 312, such as conductive wiring 114, redistribution through-holes 316, pads 318, etc.

[0059] Figures 10A to 10E are cross-sectional views of the manufacturing flow of a multilayer capacitor device according to the eighth embodiment of the present invention.

[0060] Referring to Figure 10A, first a first die S1 and a second die S2 are fabricated, and the method for fabricating the first die S1 may be the same as or different from the method for fabricating the second die S2. If the method for fabricating the first die S1 and the method for fabricating the second die S2 are the same, then a first die S1 and a second die S2 with the same or similar structure can be formed. For example, the method for fabricating the first die S1 involves forming a dielectric layer D1 on a semiconductor substrate ss1, forming a first capacitor element C1 on the surface D1s of the dielectric layer D1, then forming an oxide layer 102a on the first capacitor element C1, and forming a BEOL structure on the oxide layer 102a. The BEOL structure may include a BEOL insulating layer 104a, an internal connecting layer W1, and an aluminum pad AP that is difficult to oxidize. Next, another oxide layer 106a is formed on the BEOL structure described above. The method for fabricating the second die S2 is similar to the method for fabricating the first die S1. For example, a dielectric layer D2 is formed on a semiconductor substrate ss2, a second capacitor element C2 is formed on the surface D2s of the dielectric layer D2, then an oxide layer 102b is formed on the second capacitor element C2, a BEOL structure is formed on the oxide layer 102b, and then another oxide layer 106b is formed on the BEOL structure described above. Subsequently, the second die S2 is stacked on the first die S1, and the first surface S21 of the second die S2 faces the first surface S11 of the first die S1. The stacking method involves joining the first die and the second die by fusion bonding or hybrid bonding, and a bonding surface BS is formed between the oxide layer 106a and the oxide layer 106b.

[0061] Referring to Figure 10B, after the step of stacking the second die S2 on the first die S1, a step of thinning the second surface S22 of the second die S2 is performed to remove, for example, the semiconductor substrate ss2 in Figure 10A. First, the back surface of the semiconductor substrate ss2 may be polished using a planarization process such as CMP, and then the semiconductor substrate ss2 may be completely removed using wet etching.

[0062] Referring to Figure 10C, another photolithography / etching method is used to extend from the second surface S22 of the second die S2 to form openings VO1 and VO2 that penetrate the second die S2, with openings VO1 and VO2 being stopped by different aluminum pads AP.

[0063] Referring to Figure 10D, a liner layer 110 is formed on the inner surfaces of openings VO1 and VO2. The method for forming the liner layer 110 is, for example, conformally depositing a layer of liner material on the inner surfaces of openings VO1 and VO2 in the dielectric layer D2, but is not limited to this. Subsequently, a through-via structure V1 is formed in opening VO1, and a through-via structure V2 is formed in opening VO2. The method for forming the through-via structures V1 and V2 is, for example, to first deposit a metallic material to fill openings VO1 and VO2, and then perform an etch-back or planarization process to remove the metallic material other than openings VO1 and VO2 and the aforementioned liner material, but is not limited to this.

[0064] Referring to Figure 10E, a redistribution layer RDL may be formed on the second surface S22 of the second die S2, and the redistribution layer RDL is coupled to the through-via structures V1 and V2. A method for forming the redistribution layer RDL is, for example, to first form a plurality of conductive wirings 114 connected to the through-via structures V1 and V2, then deposit a redistribution insulating layer 112, and then form redistribution through-holes 116 and pads 118 in the redistribution insulating layer 112, and expose the pads 118, but is not limited to this. Subsequently, conductive terminals (not shown), such as BGA balls or C4 bumps, may be formed on the surface where the pads 118 are exposed.

[0065] Figure 11 is a cross-sectional view of a multilayer capacitor device according to the ninth embodiment of the present invention.

[0066] Referring to Figure 11, the difference between the multilayer capacitor device 1100 and the multilayer capacitor device 900 in Figure 9 lies in the formation of a trench capacitor TC1 separately within the dielectric layer D1. In some embodiments, the dielectric layer D1 includes a first film layer L1 and a second film layer L2. The first film layer L1 is formed on a semiconductor substrate ss1, and the second film layer L2 is formed on the first film layer L1. The trench capacitor TC1 is formed between the first film layer L1 and the second film layer L2, and the planar capacitor PC1 may be formed on the second film layer L2. The trench capacitor TC1 and the planar capacitor PC1 are, i.e., first capacitor elements arranged on the first die S1, and thus the capacitance can be further increased. The trench capacitor TC1 includes an upper electrode 400, a lower electrode 404, and a dielectric layer 402 between them. The planar capacitor PC1 also includes an upper electrode 406, a lower electrode 410, and a dielectric layer 408 between them. In some embodiments, the upper electrode 400 of the trench capacitor TC1 may be electrically connected to the upper electrode 406 of the planar capacitor PC1 via a wiring structure 412a, and the lower electrode 404 of the trench capacitor TC1 may be electrically connected to the lower electrode 410 of the planar capacitor PC1 via a wiring structure 412a. Of these, the wiring structure 412a may be connected to an internal connection layer W1 in the BEOL structure and coupled to a through-via structure V1 via an oxidation-resistant aluminum pad AP on the internal connection layer W1. The internal connection layer W1 connected to the wiring structure 412a may be connected to a through-via structure V1 (not shown) formed in another cross-section.

[0067] In Figure 11, the dielectric layer D2 in the second die S2 similarly includes a trench capacitor TC2 and a planar capacitor PC2. The dielectric layer D2 includes a first film layer L1 and a second film layer L2. Since the second die S2 is joined to the first die S1 after inversion, the second film layer L2 is located below the first film layer L1. The trench capacitor TC2 is formed between the first film layer L1 and the second film layer L2, and the planar capacitor PC2 may be formed on the second film layer L2. Therefore, the trench capacitor TC2 and the planar capacitor PC2 are second capacitor elements arranged on the second die S2. The trench capacitor TC2 is similar to the trench capacitor TC1, and the planar capacitor PC2 is similar to the planar capacitor PC1, so its circuit design and connection method can refer to the first die S1, and different electrodes of the trench capacitor TC2 and the planar capacitor PC2 can be coupled via different through-via structures V2. A third die S3 is further stacked on top of the second die S2. That is, two dies (which can be considered as two second dies S2) are stacked on top of the first die S1, and therefore the structure of the third die S3 is identical to that of the second die S2, and will not be explained again here.

[0068] Referring to Figure 11, the internal connection layer W3 connects the through-via structure V1 in the second die S2 and the through-via structure V3 in the third die S3, and can connect the lower conductive wiring 314 and the upper pad 318 via the redistribution through-hole 316 in the redistribution layer RDL. The internal connection layer W4 connects the different electrodes of the trench capacitor TC3 and the planar capacitor PC3 to different through-via structures V4, respectively, and connects them to the different upper pads 318 via the conductive wiring 314 and redistribution through-hole 316 in the redistribution layer RDL.

[0069] Figure 12 is a cross-sectional view of a multilayer capacitor device according to a 10th embodiment of the present invention.

[0070] Referring to Figure 12, the difference between the multilayer capacitor device 1200 and the ninth embodiment is that in the multilayer capacitor device 1200, the capacitor elements in the first die S1 and the second die S2 each contain multiple capacitors. For example, the first capacitor element C1 contains two multilayer capacitors SC1, and the second capacitor element C2 contains two multilayer capacitors SC2. The two multilayer capacitors SC1 may be in series or parallel with each other, and the two multilayer capacitors SC2 may be in series or parallel with each other. In addition, the die stacking method in the multilayer capacitor device 1200 is to first stack the second die S2 on the first die S1, then stack the second die S2' on the first die S1', and then stack the second die S2' on the second die S2. Of these, the first die S1' basically has the same components as the first die S1, and the second die S2' basically contains the same components as the second die S2. The only difference between the two may be in the internal connections in the backend process and the wiring of the redistribution layer. A redistribution layer RDL may be placed on the second surface S22 of the second die S2 to facilitate wiring connections. The multilayer capacitor device 1200 also further includes through-via structures V7 that penetrate the first die S1' and the second die S2'. In Figure 12, through-via structure V1'' connects internal connection layer W1' and internal connection layer W3', and through-via structure V2'' connects internal connection layer W2' and internal connection layer W3. Through-via structure V6 connects conductive wiring 314 and internal connection layer W1', and through-via structure V5 connects conductive wiring 314 and internal connection layer W2'. Although some wiring connections are not shown, it should be apparent in other cross-sectional views that they have the corresponding wiring layers.

[0071] Figures 13A to 13E are cross-sectional views of the manufacturing flow of a multilayer capacitor device according to the 11th embodiment of the present invention.

[0072] Referring to Figure 13A, first a first die S1 and a second die S2 are manufactured, and the method for manufacturing the first die S1 and the second die S2 can be described in the embodiments described above. In some embodiments, a plurality of multilayer capacitors SC1 may be formed in the first die S1, and a plurality of multilayer capacitors SC2 may be formed in the second die S2. Subsequently, the second die S2 is laminated on the first die S1, and the first surface S21 of the second die S2 faces the first surface S11 of the first die S1. Among these, the lamination method is, for example, joining the first die S1 and the second die S2 by fusion bonding or hybrid bonding, and a bonding surface BS is formed between the oxide layer 106a and the oxide layer 106b.

[0073] Next, referring to Figure 13B, after the step of depositing the second die S2 on the first die S1, the second surface S22 of the second die S2 is thinned, for example, by removing the semiconductor substrate ss2 in Figure 13A. The relevant processes can be found in the embodiments described above. Subsequently, through-via structures V1 and V2 are formed extending from the second surface S22 of the second die S2 and penetrating the second die S2. Of these, through-via structure V1 is located on the aluminum pad AP in the BEOL insulating layer 104a, and through-via structure V2 is located on the aluminum pad AP in the BEOL insulating layer 104b. Through-via structure V1 is electrically coupled to the first capacitor element C1, and through-via structure V2 is electrically coupled to the second capacitor element C2. The number of through-via structures V1 and V2 may be multiple, similar to the circuit connection method in Figure 2.

[0074] Subsequently, referring to Figure 13C, a redistribution layer RDL may be formed on the second surface S22 of the second die S2, and the redistribution layer RDL is coupled to the through via structures V1 and V2. The method for forming the redistribution layer RDL can be described by referring to the embodiments described above. Next, an oxide layer 106c may be formed on the redistribution layer RDL.

[0075] Referring to Figure 13D, the previous step may be repeated to laminate one more first die S1' and one second die S2', and another oxide layer 106d may be formed on the second surface S22 of the second die S2', and then bonded to the oxide layer 106c by fusion bonding. Subsequently, through-via structures V5 and V6 are formed by extending from the second surface S12 of the first die S1' and penetrating the first die S1'.

[0076] Referring to Figure 13E, a through-via structure V7 is formed extending from the second surface S12 of the first die S1' and penetrating the first die S1' and the second die S2, with the through-via structure V7 located on the aluminum pad AP in the second die S2. Another redistribution layer RDL is formed on the second surface S12, and the redistribution layer RDL is coupled to the through-via structures V5, V6, and V7. The method for forming the redistribution layer RDL can be described by referring to the embodiments described above, and the pad 318 is exposed. Subsequently, conductive terminals (not shown), such as BGA balls or C4 bumps, may be further formed on the surface where the pad 318 is exposed.

[0077] Although the present invention has been disclosed in the embodiments described above, these are not intended to limit the invention. Those skilled in the art can make some modifications and changes without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims. [Industrial applicability]

[0078] The multilayer capacitor device of the present invention can be used in a system-on-a-chip (SoC). [Explanation of symbols]

[0079] 100, 300, 800, 900, 1100, 1200: Multilayer capacitor devices 102a, 102b, 106a, 106b, 106c, 106d, 302, 306, 500, 502, 700, 702: Oxide layer 104a, 104b, 304: BEOL insulating layer 108, 308: Hard mask layer 110, 310: Liner layer 112, 312: Rewiring insulation layer 114, 314: Conductive wiring 116, 316: Rewiring through-holes 118, 318: Pad 400, 406: Upper electrode 402, 408: Dielectric layer 404, 410: Lower electrode 412a, 412b: Wiring structure AP: Aluminum Pad BE: Second capacitor electrode BS: Joint surface C1: First capacitor element C2: Second capacitor component C3: Third capacitor element D1, D2, D3: Dielectric layers D1s, D2s: Surface D3b: Back L1: First film layer L2: Second film layer ML1, ML2, ML3, ML4: Metal layer PC1, PC2, PC3: Planar Capacitors RDL: Redistribution layer S1, S1': First Die S11, S21, S31: 1st surface S2, S2': Second Die S12, S22, S32: 2nd surface S3: Third Die SC: Dielectric layer SC1, SC2: Multilayer Capacitors ss1, ss2, ss3: Semiconductor body material TC1, TC2, TC3: Trench Capacitors TE: First capacitor electrode V1, V1', V1", V2, V2', V2", V3, V4, V5, V6, V7: Through via structure V DD Power supply voltage VO1, VO2, VO3, VO4: Opening V SS : Ground voltage W1, W1', W2, W2', W3, W4: Internal connection layers

Claims

1. At least one first die, A first capacitor element disposed on the first surface of at least one first die, A first BEOL structure is formed above the first capacitor element and includes a first internal connection layer having a multilayer structure, wherein the first capacitor element is electrically coupled to the first internal connection layer. At least one second die stacked on the first die, A second capacitor element is disposed on the first surface of at least one second die, A second BEOL structure is formed above the second capacitor element and includes a second internal connection layer having a multilayer structure, wherein the second capacitor element is electrically coupled to the second internal connection layer. A plurality of through-via structures extending from the second surface of the at least one second die and penetrating the at least one second die, and each bonding to the first internal connecting layer and the second internal connecting layer, A liner layer is provided on the side wall of each of the through via structures and does not come into contact with the first internal connection layer and the second internal connection layer, Includes, The first surface of the at least one second die faces the first surface of the at least one first die. Multilayer capacitor device.

2. The at least one second die includes a dielectric layer, and the second capacitor element is disposed on the surface of the dielectric layer. The multilayer capacitor device according to claim 1.

3. The first capacitor element and the second capacitor element each include a plurality of multilayer capacitors. The multilayer capacitor device according to claim 1.

4. The first portion of the plurality of through via structures is coupled to the first capacitor electrode of the first capacitor element and the first capacitor electrode of the second capacitor element, The second portion of the plurality of through via structures is coupled to the second capacitor electrode of the first capacitor element and the second capacitor electrode of the second capacitor element. The multilayer capacitor device according to claim 1.

5. The number of the at least one first die is multiple, and each of the first surfaces in the multiple first dies has the first capacitor element. The number of the at least one second die is multiple, and each of the first surfaces in the multiple second dies has the second capacitor element. The multilayer capacitor device according to claim 1.

6. A step of manufacturing a first die, wherein a first capacitor element is formed on the first surface of the first die, a first BEOL structure is formed above the first capacitor element, the first BEOL structure includes a first internal connection layer having a multilayer structure, and the first capacitor element is electrically coupled to the first internal connection layer. A step of manufacturing a second die, wherein a second capacitor element is formed on the first surface of the second die, a second BEOL structure is formed above the second capacitor element, the second BEOL structure includes a second internal connection layer having a multilayer structure, and the second capacitor element is electrically coupled to the second internal connection layer. A step of stacking the second die on the first die, wherein the first surface of the second die faces the first surface of the first die, A step of thinning the second surface of the second die, wherein the second surface faces the first surface of the second die, A step of forming a plurality of through via structures, wherein the plurality of through via structures extend from the second surface of the second die and penetrate the second die, and are coupled to the first internal connecting layer and the second internal connecting layer, respectively, and a liner layer is formed on the side wall of each of the through via structures, and the liner layer does not come into contact with the first internal connecting layer and the second internal connecting layer. including, A method for manufacturing multilayer capacitor devices.

7. The first portion of the plurality of through via structures is coupled to the first capacitor electrode of the first capacitor element and the first capacitor electrode of the second capacitor element, The second portion of the plurality of through via structures is coupled to the second capacitor electrode of the first capacitor element and the second capacitor electrode of the second capacitor element. A method for manufacturing a multilayer capacitor device according to claim 6.

8. A method for laminating the second die onto the first die includes a method for joining the first die and the second die by fusion bonding or hybrid bonding. A method for manufacturing a multilayer capacitor device according to claim 6.

Images