Skip the highest data state program verification to improve program performance.

Abstract

To provide a nonvolatile memory device with improved performance and a method of operating the same.SOLUTION: The apparatus includes a memory cell coupled to a word line and storing a threshold voltage corresponding to a data state. The data states include a highest data state in which the threshold voltages of the memory cells associated therewith are higher than those of the other data states. The control means applies, during each of a plurality of program loops of a program operation, each of a series of programming pulses at a program voltage followed by verify pulses at a plurality of program verify voltages each associated with one of the data states to a selected one of the word lines to program and verify the memory cells connected to the word line, and skips verifying memory cells targeted for a highest data state in at least one of the plurality of program loops.SELECTED DRAWING: Figure 28

Description

Technical Field

[0001] The present technology relates to the operation of memory devices. Background Art

[0002] Semiconductor memory devices or apparatuses are widely used in various electronic devices, such as laptops, digital audio players, digital cameras, mobile phones, video game consoles, scientific instruments, industrial robots, medical electronic devices, solid-state drives, automotive electronic devices, Internet of Things (IOT) devices, universal serial bus (USB) devices, and the like. Semiconductor memories include both non-volatile memories and volatile memories. Non-volatile memory retains stored information without requiring an external power supply. Examples of non-volatile memory include flash memory (e.g., NAND-type and NOR-type flash memory) and Electrically Erasable Programmable Read-Only Memory (EEPROM).

[0003] A memory device can be coupled to one or more hosts, and one or more interfaces are used to access the memory device. In addition, memory devices are often managed by a controller, and among several roles, the controller is configured to interface between the host and the memory device.

[0004] To improve performance, some memory devices use various techniques to limit verify iterations for a particular data state during programming. However, although such techniques can reduce programming time, several adverse effects may occur. Accordingly, there is a need for improved non-volatile memory devices and methods of operation. Summary of the Invention

[0005] This section provides a general overview of this disclosure and does not constitute a comprehensive disclosure of its entirety or all of its features and benefits.

[0006] The object of this disclosure is to provide a memory device and a method for operating the memory device that address and overcome the shortcomings described herein.

[0007] Accordingly, one aspect of the present disclosure is to provide a memory device including memory cells, each connected to one of a plurality of word lines and configured to hold a threshold voltage corresponding to one of a plurality of data states. The plurality of data states include the highest data state in which the threshold voltage of the memory cell associated with the data state is higher than that of the other data states among the plurality of data states. The memory device also includes control means configured to apply to a selected word line of the plurality of word lines each of a set of programming pulses of a program voltage and a set of verification pulses of a plurality of program verification voltages, each associated with one of the plurality of data states, following the set of programming pulses. Thus, the memory cells connected to the selected word lines of the plurality of word lines are programmed and verified during each of a plurality of program loops of program operation. The control means is also configured to skip verification of the memory cell corresponding to the highest data state in at least one of the plurality of program loops.

[0008] In another aspect of the present disclosure, a controller is also provided that communicates with a memory device, each containing memory cells, each connected to one of a plurality of word lines. The memory cells are configured to hold a threshold voltage corresponding to one of a plurality of data states. The plurality of data states include the highest data state in which the threshold voltage of the memory cell associated with the data state is higher than that of the other data states among the plurality of data states. The controller is configured to instruct the memory device to apply each of a set of programming pulses of a program voltage, followed by a set of verification pulses of a plurality of program verification voltages, each associated to one of the plurality of data states, to a selected word line among the plurality of word lines. Thus, the selected word line among the plurality of word lines Word lines The connected memory cells are programmed and verified during each of the multiple program loops of the program operation. The controller is also configured to instruct the memory device to skip the verification of the memory cell that is subject to the highest data state in at least one of the multiple program loops.

[0009] An additional aspect of this disclosure provides a method for operating a memory device. The memory device includes memory cells, each connected to one of a plurality of word lines. The memory cells are configured to hold a threshold voltage corresponding to one of a plurality of data states. The plurality of data states include the highest data state in which the threshold voltage of the memory cell associated with the data state is higher than that of the other data states among the plurality of data states. The method includes the step of programming and verifying memory cells connected to word lines by applying each of a set of programming pulses of a program voltage and verification pulses of a plurality of program verification voltages, each associated with one of the plurality of data states, to a selected word line among the plurality of word lines during each of a plurality of program loops of program operation. The method also includes the step of skipping verification of a memory cell that is subject to the highest data state in at least one of the plurality of program loops.

[0010] Further areas of applicability will become apparent from the descriptions provided herein. The descriptions and specific examples in this summary are intended for illustrative purposes only and are not intended to limit the scope of this disclosure. [Brief explanation of the drawing]

[0011] The drawings described herein are for illustrative purposes only of selected embodiments and do not represent all possible implementations, nor are they intended to limit the scope of this disclosure. [Figure 1A] This is a top view of one embodiment of a NAND string according to an aspect of the present disclosure. [Figure 1B] This is an equivalent circuit diagram of a NAND string according to an aspect of the present disclosure. [Figure 2] This disclosure describes a non-volatile storage device which may include one or more memory dies or chips, according to an aspect of this disclosure. [Figure 3] This is a block diagram showing one embodiment of a sense block according to the present disclosure. [Figure 4] A block of NAND flash memory cells in the memory array of Figure 2, according to an aspect of this disclosure, is shown. [Figure 5] An exemplary set of threshold voltage distributions for an 8-state memory device in which each memory element stores 3 bits of data is shown according to aspects of this disclosure. [Figure 6] This disclosure demonstrates that the Vt distributions may partially overlap depending on the aspect of this disclosure. [Figure 7] This is a flowchart illustrating one embodiment of a programming process including one or more verification steps according to the aspects of this disclosure. [Figure 8] This document demonstrates the program verification operation according to the aspects of this disclosure. [Figure 9A] This disclosure describes a program verification operation that does not detect a bit count exceeding a threshold. [Figure 9B]This disclosure describes a program verification operation that detects a bit count exceeding a threshold. [Figure 10A] The voltage levels in a program verification iteration according to the aspects of this disclosure are shown. [Figure 10B] The voltage levels in a program verification iteration according to the aspects of this disclosure are shown. [Figure 10C] The voltage levels in a program verification iteration according to the aspects of this disclosure are shown. [Figure 11] This is a flowchart of one embodiment of a process for operating a data latch while programming and verifying non-volatile storage, according to an aspect of the present disclosure. [Figure 12] This is a flowchart of one embodiment of a process for operating a data latch while programming and verifying non-volatile storage, according to an aspect of the present disclosure. [Figure 13A] This is a table showing the status of the data latch across various stages of the process in Figure 12, according to the aspects of this disclosure. [Figure 13B] This is a table showing the status of the data latch across various stages of the process in Figure 12, according to the aspects of this disclosure. [Figure 13C] This is a table showing the status of the data latch across various stages of the process in Figure 12, according to the aspects of this disclosure. [Figure 13D] This is a table showing the status of the data latch across various stages of the process in Figure 12, according to the aspects of this disclosure. [Figure 14] This disclosure illustrates the use of latches between various stages of one embodiment of programming. [Figure 15] This table shows the number of program loops and verification iterations for each data state in the program operation for a ternary cell according to the embodiments of this disclosure, along with the time duration included in each program loop. [Figure 16] This is a plot of the threshold voltage distribution when program verification of the highest data state is completely skipped, according to an aspect of this disclosure. [Figure 17A]It is a table showing information stored in a first data latch, a second data latch, a third data latch, and a fourth data latch for each data state of a ternary memory cell according to an aspect of the present disclosure. [Figure 17B] It is a table showing unused bit combinations among bit combinations of bits in a first data latch, a second data latch, a third data latch, and a fourth data latch according to an aspect of the present disclosure. [Figure 18] It is a diagram showing exemplary tracking of a memory cell targeted for the highest data state through a subsequent program loop among a plurality of program loops using two unused bit combinations for Option 1 according to an aspect of the present disclosure. [Figure 19] It is another table showing information stored in a first data latch, a second data latch, a third data latch, and a fourth data latch for each data state for Option 1 according to an aspect of the present disclosure. [Figure 20] It is a table showing the impact on cache flush according to an aspect of the present disclosure. [Figure 21] It is a summary of variations in parameters that affect the operation of a memory device using Option 1 according to an aspect of the present disclosure. [Figure 22] It shows an exemplary sequence of program loops for Option 2 according to an aspect of the present disclosure. [Figure 23] It is a plot of threshold voltage distribution when program verification for the highest data state is skipped after completion of the next highest data state, and a counter is used to track program loops for slow cells targeted for the highest data state according to an aspect of the present disclosure. [Figure 24] It is a diagram showing exemplary tracking of a memory cell along with a corresponding plot of threshold voltage distribution for Option 3 according to an aspect of the present disclosure. [Figure 25] It shows simulation results for Options 1, 2, and 3 compared to no skipping of program verification for the highest data state according to an aspect of the present disclosure. [Figure 26] This is a comparison of the highest data state, option 1, option 2, and option 3 without skipping program verification, as described in this disclosure. [Figure 27A] This is a table showing information stored in the first data latch, second data latch, third data latch, and different fourth and fifth data latches for each data state of a quaternary memory cell, according to the aspects of this disclosure. [Figure 27B] This is a table showing unused bit combinations of bits in the first data latch, the second data latch, the third data latch, and different fourth and fifth data latches, according to the aspects of this disclosure. [Figure 28] Steps of a method for operating a memory device according to an aspect of this disclosure are shown.

[0012] For ease of understanding, the same reference numerals are used to indicate identical elements common to the drawings, where possible. Elements disclosed in one embodiment are intended to be usefully utilized in other embodiments without specific description. [Modes for carrying out the invention]

[0013] The following description provides details to help you understand this disclosure. In some cases, certain circuits, structures, and techniques are not described or shown in detail in order to avoid obscuring this disclosure.

[0014] Generally, this disclosure relates to a type of non-volatile memory device well suited for use in many applications. The non-volatile memory devices and associated operating methods of this disclosure are described in conjunction with one or more exemplary embodiments. However, the specific exemplary embodiments disclosed are provided only to illustrate the concepts, features, advantages, and objectives of the invention with sufficient clarity to enable a person skilled in the art to understand and implement this disclosure. Specifically, the exemplary embodiments are provided to complete this disclosure and to fully convey its scope to a person skilled in the art. Numerous specific details, such as examples of specific components, devices, and methods, are described in order to provide a complete understanding of the embodiments of this disclosure. It will be apparent to a person skilled in the art that specific details are not required to be adopted, that the exemplary embodiments may be embodied in many different forms, and that none should be construed as limiting the scope of this disclosure. In some exemplary embodiments, well-known processes, well-known device structures, and well-known techniques are not described in detail.

[0015] In some memory devices or apparatus, memory cells are joined to one another in the form of NAND strings within a block or subblock. Each NAND string comprises several memory cells connected in series between one or more drain-side selected gate SG transistors (SGD transistors) on the drain side of the NAND string connected to bit lines and one or more source-side selected gate SG transistors (SGS transistors) on the source side of the NAND string connected to source lines. Furthermore, the memory cells may be arranged with common control gate lines (e.g., word lines) that function as control gates. A set of word lines extends from the source side of the block to the drain side of the block. Memory cells may also be connected in other types of strings and in other ways.

[0016] In a 3D memory structure, memory cells may be arranged in vertical strings forming a stack, the stack comprising alternating conductive and dielectric layers. The conductive layers function as word lines connecting to the memory cells. The memory cells may include data memory cells that are qualified to store user data and dummy or non-data memory cells that are not qualified to store user data.

[0017] Before programming a particular non-volatile memory device, the memory cells are typically erased. In some devices, the erase operation removes electrons from the floating gate of the memory cell being erased, or from the charge trap layer.

[0018] Programming a set of memory cells typically involves applying a series of program voltages to the memory cells after they have been provided in an erased state. Each program voltage is applied in a program loop, also known as a program verification iteration. For example, the program voltage may be applied to a word line connected to the control gate of the memory cell. One technique involves incremental step pulse programming (step-up pulse writing), where the program voltage is increased by a step size in each program loop. A verification operation may be performed after each program voltage to determine whether the memory cell has completed programming. Once programming is complete for a memory cell, it may be locked out of further programming while programming continues for other memory cells in subsequent program loops.

[0019] Each memory cell can be associated with a data state according to the data written in a program command. Based on the data state of the memory cell, it can either remain in the erased state or be programmed to a different data state (a programmed data state). For example, a 2-bit memory device has four data states, including the erased state and three high-level data states called A, B, and C data states. A 3-bit memory device has eight data states, including the erased state and seven high-level data states called A, B, C, D, E, F, and G data states (see Figures 5 and 6). A 4-bit memory device has sixteen data states, including the erased state and fifteen high-level data states called Er or S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, and S15 data states.

[0020] When a program command is issued, the data to be written is stored in a latch associated with the memory cell. During programming, the latch of the memory cell can be read to determine the data state in which the cell should be programmed. Each programmed data state is associated with a verification voltage, and if the detection operation determines that the threshold voltage (Vth) of the detection operation is above the associated verification voltage, the memory cell with a given data state is considered to have completed programming. The detection operation can determine whether a memory cell has a Vth above the associated verification voltage by applying the associated verification voltage to the control gate and detecting the current flowing through the memory cell. A relatively high current indicates that the memory cell is in a conducting state, where Vth is below the control gate voltage. A relatively low current indicates that the memory cell is in a non-conducting state, where Vth is above the control gate voltage.

[0021] The verification voltage used to determine that a memory cell has completed programming may be called the final or lockout verification voltage. In some cases, an additional verification voltage may be used to determine that a memory cell is close to completing programming. For example, in Figures 5 and 6, a memory cell to be programmed to the A data state can be subjected to a verification test at VvA, which is the verification voltage for the A data state. To improve programming time, some later data states may not be verified until certain earlier data states have finished programming. Nevertheless, a considerable amount of programming time is consumed because all data states are verified.

[0022] Figure 1A is a top view showing one NAND string 90. Figure 1B is the equivalent circuit of the NAND string 90. The shown NAND string includes four transistors 100, 102, 104, and 106 in series, sandwiched between a first selection gate 120 and a second selection gate 122. Selection gate 120 connects the NAND string to the bit line 126. Selection gate 122 connects the NAND string to the source line 128. Selection gates 120 and 122 are controlled by applying appropriate voltages to control gates 120CG and 122CG, respectively. Each of transistors 100, 102, 104, and 106 has a control gate and a floating gate. Transistor 100 has a control gate 100CG and a floating gate 100FG. Transistor 102 includes a control gate 102CG and a floating gate 102FG. Transistor 104 includes a control gate 104CG and a floating gate 104FG. Transistor 106 includes a control gate 106CG and a floating gate 106FG. Control gates 100CG, 102CG, 104CG, and 106CG are connected to word lines WL3, WL2, WL1, and WL0, respectively. In one embodiment, transistors 100, 102, 104, and 106 are each memory cells. In other embodiments, the memory cells may include multiple transistors or may differ from the memory cells shown. Selection gates 120 and 122 are connected to the drain-side selection line SGD and the source-side selection line SGS, respectively. In addition to NAND flash memory, other types of non-volatile memory may also be used.

[0023] Figure 2 shows a non-volatile storage device 210 which may include one or more memory dies or chips 212. The memory die 212 includes an array of memory cells 200 (two-dimensional or three-dimensional), a control circuit 220, and read / write circuits 230A and 230B. In one embodiment, access to the memory array 200 by various peripheral circuits is implemented symmetrically on both sides of the array, resulting in a halving of the density of access lines and circuits on each side. The read / write circuits 230A and 230B include a plurality of sense blocks 300 which enable pages of memory cells to be read or programmed in parallel. The memory array 200 is addressable by word lines via row decoders 240A and 240B and by bit lines via column decoders 242A and 242B. In a typical embodiment, a controller 244 is included in the same memory device 210 (e.g., a removable storage card or package) as one or more memory dies 212. Commands and data are transferred between the host and the controller 244 via line 232, and between the controller and one or more memory dies 212 via line 234. One implementation configuration may include multiple chips 212.

[0024] The control circuit 220 works in cooperation with the read / write circuits 230A and 230B to perform memory operations on the memory array 200. The control circuit 220 includes a state machine 222, an on-chip address decoder 224, and a power control module 226. The state machine 222 provides chip-level control of memory operations. The on-chip address decoder 224 provides an address interface for translating between addresses used by the host or memory controller and hardware addresses used by decoders 240A, 240B, 242A, and 242B. The power control module 226 controls the power and voltage supplied to the word lines and bit lines during memory operations. In one embodiment, the power control module 226 includes one or more charge pumps capable of generating a voltage greater than the supply voltage.

[0025] In one embodiment, one or any combination of the control circuit 220, power control circuit 226, decoder circuit 224, state machine circuit 222, decoder circuit 242A, decoder circuit 242B, decoder circuit 240A, decoder circuit 240B, read / write circuit 230A, read / write circuit 230B, and / or controller 244 may be referred to as one or more control circuits.

[0026] Figure 3 is a block diagram showing one embodiment of a sense block 300. Each sense block 300 is divided into a core portion called a sense module 380 and a common portion 390. In one embodiment, there is a separate sense module 380 for each bit line and one common portion 390 for a set of multiple sense modules 380. In one example, the sense block 300 includes one common portion 390 and eight sense modules 380. Each of the sense modules in the group communicates with its associated common portion via a data bus 372.

[0027] The sense module 380 includes a sense circuit 370 that determines whether the conducted current in the connected bit line is above or below a predetermined threshold level. The sense module 380 also includes a bit line latch 382 used to set a voltage condition for the connected bit line. For example, a predetermined state latched to the bit line latch 382 results in the connected bit line being pulled to a state that specifies program disable (e.g., 1.5 to 3V). As an example, flag = 0 can disable programming, and flag = 1 does not disable programming.

[0028] The common section 390 comprises a processor 392, a set of five exemplary data latches 394, and an I / O interface 398 coupled between the set of data latches 394 and the data bus 320. One set of data latches may be provided to each sense module, and five data latches identified by ADL, BDL, CDL, DDL, and XDL may be provided to each set. The use of data latches will be further described below.

[0029] The processor 392 performs calculations. For example, one of the functions of the processor 392 is to determine the data stored in the sensed memory element and store the determined data in a set of data latches. At least some of the data latches in the set of data latches (e.g., 394) are used to store the data bits determined by the processor 392 during a read operation. At least some of the data latches in the set of data latches are also used to store data bits imported from the data bus 320 during a program operation. The imported data bits represent the write data that is to be programmed into memory. The I / O interface 398 provides an interface between the data latches 394-397 and the data bus 320.

[0030] In one embodiment, the user can stream data to be programmed into a memory element to an XDL latch. This programmed data may be transferred to the ADL, BDL, and CDL latches at the start of the programmed operation. Note that this describes programming 3 bits per memory cell. In one embodiment, during a read operation, the ADL, BDL, and CDL latches are used to store the 3 bits read from the memory cell. In one embodiment, the user can toggle the output of the read data via the XDL latch.

[0031] In one embodiment, the user has access to the XDL latch but not to the ADL, BDL, or CDL latch. For example, the user may have access to the XDL latch to perform background caching during program execution. Background caching will be described in more detail below. In one embodiment, the user's access to the XDL is restricted during program execution. For example, the user may be able to stream program data to the XDL latch before programming. However, the user may not have access to the XDL latch during one embodiment of programming. In one embodiment, the XDL latch is used to store "lockout data" for memory cells during program execution. Briefly, the lockout data may indicate that the memory element is locked out from further programming. Further details will be described below.

[0032] During read operations or other detections, the state machine 222 controls the supply of different control gate voltages to the addressed memory element. Since the sense module 380 steps across various control gate voltages corresponding to various memory states supported by the memory, the sense module 380 may trip at one of these voltages, and an output is provided from the sense module 380 to the processor 392 via the bus 372. At that point, the processor 392 determines the resulting memory state by considering the sense module trip event and information about the control gate voltage applied from the state machine via the input line 393. The processor 392 then computes a binary encoding of the memory state and stores the resulting data bits in a data latch (e.g., 394). In another embodiment of the core portion, the bit line latch 382 serves both as a latch for latching the output of the sense module 380 and as a bit line latch as described above.

[0033] Several implementations may include multiple processors 392. In one embodiment, each processor 392 includes an output line (not shown), each of which is connected to a wired OR. In some embodiments, the output lines are inverted before being connected to the wired OR line. This configuration allows a state machine receiving the wired OR to determine when all programmed bits have reached the desired level, thus enabling a quick determination of when the programming process is complete during the program verification process. For example, when each bit reaches the desired level, a logic 0 for that bit is sent to the wired OR line (or inverts the data 1). When all bits output data 0 (or inverted data 1), the state machine knows that the programming process is complete. Since each processor communicates with eight sense modules, logic is added to processor 192 for accumulating the results of the associated bit lines so that the state machine either needs to read the wired OR line eight times or read the wired OR line only once. Similarly, by accurately selecting the logic level, the global state machine can detect when a first bit changes the state of another first bit and modify the algorithm accordingly.

[0034] During programming or verification, the data to be programmed is stored in a set of data latches 394-397 from the data bus 320. Programming under the control of the state machine involves a series of programming voltage pulses applied to the control gate of an addressed memory element. Each program pulse is followed by a readback (verification) to determine whether the memory element has been programmed to the desired memory state. The processor 392 monitors the readback memory state for the desired memory state. If the two match, the processor 392 sets the bit line latch 382 to pull the bit line to a state that specifies program prohibited. This prevents further programming of the memory element coupled to the bit line, even if a program pulse appears at the control gate of the memory element. In other embodiments, the processor initially loads the bit line latch 382, ​​and the sense circuit sets the bit line latch 382 to the prohibited value during the verification process.

[0035] Each set 394-397 of the data latch stack, in one embodiment, contains a stack of data latches corresponding to a sense module 380. In one embodiment, there are five data latches for each sense module 380. The ADL, BDL, and CDL data latches may be implemented as shift registers such that parallel data stored in these data latches is converted to serial data in the XDL latch for transfer over the data bus 320, and vice versa. All ADL, BDL, and CDL data latches corresponding to read / write blocks of m memory elements can be joined together to form a block shift register such that blocks of data can be input or output by serial transfer. In particular, banks of read / write modules may be adapted so that each set of ADL, BDL, and CDL data latches in the bank sequentially shifts data to or from the XDL latch, as if these data latches were part of a shift register for the entire read / write block.

[0036] In one embodiment, one purpose of the ADL, BDL, and CDL latches is to store data to be programmed into the memory element. For example, a memory element may store 3 bits per element. In one embodiment, a memory element stores 4 bits per element. In this case, there may be an additional data latch (not shown in Figure 3) for storing a fourth bit of the data to be programmed into the memory element. In one embodiment, a memory element stores only 2 bits per element, in which case one of the ADL, BDL, and CDL latches is not required. A memory element can store 5 bits or more per element, in which case there may be one data latch for each bit.

[0037] In one embodiment, the ADL, BDL, and CDL latches may also be used to store status information during programming. For example, after a memory element reaches its target threshold voltage, each latch (ADL, BDL, CDL) can be set to "1" to indicate that programming for that memory element is complete. In one embodiment, the latches are used differently as programming progresses to different stages. In one embodiment, the ADL latch is released during programming. In one embodiment, the BDL latch is also released during programming. Further details will be described in relation to Figures 12, 13A–13D, and 14, and elsewhere.

[0038] In one embodiment, a DDL latch is used to store status information during programming. In one embodiment, programming slows down as the memory element approaches a target threshold level. For example, the DDL latch may identify that the Vth of a memory element is above a low-level verification level (e.g., VvaL or VvbL in Figure 5). If the memory element is not yet locked out, it may receive slower programming. If the DDL latch indicates that the Vth of a memory element is below a low-level verification level, the memory element may be in fast programming mode. Further details are described below.

[0039] In one embodiment, the XDL latch is used to store status information during programming. After data from the XDL latch is shifted into the ADL, BDL, and CDL data latches, the XDL latch may be set to an initial state (e.g., "0"). After the memory cell reaches its target threshold voltage, the XDL latch may be set to another state (e.g., "1"). Thus, the XDL latch may store a "lockout status". Therefore, program data in the ADL, BDL, and CDL latches can be stored both during and after program operation. Further details are described below.

[0040] Figure 4 shows a block of NAND flash memory cells in the memory array 200 of Figure 2. The memory array can contain many blocks 400. Two exemplary blocks 400 are shown in Figure 4. Each block 400 contains several NAND strings. A set of bit lines, e.g., BL0, BL1, ..., may be shared between blocks. Thus, each NAND string is associated with one bit line. Each NAND string is connected at one end to a drain selection gate (SGD), and the control gate of the drain selection gate is connected via a common SGD line. The other end of the NAND string is connected to a source selection gate, which is connected to a common source line 420. Sixty-four word lines, e.g., WL0 to WL63, extend between the source selection gate and the drain selection gate.

[0041] In addition to NAND flash memory, other types of non-volatile memory can also be used. For example, another type of memory cell effective in flash EEPROM systems utilizes a non-conductive dielectric material instead of a conductive floating gate to store charge in a non-volatile manner. A triple-layer dielectric formed of silicon oxide, silicon nitride, and silicon oxide ("ONO") is sandwiched between a conductive control gate and the surface of a semiconductor substrate above the memory cell channel. The cell is programmed by injecting electrons from the cell channel into the nitride, where the electrons are trapped and stored in a restricted region. This stored charge then causes a detectable change in the threshold voltage of a portion of the cell's channel. The cell is erased by injecting hot holes into the nitride. A similar cell can be provided in a split-gate configuration in which a doped polysilicon gate extends over a portion of the memory cell channel to form a separate select transistor.

[0042] Another approach uses NROM cells. For example, two bits are stored in each NROM cell, in which an ONO dielectric layer extends across a channel between the source diffusion region and the drain diffusion region. The charge of one data bit is localized in the dielectric layer adjacent to the drain, and the charge of the other data bit is localized in the dielectric layer adjacent to the source. Multi-state data storage is obtained by separately reading the binary states of spatially separated charge storage regions within the dielectric. Other types of non-volatile memory are also known.

[0043] It should be noted that there can be thousands or even tens of thousands of bit lines. Therefore, a single word line may be used by tens of thousands of memory elements. Typically, a driver is located at one end of the word line, providing a read reference voltage or programming voltage.

[0044] Figure 5 shows an exemplary set of threshold voltage distributions for an 8-state memory device in which each memory element stores 3 bits of data. A first threshold voltage (Vth) distribution is provided for an erased (Er state) memory element. The seven Vth distributions represent programmed states A through G. In one embodiment, the threshold voltage in the Er state is negative, and the threshold voltages in the A through G distributions are positive. However, all or part of the threshold distribution in the Er state may be positive. Also, all or part of the threshold distribution in state A may be negative (and so on for other data states).

[0045] Read reference voltages Vra, Vrb, Vrc, etc., are also provided for reading data from the memory element. By testing whether the threshold voltage of a given memory element is above or below Vra, Vrb, Vrc, etc., the system can determine the state of the memory element, such as the programming condition.

[0046] Furthermore, verification reference voltages such as Vva, Vvb, and Vvc are provided. When programming memory elements to states A, B, C, etc., the system tests whether those memory elements have threshold voltages above Vva, Vvb, Vvc, etc.

[0047] In one embodiment known as full-sequence programming, memory elements can be programmed directly from the Er state to one of the programmed states A through G. For example, a group of memory elements to be programmed can be first erased so that all memory elements in the group are in the Er state. Then, a series of program pulses are used to program the memory elements to their respective target states A through G. Some memory elements may be programmed from the Er state to state A, while others may be programmed from the Er state to state B, and so on.

[0048] Figure 5 also shows verification low reference voltages VvAL, VvBL, VvCL, etc. These reference voltages can be used during program verification to determine whether a memory element is close to its intended target threshold. If so, the programming speed can be slowed down. In one embodiment, Vdd is applied to a bit line that has reached the target state and for which further programming is prohibited. Bit lines of memory elements that remain below the verification low level may be grounded to enable high-speed programming. However, when between the verification low level and the normal verification level, the bit line may receive an intermediate voltage (e.g., between ground and Vdd) to induce low-speed or medium-speed programming. As an example, the intermediate voltage may be about 0.6V to 0.8V. However, the intermediate voltage may be either below or above this range. In one embodiment, a DDL latch indicates where the memory element is in this programming sequence. Further details are described below. In one embodiment, a memory element programmed to the G state does not receive low-speed (or medium-speed) programming. Therefore, the verification low reference voltage is not shown in Figure 5 for the G state. However, if desired, a VvGL for the G state may be provided.

[0049] In one embodiment, multiple paths may be used to program the memory element. For example, one path may be used to program each bit. Thus, if three bits are stored per memory cell, there may be three paths. If two bits are stored per memory cell, there may be two paths. In one embodiment, a multi-state memory element stores data for three different pages: a lower page, a middle page, and an upper page. The eight states and the bits they represent may be: Er state (111), A state (011), B state (101), C state (001), D state (110), E state (010), F state (100), and G state (000). For the Er state, all pages store "1". For the A state, the lower page stores "0", the middle page stores "1", and the upper page stores "1". Other states can be similarly inferred. Note that a specific bit pattern is assigned to each state, but different bit patterns may be assigned. Furthermore, it should be noted that this bit and page allocation may also be used in other programming sequences, such as the fast / slow programming described above.

[0050] In the first programming pass of one embodiment, a lower page is programmed for the selected word line WLn. If the lower page remains data 1, the state of the memory element remains erased. If the data is programmed to 0, the threshold voltage of the memory element on WLn rises so that the memory element is programmed into an intermediate state. This intermediate state may have a lower tail just below VvD. In the second programming pass of one embodiment, a middle page is programmed for the selected word line WLn. As a result, two or more threshold voltage distributions are created (one added to each of the previous distributions). In the third programming pass of one embodiment, a higher page is programmed for the selected word line WLn. As a result, four or more threshold voltage distributions are generated (one added to each of the previous four distributions).

[0051] The programming example shows eight data states and three pages of data, but the concepts taught can be applied to other implementations having more or fewer than eight states and more or fewer than three pages. Furthermore, in the exemplary programming technique described, the Vth of the memory element gradually increases as it is programmed to the target data state. However, a programming technique can be used in which the Vth of the memory element gradually decreases as it is programmed to the target data state. Programming techniques that measure the memory element current can also be used. The concepts herein can be adapted to different programming techniques.

[0052] Figure 6 shows that the Vt distribution may partially overlap because the error correction algorithm can handle a specific percentage of erroneous cells. In some embodiments, at one point in time, the threshold voltage distribution may resemble that in Figure 5, and at another point in time, the threshold voltage distribution may overlap, as shown in Figure 6. For example, immediately after programming, the threshold voltage distribution may resemble that in Figure 5. However, over time, the threshold voltages of the memory cells may shift so that overlap is possible.

[0053] However, immediately after programming, there may be overlaps between at least some adjacent threshold distributions. Note that if there are overlaps between adjacent Vt thresholds, detecting word line defects can be extremely difficult.

[0054] Furthermore, it should be noted that, in contrast to the equal spacing / width of the threshold voltage distribution shown, various distributions may have different widths / spacing to accommodate the varying sensitivity of the data retention loss.

[0055] Figure 7 is a flowchart illustrating one embodiment of a programming process that includes one or more verification steps. In step 810, the program voltage (Vpgm) is set to an initial value. Also, in step 710, the program counter (PC) is initialized to 0. In step 720, a program pulse is applied.

[0056] In step 722, the verification process is performed. In one embodiment, the verification is a simultaneous coarse / fine verification. Referring to Figure 5, some memory cells programmed to state A are verified for the VvaL level, while other memory cells programmed to state A are verified for the Vva level. Coarse programming is applied during the initial programming step when the threshold voltage of the memory cell is well below the final level (Vva). However, after the threshold voltage of the memory cell reaches VvaL, fine programming is used. Thus, some memory cells are verified for coarse programming, while others are verified for fine programming. Note that with coarse / fine programming, some memory cells are verified for one state (e.g., state A), while others are verified for another state (e.g., state B). Note that once a particular memory cell is verified to be programmed to its intended state, it may be locked out from further programming.

[0057] However, it should be noted that if there is a break in the programmed selected word line, the verification may produce incorrect results. As mentioned above, a break in the word line may result in the memory element on the far side of the break receiving a lower reference voltage than intended. For example, a memory element intended to be programmed into the G state should receive a reference voltage VvG (see Figure 5) at the control gate of the memory element. However, the memory element may actually receive a lower voltage due to the break. Under normal circumstances, if the memory element has not yet reached its target state (e.g., the actual Vt of the memory element is less than the reference voltage), the memory element will turn on in response to the verification voltage. On the other hand, if the memory element has reached its target state (e.g., the actual Vt of the memory element is greater than or equal to the reference voltage), the memory element should not turn on. For example, consider the case where a memory element is subject to the G state. This memory element is verified by applying VvG to the selected word line. If its actual Vt is less than VvG, it conducts current. After the actual Vt of the memory element exceeds VvG, the memory element no longer turns on, indicating that the memory element has reached its target state.

[0058] However, a memory element that has passed the break point may not turn on if its actual Vt is less than the target Vt, because it receives an excessively low verification voltage. A memory element that has passed the break point may encounter a lower verification voltage than intended. For example, a memory element subject to the G state should encounter a verification voltage of VvG, but may encounter a lower voltage at the control gate of the memory element. In one specific example, a memory element that has passed the break point may encounter only a verification voltage of VvF. Therefore, in this particular example, it will pass the verification test if its actual Vt is greater than VvF. In general, a memory element that has passed the break point may pass the verification test if its actual threshold voltage is less than VvG. Therefore, programming will stop for that memory element. However, it may not actually be programmed.

[0059] In step 724, it is determined whether all memory cells have verified that the threshold voltage of each memory cell is at the final target voltage of that memory cell. If so, the programming process completes successfully in step 726 (status=pass). If not all memory cells have been verified, it is determined whether the program counter (PC) is less than a maximum value, such as 20. If the program counter (PC) is greater than or equal to max (step 728), the programming process has failed (step 730). If the program counter (PC) is less than a maximum value (e.g., 20), in step 832, the program counter (PC) is incremented by 1 and the program voltage is stepped up to the next pulse. Following step 732, the process loops back to step 720, and the next program pulse is applied to the memory cell.

[0060] Figure 8 shows the threshold voltage (Vt) distribution during program operation, examining the first memory state, shown here as state B, and the second memory state, shown here as state C. While states B and C are used to illustrate this concept, it will be recognized that similar principles can be applied to other consecutive states. The horizontal axis represents voltage.

[0061] In NAND memory, the logical value stored in a memory cell is determined by the voltage window in which the cell's Vt exists. Vt is the voltage stored in the cell after the program pulse. As cell size decreases and more bits are stored per cell, the threshold voltage window used to represent each value becomes smaller, leading to an increased error rate in determining the cell's value. This is because process variability becomes more prevalent as the amount of charge stored in the flash cell decreases with feature size, leading to significantly different Vt values ​​for different cells storing the same value. Therefore, determining which logical value a cell's threshold voltage corresponds to is necessary for reliability, but it is becoming increasingly difficult.

[0062] After each program pulse is applied to a memory cell, the memory operation performs a verification step that can detect the voltage distribution stored in the memory cell. Each memory state (e.g., states A-G) has its own Vt, which increases with each successive state. The Vt distribution 801 results from the first program pulse applied to the memory cell and shows the number of bit scan counts of the memory cell as a function of voltage. The upper tail of the distribution 801 contains several scanned bits (memory cells) that exceed the voltage verification level of state B. This is represented in region 803 to the right of the voltage verification level of state B. If the bit scan in region 803 does not exceed the threshold, the memory system applies the next program pulse resulting in distribution 805. If the bit scan count in region 803 meets or exceeds the threshold, the memory system triggers a program verification pulse for state C, resulting in bit scan distribution 805. Prior to the trigger, some program verification counts are saved for state C, and no prior program verification, known as smart skip program verification, is applied. This subsequent program pulse and verification results in a distribution 807 that exceeds distribution 805 (at a higher voltage). In an exemplary embodiment, when the Vt distribution is in a particular memory cell state, e.g., states A through F, the verification process can trigger verification at the next voltage level in the same verification process without triggering the next program pulse. In an exemplary embodiment, the verification process counts the bits to the right of Vt in state B and triggers verification for state C, which occurs in the same verification loop, by detecting bits that exceed Vt in state B.

[0063] During a program verification operation in memory, one exemplary embodiment typically performs program verification of all states, e.g., states A through G, in accordance with a set scheme. See, for example, Figure 10A of U.S. Patent No. 10,014,063, which is incorporated herein by reference in its entirety. In some practical applications, performing verification of states C through G after the first program pulse may be a waste of time and resources. Therefore, smart skip program verification detects when the upper tail of a lower state (e.g., state A or B) exceeds a certain threshold and triggers program verification for the next higher state before initiating the next program / verification loop. This reduces unnecessary program / verification loops for higher states in subsequent program loops. To trigger the next state verification, the methodology triggers the next state verification after the next program pulse when, during program operation, there is a predetermined bit count in the memory circuitry and the bit scan result indicates that the upper tail has a higher bit count (or reaches the threshold) compared to a stored threshold.

[0064] The smart skip program verification operation detects the upper tail of the "n" state and determines whether to verify the triggering n+1 state based on a threshold. The threshold can be set based on statistical analysis of the memory device. If it is desirable to determine when to skip from the current state (n) being verified to the next state (n+1), even using a minimum voltage increase of the programming voltage, any early program verification on the next loop (n+1 loop) instead of the current loop (n) can lead to overprogramming.

[0065] Figure 9A shows Figure 900, which includes the threshold voltage distribution 901 from the verification operation, i.e., the bit scan count. This is used to verify the programmed bit values ​​stored in the addressed memory cell at state verification level 903. The region 905 (upper tail of verification pulse 901), to the right of the voltage level and below the curve of verification pulse 901, is the bit scan count (i.e., the count of memory cells whose voltage exceeds the state voltage level). Region 905 does not show a sufficient count to exceed the threshold and trigger a skip to the next state level in the same verification iteration.

[0066] Figure 9B shows a diagram including the threshold voltage distribution 910 from the verification operation, i.e., the bit scan count. This is used to verify the programmed bit value stored in the addressed memory cell at state level 903. The region 915 to the right of the voltage level and below the curve of the verification pulse 910 (e.g., the upper tail of the distribution 910) is the bit scan count (i.e., the number of memory cells whose voltage exceeds the state voltage level). Region 905 shows the count that exceeds the threshold and is sufficient to trigger a programmed verification to the next state level in the same verification iteration. In an exemplary embodiment, the method triggers the verification before applying the next programmed pulse.

[0067] Figure 10A shows a program verification operation 1000A with two program verification iterations. Operation 1000A is a partial example of a memory cell programming operation for a multi-state memory device having an erase state (Er) and three programmed memory states (e.g., A, B, C). The horizontal axis represents time. The vertical axis represents the control gate voltage or word line voltage. Generally, a programming operation may involve applying a pulse train to a selected word line, and the pulse train may consist of multiple program loops or program verification iterations. The program portion of a program verification iteration includes a Vpgm pulse (voltage pulse 1003 or 1004), and the verification portion of a program verification iteration includes one or more verification pulses (e.g., voltage pulses 1007, 1008, or voltage pulses 1010, 1011).

[0068] For each Vpgm pulse 1003, 1004, a square waveform is shown for simplification, but other shapes such as multi-level or ramp shapes are also possible. Furthermore, in this example, step-up pulse programming (ISPP) is used, and the Vpgm pulse amplitude steps up in each continuous program loop, shown as a voltage increase 1005. This example uses ISPP in a single programming pass where programming is completed. ISPP can also be used in each programming pass of multipath operation.

[0069] A pulse train typically includes Vpgm pulses whose amplitude increases incrementally in each program verification iteration, using a fixed or variable step size, e.g., voltage step 1005. A new pulse train begins at an initial Vpgm pulse level (e.g., for level A) and ends at a final Vpgm pulse level (e.g., level G for a 3-bit multi-level memory) that does not exceed the maximum allowable level.

[0070] Operation 1000A includes a series of Vpgm pulses 1003, 1004 applied to a selected word line for programming, and an associated set of non-volatile memory cells. Based on the target memory state being verified, one, two, or three verification voltage pulses are provided, for example, after each Vpgm pulse. A voltage of 0V (indicated here by 1015) may be applied to the selected word line between the Vpgm pulses 1003, 1004 and the verification voltage pulses 1007, 1008, and 1010, 1011.

[0071] In one embodiment, an A-state verification voltage VvA (e.g., waveform or signal 1007) may be applied after the first Vpgm pulse 1003. A B-state verification voltage VvB (e.g., waveform or signal 1008) may be applied after waveform 1007. A bit scan is performed to count the number of memory cells that exceed the B-state level. This is the operation shown and described with reference to Figure 9B. When the bit scan count exceeds a threshold, the memory controller triggers operation 1000A in the next iteration 1002, triggering the C-state level verification signal 1001.

[0072] The next iteration 1002 increases the Vpgm pulse 1004 by a voltage of 1005 from the first program pulse 1003. The signal level drops to approximately 0 volts, after which the B-state and C-state program verification pulses 1010 and 1011 are applied. The B-state verification voltage VvB (e.g., waveform or signal 1010) may be applied after the second Vpgm pulse 1003. The C-state verification voltage VvC (e.g., waveform or signal 1011) may be applied after waveform 1010. Thus, the bit count of the B-state triggered the verification of the C-state in the subsequent verification iteration.

[0073] Figure 10B shows a program operation 1000B similar to operation 1000A, and the same signals, such as voltage levels, are given the same reference numbers as in Figure 10A. However, there are differences. When bit counting from a bit scan is performed in state B, for example based on signal 1008, the bit count triggers operation 1000B to perform a C-level verification in the same iteration. That is, the C-level verification is performed in the same iteration as the preceding B state in which the bit scan count threshold was exceeded. The initial C-level verification is performed before the incremented program signal 1004. This is schematically shown in box 1020, where the B-state bit scan count is performed and the memory controller detects that the count threshold has been met or exceeded. The memory controller then applies the next verification state level before proceeding to iteration 1002.

[0074] The above example uses states A, B, and C for illustrative purposes, but applying the same determination that the bit scan count meets or exceeds a count threshold to trigger the verification of subsequent states is within the scope of additional embodiments. For example, state C may trigger the verification of state D in the same iteration. The state D bit scan count determination may trigger the verification of state E in the same iteration. The state E bit scan count determination may trigger the verification of state F in the same iteration. The state F bit scan count determination may trigger the verification of state G in the same iteration.

[0075] Figure 10C shows a program and verification operation 1000C similar to those in Figures 9A and 9B, with the same reference numerals used for the same elements. However, this operation 1000C occurs when the bit scan count for state B does not exceed or does not meet the threshold. This is the operation 1000C that results from the embodiment shown in Figure 9A. State C is not triggered early by the count in the first iteration, and therefore not in the second iteration 1002, nor in the first iteration 1001.

[0076] Figure 11 is a flowchart of one embodiment of process 1100 for operating a data latch while programming and verifying non-volatile storage. Process 1100 provides details for maintaining information indicating which memory elements are programmed to a particular state. Note that the data latch that initially indicates which state a memory element should be programmed to may be released during programming. Therefore, this information may be lost during the programming process. In one embodiment, process 1100 “tracks” or maintains information about a single state. By tracking a state, process 1100 means that after programming is complete, it maintains information about which memory elements were intended to be programmed to a particular (tracked) state. Note that this may be an erased state or any of the programmed states.

[0077] Process 1100 provides further details of one embodiment of steps 1002 and 1004 from Figure 10. Refer to the set of data latches 394 in Figure 3. As described above, the three data latches ADL, BDL, and CDL initially store the data to be programmed into the memory element. Thus, in one embodiment, the memory element stores 3 bits. A fourth data latch DDL is used for what is referred to herein as a “quick pass write” (QPW) state. Note that there may be more or fewer than four latches.

[0078] In step 1102, the data latch is set to the target program state of the data latch. In one embodiment, the ADL, BDL, and CDL latches are set as shown in Figure 13A. Note that different bit assignments may be used.

[0079] In step 1104, the DDL latch is set to its initial state. In one embodiment, the DDL latch is set as shown in Figure 13A. In that embodiment, the DDL latch for all memory elements is set to "0", except for memory elements that should remain in the erased state. In one embodiment, all DDL latches are set to "0". In one embodiment, setting the DDL latch for all states to "0" is used when tracking the erased state.

[0080] In step 1106, a programming condition is applied, at least in part, to the data latch. In one embodiment, a bit line voltage is set. In one embodiment, three categories are used: one for memory elements that are locked out (or prohibited) from any further programming; one for memory elements that continue to receive high-speed programming; and one for memory elements that should receive slower programming because they are close to their target threshold voltage.

[0081] In one embodiment, the bit line for locked-out or disabled memory elements is set to Vdd, the bit line for memory elements undergoing nominal (or fast) programming is set to ground (e.g., Vss), and the bit line for a third category is set to an intermediate voltage between ground and Vdd. This intermediate voltage slows down the programming to some extent.

[0082] In step 1108, one or more programming pulses are applied to the selected word line. A pass voltage (e.g., Vpass) may be applied to the unselected word line.

[0083] In step 1110, a verification low pulse is applied to the selected word line. Referring to Figure 5, VvAL may be applied. In step 1112, a detection is performed to determine whether the memory element intended to be programmed into a state associated with the verification low pulse has reached the verification low. For example, a memory element intended to be programmed into state A (as shown in ADL, BDL, CDL) is detected to determine whether the threshold voltage of the memory element is greater than or equal to VvAL. In one embodiment, the current of the bit line is detected.

[0084] In step 1114, the DDL latch is set based on the result of step 1112. Note that the DDL latch in question is related to the state that has just been verified. In one embodiment, the DDL latch is set to "1" to indicate that slow programming should be performed. For example, a memory element intended to be programmed to state A, which has a threshold voltage above VvAL, has its DDL latch set to "1".

[0085] In step 1116, the verification reference voltage is increased to the associated verification high reference voltage for the current state being verified. For example, the reference voltage is set to VvA (see Figure 5). In one embodiment, step 1116 involves increasing the voltage on the selected word line.

[0086] In step 1118, a detection is performed to determine whether a memory element intended to be programmed into a state associated with a nominal verification pulse has reached a nominal verification point. For example, a memory element intended to be programmed into state A is detected to determine whether the threshold voltage of the memory element is greater than or equal to VvA. In one embodiment, the current of the bit line is detected.

[0087] In step 1120, the ADL, BDL, and CDL latches are set based on the results of step 1120. Note that the latches in question are those associated with the state that has just been verified. In one embodiment, one or more of the ADL, BDL, and CDL latches are set to "1" to indicate that programming is prohibited. For example, a memory element intended to be programmed to state A, which has a threshold voltage above VvA, has its ADL, BDL, and CDL latches set to "1".

[0088] Under certain conditions, only one or two of the data latches may be required to indicate a lockout condition. Therefore, step 1120, in one embodiment, includes setting one or more of the latches ADL, BDL, and CDL to "1". In one embodiment, process 1100 tracks how far along the programming process it is and uses different sets of latches to indicate lockouts depending on the stage of programming. Further details are described below.

[0089] In step 1122, the DDL latch of a tracked memory element may be set to "0" if the memory element has just passed program verification. For example, if state A is tracked, the DDL latch of those memory elements that have just passed program verification for state A will be set to "0". However, if a state other than state A is tracked (e.g., state A is not tracked), the DDL latch remains "1". Note that if a memory element passes nominal verification (e.g., VvA) in steps 1116-1118, the memory element should also have passed verification low (e.g., VvAL) in steps 1112-1114, and therefore the DDL latch should be "1". Note that by appropriately setting the DDL latch in step 1112, it is possible to maintain information about the intended program state for one of the states.

[0090] Note that the tracked states may also include the erased state. Note that there is no verification operation for memory elements that should remain in the erased state. Therefore, the status of the DDL latch for these memory elements should not change in step 1114. When a state other than the erased state is tracked, the DDL latch for memory elements that remain erased may initially be set to "1". On the other hand, when the erased state is tracked, the DDL latch may initially be set to "0". Therefore, the DDL latch should remain "0" throughout the programming. In contrast, the DDL latch for other states may be set to "1" if the verification low passes.

[0091] In step 1124, a determination is made as to whether there are any additional states to verify. Note that it is not necessary to verify all states at the beginning of the programming operation. If there are further states to verify, in step 1126, the verification reference voltage is increased. The reference voltage may be increased to the verification low reference level for the next state. Then, in step 1110, a verification low pulse may be applied. If all states to be verified at this point have been verified, in step 1128, a determination is made as to whether all memory elements have passed verification. Note that some memory elements may not reach their intended state but can be ignored. This may help speed up programming.

[0092] If not all memory elements pass verification (considering that some may fail), process 1100 returns to step 1106 and applies programming conditions based on latch 394. For memory elements that are currently locked out (as indicated by one or more of the latches ADL, BDL, CDL), the bit line of the memory element may be set to Vdd. For a memory element to receive slow programming, the bit line of the memory element may be set to an intermediate voltage. In one embodiment, the DDL latch of those memory elements that are not locked out from further programming is checked to determine whether slow programming should be performed.

[0093] Figure 12 is a flowchart of one embodiment of process 1200 for operating data latches while programming and verifying non-volatile storage. Process 1200 provides further details on how the data latches are used differently depending on the stage of the programming process. Figures 13A to 13D are tables showing the status of data latch ADL, BDL, CDL, and DDL throughout the various stages of process 1200.

[0094] Figure 14 illustrates the use of latches between various stages of one embodiment of programming. Briefly, the programming process can be divided into the following stages: In the pre-lockout stage, data latches can be set up. In the ABCDEFG stage, all states are programmed. In the EFG stage, only states E, F, and G are programmed. In the G-program stage, only state G is programmed. In the EPD stage, false program detection is performed. In one embodiment, word line defects are detected during the EPD stage. Also note that the ADL latch is reset between the ABCDEFG and EFG stages. Similarly, the BDL latch is reset between the EFG and G stages. Further details will be explained in relation to the description of Figure 12.

[0095] Process 1200 describes one embodiment in which the G state is a tracking state. In step 1202, the target data state is stored in the latch. Figure 13A shows a table of initial states for the latch ADL, BDL, and CDL.

[0096] In step 1204, the initial state of the DDL latch is set. In this embodiment, the initial state for memory elements to remain in the erased state is set to "1". The DDL for all other memory elements is set to "0". Figure 13A shows a table of the initial states of the DDL latch for memory cells subject to various states. Steps 1202 and 1204 may be performed during the pre-lockout phase (see Figure 14).

[0097] In step 1206, one or more programming pulses are applied, followed by the verification of one or more states. One embodiment of step 1206 includes performing steps 1108, 1110, 1112, 1116, and 1118 of Figure 11 one or more times. For example, step 1108 may be performed once, followed by steps 1110, 1112, 1116, and 1118 to verify different states.

[0098] First, programming begins in the ABCDEFG phase (see Figure 14). The black bars in Figure 14 indicate when a data latch is actively used for programming or EPD. During the ABCDEFG phase, the ADL, BDL, and CDL latches are used to store lockout information. The DDL latch is used to store the QPW status.

[0099] Figure 13B shows an example of latch use during the ABCDEFG stages. At this point, any locked-out memory element has a "1" in all of its ADL, BDL, and CDL latches. The erase case is shown in this state. For states A through G, the data programmed into the memory element is shown. However, once a memory element reaches its intended target state, the ADL, BDL, and CDL latches of the memory element may be set to "1". This was previously explained as one possibility in step 1120 of Figure 11. Therefore, the status of ADL, BDL, and CDL may be checked when determining whether a memory element is locked out during the ABCDEFG stages.

[0100] Figure 13B also shows an example of the use of a DDL latch during the ABCDEFG stages. In one embodiment, a "1" in the DDL latch means that slow programming should be used. Thus, a memory element that is not locked out and has a "1" in the DDL latch can receive slow programming.

[0101] Note that the DDL latch is used differently for G states. For memory elements programmed into G states, the DDL latch is maintained at "0" throughout the entire programming process in one embodiment.

[0102] In step 1208, it is determined whether the memory elements subject to states A through D are programmed or not. Note that it is not necessary for any of the memory elements subject to these states to reach their intended state. In one embodiment, some memory elements may remain in an incomplete state. If the programming for states A through D is not yet complete, the process returns to step 1206.

[0103] When the memory elements in states A through D are programmed, the ADL latch is released in step 1210. This is reflected in the ADL reset in Figure 14 after the ABCDEFG programming stages. Referring to Figure 13C, the ADL latch is free at this point. Since the ADL latch is free, it can be used for background caching, for example. Further details on using data latches released during program operation are described in U.S. Patent No. 7,502,260 by Li et al., entitled "Method for Non-Volatile Memory with Background Data Latch Caching Operations During Program Operations," which is incorporated herein by reference in its entirety for all purposes.

[0104] Note that after the ADL latch is released, programming proceeds to the EFG programming stage (see Figure 14). At this point, in one embodiment, only the BDL and CDL latches are used to store the lockout information. Also, only the BDL and CDL latches are needed to contain the information necessary to uniquely define which state the memory element is programmed to. For example, in one embodiment, combination "01" uniquely defines the E state, combination "10" uniquely defines the F state, combination "00" uniquely defines the G state, and combination "11" uniquely defines the lockout state. Other bit assignments may be used.

[0105] Furthermore, in Figure 13C, the DDL latch for all memory elements below the E state should be "1". Memory elements programmed to either the E or F state can have either a "1" or a "0" in their DDL latch, depending on whether the verification low passed. As before, the DDL latch for G state memory elements remains "0". In one embodiment, the verification low for G state memory elements is not performed. Therefore, the DDL latch should show "0" throughout the programming. However, as an example, the verification low for the G state can be performed as long as the DDL latch is set to "0" when the memory element is locked out.

[0106] Next, programming proceeds to the EFG stage (see Figure 14). When determining how to apply the programming conditions (steps 1211 in Figure 12), the status of the BDL and CDL latches may be used for lockout. Memory elements that are not locked out and have a "1" in the DDL latch may receive slow programming.

[0107] In step 1212, it is determined whether states E and F are programmed. If not, the process continues programming and verification using the status of latch BDL, CDL, and DDL.

[0108] Once the E and F states are programmed, the BDL latch is released in step 1214. This is reflected by the BDL reset at the end of the EFG programming phase (see Figure 14). Like the ADL latch, the BDL latch is free for purposes such as background caching.

[0109] Figure 13D shows a table representing the released BDL latches. At this point, only memory elements that remain programmed are memory elements in the G state. Therefore, the status of the CDL latch can uniquely describe whether the memory element should be programmed into the G state (0 in this example) or locked out (1 in this example).

[0110] Note that the status of the DDL latch is "0" for the G state memory element at this point. As mentioned earlier, the DDL latch can remain "0" for the G state memory element throughout the entire programming.

[0111] Next, the programming proceeds to the G-program stage (see Figure 14). In step 1215, program conditions based on the CDL and DDL states are applied. The status of the CDL latch can be used to determine which memory elements are locked out. In one embodiment, the status of the DDL latch remains "0" for all G-state memory elements. However, in one embodiment, the DDL latch may be used for the QPW status. In this case, memory elements that are not locked out and whose DDL latch is set to "1" may receive slow programming.

[0112] Once the G-state memory elements are programmed (step 1216), the G-programming phase ends. At this point, the CDL latch for all G-state memory elements should be "1". The DDL latch for all G-state memory elements should be "0". Note that in one embodiment, the DDL latch is "0" because it is not permitted to be set to "1" during the programming operation.

[0113] However, in one embodiment, the DDL latch is permitted to be set to "1" when the G state memory element passes verification low. In this case, the DDL latch may be set to "0" when the G state memory element passes verification high.

[0114] Regardless of whether the information from the DDL latch is held in that latch or transferred to another latch or some other memory location, information about which memory elements became subject to the G state is maintained after the programming operation. Note that no extra data latches are needed. Also note that two of the data latches are released during programming for purposes such as background caching.

[0115] As mentioned above, a considerable amount of programming time is consumed when all data states are verified. Specifically, the programming operation for a triple-level cell (TLC) may involve the application of a program pulse, followed by verification iterations or program verification (pvfy) for each data state, repeated until almost each program verification voltage or level (with an acceptable amount for slow cells, set by parameters) of the memory cell is passed. Figure 15 is a table showing the number of program loops and verification iterations (shaded) for each data state in the programming operation for a triple-level cell (TLC), along with the time duration included in each program loop. As shown, the program time tPROG mainly consists of the program pulse (P, PD, PR clock or period) and the verification time for each state (R, QPW, RWL, QPW, RR clock or period). Algorithms have been developed to optimize the number of verification iterations required for each state (e.g., smart PCV) and to fine-tune the ideal starting program voltage VPGM for the optimized program pulse (e.g., smart verification). However, it is desirable to reduce the program time tPROG required when verifying memory cells for all data states.

[0116] As a result, this specification describes a memory device (e.g., a non-volatile memory device 210 in Figure 2) that includes memory cells (e.g., transistors 100, 102, 104, and 106 in Figure 1B) each connected to one of a plurality of word lines (e.g., word lines WL3, WL2, WL1, and WL0 in Figure 1B, or WL0 to WL63 in Figure 4). The memory cells are configured to hold a threshold voltage Vt or Vth corresponding to one of a plurality of memory states or data states (e.g., Figures 5 and 6). In a plurality of data states, including the highest data state (e.g., data state G in Figures 5 and 6), the threshold voltage of the memory cell associated with the highest data state is higher than that of the other data states (e.g., the erase state and data states A to F in Figures 5 and 6). The memory device also includes a control circuit or means (for example, one or any combination of the control circuit 220, decoders 240A, 240B, 242A, and 242B, power control module 226, sense block 300, read / write circuits 230A and 230B, controller 244, etc., in Figure 2). The control means is configured to program and verify memory cells connected to word lines by applying, between each of a plurality of program loops of program operation, each of a series of programming pulses of program voltage, followed by verification pulses of a plurality of program verification voltages, each associated with one of a plurality of data states, to selected word lines from a plurality of word lines. The control means is also configured to skip verification of memory cells subject to the highest data state in at least one of the plurality of program loops. Therefore, as detailed below, the program time tPROG can be further reduced by eliminating / reducing verification of the memory cell targeted by the highest data state (e.g., the data state in Figures 5 and 6) and by controlling the programming of the memory cell targeted by the highest data state solely through the program loop count and / or bit line bias. The highest data state is selected because it can tolerate a wider threshold voltage distribution as long as it does not affect the required read path voltage VREAD.

[0117] In one embodiment, program verification of the highest data state (e.g., data state G) may be completely skipped, and a loop count can be tracked using a data latch; such a technique is referred to herein as Option 1. As described above, memory cells may be arranged in memory holes, each coupled to one of a plurality of bit lines (e.g., bit lines BL0 to BL13 in Figure 4) (e.g., a NAND string in Figure 4). Furthermore, the memory device may further include a plurality of data latches (e.g., data latches 394, 395, 396, 397 in Figure 3), each configured to store data to be programmed during program operation and to control one of the plurality of bit lines to allow or prohibit programming of memory cells in memory holes coupled to one of the plurality of bit lines. Each of the plurality of data latches stores one bit to define a bit combination. Thus, the control means may further be configured to operate and update the plurality of data latches based on the data programmed into the memory cells, the threshold voltage of the memory cells, and which of the plurality of data states is programmed and verified during program operation. The control means is also configured to use one or more bit combinations to update multiple data latches to track the number of subsequent program loops among multiple program loops for each of the target memory cells so that it is programmed to the highest data state.

[0118] Figure 16 is a plot of the threshold voltage distribution when program verification for the highest data state is completely skipped. As shown, the erase state or Er (forbidden) and states A-F are normal program verification and lockout. For a G state cell, once it passes the pvfy F level (i.e., the program verification voltage for data state F), the count program loops until it is locked out (forbidden). G state cells are tracked cell by cell. As described, each memory cell may be configured to store 3 bits. Therefore, for example, continuing to refer to Figure 16, the multiple data states may include the erase data state (Er), and the first data state (A), the second data state (B), the third data state (C), the fourth data state (D), the fifth data state (E), the sixth data state (F), and the seventh data state (G), in order of increasing threshold voltage magnitude. Thus, the highest data state is the seventh data state. Therefore, according to another embodiment, the data latch includes a first data latch ADL, a second data latch BDL, and a third data latch CDL, each configured to store data to be programmed during program operation. The data latch may also include a fourth data latch DDL configured to control one of the bit lines to allow or prohibit programming of a memory cell in a memory hole coupled to one of the bit lines. The bit combination includes 16 bit combinations.

[0119] Figure 17A is a table showing the information stored in the first data latch ADL(L), the second data latch BDL(M), the third data latch CDL(U), and the fourth data latch DDL(QPW) for each data state of the tri-value memory cell. As shown, 14 bit combinations are required for distinction: 12 are required for the A-F state fast program (bit lines set to steady-state voltage VSS) and the QPW program (bit lines set to VBLC_QPW), 1 is required for the forbidden case Er or the pass program verification high VH case, and 1 is required for the single G state case (no QPW). However, since the four data latches ADL, BDL, CDL, and DDL can represent 16 bit combinations, this leaves 2 unused bit or code combinations. Figure 17B is a table showing unused bit combinations of bits in the first data latch ADL(L), second data latch BDL(M), third data latch CDL(U), and fourth data latch DDL(QPW). These unused bit combinations can be used, for option 1, to track the memory cell in the highest data state (e.g., state G) after passing the verification voltage level for the next highest data state (data state F). No change to the XDL latch (user cache) limit is required. Thus, the control means is further configured to update at least one of the first data latch ADL, second data latch BDL, third data latch CDL, and fourth data latch DDL associated with each memory cell among the memory cells subject to the seventh data state to a first unused bit combination of 16 bit combinations, in response to one of the memory cells having a threshold voltage greater than one of the multiple program verification voltages associated with the sixth data state, detected during one of the verification pulses of one of the multiple program verification voltages associated with the sixth data state.The control means is also configured to update at least one of the first data latch ADL, second data latch BDL, third data latch CDL, and fourth data latch DDL associated with one of the memory cells subject to the seventh data state, from a first unused bit combination of the sixteen bit combinations, to a second unused bit combination of the sixteen bit combinations, following the application of a first subsequent programming pulse from a series of programming pulses of program voltage to one of the memory cells subject to the seventh data state. The control means is also configured to update at least one of the first data latch ADL, second data latch BDL, third data latch CDL, and fourth data latch DDL associated with one of the memory cells subject to the seventh data state, from a second unused bit combination of the sixteen bit combinations, to one of the sixteen bit combinations associated with the erased data state, following the application of a second subsequent programming pulse from a series of programming pulses of program voltage to one of the memory cells subject to the seventh data state, in order to prohibit programming of one of the memory cells subject to the seventh data state.

[0120] Figure 18 shows an exemplary trace of the memory cell targeted for the highest data state through subsequent program loops among multiple program loops, using two unused bit combinations, for Option 1. Figure 19 is another table showing the information stored in the first data latch ADL(L), second data latch BDL(M), third data latch CDL(U), and fourth data latch DDL(QPW) for each data state of Option 1. Figure 20 is a table showing the impact on cache release (i.e., in which of the multiple program loops a data latch can be released to allow user data for the next page to be stored). In memory devices that do not employ Option 1, the G state does not support QPW and uses only one bit combination, whereas, as described, the G state in Option 1 uses three combinations of codes and therefore may require a delay in internal cache release. Figure 21 summarizes the parameter variations affecting the operation of memory devices using Option 1. As shown, by using XDL (a fifth data latch) in the TLC, it is still possible to implement more than two program pulses for the G state. Such an approach affects user cache release and causes delays for the release of the internal second and third bit caches.

[0121] Instead of completely skipping program verification for the highest data state (e.g., state G), the memory device may skip only the program verification for the highest data state after the next highest data state (e.g., state F) has completed. Such a technique is referred to herein as Option 2. In Option 2, a counter can be used to track the program loop. As described, for example, referring again to Figure 16, the multiple data states may include, in order of increasing threshold voltage magnitude, the erased data state (Er), the next highest data state (F), and the highest data state (G). Thus, the control means may be further configured to program and verify memory cells among memory cells using a series of programming pulses of a program voltage and a series of verification pulses of a series of program verification voltages associated with the series of programming pulses, before the next highest data state has completed verification (i.e., in response to a predetermined number of memory cells among the memory cells subject to the next highest data state and the highest data state not having a threshold voltage greater than one of a series of verification voltages associated with the next highest data state), and to lock out memory cells having a threshold voltage greater than one of a series of verification voltages of one of the multiple data states subject to the multiple data states from further programming. The control means may be configured to stop further verification of the memory cells among the memory cells subject to the next highest data state and to count subsequent program loops among the plurality of program loops after the next highest data state has completed verification (i.e., in response to a predetermined number of memory cells among the memory cells subject to the next highest data state having a threshold voltage greater than one of a plurality of verification voltages associated with the next highest data state). The control means may also be configured to prohibit programming of the memory cells among the memory cells subject to the highest data state in response to a predetermined slow cell count threshold exceeding a predetermined slow cell count threshold.

[0122] As explained, each memory cell may be configured to store 3 bits. Therefore, referring again to Figure 16, for example, the multiple data states include, in increasing order of threshold voltage magnitude, the erase data state (Er), the first data state (A), the second data state (B), the third data state (C), the fourth data state (D), the fifth data state (E), the sixth data state (F), and the seventh data state (G). Thus, the next highest data state is the sixth data state (F), and the highest data state is the seventh data state (G). Therefore, the control means may be further configured to program and verify a memory cell among the memory cells subject to the first, second, third, fourth, fifth, sixth, and seventh data states using a series of programming pulses of a program voltage, followed by a series of verification pulses of a plurality of program verification voltages associated with the programming pulses, before the sixth data state completes verification. The control means may be configured to lock out memory cells that have a threshold voltage greater than one of the multiple verification voltages of one of the multiple data states in response to the memory cells among the memory cells subject to the sixth and seventh data states having a threshold voltage greater than one of the multiple verification voltages associated with the sixth data state, from further programming. Next, after the highest data state has completed verification, the control means may be configured to stop further verification of memory cells among the memory cells subject to the seventh data state in response to the memory cells among the memory cells subject to the sixth and seventh data states having a threshold voltage greater than one of the multiple verification voltages associated with the sixth data state, and to count subsequent program loops among the multiple program loops. The control means may also be configured to prohibit programming of memory cells among the memory cells subject to the seventh data state in response to the number of subsequent program loops among the multiple program loops exceeding a predetermined slow cell count threshold.

[0123] Therefore, for Option 2, before the F state is completed (e.g., failing data state F bit scan), the Er state (prohibited) and A-G states are programmed and locked out as usual. After the F state is completed (passing data state F bit scan), no programmed verification is performed. The remaining G state slow cells count the programmed loop using a counter until they are locked out (prohibited). Figure 22 shows an exemplary sequence of programmed loops for the two options. As shown, the number of programmed pulses applied to slow G state cells can be tracked by a counter (not a data latch). Such an approach can have more or fewer loops than two, providing easier control and having no impact on cache release. Figure 23 is a plot of threshold voltage distribution when programmed verification of the highest data state is skipped after the next highest data state (e.g., F state) is completed, and programmed loops for slow cells subject to the highest data state are tracked using a counter. As shown, after the F state is completed (i.e., F pass is detected), all G state cells that have not passed the G program verification receive the same number of program pulses, which can further widen the threshold voltage distribution for the highest data state.

[0124] In another embodiment, the memory device is similar to Option 2, but uses a data latch to track a program loop count instead of a counter, and may skip program verification only for the highest data state (e.g., state G) after the next highest data state (e.g., state F) has completed. Such a technique is referred to herein as Option 3. For Option 3, the control means is configured to program and verify memory cells among memory cells using a series of programming pulses of a program voltage and a series of verification pulses among a series of program verification voltages associated with the series of programming pulses, before the next highest data state has completed verification (i.e., in response to a predetermined number of memory cells among the memory cells subject to the next highest data state and the highest data state not having a threshold voltage greater than one of a plurality of verification voltages associated with the next highest data state). The control means locks out memory cells having a threshold voltage greater than one of a plurality of verification voltages for one of the plurality of data states subject to the data state from further programming. Next, after the highest data state has completed verification (i.e., in response to a predetermined number of memory cells among the memory cells subject to the next highest data state and the highest data state having a threshold voltage greater than one of a plurality of verification voltages associated with the next highest data state), the control means stops further verification of the memory cells among the memory cells subject to the highest data state and updates a plurality of data latches using one or more bit combinations to track the amount of subsequent program loops among a plurality of program loops for each of the memory cells subject to be programmed to the highest data state.

[0125] More specifically, for option 3, the control means is further configured to update at least one of the first data latch ADL and second data latch BDL and third data latch CDL and fourth data latch DDL associated with each memory cell among the memory cells Before the sixth data state completes verification, at least one of the first data latch ADL, second data latch BDL, third data latch CDL, and fourth data latch DDL associated with one of the memory cells subject to the seventh data state is updated to one of the 16 bit combinations associated with the erased data state to prohibit programming of one of the memory cells subject to the seventh data state, in response to one of the memory cells having a threshold voltage greater than one of the multiple program verification voltages associated with the seventh data state, as detected during one of the verification pulses of one of the multiple program verification voltages associated with the seventh data state.Before the sixth data state has completed verification, the control means updates at least one of the first data latch ADL, second data latch BDL, third data latch CDL, and fourth data latch DDL associated with one of the memory cells subject to the seventh data state, from a first unused bit combination of the sixteen bit combinations, to a second unused bit combination of the sixteen bit combinations, following the application of one of a series of programming pulses of program voltage to one of the memory cells subject to the seventh data state. After the sixth data state has completed verification (i.e., in response to a predetermined number of memory cells among the memory cells subject to the sixth and seventh data states having a threshold voltage greater than one of the plurality of verification voltages associated with the sixth data state), the control means updates at least one of the first data latch ADL, second data latch BDL, third data latch CDL, and fourth data latch DDL associated with one of the memory cells subject to the seventh data state, from a second unused bit combination of the sixteen bit combinations and from a first unused bit combination of the sixteen bit combinations, to one of the sixteen bit combinations associated with the erased data state, following the application of a first subsequent programming pulse from a series of programming pulses of program voltage to one of the memory cells subject to the seventh data state, in response to the memory cell subject to the seventh data state having a threshold voltage greater than one of the plurality of verification voltages associated with the sixth data state and less than one of the plurality of verification voltages associated with the seventh data state.After the sixth data state has completed verification, the control means updates at least one of the first data latch ADL, second data latch BDL, third data latch CDL, and fourth data latch DDL associated with one of the memory cells subject to the seventh data state from a first unused bit combination of the sixteen bit combinations to a second unused bit combination of the sixteen bit combinations, following the application of a second subsequent programming pulse of a series of programming pulses of program voltage to one of the memory cells subject to the seventh data state, in response to the memory cell subject to the seventh data state having a threshold voltage greater than one of the plurality of verification voltages associated with the sixth data state and less than one of the plurality of verification voltages associated with the seventh data state.

[0126] Therefore, before the F state is completed (e.g., failing data state F bit scan), the Er (prohibited) and A-G states are programmed, verified, and locked out as usual. After the F state is completed (passing data state F bit scan), no program verification is performed. The remaining G state slow cell count program loops until lockout (prohibited) occurs by tracking each individual slow cell loop count using the data latch. The program time tPROG savings are the same as in option 2, but the impact of the 3-bit cache is the same as in option 1. Figure 24 shows an exemplary tracking of the memory cell for option 3, along with a corresponding plot of threshold voltage distribution. Figure 25 shows the simulation results for options 1, 2, and 3 compared to no program verification skip (POR) for the highest data state. Specifically, individual cell threshold voltage Vt data versus program pulse (no QPW programming) data are collected to evaluate the impact from the three options. This data is then used to simulate the options. The G state threshold voltage Vt distribution is shown in Figure 25. As shown, options 1 and 3 are identical and very similar to POR. Option 2 carries the risk of overprogramming. Option 1 achieves the fastest program time tPROG and maintains a very good threshold voltage Vt distribution. Option 2 has a simpler implementation form (eliminating the need for data latch loop tracking) but instead carries the risk of overprogramming. Option 3, at least in this simulation, shows no benefit compared to option 1 and shows little improvement in program time tPROG. Options 3 and 1 have the same lower tail of the threshold voltage distribution and suggest a small risk for cells that may require two or more pulses after passing F verification. Options 3 and 1 have the same upper tail and suggest a small risk for cells that may require only one extra pulse after passing F verification.

[0127] Figure 26 shows a comparison of the highest data states, Option 1, Option 2, and Option 3 without skipping program verification. All three options can be applied to a four-level cell (QLC) memory device, also to save program verification S15. Figure 27A is a table showing the information stored in the first data latch ADL(L), second data latch BDL(M), third data latch CDL(U), and different fourth data latches (T) and fifth data latches DDL(QPW) for each data state of a four-level memory cell (QLC). As shown, 30 bit combinations are required to distinguish between them, 28 are required for the fast program (bit line set to steady-state voltage VSS) and QPW program (bit line set to VBLC_QPW) for states S1-S14, 1 is required for the prohibited case (Er or pass program verification high VH), and 1 is required for one S15 state (no QPW). Nevertheless, since the five data latches can represent 32 bit combinations, two unused bit or code combinations remain. Figure 27B is a table showing the unused bit combinations of bits in the first data latch ADL(L), the second data latch BDL(M), the third data latch CDL(U), and the different fourth data latch (T) and fifth data latch DDL(QPW). Again, there is no change to the XDL (User Cache) limit, but there is a delay for the internal second and third bit cache release.

[0128] Figure 28 shows the steps of a method for operating a memory device (e.g., the non-volatile memory device 210 in Figure 2). As described above, the memory device includes memory cells (e.g., transistors 100, 102, 104, and 106 in Figure 1B), each connected to one of several word lines (e.g., word lines WL3, WL2, WL1, and WL0 in Figure 1B, or WL0 to WL63 in Figure 4). The memory cells are configured to hold a threshold voltage Vt or Vth corresponding to one of several memory states or data states (e.g., Figures 5 and 6). In several data states, including the highest data state (e.g., data state G in Figures 5 and 6), the threshold voltage of the memory cell associated with the highest data state is higher than that of the other data states (e.g., the erase state and data states A to F in Figures 5 and 6). The method includes step 2800, during each of a plurality of program loops of program operation, applying each of a series of programming pulses of program voltage and each of a plurality of verification pulses of program verification voltage, each associated with one of a plurality of data states, to a selected word line from a plurality of word lines to program and verify a memory cell connected to a word line. The method also includes step 2802, in at least one of the plurality of program loops, to skip verification of the memory cell that is subject to the highest data state.

[0129] Here again, program verification of the highest data state (e.g., data state G) may be completely skipped, and a data latch can be used to track the loop count for option 1. As described above, memory cells may be arranged in memory holes, each coupled to one of a plurality of bit lines (e.g., bit lines BL0 to BL13 in Figure 4) (e.g., a NAND string in Figure 4). In addition, the memory device may further include a plurality of data latches (e.g., data latches 394, 395, 396, 397 in Figure 3), each configured to store data to be programmed during program operation and to control one of the plurality of bit lines to allow or deny programming of the memory cells in the memory holes coupled to one of the plurality of bit lines. Each of the plurality of data latches stores one bit to define a bit combination. Thus, the method may further include the step of operating and updating the plurality of data latches based on the data programmed into the memory cells, the threshold voltage of the memory cells, and which of the plurality of data states is programmed and verified during program operation. The method may also include the step of using one or more bit combinations to update multiple data latches to track the number of subsequent program loops among multiple program loops for each of the memory cells in question so that it is programmed to the highest data state.

[0130] For example, referring again to Figure 16, the multiple data states may include, in order of increasing threshold voltage magnitude, the erase data state (Er), the first data state (A), the second data state (B), the third data state (C), the fourth data state (D), the fifth data state (E), the sixth data state (F), and the seventh data state (G). Thus, the highest data state is the seventh data state. In another embodiment, the multiple data latches include a first data latch ADL, a second data latch BDL, and a third data latch CDL, each configured to store data to be programmed during a program operation. The multiple data latches may also include a fourth data latch DDL configured to control one of the multiple bit lines to allow or deny programming of a memory cell in a memory hole coupled to one of the multiple bit lines. The bit combinations include 16 bit combinations.

[0131] As described above with reference to Figures 17A and 17B, when using four data latches, there are two unused bits or code combinations. Therefore, the method may further include the step of updating at least one of the first data latch ADL, second data latch BDL, third data latch CDL, and fourth data latch DDL associated with each memory cell among the memory cells subject to the seventh data state to the first unused bit combination of the 16 bit combinations, in response to one of the memory cells having a threshold voltage greater than one of the multiple program verification voltages associated with the sixth data state, detected during one of the verification pulses of one of the multiple program verification voltages associated with the sixth data state. In addition, the method may include updating at least one of the first data latch ADL, second data latch BDL, third data latch CDL, and fourth data latch DDL associated with one of the memory cells subject to the seventh data state, from a first unused bit combination of the sixteen bit combinations, to a second unused bit combination of the sixteen bit combinations, following the application of a first subsequent programming pulse from a series of programming pulses of program voltage to one of the memory cells subject to the seventh data state. In addition, the method may also include updating at least one of the first data latch ADL, second data latch BDL, third data latch CDL, and fourth data latch DDL associated with one of the memory cells subject to the seventh data state, from a second unused bit combination of the sixteen bit combinations, to one of the sixteen bit combinations associated with an erased data state, following the application of a second subsequent programming pulse from a series of programming pulses of program voltage to one of the memory cells subject to the seventh data state, to prohibit programming of one of the memory cells subject to the seventh data state.

[0132] Here again, instead of completely skipping the program verification of the highest data state (e.g., state G), the memory device may skip only the program verification of the highest data state after the next highest data state (e.g., state F) has completed for option 2. So, for example, referring again to Figure 16, the multiple data states may include, in order of increasing threshold voltage magnitude, the erased data state (Er), the next highest data state (F), and the highest data state (G). Thus, the method may further include the steps of: programming and verifying memory cells among memory cells using a series of programming pulses of a program voltage and verification pulses of a series of program verification voltages associated with the series of programming pulses, before the next highest data state has completed verification; and locking out memory cells having a threshold voltage greater than one of the multiple verification voltages of one of the multiple data states of interest from further programming. In addition, after the next highest data state has completed verification, further verification of the memory cells among the memory cells of interest for the highest data state is stopped and the subsequent program loops of the multiple program loops are counted. The method may also include a step of prohibiting programming of a memory cell among the memory cells that are subject to the highest data state in response to the number of subsequent program loops among multiple program loops exceeding a predetermined slow cell count threshold.

[0133] Referring again to Figure 16, the multiple data states, in order of increasing threshold voltage magnitude, include the erase data state (Er), the first data state (A), the second data state (B), the third data state (C), the fourth data state (D), the fifth data state (E), the sixth data state (F), and the seventh data state (G). Therefore, the next highest data state is the sixth data state (F), and the highest data state is the seventh data state (G). Therefore, the method may further include the steps of: programming and verifying memory cells among the memory cells subject to the first, second, third, fourth, fifth, sixth, and seventh data states, using a series of programming pulses of a program voltage and verification pulses of a plurality of program verification voltages associated with the series of programming pulses, following the series of programming pulses, before the sixth data state has completed verification; locking out memory cells having a threshold voltage greater than one of a plurality of verification voltages of one of the plurality of data states from further programming in response that the memory cells among the memory cells subject to the sixth and seventh data states do not have a threshold voltage greater than one of a plurality of verification voltages associated with the sixth data state. The method may further include the steps of: stopping further verification of memory cells among the memory cells subject to the seventh data state in response that, after the next highest data state has completed verification, the memory cells among the memory cells subject to the sixth and seventh data states have a threshold voltage greater than one of a plurality of verification voltages associated with the sixth data state; and counting subsequent program loops among a plurality of program loops. The method may also include prohibiting programming of memory cells among the memory cells subject to the seventh data state in response to the number of subsequent program loops among a plurality of program loops exceeding a predetermined slow cell count threshold.

[0134] Here again, in another embodiment, the memory device is similar to option 2, but for option 3, it may use data latches to track program loop counts instead of counters, and after the next highest data state (e.g., state F) has completed, it may skip only the program verification of the highest data state (e.g., state G). For option 3, the method may include the steps of: programming and verifying memory cells among memory cells using a series of programming pulses of a program voltage and verification pulses of a series of program verification voltages associated with the series of programming pulses, before the next highest data state has completed verification; and locking out memory cells having a threshold voltage greater than one of a series of verification voltages of one of the multiple data states of interest from further programming. The method may also include the steps of: stopping further verification of memory cells among the memory cells of interest in the highest data state after the next highest data state has completed verification; and updating a series of data latches using one or more bit combinations to track the amount of subsequent program loops among a series of program loops for each of the memory cells of interest to be programmed to the highest data state.

[0135] For option 3, the method may further include the step of updating at least one of the first data latch ADL, second data latch BDL, third data latch CDL, and fourth data latch DDL associated with each memory cell among the memory cells subject to the seventh data state to a first unused bit combination of 16 bit combinations, in response to one of the memory cells having a threshold voltage greater than one of the multiple program verification voltages associated with the sixth data state, detected during one of the verification pulses of one of the multiple program verification voltages associated with the sixth data state, before the sixth data state has completed verification. The method may also include, before the verification of the sixth data state is complete, updating at least one of the first data latch ADL, second data latch BDL, third data latch CDL, and fourth data latch DDL associated with one of the memory cells subject to the seventh data state to one of the 16 bit combinations associated with the erased data state, in response to the memory cell having a threshold voltage greater than one of the multiple program verification voltages associated with the seventh data state, as detected during one of the verification pulses of one of the multiple program verification voltages associated with the seventh data state, to prohibit programming of the memory cell subject to the seventh data state. Furthermore, the method may include, before the verification of the sixth data state is complete, updating at least one of the first data latch ADL, second data latch BDL, third data latch CDL, and fourth data latch DDL associated with one of the memory cells subject to the seventh data state, from a first unused bit combination of the sixteen bit combinations, to a second unused bit combination of the sixteen bit combinations, following the application of one of a series of programming pulses of program voltage to one of the memory cells subject to the seventh data state.The method may also include the step of updating, after the sixth data state has completed verification, at least one of the first data latch ADL, second data latch BDL, third data latch CDL, and fourth data latch DDL associated with one of the memory cells subject to the seventh data state, from the first unused bit combination of the 16 bit combinations, from the second unused bit combination of the 16 bit combinations, to one of the memory cells subject to the seventh data state, in response to the application of a first subsequent programming pulse of a series of programming pulses of program voltage to one of the memory cells subject to the seventh data state, to prohibit programming of one of the memory cells subject to the seventh data state, in response to the memory cell having a threshold voltage greater than one of the multiple verification voltages associated with the sixth data state and less than one of the multiple verification voltages associated with the seventh data state. In addition, the method may include, after the verification of the sixth data state is complete, updating at least one of the first data latch ADL, second data latch BDL, third data latch CDL, and fourth data latch DDL associated with one of the memory cells subject to the seventh data state from a first unused bit combination of the sixteen bit combinations to a second unused bit combination of the sixteen bit combinations, following the application of a second subsequent programming pulse of a series of programming pulses of program voltage to one of the memory cells subject to the seventh data state, in response that one of the memory cells subject to the seventh data state has a threshold voltage greater than one of the plurality of verification voltages associated with the sixth data state and less than one of the plurality of verification voltages associated with the seventh data state.

[0136] As will be apparent, modifications can be made to those described and illustrated herein, but without departing from the scope defined in the appended claims. The above description of embodiments is provided for illustrative and explanatory purposes. The above description is not intended to be exhaustive or to limit the disclosure. Individual elements or features of a particular embodiment are generally interchangeable and can be used in a selected embodiment where applicable, even if not specifically illustrated or described, although they are not limited to that particular embodiment. The same may also be modified in many ways. Such modifications should not be considered departures from the disclosure, and all such modifications are intended to be within the scope of the disclosure.

[0137] Various terms are used to refer to specific system components. Different companies may refer to components by different names, and this document is not intended to distinguish components that have different names but the same function. In the following description and claims, the terms “including” and “comprising” are used in an open-ended manner and should therefore be interpreted as “including, but not limited to…”. Also, the terms “couple” or “couples” are intended to mean either an indirect connection or a direct connection. Thus, when a first device couples with a second device, the connection may be a direct connection or an indirect connection via other devices and connections.

[0138] Furthermore, when it is mentioned that a layer or element is "on top of" another layer or substrate, it may be directly on top of the other layer of the substrate, or there may be an intervening layer. Moreover, when it is mentioned that a layer is "below" another layer, it will be understood that it may be directly below, or there may be one or more intervening layers. Furthermore, when it is mentioned that a layer is "between" two layers, it may be the only layer between the two layers, or there may be one or more intervening layers.

[0139] As described herein, a controller includes individual circuit components, application-specific integrated circuits (ASICs), microcontrollers with control software, digital signal processors (DSPs), processors with control software, field programmable gate arrays (FPGAs), or combinations thereof.

Claims

1. A memory cell, each connected to one of a plurality of word lines and configured to hold a threshold voltage corresponding to one of a plurality of data states, wherein the plurality of data states include the highest data state, and in the highest data state, the threshold voltage of the memory cell associated with the highest data state is higher than that of the other data states among the plurality of data states, The system comprises a control means, and the control means is Between each of the multiple program loops of the program operation, a series of programming pulses of program voltage and verification pulses of multiple program verification voltages, each associated with one of the multiple data states, following each of the series of programming pulses, are applied to a selected word line among the multiple word lines to program and verify the memory cell connected to the word line. A memory device configured such that, in at least one of the plurality of program loops, verification of the memory cell that is the target of the highest data state is skipped, The memory cells are disposed in memory holes, each coupled to one of a plurality of bit lines, and the memory device further includes a plurality of data latches, each configured to store data to be programmed during the program operation and to control one of the plurality of bit lines to allow or prohibit programming of the memory cells in the memory holes coupled to one of the plurality of bit lines, each of the plurality of data latches storing one bit to define a bit combination, and the control means, Based on the data programmed into the memory cell, the threshold voltage of the memory cell, and which of the plurality of data states is programmed and verified during the program operation, the plurality of data latches are operated and updated. A memory device further configured to update the plurality of data latches to track the amount of subsequent program loops among the plurality of program loops for each of the memory cells targeted to be programmed to the highest data state, using one or more of the bit combinations.

2. Each of the memory cells is configured to store 3 bits, and the plurality of data states include, in order of increasing threshold voltage magnitude, an erased data state, a first data state, a second data state, a third data state, a fourth data state, a fifth data state, a sixth data state, and a seventh data state, the highest data state being the seventh data state, and the plurality of data latches include a first data latch, a second data latch, and a third data latch, each configured to store the data programmed during the program operation, and the plurality of data latches includes a fourth data latch, configured to control one of the plurality of bit lines to allow or prohibit programming of the memory cell of the memory hole coupled to one of the plurality of bit lines, and the bit combination includes 16 bit combinations, and the control means is In response to one of the memory cells having a threshold voltage greater than one of the multiple program verification voltages associated with the sixth data state, detected during one of the verification pulses of the multiple program verification voltages associated with the sixth data state, at least one of the first, second, third, and fourth data latches associated with each memory cell of the memory cells subject to the seventh data state is updated to the first unused bit combination of the 16 bit combinations. From the first unused bit combination of the 16 bit combinations, at least one of the first, second, third, and fourth data latches associated with one of the memory cells subject to the seventh data state is updated with the second unused bit combination of the 16 bit combinations, following the application of a first subsequent programming pulse of the series of programming pulses of the program voltage to one of the memory cells subject to the seventh data state. The memory device according to claim 1, further configured to update at least one of the first, second, third, and fourth data latches associated with one of the memory cells subject to the seventh data state, from the second unused bit combination of the sixteen bit combinations, to one of the sixteen bit combinations associated with the erased data state, following the application of a second subsequent programming pulse of the series of programming pulses of the program voltage to one of the memory cells subject to the seventh data state, to prohibit programming of the one of the memory cells subject to the seventh data state.

3. A memory cell, each connected to one of a plurality of word lines and configured to hold a threshold voltage corresponding to one of a plurality of data states, wherein the plurality of data states include the highest data state, and in the highest data state, the threshold voltage of the memory cell associated with the highest data state is higher than that of the other data states among the plurality of data states, The system comprises a control means, and the control means is Between each of the multiple program loops of the program operation, a series of programming pulses of program voltage and verification pulses of multiple program verification voltages, each associated with one of the multiple data states, following each of the series of programming pulses, are applied to a selected word line among the multiple word lines to program and verify the memory cell connected to the word line. A memory device configured such that, in at least one of the plurality of program loops, verification of the memory cell that is the target of the highest data state is skipped, The plurality of data states include, in order of increasing magnitude of the threshold voltage, the erased data state, the next highest data state, and the highest data state, and the control means, Before the next highest data state completes verification, the memory cells among the memory cells are programmed and verified using the series of programming pulses of the program voltage and the verification pulses of the plurality of program verification voltages associated with the series of programming pulses, following the series of programming pulses, and the memory cells having a threshold voltage greater than one of the plurality of verification voltages of the plurality of data states to be targeted are locked out from further programming. After the next highest data state has completed verification, further verification of the memory cell among the memory cells that are the target of the highest data state is stopped, and the subsequent program loop among the plurality of program loops is counted. A memory device further configured to prohibit programming of the memory cell among the memory cells subject to the highest data state in response to the amount of the subsequent program loop among the plurality of program loops exceeding a predetermined low-speed cell count threshold.

4. Each of the memory cells is configured to store 3 bits, and the plurality of data states include, in order of increasing threshold voltage magnitude, the erased data state, the first data state, the second data state, the third data state, the fourth data state, the fifth data state, the sixth data state, and the seventh data state, the next highest data state being the sixth data state, the highest data state being the seventh data state, and the control means, Before the verification of the sixth data state is completed, the memory cells among the memory cells subject to the first, second, third, fourth, fifth, sixth, and seventh data states are programmed and verified using the series of programming pulses of the program voltage and the verification pulses of the plurality of program verification voltages associated with the series of programming pulses, following the series of programming pulses, and the memory cells having a threshold voltage greater than one of the plurality of verification voltages of one of the plurality of data states are locked out from further programming in response that the memory cells among the memory cells subject to the sixth and seventh data states do not have a threshold voltage greater than one of the plurality of verification voltages associated with the sixth data state. After the next highest data state has completed verification, in response to the memory cell among the memory cells subject to the sixth and seventh data states having a threshold voltage greater than one of the plurality of verification voltages associated with the sixth data state, further verification of the memory cell among the memory cells subject to the seventh data state is stopped, and the subsequent program loop among the plurality of program loops is counted. The memory device according to claim 3, further configured to prohibit programming of the memory cell among the memory cells subject to the seventh data state in response to the amount of the subsequent program loop among the plurality of program loops exceeding a predetermined low-speed cell count threshold.

5. A memory cell, each connected to one of a plurality of word lines and configured to hold a threshold voltage corresponding to one of a plurality of data states, wherein the plurality of data states include the highest data state, and in the highest data state, the threshold voltage of the memory cell associated with the highest data state is higher than that of the other data states among the plurality of data states, The system comprises a control means, and the control means is Between each of the multiple program loops of the program operation, a series of programming pulses of program voltage and verification pulses of multiple program verification voltages, each associated with one of the multiple data states, following each of the series of programming pulses, are applied to a selected word line among the multiple word lines to program and verify the memory cell connected to the word line. A memory device configured such that, in at least one of the plurality of program loops, verification of the memory cell that is the target of the highest data state is skipped, The memory cells are disposed in memory holes, each coupled to one of a plurality of bit lines, and the memory device further includes a plurality of data latches, each configured to store data to be programmed during the program operation and to control one of the plurality of bit lines to allow or prohibit programming of the memory cells in the memory holes coupled to one of the plurality of bit lines, each of the plurality of data latches storing one bit to define a bit combination, and the plurality of data states include, in order of increasing magnitude of the threshold voltage, an erased data state, the next highest data state, and the highest data state, and the control means, Before the next highest data state completes verification, the memory cells among the memory cells are programmed and verified using the series of programming pulses of the program voltage and the verification pulses of the plurality of program verification voltages associated with the series of programming pulses, following the series of programming pulses, and the memory cells having a threshold voltage greater than one of the plurality of verification voltages of the plurality of data states to be targeted are locked out from further programming. A memory device further configured to stop further verification of the memory cells among the memory cells subject to the highest data state after the verification of the next highest data state has been completed, and to update the plurality of data latches to track the amount of subsequent program loops among the plurality of program loops for each of the memory cells subject to being programmed to the highest data state using one or more of the bit combinations.

6. Each of the memory cells is configured to store 3 bits, and the plurality of data states include, in order of increasing threshold voltage magnitude, an erased data state, a first data state, a second data state, a third data state, a fourth data state, a fifth data state, a sixth data state, and a seventh data state, the highest data state being the seventh data state, and the plurality of data latches include a first data latch, a second data latch, and a third data latch, each configured to store the data programmed during the program operation, and the plurality of data latches includes a fourth data latch, configured to control one of the plurality of bit lines to allow or prohibit programming of the memory cell of the memory hole coupled to one of the plurality of bit lines, and the bit combination includes 16 bit combinations, and the control means is Before the verification of the sixth data state is completed, in response to one of the memory cells having a threshold voltage greater than one of the multiple program verification voltages associated with the sixth data state, detected during one of the verification pulses of the multiple program verification voltages associated with the sixth data state, at least one of the first, second, third, and fourth data latches associated with each memory cell of the memory cells subject to the seventh data state is updated to a first unused bit combination of the 16 bit combinations. Before the verification of the sixth data state is completed, at least one of the first, second, third, and fourth data latches associated with one of the memory cells subject to the seventh data state is updated to one of the 16 bit combinations associated with the erased data state in response to the detection during one of the verification pulses of one of the plurality of program verification voltages associated with the seventh data state that the one of the memory cells has a threshold voltage greater than one of the plurality of program verification voltages associated with the seventh data state, to prohibit programming of the one of the memory cells subject to the seventh data state. Before the verification of the sixth data state is completed, at least one of the first, second, third, and fourth data latches associated with one of the memory cells subject to the seventh data state, from the first unused bit combination of the sixteen bit combinations, is updated to the second unused bit combination of the sixteen bit combinations, following the application of one of the series of programming pulses of the program voltage to one of the memory cells subject to the seventh data state. After the verification of the sixth data state is complete, at least one of the first, second, third, and fourth data latches associated with one of the memory cells subject to the seventh data state, from the second unused bit combination of the sixteen bit combinations, from the first unused bit combination of the sixteen bit combinations, is updated to one of the sixteen bit combinations associated with the erased data state, in response to the application of a first subsequent programming pulse of the series of programming pulses of the program voltage to one of the memory cells subject to the seventh data state, so as to prohibit programming of one of the memory cells subject to the seventh data state, in response to the memory cell subject to the seventh data state having a threshold voltage greater than one of the plurality of verification voltages associated with the sixth data state and smaller than one of the plurality of verification voltages associated with the seventh data state. After the verification of the sixth data state is complete, at least one of the first, second, third, and fourth data latches associated with one of the memory cells subject to the seventh data state, from the first unused bit combination of the sixteen bit combinations, is updated to the second unused bit combination of the sixteen bit combinations, following the application of a second subsequent programming pulse of the series of programming pulses of the program voltage to one of the memory cells subject to the seventh data state, in response that the memory cell subject to the seventh data state has the threshold voltage which is greater than one of the plurality of verification voltages associated with the sixth data state and less than one of the plurality of verification voltages associated with the seventh data state, according to claim 5.

7. A controller for communicating with a memory device including memory cells, each memory cell connected to one of a plurality of word lines and configured to hold a threshold voltage corresponding to one of a plurality of data states, wherein the plurality of data states include the highest data state, and in the highest data state, the threshold voltage of the memory cell associated with the highest data state is higher than that of the other data states among the plurality of data states, the controller Between each of the multiple program loops of the program operation, the memory device is instructed to program and verify the memory cell connected to the word line by applying each of a series of programming pulses of program voltage and each of a series of verification pulses of program verification voltage, each associated with one of the multiple data states, to a selected word line among the multiple word lines. A controller configured to instruct the memory device to skip the verification of the memory cell that is the target of the highest data state in at least one of the plurality of program loops, The memory cells are disposed in memory holes, each coupled to one of a plurality of bit lines, and the memory device further includes a plurality of data latches, each configured to store data to be programmed during the program operation and to control one of the plurality of bit lines to allow or prohibit programming of the memory cells in the memory holes coupled to one of the plurality of bit lines, each of the plurality of data latches storing one bit to define a bit combination, and the controller, The memory device is instructed to operate and update the plurality of data latches based on the data programmed in the memory cell, the threshold voltage of the memory cell, and which of the plurality of data states is programmed and verified during the program operation. A controller further configured to instruct the memory device to update the plurality of data latches to track the amount of subsequent program loops among the plurality of program loops for each of the memory cells targeted to be programmed to the highest data state, using one or more of the bit combinations.

8. Each of the memory cells is configured to store 3 bits, and the plurality of data states include, in order of increasing threshold voltage magnitude, an erased data state, a first data state, a second data state, a third data state, a fourth data state, a fifth data state, a sixth data state, and a seventh data state, the highest data state being the seventh data state, and the plurality of data latches include a first data latch, a second data latch, and a third data latch, each configured to store the data to be programmed during the program operation, and the plurality of data latches includes a fourth data latch, configured to control one of the plurality of bit lines to allow or prohibit programming of the memory cell of the memory hole coupled to one of the plurality of bit lines, and the bit combinations include 16 bit combinations, and the controller is, In response to the fact that one of the memory cells has a threshold voltage greater than one of the multiple program verification voltages associated with the sixth data state, detected during one of the verification pulses of the multiple program verification voltages associated with the sixth data state, the memory device is instructed to update at least one of the first, second, third, and fourth data latches associated with each memory cell of the memory cells subject to the seventh data state to the first unused bit combination of the 16 bit combinations, The memory device is instructed to update at least one of the first, second, third, and fourth data latches associated with one of the memory cells subject to the seventh data state, from the first unused bit combination of the sixteen bit combinations, to the second unused bit combination of the sixteen bit combinations, following the application of a first subsequent programming pulse of the series of programming pulses of the program voltage to one of the memory cells subject to the seventh data state. The controller according to claim 7, further configured to instruct the memory device to update at least one of the first, second, third, and fourth data latches associated with one of the memory cells subject to the seventh data state, from the second unused bit combination of the sixteen bit combinations, to one of the sixteen bit combinations associated with the erased data state, following the application of a second subsequent programming pulse of the series of programming pulses of the program voltage to one of the memory cells subject to the seventh data state, to prohibit programming of that memory cell subject to the seventh data state.

9. A controller for communicating with a memory device including memory cells, each of which is connected to one of a plurality of word lines and configured to hold a threshold voltage corresponding to one of a plurality of data states, wherein the plurality of data states include a highest data state, and in the highest data state, the threshold voltage of the memory cell associated with the highest data state is higher than that of the other data states among the plurality of data states, the controller Between each of the multiple program loops of the program operation, the memory device is instructed to program and verify the memory cell connected to the word line by applying each of a series of programming pulses of program voltage and each of a series of verification pulses of program verification voltage, each associated with one of the multiple data states, to a selected word line among the multiple word lines. A controller configured to instruct the memory device to skip the verification of the memory cell that is the target of the highest data state in at least one of the plurality of program loops, The plurality of data states include, in order of increasing threshold voltage magnitude, the erased data state, the next highest data state, and the highest data state, and the controller, Before the next highest data state completes verification, the memory device is instructed to program and verify a memory cell among the memory cells using the series of programming pulses of the program voltage and the verification pulses of the plurality of program verification voltages associated with the series of programming pulses, and to lock out any memory cell having a threshold voltage greater than one of the plurality of verification voltages among the plurality of data states of interest from further programming. After the verification of the next highest data state is completed, the memory device is instructed to stop further verification of the memory cell among the memory cells that are the target of the highest data state and to count the subsequent program loop among the plurality of program loops. A controller further configured to prohibit programming of the memory cell among the memory cells subject to the highest data state in response to the amount of the subsequent program loop among the plurality of program loops exceeding a predetermined low-speed cell count threshold.

10. Each of the memory cells is configured to store 3 bits, and the plurality of data states include, in order of increasing threshold voltage magnitude, the erased data state, the first data state, the second data state, the third data state, the fourth data state, the fifth data state, the sixth data state, and the seventh data state, the next highest data state being the sixth data state, the highest data state being the seventh data state, and the controller, Before the verification of the sixth data state is completed, the memory cells among the memory cells subject to the first data state, the second data state, the third data state, the fourth data state, the fifth data state, the sixth data state, and the seventh data state are programmed and verified using the series of programming pulses of the program voltage and the verification pulses of the plurality of program verification voltages associated with the series of programming pulses, following the series of programming pulses, and the memory device is instructed to lock out any memory cell having a threshold voltage greater than one of the plurality of verification voltages of one of the plurality of data states, in response to the memory cell among the memory cells subject to the sixth data state and the seventh data state not having a threshold voltage greater than one of the plurality of verification voltages associated with the sixth data state. After the next highest data state has completed verification, in response to the memory cell among the memory cells subject to the sixth and seventh data states having a threshold voltage greater than one of the plurality of verification voltages associated with the sixth data state, the memory device is instructed to stop further verification of the memory cell among the memory cells subject to the seventh data state and to count the subsequent program loop among the plurality of program loops. The controller according to claim 9, further configured to instruct the memory device to prohibit programming of the memory cells among the memory cells subject to the seventh data state in response to the amount of the subsequent program loop among the plurality of program loops exceeding a predetermined low-speed cell count threshold.

11. A controller for communicating with a memory device including memory cells, each of which is connected to one of a plurality of word lines and configured to hold a threshold voltage corresponding to one of a plurality of data states, wherein the plurality of data states include a highest data state, and in the highest data state, the threshold voltage of the memory cell associated with the highest data state is higher than that of the other data states among the plurality of data states, the controller Between each of the multiple program loops of the program operation, the memory device is instructed to program and verify the memory cell connected to the word line by applying each of a series of programming pulses of program voltage and each of a series of verification pulses of program verification voltage, each associated with one of the multiple data states, to a selected word line among the multiple word lines. A controller configured to instruct the memory device to skip the verification of the memory cell that is the target of the highest data state in at least one of the plurality of program loops, The memory cells are disposed in memory holes, each coupled to one of a plurality of bit lines, and the memory device further includes a plurality of data latches, each configured to store data to be programmed during the program operation and to control one of the plurality of bit lines to allow or prohibit programming of the memory cells in the memory holes coupled to one of the plurality of bit lines, each of the plurality of data latches storing one bit to define a bit combination, and the plurality of data states include, in order of increasing magnitude of the threshold voltage, an erased data state, the next highest data state, and the highest data state, and the controller, Before the next highest data state completes verification, the memory device is instructed to program and verify a memory cell among the memory cells using the series of programming pulses of the program voltage and the verification pulses of the plurality of program verification voltages associated with the series of programming pulses, and to lock out any memory cell having a threshold voltage greater than one of the plurality of verification voltages among the plurality of data states of interest from further programming. A controller further configured to stop further verification of the memory cells among the memory cells subject to the next highest data state after the verification of the next highest data state has been completed, and to instruct the memory device to update the plurality of data latches to track the amount of subsequent program loops among the plurality of program loops for each of the memory cells subject to being programmed to the highest data state using one or more of the bit combinations.

12. A method for operating a memory device including memory cells, each connected to one of a plurality of word lines and configured to hold a threshold voltage corresponding to one of a plurality of data states, wherein the plurality of data states include a highest data state, and in the highest data state, the threshold voltage of the memory cell associated with the highest data state is higher than that of the other data states among the plurality of data states, The steps of programming and verifying the memory cell connected to the word line by applying each of a series of programming pulses of program voltage and each of a series of verification pulses of program verification voltage, each associated with one of the multiple data states, to a selected word line among the multiple word lines, between each of the multiple program loops of the program operation, A method comprising the step of skipping verification of the memory cell that is subject to the highest data state in at least one of the plurality of program loops, The memory cell is disposed in a memory hole, each coupled to one of a plurality of bit lines, and the memory device further includes a plurality of data latches, each configured to store data to be programmed during the program operation and to control one of the plurality of bit lines to allow or prohibit programming of the memory cell in the memory hole coupled to one of the plurality of bit lines, each of the plurality of data latches storing one bit to define a bit combination, and the method is A step of operating and updating the plurality of data latches based on the data programmed in the memory cell, the threshold voltage of the memory cell, and which of the plurality of data states is programmed and verified during the program operation. A method further comprising the step of updating the plurality of data latches to track the amount of subsequent program loops among the plurality of program loops for each of the memory cells targeted to be programmed to the highest data state, using one or more of the bit combinations.

13. Each of the memory cells is configured to store 3 bits, and the plurality of data states include, in order of increasing threshold voltage, an erased data state, a first data state, a second data state, a third data state, a fourth data state, a fifth data state, a sixth data state, and a seventh data state, the highest data state being the seventh data state, and the plurality of data latches include a first data latch, a second data latch, and a third data latch, each configured to store the data to be programmed during the program operation, and the plurality of data latches includes a fourth data latch, configured to control one of the plurality of bit lines to allow or prohibit programming of the memory cell of the memory hole coupled to one of the plurality of bit lines, and the bit combination includes 16 bit combinations, and the method is In response to the fact that one of the memory cells has a threshold voltage greater than one of the multiple program verification voltages associated with the sixth data state, detected during one of the verification pulses of the multiple program verification voltages associated with the sixth data state, the step of updating at least one of the first data latch, second data latch, third data latch, and fourth data latch associated with each memory cell of the memory cells subject to the seventh data state to the first unused bit combination of the 16 bit combinations, The steps include updating at least one of the first, second, third, and fourth data latches associated with one of the memory cells subject to the seventh data state, from the first unused bit combination of the sixteen bit combinations, to the second unused bit combination of the sixteen bit combinations, following the application of a first subsequent programming pulse of the series of programming pulses of the program voltage to one of the memory cells subject to the seventh data state; The method according to claim 12, further comprising the step of updating at least one of the first, second, third, and fourth data latches associated with one of the memory cells subject to the seventh data state, from the second unused bit combination of the sixteen bit combinations, to one of the sixteen bit combinations associated with the erased data state, following the application of a second subsequent programming pulse of the series of programming pulses of the program voltage to one of the memory cells subject to the seventh data state, to prohibit programming of that memory cell subject to the seventh data state.

14. A method for operating a memory device including memory cells, each connected to one of a plurality of word lines and configured to hold a threshold voltage corresponding to one of a plurality of data states, wherein the plurality of data states include a highest data state, and in the highest data state, the threshold voltage of the memory cell associated with the highest data state is higher than that of the other data states of the plurality of data states, The steps of programming and verifying the memory cell connected to the word line by applying each of a series of programming pulses of program voltage and each of a series of verification pulses of program verification voltage, each associated with one of the multiple data states, to a selected word line among the multiple word lines, between each of the multiple program loops of the program operation, A method comprising the step of skipping verification of the memory cell that is subject to the highest data state in at least one of the plurality of program loops, The plurality of data states include, in order of increasing magnitude of the threshold voltage, the erased data state, the next highest data state, and the highest data state, and the method is, Before the next highest data state completes verification, the memory cells among the memory cells are programmed and verified using the series of programming pulses of the program voltage and the verification pulses of the plurality of program verification voltages associated with the series of programming pulses, and the memory cells having a threshold voltage greater than one of the plurality of verification voltages among the plurality of data states of interest are locked out from further programming. After the verification of the next highest data state is completed, the further verification of the memory cell among the memory cells that are the target of the highest data state is stopped, and the subsequent program loop among the plurality of program loops is counted. A method further comprising the step of prohibiting programming of the memory cell among the memory cells subject to the highest data state in response to the amount of the subsequent program loop among the plurality of program loops exceeding a predetermined slow cell count threshold.

15. Each of the memory cells is configured to store 3 bits, and the plurality of data states include, in order of increasing threshold voltage, the erased data state, the first data state, the second data state, the third data state, the fourth data state, the fifth data state, the sixth data state, and the seventh data state, the next highest data state being the sixth data state, and the highest data state being the seventh data state, and the method is, Before the verification of the sixth data state is completed, the memory cells among the memory cells subject to the first data state, the second data state, the third data state, the fourth data state, the fifth data state, the sixth data state, and the seventh data state are programmed and verified using the series of programming pulses of the program voltage and the verification pulses of the plurality of program verification voltages associated with the series of programming pulses, following the series of programming pulses, and the memory cells having a threshold voltage greater than one of the plurality of verification voltages of one of the plurality of data states are locked out from further programming in response that the memory cells among the memory cells subject to the sixth data state and the seventh data state do not have a threshold voltage greater than one of the plurality of verification voltages associated with the sixth data state. After the next highest data state has completed verification, the memory cell among the memory cells subject to the sixth and seventh data states has a threshold voltage greater than one of the plurality of verification voltages associated with the sixth data state, in response to this, the further verification of the memory cell among the memory cells subject to the seventh data state is stopped, and the subsequent program loops among the plurality of program loops are counted. The method according to claim 14, further comprising the step of prohibiting programming of the memory cell among the memory cells subject to the seventh data state in response to the amount of the subsequent program loop among the plurality of program loops exceeding the predetermined slow cell count threshold.

16. A method for operating a memory device including memory cells, each connected to one of a plurality of word lines and configured to hold a threshold voltage corresponding to one of a plurality of data states, wherein the plurality of data states include a highest data state, and in the highest data state, the threshold voltage of the memory cell associated with the highest data state is higher than that of the other data states of the plurality of data states, The steps of programming and verifying the memory cell connected to the word line by applying each of a series of programming pulses of program voltage and each of a series of verification pulses of program verification voltage, each associated with one of the multiple data states, to a selected word line among the multiple word lines, between each of the multiple program loops of the program operation, A method comprising the step of skipping verification of the memory cell that is subject to the highest data state in at least one of the plurality of program loops, The memory cells are disposed in memory holes, each coupled to one of a plurality of bit lines, and the memory device further includes a plurality of data latches, each configured to store data to be programmed during the program operation and to control one of the plurality of bit lines to allow or prohibit programming of the memory cells in the memory holes coupled to one of the plurality of bit lines, each of the plurality of data latches storing one bit to define a bit combination, and the plurality of data states include, in order of increasing magnitude of the threshold voltage, an erased data state, then the highest data state, and the highest data state, and the method is Before the next highest data state completes verification, the memory cells among the memory cells are programmed and verified using the series of programming pulses of the program voltage and the verification pulses of the plurality of program verification voltages associated with the series of programming pulses, and the memory cells having a threshold voltage greater than one of the plurality of verification voltages among the plurality of data states of interest are locked out from further programming. A method further comprising the steps of: stopping further verification of the memory cells among the memory cells subject to the next highest data state after the verification of the next highest data state has been completed; and updating the plurality of data latches to track the amount of subsequent program loops among the plurality of program loops for each of the memory cells subject to being programmed to the highest data state using one or more of the bit combinations.

17. Each of the memory cells is configured to store 3 bits, and the plurality of data states include, in order of increasing threshold voltage, an erased data state, a first data state, a second data state, a third data state, a fourth data state, a fifth data state, a sixth data state, and a seventh data state, the highest data state being the seventh data state, and the plurality of data latches include a first data latch, a second data latch, and a third data latch, each configured to store the data to be programmed during the program operation, and the plurality of data latches includes a fourth data latch, configured to control one of the plurality of bit lines to allow or prohibit programming of the memory cell of the memory hole coupled to one of the plurality of bit lines, and the bit combination includes 16 bit combinations, and the method is Before the verification of the sixth data state is completed, in response to the fact that one of the memory cells has a threshold voltage greater than one of the multiple program verification voltages associated with the sixth data state, detected during one of the verification pulses of the multiple program verification voltages associated with the sixth data state, at least one of the first data latch, second data latch, third data latch, and fourth data latch associated with each memory cell of the memory cells subject to the seventh data state is updated to a first unused bit combination of the 16 bit combinations; Before the verification of the sixth data state is completed, update at least one of the first, second, third, and fourth data latches associated with one of the memory cells subject to the seventh data state to one of the 16 bit combinations associated with the erased data state, in response to the detection during one of the verification pulses of one of the plurality of program verification voltages associated with the seventh data state that one of the memory cells has a threshold voltage greater than one of the plurality of program verification voltages associated with the seventh data state, to prohibit programming of the one of the memory cells subject to the seventh data state; Before the verification of the sixth data state is completed, the steps include updating at least one of the first, second, third, and fourth data latches associated with one of the memory cells subject to the seventh data state, from the first unused bit combination of the sixteen bit combinations to the second unused bit combination of the sixteen bit combinations, following the application of one of the series of programming pulses of the program voltage to one of the memory cells subject to the seventh data state, After the verification of the sixth data state is complete, the steps include updating at least one of the first, second, third, and fourth data latches associated with one of the memory cells subject to the seventh data state, from the second unused bit combination of the sixteen bit combinations, from the first unused bit combination of the sixteen bit combinations, to one of the sixteen bit combinations associated with the erased data state, in response to the one of the memory cells subject to the seventh data state having a threshold voltage greater than one of the plurality of verification voltages associated with the sixth data state and smaller than one of the plurality of verification voltages associated with the seventh data state, following the application of a first subsequent programming pulse of the series of programming pulses of the program voltage to the one of the memory cells subject to the seventh data state, to prohibit programming of the one of the memory cells subject to the seventh data state; The method according to claim 16, further comprising the step of updating, after the verification of the sixth data state has been completed, at least one of the first, second, third, and fourth data latches associated with one of the memory cells subject to the seventh data state from a first unused bit combination of the sixteen bit combinations to the one of the memory cells subject to the seventh data state, following the application of a second subsequent programming pulse of the series of programming pulses of the program voltage to the one of the memory cells subject to the seventh data state, in response that the one of the memory cells subject to the seventh data state has a threshold voltage greater than one of the plurality of verification voltages associated with the sixth data state and less than one of the plurality of verification voltages associated with the seventh data state.

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