Adjustment of the voltage setpoint in pulsed RF signals for adjustable edge sheath systems.

Abstract

To provide a method for tuning a voltage setpoint for a multi-state pulsed RF signal in a plasma processing system.SOLUTION: The method includes: applying RF power from a first generator to an electrostatic chuck (ESC), where the RF power from the first generator defines a first multi-state pulsed RF signal; applying RF power from a second generator to an edge electrode that surrounds the ESC and is disposed below an edge ring that surrounds the ESC, where the RF power from the second generator defines a second multi-state pulsed RF signal having a first state and a second state, where, for each state of the second multi-state pulsed RF signal, the second generator automatically introduces a phase adjustment to substantially match phase with a corresponding state of the first multi-state pulsed RF signal; and adjusting a voltage setpoint for the second state of the second multi-state pulsed RF signal to tune the phase adjustment to a target phase adjustment setting.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] This disclosure relates to the manufacture of semiconductor devices. [Background technology]

[0002] Plasma etching is a frequently used process in the manufacturing of semiconductor devices on semiconductor wafers. In plasma etching, a semiconductor wafer containing the semiconductor device being manufactured is exposed to plasma generated within a plasma processing volume. The plasma interacts with the material on the semiconductor wafer, thereby removing and / or altering the material, which can then be removed from the wafer. Plasma can be generated using specific reactive gases, which interact with the plasma components and the material being removed / modified from the semiconductor wafer, without significant interaction with other materials on the wafer that should not be removed / modified. Plasma is generated using high-frequency signals that energize the specific reactive gases. These high-frequency signals are transmitted through the plasma processing volume containing the reactive gases while the semiconductor wafer is exposed to it. The transmission path of the high-frequency signals through the plasma processing volume can influence the form in which the plasma is generated within the plasma processing volume. For example, in regions of the plasma processing volume where more high-frequency signal power is transmitted, more energy may be imparted to the reaction gas, thereby causing spatial non-uniformity of the plasma properties throughout the plasma processing volume. This spatial non-uniformity of plasma properties can manifest as spatial non-uniformity of ion density, ion energy, and / or reactive component density, among other plasma properties. This spatial non-uniformity of plasma properties can, in turn, cause spatial non-uniformity of the plasma processing results on the semiconductor wafer. Therefore, the manner in which the high-frequency signal is transmitted through the plasma processing volume can affect the uniformity of the plasma processing results on the semiconductor wafer. It is in this context that the present disclosure arises. [Overview of the Initiative]

[0003] Broadly speaking, embodiments of the present disclosure provide a method and system for adjusting the voltage setpoint of the secondary state of a pulsed RF signal in an adjustable edge sheath (TES) system, wherein the edge electrode is powered separately and independently from the main electrode of an electrostatic chuck (ESC).

[0004] In some implementations, a method is provided for adjusting a voltage setpoint for a multi-state pulsed RF signal in a plasma processing system, the method comprising: applying RF power from a first generator to an ESC, the RF power from the first generator defining a first multi-state pulsed RF signal; applying RF power from a second generator to an edge electrode located beneath an edge ring surrounding the ESC, the RF power from the second generator defining a second multi-state pulsed RF signal having a first state and a second state, the second generator automatically introducing a phase adjustment for each state of the second multi-state pulsed RF signal to substantially match the phase of the first multi-state pulsed RF signal to the corresponding state; and adjusting a voltage setpoint for the second state of the second multi-state pulsed RF signal to adjust the phase adjustment to a target phase adjustment setting.

[0005] In some implementations, the target phase adjustment setting is captured via the user interface.

[0006] In some implementations, the target phase adjustment setting is calculated based on the model.

[0007] In some implementations, the target phase adjustment setting defines a predetermined amount of phase adjustment used when the phase of the RF power from the second generator is adjusted.

[0008] In some implementations, adjusting the voltage setpoint to adjust the phase adjustment involves making stepwise adjustments to the voltage setpoint until the phase adjustment reaches the target phase adjustment setting.

[0009] In some implementations, stepwise adjustment is based on a specific voltage setpoint associated with the first state of the second multi-state pulsed RF signal.

[0010] In some implementations, the phase adjustment is adjusted to the target phase adjustment setting when the phase adjustment reaches the target phase adjustment setting or when the phase adjustment is within a predetermined range of the target phase adjustment setting.

[0011] In some implementations, by adjusting the voltage setpoint and adjusting the phase adjustment to the target phase adjustment setting, the voltage setpoint is positioned in the middle of the allowable range of the voltage setpoint.

[0012] In some implementations, the target phase adjustment setting, which facilitates the positioning of the voltage setpoint in the middle of the allowable range of the voltage setpoint, remains substantially the same with respect to changes in the capacitance of the matching circuit through which the RF power from the second generator passes when applied to the edge electrode.

[0013] In some implementations, a change in the capacitance of the matching circuit responds to a change in the voltage setpoint of the first state of the second multi-state pulsed RF signal.

[0014] In some implementations, the change in the voltage setpoint of the first state occurs based on the amount of edge ring usage.

[0015] In some implementations, the amount of edge ring usage is defined as the amount of time the edge ring is exposed to RF.

[0016] In some implementations, a method is provided for adjusting the voltage setpoint for a multi-state pulsed RF signal in a plasma processing system, the method comprising: applying RF power from a first generator to an ESC, wherein the RF power from the first generator defines a first pulsed RF signal having a first state and a second state; and applying RF power from a second generator to an edge electrode located below the edge ring surrounding the ESC, wherein the RF power from the second generator defines a second pulsed RF signal having a first state and a second state, the second generator being... The second generator automatically introduces a first phase adjustment to substantially match the phase of the first state of the second pulse RF signal to the first state of the second pulse RF signal, and the second generator automatically introduces a second phase adjustment to substantially match the phase of the second state of the second pulse RF signal to the second state of the first pulse RF signal, with the second phase adjustment being adjusted to a target phase adjustment setting; and in response to detecting a change in the second phase adjustment that causes it to deviate from the target phase adjustment setting, the second generator adjusts the voltage setpoint for the second state of the second pulse RF signal to return the second phase adjustment to the target phase adjustment setting.

[0017] In some implementations, the target phase adjustment setting is captured via the user interface.

[0018] In some implementations, the target phase adjustment setting is calculated based on the model.

[0019] In some implementations, the target phase adjustment setting defines a predetermined phase adjustment amount used when the phase of the second state of the second pulse RF signal is adjusted.

[0020] In some implementations, adjusting the voltage setpoint to restore the second phase adjustment involves performing stepwise adjustments to the voltage setpoint until the second phase adjustment reaches the target phase adjustment setting.

[0021] In some implementations, stepwise adjustment is based on a specific voltage setpoint associated with the first state.

[0022] In some implementation modes, when the second phase adjustment reaches the target phase adjustment setting, or when the second phase adjustment is within a predetermined range of the target phase adjustment setting, the second phase adjustment is restored to the target phase adjustment setting.

[0023] In some implementation modes, by adjusting the voltage set point to restore the second phase adjustment to the target phase adjustment setting, the voltage set point is positioned at an intermediate portion of the allowable range of the voltage set point.

[0024] In some implementation modes, the target phase adjustment setting that facilitates positioning the voltage set point at the intermediate portion of the allowable range of the voltage set point remains substantially unchanged with respect to changes in the capacitance of a matching circuit through which RF power from a second generator passes when applied to an edge electrode.

[0025] In some implementation modes, a change in the capacitance of the matching circuit is responsive to a change in the voltage set point in a first state of a second pulsed RF signal.

[0026] In some implementation modes, a change in the voltage set point in the first state of the second pulsed RF signal occurs based on an amount of usage of an edge ring.

[0027] In some implementation modes, the amount of usage of the edge ring is defined as an amount of time that the edge ring is exposed to RF. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] [Figure 1] Figure 1 shows a vertical cross-sectional view of a portion of a plasma processing system 100 for use in semiconductor chip manufacturing, in accordance with some embodiments.

[0029] [Figure 2] Figure 2 shows a vertical cross-sectional view of a plasma processing system for use in semiconductor chip manufacturing, in accordance with some embodiments.

[0030] [Figure 3]Figure 3 shows an exemplary schematic circuit diagram of a TES impedance matching system according to several embodiments.

[0031] [Figure 4] Figure 4 conceptually shows the components of the TES high-frequency signal generator 403 according to the embodiment of this disclosure.

[0032] [Figure 5] Figure 5 shows the relationship between the voltage setpoint and time for the TES multi-state pulse RF signal generated by the TES RF signal generator 403 in an implementation of the present disclosure.

[0033] [Figure 6] Figure 6 is a graph conceptually showing the allowable range of the voltage setpoint for state S0 or S2 according to the implementation of this disclosure.

[0034] [Figure 7] Figure 7 is a graph conceptually illustrating the relationship between phase adjustment for state S0 / S2 and the voltage setpoint for state S0 / S2 in the implementation of this disclosure.

[0035] [Figure 8] Figure 8 conceptually illustrates a method for maintaining a voltage setpoint within a schematic intermediate range of acceptable voltage setpoints for the state of a pulsed RF signal, according to an implementation of this disclosure.

[0036] [Figure 9] Figure 9 is a graph that conceptually shows the change in the voltage setpoint for various states of a pulsed RF signal according to the implementation of this disclosure.

[0037] [Figure 10] Figure 10 shows an illustrative schematic diagram of the control system shown in Figure 2, according to several embodiments. [Modes for carrying out the invention]

[0038] The following description contains numerous specific details to provide an understanding of embodiments of the Disclosure. However, it will be apparent to those skilled in the art that the Disclosure can be carried out even without some or all of these specific details. Where otherwise, well-known process operations are not described in detail so as not to unnecessarily obscure the Disclosure.

[0039] In plasma etching systems for semiconductor wafer fabrication, the spatial variation of the etching results across the semiconductor wafer can be characterized by radial etching uniformity and azimuthal etching uniformity. Radial etching uniformity can be characterized by the variation in etching rate as a function of the radial position on the semiconductor wafer, extending outward from the center of the semiconductor wafer to the edge of the semiconductor wafer, at a given azimuthal position on the semiconductor wafer. Azimuthal etching uniformity can be characterized by the variation in etching rate as a function of the azimuthal position on the semiconductor wafer, around the center of the semiconductor wafer, at a given radial position on the semiconductor wafer. In some plasma processing systems, such as the systems described herein, the semiconductor wafer is placed on electrodes, and a high-frequency signal is emitted from the electrodes to generate plasma in a plasma generation region on the semiconductor wafer, and the plasma has properties controlled to produce a specified etching process on the semiconductor wafer.

[0040] Advances in two-state RF pulse application enable high aspect ratio etching by improving the relationship between process margin and etching selectivity, profile warpage, critical dimension (CD), and etching rate uniformity. In current two-state RF pulse nomenclature, "State 1" (or "S1") represents a state with high bias and source power, e.g., 1 kW, operating at a pressure of less than 30 mTorr and having an ion energy above 3 keV to obtain a narrow IAF. The other state in the pulse, referred to as "State 0" (or "S0"), represents a deposition step with low bias and source power, e.g., less than 1 kW, and an ion energy of less than 100 eV. State 0 primarily provides passivation resulting from different mechanisms such as direct ion deposition and ion-activated neutral deposition. Typical pulse repetition rates for operating this two-state RF pulse regime are approximately 100 Hz to 2 kHz.

[0041] Currently, state-of-the-art dielectric etching processes rely on the implementation of one or two RF regimes supported by on / off RF pulse application or level-level RF pulse application to combine the benefits of high vertical etching rates and sufficient sidewall passivation.

[0042] However, according to the realizations of this disclosure, additional regimes can independently recover or add more margin in the process. Realizations based on such regimes can incorporate suitable intermediate states based on the implementation of a multi-state RF pulse application scheme, which overcomes fundamental process development limitations and barriers in existing etching techniques. The intermediate states are based on selective trimming of mask neck polymers in low ion energy states to facilitate more aggressive high-energy states (on / high state) and more polymer-friendly passivation states (off / low state). Introducing such low ion energy states by source power serves only to control the neck / mask shape. Combining this technique with on-off pulse application instead of level-level pulse application results in more polymer deposition on the top of the mask, passivating the top of the mask and controlling the mask etching rate. This technique fundamentally breaks the trade-off between mask neck / process margin and selectivity ratio.

[0043] A pulsed RF cycle can be characterized as a three-level pulsed RF using three different states of RF. In some realizations, S1 is configured to supply high source power and high bias power. This results in high aspect ratio (HAR) etching, but also sputtering of the mask, causing a neck to form. S0 is configured as a low / off state where the applied source power or bias power is low / absent. S0 protects the mask by causing more neutral deposition on top. In some realizations, S0 is configured to provide direct ion deposition and ion-assisted neutral deposition.

[0044] In some implementations, the intermediate state S2 (state 2) is configured as a (substantially) source-power-only state (e.g., 60 MHz, high frequency) using low source power and very low or zero (or substantially zero) bias power. S2 causes dissociation and helps to open up any neck that may have formed by etching. Therefore, state S2 is configured to open up the neck.

[0045] In summary, according to the implementation of this disclosure, S1 uses high-energy ions to form a neck, S2 opens the neck, and S0 results in passivation. The resulting feature has an open neck and, furthermore, more mask due to the increased passivation. This raises the challenge of a trade-off between necking and selectivity.

[0046] In contrast, in a level-level RF pulse application regime where only S1 and S0 are activated, not only is there potentially very large passivation, but there can also be a neck, which tends to cause clogging. However, a three-level RF pulse application using S1, S0, and S2 provides an open neck and passivation, thereby breaking the trade-off between selectivity and cap margin. Roughly speaking, state S0 provides selectivity, while state S2 improves the cap margin.

[0047] Generally speaking, in some implementations, the bias power frequency is less than approximately 10 MHz. In some implementations, the bias power frequency is approximately 400 kHz.

[0048] In some implementations, the source power frequency exceeds approximately 10 MHz. In some implementations, the source power frequency exceeds approximately 20 MHz. In some implementations, the source power frequency is approximately 60 MHz.

[0049] While states S1, S0, and S2 described above relate to the RF power applied to the main electrode of the ESC, in plasma processing systems implementing a tunable edge sheath (TES) system, bias RF power is independently supplied to the edge electrodes surrounding the ESC, thereby enabling control of the plasma sheath and plasma characteristics in the wafer edge region. The RF power applied to the edge electrodes is synchronized with the main electrode and therefore includes the corresponding states S1, S0, and S2, but the attributes of these states in the TES RF signal are controlled independently of the main bias RF signal.

[0050] Figure 1 shows a partial vertical cross-sectional view of a plasma processing system 100 for use in semiconductor chip manufacturing, according to several embodiments. The plasma processing system 100 includes an electrode 109, which in some embodiments is made of aluminum. A ceramic layer 110 is formed on the upper surface of the electrode 109. The ceramic layer 110 is configured to receive and support the wafer W while the plasma processing operation is being performed on the wafer W. In some realizations, the ceramic layer 110, the electrode 109, and associated components define an electrostatic chuck (ESC).

[0051] A first high-frequency signal generator 147 (e.g., about 60 MHz) and a second high-frequency signal generator 149 (e.g., about 400 kHz) supply high-frequency power to the electrode 109 via an impedance matching system 143. By applying high-frequency power to a gas species introduced into the process space on the wafer, a plasma 180 for wafer processing, such as etching, is generated.

[0052] The edge ring 167 surrounds the ceramic layer 110 and is configured to facilitate the extension of the plasma sheath radially outward beyond the outer edge of the wafer W, thereby improving process results near the periphery of the wafer W.

[0053] The adjustable edge sheath (TES) system is implemented to include a TES electrode 415 positioned (embedded) within a coupling ring 161. A TES high-frequency signal generator 403 supplies high-frequency power to the TES electrode 415 via a TES impedance matching system 401. The TES system can control the properties of the plasma 180 near the outer edge of the wafer W, for example, by controlling the plasma sheath, plasma density, and ion attraction or repulsion properties. Broadly speaking, by applying high-frequency power to the TES electrode 415, the TES system enables the adjustment of the plasma at the wafer edge, improving radial uniformity.

[0054] For a given process recipe, process recipe parameters are set, and these parameters include parameters of the TES system that provide radial uniformity. For example, in the illustrated embodiment, high-frequency power is supplied by the TES high-frequency signal generator 403 to an edge ring 167 having an initial thickness J1, in a state S1 at a first voltage V1, which is configured to adjust the plasma sheath indicated by S1 to have a height H1 at the edge or peripheral region of the wafer W, above the upper surface of the wafer W.

[0055] However, during plasma processing, the edge ring 167 is partially consumed or worn down, and therefore, as RF time and process cycles accumulate, the thickness of the edge ring 167 gradually decreases. Thus, for example, during RF time lasting several hours, the thickness of the edge ring 167 may decrease from thickness J1 to thickness J2. With voltage V1 applied to state S1 during processing, as the thickness of the edge ring 167 decreases, the level of the plasma sheath also decreases. For example, if the thickness of the edge ring 167 is worn down to thickness J2, the plasma sheath will drop to the level indicated in S2, thereby reducing its height above the upper surface of the wafer W at the wafer edge to H2.

[0056] This reduction in edge ring thickness, and the resulting change in plasma sheath level at the wafer edge, leads to radial non-uniformity at the edge. For example, this can result in differences in etching rate between the wafer edge and the central portion (non-uniformity of etching rate and etching depth), and inclination of the feature profile at the edge (non-uniformity of etching direction).

[0057] Therefore, in order to offset the effects of edge ring wear / consumption and maintain the plasma sheath level despite the loss of edge ring thickness, the voltage applied to the TES electrode 415 for state S1 can be increased to a second voltage V2. In the illustrated embodiment, when a voltage V2 (greater than voltage V1) is applied by the TES high-frequency signal generator 403 for state S1, and the thickness of the edge sheath decreases to thickness J2, the plasma sheath recovers to the state shown in reference S1. That is, even if the thickness of the edge ring 167 decreases, the plasma sheath level is maintained in the TES system by applying an increased voltage for state S1.

[0058] However, increasing the voltage applied to the TES electrode 415 in state S1 changes the system impedance and causes an increase in the reflection of high-frequency power in state S1. To minimize the high-frequency power reflected in state S1, the capacitance setting in the TES impedance matching system 401 can be adjusted as will be discussed in more detail below.

[0059] It should be noted that the TES high-frequency signal generator 403 is configured to automatically adjust the phase of the generated high-frequency signal state S1 to match the phase of the high-frequency signal generated by the high-frequency signal generator 149 (for example, at 400 kHz). Therefore, as the voltage of state S1 applied to the TES electrode 415 increases, the TES high-frequency signal generator 401 is automatically adjusted to maintain phase matching with the state S1 of the high-frequency signal from the high-frequency signal generator 149. It has been found that by adjusting the capacitance setting in the TES impedance matching system to minimize reflection of high-frequency power, the (automatically occurring) phase adjustment by the TES high-frequency signal generator 403 results in its phase adjustment amount returning to the original voltage (the first voltage of state S1 before it was increased to compensate for edge ring wear). Therefore, the capacitance setting in the TES impedance matching system can be optimized using the phase adjustment amount for state S1.

[0060] Figure 2 shows a vertical cross-sectional view of a plasma processing system 100 for use in semiconductor chip manufacturing, according to several embodiments. The system 100 includes a chamber 101 formed by a wall 101A, an upper member 101B, and a bottom member 101C. Collectively, the wall 101A, the upper member 101B, and the bottom member 101C form an inner region 103 within the chamber 101. The bottom member 101C includes an exhaust port 105 into which exhaust gases from the plasma processing operation are introduced. In some embodiments, during operation, a suction force is applied at the exhaust port 105 by a turbopump or other vacuum device, etc., to draw process exhaust gases out of the inner region 103 of the chamber 101. In some embodiments, the chamber 101 is made of aluminum. However, in various embodiments, the chamber 101 can be formed from any material that provides sufficient mechanical strength and acceptable thermal performance, and is chemically compatible with other materials that the chamber interfaces with and to which the chamber is exposed during plasma processing operations within the chamber 101, such as stainless steel, among others. At least one wall 101A of the chamber 101 includes a door 107 through which the semiconductor wafer W is transferred into and out of the chamber 101. In some embodiments, the door 107 is configured as a slit valve door.

[0061] In some embodiments, the semiconductor wafer W is a semiconductor wafer undergoing a manufacturing process. For the sake of ease of discussion, the semiconductor wafer W will hereafter be referred to as wafer W. However, it should be understood that in various embodiments, wafer W can essentially be any type of substrate undergoing a plasma-based manufacturing process. For example, in some embodiments, wafer W as referred to herein may be a substrate formed of silicon, sapphire, GaN, GaAs or SiC, or other substrate materials, and may include glass panels / substrates, metal foils, metal sheets, polymer materials, etc. Also, in various embodiments, wafer W as referred to herein may vary in shape, form, and / or size. For example, in some embodiments, wafer W as referred to herein may correspond to a circular semiconductor wafer on which integrated circuit devices are manufactured. In various embodiments, the circular wafer W may have a diameter of 200 mm, 300 mm, 450 mm, or other sizes. Also, in some embodiments, wafer W as referred to herein may correspond to a non-circular substrate, such as a rectangular substrate for a flat panel display, among other shapes.

[0062] The plasma processing system 100 includes an electrode 109 positioned on an equipment plate 111. In some embodiments, the electrode 109 and the equipment plate 111 are made of aluminum. However, in other embodiments, the electrode 109 and the equipment plate 111 can be made of another conductive material having sufficient mechanical strength and suitable thermal and chemical performance properties. A ceramic layer 110 is formed on the upper surface of the electrode 109. In some embodiments, the ceramic layer has a vertical thickness of about 1.25 millimeters (mm), measured perpendicular to the upper surface of the electrode 109. However, in other embodiments, the ceramic layer 110 can have a vertical thickness greater than or less than 1.25 mm. The ceramic layer 110 is configured to receive and support the wafer W while the plasma processing operation is being performed on the wafer W. In some embodiments, the upper surface of the electrode 190 and the outer peripheral side surface of the electrode 109, located radially outside the ceramic layer 110, are covered with a ceramic spray coat.

[0063] The ceramic layer 110 includes a configuration of one or more clamp electrodes 112 for generating an electrostatic force to hold the wafer W against the upper surface of the ceramic layer 110. In some embodiments, the ceramic layer 110 includes a configuration of two clamp electrodes 112 that operate in a bipolar configuration to supply clamping force to the wafer W. The clamp electrodes 112 are connected to a direct current (DC) supply unit 117, which generates a controlled clamping voltage to hold the wafer W against the upper surface of the ceramic layer 110. Wires 119A and 119B are connected between the DC supply unit 117 and the equipment plate 111. Wires / conductors are fed through the equipment plate 111 and electrode 109 to electrically connect wires 119A and 119B to the clamp electrodes 112. The DC supply unit 117 is connected to a control system 120 through one or more signal conductors 121.

[0064] The electrode 109 also includes a temperature-controlled fluid channel 123 through which a temperature-controlled fluid flows to control the temperature of the electrode 109, thereby controlling the temperature of the wafer W. The temperature-controlled fluid channel 123 is piped (fluid-connected) to a port on the equipment plate 111. A temperature-controlled fluid supply unit and return line are connected to these ports on the equipment plate 111 and to the temperature-controlled fluid circulation system 125, as indicated by arrow 126. The temperature-controlled fluid circulation system 125, among other devices, includes a temperature-controlled fluid supply unit, a temperature-controlled fluid pump, and a heat exchanger, to supply a controlled flow of temperature-controlled fluid through the electrode 109 to obtain and maintain a specified wafer W temperature. The temperature-controlled fluid circulation system 125 is connected to the control system 120 through one or more signal conductors 127. In various embodiments, various types of temperature-controlled fluids, such as water or cooling liquid / gas, can be used. In some embodiments, the temperature control fluid channel 123 is configured to enable spatially variable control of the wafer W temperature, for example, two-dimensional (x and y) control across the entire wafer W.

[0065] The ceramic layer 110 also includes the configuration of a back gas supply port (not shown) which is fluidly connected to a corresponding back gas supply channel in the electrode 109. The back gas supply channel in the electrode 109 is supplied through the electrode 109 to the interface between the electrode 109 and the equipment plate 111. One or more back gas supply lines are connected to ports on the equipment plate 111 and to the back gas supply system 129, as indicated by arrows 130. The equipment plate 111 is configured to supply back gas from one or more back gas supply lines to the back gas supply channels in the electrode 109. The back gas supply system 129 includes, among other devices, a back gas supply unit, a mass flow controller, and a flow control valve to provide a controlled flow of back gas through the configuration of the back gas supply port in the ceramic layer 110. In some embodiments, the back gas supply system 129 also includes one or more components for controlling the temperature of the back gas. In some embodiments, the back gas is helium. In some embodiments, a back-side gas supply system 129 can be used to supply clean, dry air (CDA) to the back-side gas supply ports within the ceramic layer 110. The back-side gas supply system 129 is connected to a control system 120 through one or more signal conductors 131.

[0066] Three lift pins 132 extend through the equipment plate 111, the electrodes 109, and the ceramic layer 110, resulting in the vertical movement of the wafer W relative to the upper surface of the ceramic layer 110. In some embodiments, the vertical movement of the lift pins 132 is controlled by corresponding electromechanical and / or pneumatic lifting devices 133 connected to the equipment plate 111. The three lifting devices 133 are connected to a control system 120 through one or more signal conductors 134. In some embodiments, the three lift pins 132 are arranged to have substantially equal azimuthal spacing around the vertical centerline of the electrodes 109 / ceramic layer 110, extending perpendicular to the upper surface of the ceramic layer 110. It should be understood that the lift pins 132 are lifted to accommodate the wafer W into the chamber 101 and to remove the wafer W from the chamber 101. Also, during processing of the wafer W, the lift pins 132 are lowered to allow the wafer W to be placed on the upper surface of the ceramic layer 110.

[0067] In various embodiments, one or more of the electrodes 109, the equipment plate 111, the ceramic layer 110, the clamp electrode 112, the lift pin 132, or any other components essentially associated therewith, may be equipped with one or more sensors, for example, sensors for temperature measurement, voltage measurement, and current measurement, among others. Any sensors located within the electrodes 109, the equipment plate 111, the ceramic layer 110, the clamp electrode 112, the lift pin 132, or any other components essentially associated therewith, are connected to the control system 120 via wires, optical fibers, or wireless connections.

[0068] The equipment plate 111 is provided within an opening in the ceramic support 113 and supported by the ceramic support 113. The ceramic support 113 is positioned on a support surface 114 of the cantilever arm assembly 115. In some embodiments, the ceramic support 113 has a substantially annular shape, thereby substantially surrounding the radial outer circumference of the equipment plate 111, while also providing a support surface 116 on which the bottom outer surface of the equipment plate 111 rests. The cantilever arm assembly 115 extends through the wall 101A of the chamber 101. In some embodiments, a sealing mechanism 135 is provided within the wall 101A of the chamber 101 where the cantilever arm assembly 115 is located, providing sealing of the inner region 103 of the chamber 101, while also allowing the cantilever arm assembly 115 to move upward and downward in the z direction in a controlled manner.

[0069] The cantilever arm assembly 115 has an opening region 118 through which various devices, wires, cables, and tubes are fed to support the operation of the system 100. The opening region 118 within the cantilever arm assembly is exposed to ambient atmospheric conditions outside the chamber 101, such as air composition, temperature, pressure, and relative humidity. A high-frequency signal supply rod 137 is also located inside the cantilever arm assembly 115. More specifically, the high-frequency signal supply rod 137 is located inside a conductive tube 139, thereby spacing the high-frequency signal supply rod 137 from the inner wall of the tube 139. The sizes of the high-frequency signal supply rod 137 and the tube 139 may vary. The area inside the tube 139 between the inner wall of the tube 139 and the high-frequency signal supply rod 137 is occupied by air along the entire length of the tube 139. In some embodiments, the outer diameter (D rod ) and the inner diameter (D tube ) is the relation ln(D tube / D rod )≧e 1 It will be set to satisfy the following conditions.

[0070] In some embodiments, the high-frequency signal supply rod 137 is substantially centrally located within the tube 139, thereby creating a substantially uniform radial thickness of air between the high-frequency signal supply rod 137 and the inner wall of the tube 139 along its length. However, in some embodiments, the high-frequency signal supply rod 137 is not centrally located within the tube 139, but an air gap exists within the tube 139 at all points between the high-frequency signal supply rod 137 and the inner wall of the tube 139 along its length. The delivery end of the high-frequency signal supply rod 137 is electrically and physically connected to the lower end of the high-frequency signal supply shaft 141. In some embodiments, the delivery end of the high-frequency signal supply rod 137 is bolted to the lower end of the high-frequency signal supply shaft 141. The upper end of the high-frequency signal supply shaft 141 is electrically and physically connected to the bottom of the equipment plate 111. In some embodiments, the upper end of the high-frequency signal supply shaft 141 is bolted to the bottom of the equipment plate 111. In some embodiments, both the high-frequency signal supply rod 137 and the high-frequency signal supply shaft 141 are made of copper. In some embodiments, the high-frequency signal supply rod 137 is made of copper, or aluminum, or anodized aluminum. In some embodiments, the high-frequency signal supply shaft 141 is made of copper, or aluminum, or anodized aluminum. In other embodiments, the high-frequency signal supply rod 137 and / or the high-frequency signal supply shaft 141 are made of another conductive material that transmits high-frequency electrical signals. In some embodiments, the high-frequency signal supply rod 137 and / or the high-frequency signal supply shaft 141 are coated with a conductive material (e.g., silver or another conductive material) that transmits high-frequency electrical signals. Also, in some embodiments, the high-frequency signal supply rod 137 is a solid rod. However, in other embodiments, the high-frequency signal supply rod 137 is a tube. It should also be understood that the region 140 surrounding the connection between the high-frequency signal supply rod 137 and the high-frequency signal supply shaft 141 is occupied by air.

[0071] The supply end of the high-frequency signal supply rod 137 is electrically and physically connected to an impedance matching system 143. The impedance matching system 143 is connected to a first high-frequency signal generator 147 and a second high-frequency signal generator 149. The impedance matching system 143 is also connected to a control system 120 through one or more signal conductors 144. The first high-frequency signal generator 147 is also connected to the control system 120 through one or more signal conductors 148. The second high-frequency signal generator 149 is also connected to the control system 120 through one or more signal conductors 150. The impedance matching system 143 includes an inductor and capacitor configuration sized and connected to provide impedance matching so that high-frequency power can be transmitted along the high-frequency signal supply rod 137, along the high-frequency signal supply shaft 141, through the equipment plate 111, through the electrode 109, and into the plasma processing area 182 above the ceramic layer 110. In some embodiments, the first high-frequency signal generator 147 is a high-frequency signal generator, and the second high-frequency signal generator 149 is a low-frequency signal generator. In some embodiments, the first high-frequency signal generator 147 generates high-frequency signals in the range of approximately 50 megahertz (MHz) to approximately 70 MHz, or in the range of approximately 54 MHz to approximately 63 MHz, or approximately 60 MHz. In some embodiments, the first high-frequency signal generator 147 supplies high-frequency power in the range of approximately 5 kilowatts (kW) to approximately 25 kW, or in the range of approximately 10 kW to approximately 20 kW, or in the range of approximately 15 kW to approximately 20 kW, or approximately 10 kW, or approximately 16 kW. In some embodiments, the second high-frequency signal generator 149 generates high-frequency signals in the range of approximately 50 kilowatts (kHz) to approximately 500 kHz, or in the range of approximately 330 kHz to 440 kHz, or approximately 400 kHz. In some embodiments, the second high-frequency signal generator 149 supplies high-frequency power ranging from about 15 kW to about 100 kW, or from about 30 kW to about 50 kW, or about 34 kW, or about 50 kW.In an exemplary embodiment, the first high-frequency signal generator 147 is configured to generate a high-frequency signal having a frequency of approximately 60 MHz, and the second high-frequency signal generator 149 is configured to generate a high-frequency signal having a frequency of approximately 400 kHz.

[0072] A bonding ring 161 is configured and positioned to extend around the radial outer circumference of the electrode 109. In some embodiments, the bonding ring 161 is made of a ceramic material. A quartz ring 163 is configured and positioned to extend around the radial outer circumference of both the bonding ring 161 and the ceramic support 113. In some embodiments, when the quartz ring 163 is positioned around both the bonding ring 161 and the ceramic support 113, the bonding ring 161 and the quartz ring 163 are configured to have substantially aligned upper surfaces. In some embodiments, the substantially aligned upper surfaces of the bonding ring 161 and the quartz ring 163 are substantially aligned with respect to the upper surface of the electrode 109, and the upper surfaces are located outside the radial periphery of the ceramic layer 110. In some embodiments, a covering ring 165 is configured and positioned to extend around the radial outer circumference of the upper surface of the quartz ring 163. In some embodiments, the covering ring 165 is made of quartz. In some embodiments, the covering ring 165 is configured to extend perpendicularly above the upper surface of the quartz ring 163. Thus, the covering 165 provides a peripheral boundary in which the edge ring 167 is positioned.

[0073] The edge ring 167 is configured to facilitate the extension of the plasma sheath radially outward beyond the outer edge of the wafer W, thereby improving process results near the periphery of the wafer W. In various embodiments, the edge ring 167 is formed of a conductive material, among other materials, such as crystalline silicon, polycrystalline silicon (polysilicon), boron-doped single-crystal silicon, aluminum oxide, quartz, aluminum nitride, silicon nitride, silicon carbide or silicon carbide layer on an aluminum oxide layer, or silicon alloy, or a combination thereof. It should be understood that the edge ring 167 is formed as an annular structure, for example, as a ring-shaped structure. The edge ring 167 can perform many functions, including shielding components beneath the edge ring 167 from damage by ions of the plasma 180 formed within the plasma processing region 182. The edge ring 167 also improves the uniformity of the plasma 180 in and along the outer peripheral region of the wafer W.

[0074] A fixed outer support flange 169 is attached to the cantilever arm assembly 115. The fixed outer support flange 169 is configured to extend around the outer vertical side of the ceramic support 113, around the outer vertical side of the quartz ring 163, and around the lower outer vertical side of the covering ring 165. The fixed outer support flange 169 has an annular shape that surrounds the assembly of the ceramic support 113, the quartz ring 163, and the covering ring 165. The fixed outer support flange 169 has an L-shaped vertical cross-section that includes a vertical portion and a horizontal portion. The vertical portion of the L-shaped cross-section of the fixed outer support flange 169 has an inner vertical surface that is in contact with the outer vertical side of the ceramic support 113, the outer vertical side of the quartz ring 163, and the lower outer vertical side of the covering ring 165. In some embodiments, the vertical portion of the L-shaped cross-section of the fixed outer support flange 169 extends over the entire outer vertical surface of the ceramic support 113, over the entire outer vertical surface of the quartz ring 163, and over the lower outer vertical surface of the covering ring 165. In some embodiments, the covering ring 165 extends radially outward over the upper surface of the vertical portion of the L-shaped cross-section of the fixed outer support flange 169. In some embodiments, the upper outer vertical surface of the covering ring 165 (located above the upper surface of the vertical portion of the L-shaped cross-section of the fixed outer support flange 169) is aligned substantially perpendicular to the outer vertical surface of the vertical portion of the L-shaped cross-section of the fixed outer support flange 169. The horizontal portion of the L-shaped cross-section of the fixed outer support flange 169 rests on and is fixed to the support surface 114 of the cantilever arm assembly 115. The fixed outer support flange 169 is formed of a conductive material. In some embodiments, the fixed outer support flange 169 is formed of aluminum or anodized aluminum. However, in other embodiments, the fixed outer support flange 169 may be formed of another conductive material such as copper or stainless steel. In some embodiments, the horizontal portion of the L-shaped cross-section of the fixed outer support flange 169 is bolted to the support surface 114 of the cantilever arm assembly 115.

[0075] The articulated outer support flange 171 is configured and positioned to extend around the outer vertical surface 169D of the vertical portion of the L-shaped cross-section of the fixed outer support flange 169, and around the upper outer vertical side surface of the covering 165. The articulated outer support flange 171 has an annular shape that surrounds both the vertical portion of the L-shaped cross-section of the fixed outer support flange 169 and the upper outer vertical side surface of the covering 165. The articulated outer support flange 171 has an L-shaped vertical cross-section that includes a vertical portion and a horizontal portion. The vertical portion of the L-shaped cross-section of the articulated outer support flange 171 has an inner vertical surface, which is positioned close to and spaced apart from both the outer vertical side surface of the vertical portion of the L-shaped cross-section of the fixed outer support flange 169 and the upper outer vertical side surface of the covering 165. Thus, the articulated outer support flange 171 is movable vertically (in the z-direction) along both the vertical portion of the L-shaped vertical cross-section of the fixed outer support flange 169 and the upper outer vertical side surface of the covering 165. The articulated outer support flange 171 is formed of a conductive material. In some embodiments, the articulated outer support flange 171 is formed of aluminum or anodized aluminum. However, in other embodiments, the articulated outer support flange 171 can be formed of another conductive material such as copper or stainless steel.

[0076] Multiple conductive straps 173 are connected between the articulated outer support flange 171 and the fixed outer support flange 169 around the radial circumference of both the articulated outer support flange 171 and the fixed outer support flange 169. In exemplary embodiments, the conductive straps 173 are shown to have an "outward-facing" configuration in that the conductive straps 173 are curved outward away from the fixed outer support flange 169. In some embodiments, the conductive straps 173 are formed of stainless steel. However, in other embodiments, the conductive straps 173 can be formed of another conductive material, for example, aluminum or copper, among other things.

[0077] In some embodiments, 48 ​​conductive straps 173 are distributed substantially equally around the radial periphery of the articulated outer support flange 171 and the fixed outer support flange 169. However, it should be understood that in different embodiments, the number of conductive straps 173 can be varied. In some embodiments, the number of conductive straps 173 is in the range of about 24 to about 80, or in the range of about 36 to about 60, or in the range of about 40 to about 56. In some embodiments, the number of conductive straps 173 is less than 24. In some embodiments, the number of conductive straps 173 is more than 80. The number of conductive straps 173 affects the ground feedback path of the high-frequency signal around the periphery of the plasma processing area 182, and therefore the number of conductive straps 173 can affect the uniformity of the process results across the wafer W. Also, in different embodiments, the size of the conductive straps 173 can be varied.

[0078] In some embodiments, the conductive strap 173 is connected to the fixed outer support flange 169 by a clamping force applied by fixing the clamp ring 175 to the upper surface of the horizontal portion of the L-shaped cross-section of the fixed outer support flange 169. In some embodiments, the clamp ring 175 is bolted to the fixed outer support flange 169. In some embodiments, the bolts that secure the clamp ring 175 to the fixed outer support flange 169 are located between the conductive straps 173. However, in some embodiments, one or more bolts that secure the clamp ring 175 to the fixed outer support flange 169 may be arranged to extend through the conductive straps 173. In some embodiments, the clamp ring 175 is formed of the same material as the fixed outer support flange 169. However, in other embodiments, the clamp ring 175 and the fixed outer support flange 169 may be formed of different materials.

[0079] In some embodiments, the conductive straps 173 are connected to the articulated outer support flange 171 by a clamping force applied by fixing a clamping ring 177 to the bottom surface of the horizontal portion of the L-shaped cross-section of the articulated outer support flange 171. Alternatively, in some embodiments, the first end portion of each of the multiple conductive straps 173 is connected by the clamping ring 177 to the top surface of the horizontal portion of the articulated outer support flange 171. In some embodiments, the clamping ring 177 is bolted to the articulated outer support flange 171. In some embodiments, the bolts that secure the clamping ring 177 to the articulated outer support flange 171 are located between the conductive straps 173. However, in some embodiments, one or more bolts that secure the clamping ring 177 to the articulated outer support flange 171 may be arranged to extend through the conductive straps 173. In some embodiments, the clamping ring 177 is formed of the same material as the articulated outer support flange 171. However, in other embodiments, the clamp ring 177 and the articulated outer support flange 171 can be formed from different materials.

[0080] A set of support rods 201 are arranged around a cantilever arm assembly 115 and extend vertically through the horizontal portion 169B of the L-shaped cross-section of a fixed outer support flange 169. The upper end of each support rod 201 is configured to engage with the bottom surface of the horizontal portion of the L-shaped cross-section of an articulated outer support flange 171. In some embodiments, the lower end of each support rod 201 engages with a resistance mechanism 203. The resistance mechanism 203 is configured to allow some downward movement of the support rods 201 while providing an upward force to the corresponding support rod 201 that will resist downward movement of the support rod 201. In some embodiments, the resistance mechanism 203 includes a spring to provide the upward force to the corresponding support rod 201. In some embodiments, the resistance mechanism 203 includes a material with a sufficient spring constant, e.g., a spring and / or rubber, to provide the upward force to the corresponding support rod 201. It should be understood that as the articulated outer support flange 171 moves downward and engages with the set of support rods 201, the set of support rods 201 and corresponding resistance mechanisms 203 provide an upward force to the articulated outer support flange 171. In some embodiments, the set of support rods 201 includes three support rods 201 and corresponding resistance mechanisms 203. In some embodiments, the support rods 201 are arranged to have substantially equal azimuthal spacing with respect to the vertical centerline of the electrode 109. However, in some embodiments, the support rods 201 are arranged to have unequal azimuthal spacing with respect to the vertical centerline of the electrode 109. Also, in some embodiments, three or more support rods 201 and corresponding resistance mechanisms 203 are provided to support the articulated outer support flange 171.

[0081] Referring again to Figure 2, the plasma processing system 100 further includes a C-shroud member 185 positioned above the electrode 109. The C-shroud member 185 is configured to interface with an articulated outer support flange 171. Specifically, a seal 179 is positioned on the upper surface of the horizontal portion of the L-shaped cross-section of the articulated outer support flange 171, so that when the articulated outer support flange 171 moves upward toward the C-shroud member 185, the C-shroud member 185 engages with the seal 179. In some embodiments, the seal 179 is conductive to help establish conductivity between the C-shroud member 185 and the articulated outer support flange 171. In some embodiments, the C-shroud member 185 is formed of polysilicon. However, in other embodiments, the C-shroud member 185 is formed of another type of conductive material that is chemically compatible with the process formed in the plasma processing region 182 and has sufficient mechanical strength.

[0082] The C shroud extends around the plasma processing area 182 and is configured to provide a radial extension of the plasma processing area 182 volume into a defined area within the C shroud member 185. The C shroud member 185 includes a lower wall 185A, an outer vertical wall 185B, and an upper wall 185C. In some embodiments, the outer vertical wall 185B and the upper wall 185C of the C shroud member 185 are solid, unperforated members, and the lower wall 185A of the C shroud member 185 includes a plurality of vents 186 through which process gas flows out of the plasma processing area 182. In some embodiments, a throttle member 196 is positioned below the vents 186 of the C shroud member 185 to control the flow of process gas through the vents 186. More specifically, in some embodiments, the throttle member 196 is configured to move vertically perpendicular to the z-direction relative to the C shroud member 185 to control the flow of process gas through the vent 186. In some embodiments, the throttle member 196 is configured to engage with and / or enter the vent 186.

[0083] The upper wall 185C of the C shroud member 185 is configured to support the upper electrodes 187A / 187B. In some embodiments, the upper electrodes 187A / 187B include an inner upper electrode 187A and an outer upper electrode 187B. Alternatively, in some embodiments, the inner upper electrode 187A is present and the outer upper electrode 187B is absent, with the inner upper electrode 187A extending radially to cover the area that would be occupied by the outer upper electrode 187B. In some embodiments, the inner upper electrode 187A is formed of single-crystal silicon and the outer upper electrode 187B is formed of polysilicon. However, in other embodiments, the inner upper electrode 187A and the outer upper electrode 187B can be formed of other materials that are structurally, chemically, electrically, and mechanically compatible with the process carried out within the plasma processing area 182. The inner upper electrode 187A includes a plurality of through-ports 197, defined as holes extending through the entire vertical thickness of the inner upper electrode 187A. The through-ports 197 are distributed across the entire inner upper electrode 187A in the xy plane, supplying a flow of process gas from the plenum region 188 above the upper electrodes 187A / 187B to the plasma processing region 182 below the upper electrodes 187A / 187B.

[0084] It should be understood that the distribution of through-ports 197 throughout the inner upper electrode 187A can be configured in different forms in different embodiments. For example, the total number of through-ports 197 within the inner upper electrode 187A, and / or the spatial distribution of through-ports 197 within the inner upper electrode 187A, can differ between different embodiments. Also, the diameter of the through-ports 197 can differ between different embodiments. Generally, it is of interest to reduce the diameter of the through-ports 197 to a size small enough to prevent plasma 180 from entering the through-ports 197 from the plasma processing area 182. In some embodiments, as the diameter of the through-ports 197 is reduced, the total number of through-ports 197 within the inner upper electrode 187A is increased to maintain a specified overall flow rate of process gas flowing from the process gas plenum area 188 through the inner upper electrode 187A to the plasma processing area 182. Also, in some embodiments, the upper electrodes 187A / 187B are electrically connected to a reference ground potential. However, in other embodiments, the inner upper electrode 187A and / or the outer upper electrode 187B are electrically connected to the corresponding DC power supply or the corresponding high-frequency power supply via the corresponding impedance matching circuit.

[0085] The plenum region 188 is defined by the upper element 189. One or more gas supply ports 192 are formed through the chamber 101 and the upper element 189 to fluidly communicate with the plenum region 188. One or more gas supply ports 192 are fluidly connected (pipe-connected) to the process gas supply system 191. The process gas supply system 191 includes, among other devices, one or more process gas supply units, one or more mass flow controllers, and one or more flow control valves to supply one or more controlled flows of process gas to the plenum region 188 through one or more gas supply ports 192, as indicated by arrow 193. In some embodiments, the process gas supply system 191 also includes one or more components for controlling the temperature of the process gas. The process gas supply system 191 is connected to the control system 120 through one or more signal conductors 194.

[0086] The processing gap (g1) is defined as the vertical (z-direction) distance measured between the upper surface of the ceramic layer 110 and the bottom surface of the inner upper electrode 187A. The size of the processing gap (g1) can be adjusted by moving the cantilever arm assembly 115 vertically (z-direction). As the cantilever arm assembly 115 moves upward, the articulated outer support flange 171 eventually engages with the lower wall 185A of the C shroud member 185, and at that point, as the cantilever arm assembly 115 continues to move upward, the articulated outer support flange 171 moves along the fixed outer support flange 169, which continues until a set of support rods 201 engages with the articulated outer support flange 171 and the specified processing gap (g1) size is achieved. Next, in order to reverse this movement in order to remove the wafer W from the chamber, the cantilever arm assembly 115 is moved downward until the articulated outer support flange 171 moves away from the lower wall 185A of the C shroud member 185. In various embodiments, the size of the processing gap (g1) of the wafer W during plasma processing is controlled to a range of up to approximately 10 centimeters, or up to approximately 8 centimeters, or up to approximately 5 centimeters. Figure 2 should be understood to show a closed system 100 in which the wafer W on the ceramic layer 110 is in position for plasma processing.

[0087] During plasma processing operations within the plasma processing system 100, one or more process gases are supplied to the plasma processing area 182 via the process gas supply system 191, the plenum area 188, and the through-port 197 in the inner upper electrode 187A. High-frequency signals are also transmitted to the plasma processing area 182 via the first and second high-frequency signal generators 147, 149, the impedance matching system 143, the high-frequency signal supply rod 137, the high-frequency signal supply shaft 141, the equipment plate 111, the electrode 109, and through the ceramic layer 110. The high-frequency signals convert the process gases within the plasma processing area 182 into plasma 180. Ions and / or reactive components of the plasma interact with one or more materials on the wafer W, altering the composition and / or shape of specific materials on the wafer W. The exhaust gas from the plasma processing area 182 is affected by the suction force applied at the exhaust port 105 and flows through the vent 186 in the C shroud member 185, through the inner region 103 in the chamber 101, and back to the exhaust port 105, as indicated by arrow 195.

[0088] In various embodiments, the electrode 109 can be configured to have different diameters. However, in some embodiments, the diameter of the electrode 109 is extended to increase the surface area of ​​the electrode 109 on which the edge ring 167 is placed. In some embodiments, the conductive gel 226 is placed between the bottom of the edge ring 167 and the top of the electrode 109 and / or between the bottom of the edge ring 167 and the top of the bonding ring 161. In these embodiments, the increased diameter of the electrode 109 increases the surface area on which the conductive gel is placed between the edge ring 167 and the electrode 109.

[0089] It should be understood that the combination of the articulated outer support flange 171, the conductive strap 173, and the fixed outer support flange 169 is electrically at a reference ground potential, and collectively they form a ground feedback path for high-frequency signals transmitted from the electrode 109 through the ceramic layer 110 into the plasma processing area 182. The uniformity of the azimuthal direction of this ground feedback path around the outer periphery of the electrode 109 can affect the uniformity of the process results on the wafer W. For example, in some embodiments, the uniformity of the etching rate across the wafer W may be affected by the uniformity of the azimuthal direction of the ground feedback path around the outer periphery of the electrode 109. For this purpose, it should be understood that the number, configuration, and arrangement of the conductive straps 173 around the outer periphery of the electrode 109 can affect the uniformity of the process results across the wafer W.

[0090] Referring again to Figure 2, the adjustable edge sheath (TES) system is implemented to include a TES electrode 415 positioned (embedded) within a coupling ring 161. The TES system also includes a number of TES high-frequency signal supply pins 413 that are physically and electrically connected to the TES electrode 415. Each TES high-frequency signal supply pin 413 extends through a corresponding insulating feedthrough member 421 configured to electrically isolate the TES high-frequency signal supply pin 413 from the surrounding structure, for example, the ceramic support 113 and the cantilever arm assembly 115 structure. In some embodiments, O-rings 417 and 419 are positioned to ensure that areas inside the insulating feedthrough member 421 are not exposed to any material / gas present in the plasma processing area 182. In some embodiments, the TES high-frequency signal supply pins 413 are formed of copper, or aluminum, or anodized aluminum, among other things.

[0091] The TES high-frequency signal supply pins 413 extend into an opening region 118 inside the cantilever arm assembly 115, and each of the TES high-frequency signal supply pins 413 is electrically connected to a TES high-frequency signal supply conductor 409 through a corresponding TES high-frequency signal filter 411. In some embodiments, three TES high-frequency signal supply pins 413 are arranged to be physically and electrically connected to the TES electrode 415 at azimuthal locations substantially equally spaced around the centerline of the electrode 109. However, it should be understood that other embodiments may have three or more TES high-frequency signal supply pins 413 that are physically and electrically connected to the TES electrode 415. Also, some embodiments may have one or two TES high-frequency signal supply pins 413 that are physically and electrically connected to the TES electrode 415. Each TES high-frequency signal supply pin 413 is electrically connected to a corresponding TES high-frequency signal filter 411, and each TES high-frequency signal filter 411 is electrically connected to a TES high-frequency signal supply conductor 409. In some embodiments, each TES high-frequency signal filter 411 is configured as an inductor. For example, in some embodiments, each TES high-frequency signal filter 411 is configured as a coiled conductor, such as a metal coil wound around a dielectric core structure. In various embodiments, the metal coil can be formed from, among other things, a solid copper rod, copper tube, aluminum rod, or aluminum tube. Also, in some embodiments, each TES high-frequency signal filter 411 can be configured as a combination of inductive and capacitive structures. To improve the uniformity of the plasma processing results across the entire wafer W, each of the TES high-frequency signal filters 411 has substantially the same configuration.

[0092] In some embodiments, the TES high-frequency signal supply conductor 409 is formed as a ring-shaped (annular) structure extending around an opening region 118 inside the cantilever arm assembly 115, enabling physical and electrical connections between the azimuthal-dispersed TES high-frequency signal filter 411 and the TES high-frequency signal supply conductor 409. In some embodiments, the TES high-frequency signal supply conductor 409 is formed as a solid (non-tubular) structure. Alternatively, in some embodiments, the TES high-frequency signal supply conductor 409 is formed as a tubular structure. In some embodiments, the TES high-frequency signal supply conductor 409 is formed of copper, or aluminum, or anodized aluminum, among other things.

[0093] The TES high-frequency signal supply conductor 409 is electrically connected to the TES high-frequency supply cable 407. A capacitor 408 is connected between the TES high-frequency signal supply conductor 409 and a reference ground potential, for example, the structure of the cantilever arm assembly 115. More specifically, the capacitor 408 has a first end electrically connected to both the TES high-frequency supply cable 407 and the TES high-frequency signal supply conductor 409, and a second end electrically connected to the reference ground potential. In some embodiments, the capacitor 408 is a variable capacitor. In some embodiments, the capacitor 408 is a fixed capacitor. In some embodiments, the capacitor 408 is set to have a capacitance ranging from about 10 picofarads to about 100 picofarads. The TES high-frequency supply cable 407 is connected to the TES impedance matching system 401. The TES impedance matching system 401 is connected to the TES high-frequency signal generator 403. The high-frequency signal generated by the TES high-frequency signal generator 403 is transmitted through the TES impedance matching system 401 to the TES high-frequency supply cable 407, then to the TES high-frequency signal supply conductor 409, then through the TES high-frequency signal filter 411 to the corresponding TES high-frequency signal supply pin 413, and finally to the TES electrode 415 in the coupling ring 161. In some embodiments, the TES high-frequency signal generator 403 is configured and operated to generate high-frequency signals in a frequency range extending from about 50 kilohertz to about 27 MHz. In some embodiments, the TES high-frequency signal generator 403 supplies high-frequency power in a range extending from about 50 watts to about 10 kilowatts. The TES high-frequency signal generator 403 is also connected to the control system 120 through one or more signal conductors 405.

[0094] The TES impedance matching system 401 includes a configuration of inductors and capacitors sized and connected to provide impedance matching so that high-frequency power can be transmitted from the TES high-frequency signal generator 403, along the TES high-frequency supply cable 407, along the TES high-frequency signal supply conductor 409, through the TES high-frequency signal filter 411, through the corresponding TES high-frequency signal supply pin 413, to the TES electrode 415 in the coupling ring 161, and into the plasma processing area 182 above the edge ring 167. Figure 3 shows an exemplary schematic circuit diagram of the TES impedance matching system 401 according to several embodiments. The TES impedance matching system 401 includes an input line 321 electrically connected to the TES high-frequency signal generator 403. The TES input line 321 is electrically connected to the input terminal of a first inductor 322. The output terminal of the first inductor 322 is electrically connected to an internal node 328. A second inductor 324 has an input terminal electrically connected to the internal node 328. The output terminal of the second inductor 324 is electrically connected to the second internal node 329. The first capacitor 326 has an input terminal that is electrically connected to the second internal node 329. The output terminal of the first capacitor 326 is electrically connected to the input terminal of the third inductor 327. The output terminal of the third inductor 327 is electrically connected to the TES high-frequency supply cable 407. The second capacitor 323 also has an input terminal that is electrically connected to the first internal node 328. The second capacitor 323 has an output terminal that is electrically connected to the reference ground potential. In some embodiments, the second capacitor 323 is a variable capacitor. The third capacitor 325 also has an input terminal that is electrically connected to the second internal node 329. The third capacitor 325 has an output terminal that is electrically connected to the reference ground potential. It should be understood that the electrical configuration of the TES impedance matching system 401 shown in Figure 3 is provided as an example. In other embodiments, the TES impedance matching system 401 may have a different inductor and / or capacitor configuration than that shown in the embodiment of Figure 3.The TES impedance matching system 401 is also connected to the control system 120 through one or more signal conductors 404.

[0095] By transmitting high-frequency signals / power through TES electrodes 415 positioned (embedded) within the coupling ring 161, the TES system can control the properties of the plasma 180 near the outer edge of the wafer W. For example, in some embodiments, the properties of the plasma 180 sheath near the edge ring 167 are controlled by activating the TES system to control the shape of the plasma 180 sheath and / or the size (either increasing or decreasing the sheath thickness). Also in some embodiments, various properties of the bulk plasma 180 above the wafer W can be controlled by controlling the shape of the plasma 180 sheath near the edge ring 167. Furthermore, in some embodiments, the density of the plasma 180 near the edge ring 167 is controlled by activating the TES system. For example, in some embodiments, the density of the plasma 180 near the edge ring 167 is increased or decreased by activating the TES system. Furthermore, in some embodiments, the TES system is activated to control the bias voltage present in the edge ring 167, and this bias voltage then controls / influences the movement of ions and other charged components in the plasma 180 near the edge ring 167. For example, in some embodiments, the TES system is activated to control the bias voltage present in the edge ring 167 to attract more ions from the plasma 180 toward the edge of the wafer W. And in some embodiments, the TES system is activated to control the bias voltage present in the edge ring 167 to repel ions from the plasma 180 away from the edge of the wafer W. It should be understood that by activating the TES system, various different functions, among others, the functions described above, can be performed individually or in combination.

[0096] In some embodiments, the bonding ring 161 is formed of a dielectric material, such as, in particular, quartz, or ceramic, or alumina (Al2O3), or polymer.

[0097] The bottom surface of the edge ring 167 has a portion that is bonded to the upper surface of the bonding ring 161 via a layer of thermally and electrically conductive gel, making the edge ring 167 a heat sink for the bonding ring 161. The bottom surface of the edge ring 167 also has another portion that is bonded to the upper surface of the electrode 109 via a layer of thermally and electrically conductive gel. Examples of thermally and electrically conductive gels include, among others, polyimide, polyketone, polyetherketone, polyethersulfone, polyethylene terephthalate, fluoroethylene propylene copolymer, cellulose, triacetate, and silicone. In some embodiments, the thermally and electrically conductive gel is formed as a double-sided tape. In some embodiments, the edge ring 167 has an inner diameter sized to be close to the outer diameter of the ceramic layer 110.

[0098] In various embodiments, the TES electrode 415 is formed of a conductive material, for example, platinum, steel, aluminum, or copper, among others. During operation, capacitive coupling occurs between the TES electrode 415 and the edge ring 167, resulting in the edge ring 167 being powered and influencing the processing of the wafer W near the outer periphery of the wafer W.

[0099] Figure 4 conceptually shows the components of the TES high-frequency signal generator 403 according to an implementation of the present disclosure. Figure 5 is a graph showing the various states of the (multi-state / pulsed) TES high-frequency signal generated by the TES high-frequency signal generator 403 and applied to the TES electrode according to an implementation of the present disclosure. Referring to both Figures 4 and 5, the various states of the (multi-state / pulsed) TES high-frequency (RF) signal and the corresponding operations of the TES high-frequency signal generator 403 to realize these states are described herein.

[0100] Figure 5 shows the relationship between the voltage setpoint and time for a TES RF signal generated by the TES RF signal generator 403 in an implementation of the present disclosure. As shown in the figure, the TES RF signal is defined to have a 3-state pulse RF cycle, in which states S1, S0, and S2 are repeated periodically in sequence. In the illustrated implementation, state S0 precedes state S2, but in other implementations, this order is reversed, for example, state S2 precedes state S0. As shown in the figure, each state has a voltage setpoint that defines the target voltage realized by the TES RF signal generator 403 for that state.

[0101] For state S1 of the TES RF signal, the voltage setpoint is Vs1, which in some implementations is configured to provide high aspect ratio etching. For state S0 of the TES RF signal, the voltage setpoint is Vs0, which in some implementations is configured to induce passivation. For state S2 of the TES RF signal, the voltage setpoint is Vs2, which in some implementations is configured to facilitate dissociation and neck opening in the feature.

[0102] As can be seen from the figure, the voltage setpoints for states S0 and S2 are lower than the voltage setpoint for state S1. Therefore, to efficiently realize a 3-state pulse TES RF signal, the TES RF signal generator 403 uses a single power amplifier 431 to control the RF output power to achieve the voltage setpoint for state S1 (Vs1), and uses drive actuators 433 and 435 to selectively attenuate the RF output to achieve the voltage setpoints for states S0 and S2 (Vs0 and Vs2). The output level of the power amplifier 431 is adjusted to generate the RF signal according to the voltage setpoint for S1, which is Vs1. In some implementations, the RF signal from the power amplifier 431 further includes additional voltage states that are lower than Vs1 but not too low to achieve the desired voltage setpoints Vs0 and Vs2. To fully generate state S0 for the TES RF signal, the drive actuator 433 is configured to selectively attenuate the relevant portion of the power amplifier signal by an attenuation amount D1 to achieve the voltage setpoint Vs0 for S0. Similarly, in order to fully generate state S2, the drive actuator 435 is configured to selectively attenuate the relevant portion of the power amplifier signal by an attenuation amount D2 to realize the voltage setpoint Vs2 of S2. Thus, according to the implementation of this disclosure, the voltage levels of states S0 and S2 are realized by attenuating the output of the power amplifier as needed to realize the voltage setpoints Vs0 and Vs2.

[0103] While the voltages of each state are related as described above, the phase of each state can be controlled independently according to the implementation of this disclosure. Roughly speaking, it is optimal to match the phase of each state of the pulsed TES RF signal to the phase of the corresponding state of the pulsed RF signal applied to the electrode 109 by the RF signal generator 149. That is, the phase of state S1 of the TES RF signal (generated by the RF signal generator 403) is adjusted to match the phase of state S1 of the bias RF signal (generated by the RF signal generator 149), the phase of state S0 of the TES RF signal (generated by the RF signal generator 403) is adjusted to match the phase of state S0 of the bias RF signal (generated by the RF signal generator 149), and the phase of state S2 of the TES RF signal (generated by the RF signal generator 403) is adjusted to match the phase of state S2 of the bias RF signal (generated by the RF signal generator 149).

[0104] According to the embodiment of this disclosure, the TES high-frequency signal generator 403 is configured to automatically and independently adjust the phases of various states of the TES high-frequency signal it generates to match the phases of the corresponding states of the high-frequency signal generated by the high-frequency signal generator 149. To achieve this, the TES RF signal generator 403 includes a phase actuator 437 for state S1, a phase actuator 439 for state S0, and a phase actuator 441 for state S2. The phase actuator 437 applies a phase adjustment PA1 to automatically adjust the phase of state S1 in the TES RF signal to match the corresponding state S1 in the RF signal generated by the high-frequency signal generator 149 with respect to the electrode 109. The phase actuator 439 applies a phase adjustment PA2 to automatically adjust the phase of state S0 in the TES RF signal to match the corresponding state S0 in the RF signal generated by the high-frequency signal generator 149 with respect to the electrode 109. The phase actuator 441 applies phase adjustment PA3 to automatically adjust the phase of state S2 in the TES RF signal to match the corresponding state S2 in the RF signal generated by the high-frequency signal generator 149 with respect to the electrode 109.

[0105] In some implementations, the voltage setpoint for state S1 applied to the TES electrode 415 is increased to compensate for wear of the edge ring 167 due to the accumulation of RF time. Accordingly, the TES high-frequency signal generator 403 is then automatically adjusted to maintain phase matching of the high-frequency signal from the high-frequency signal generator 149 with state S1. As described above, it has been found that by adjusting the capacitance setting in the TES impedance matching system 401 to minimize the reflection of the high-frequency power in state S1, the (automatically occurring) phase adjustment by the TES high-frequency signal generator 403 results in its phase adjustment amount returning to the original voltage (the first voltage of state S1 before it was increased to compensate for edge ring wear). Therefore, the capacitance setting of the variable capacitor 323 in the TES impedance matching system 401 can be optimized using the phase adjustment amount for state S1.

[0106] However, according to the implementation of this disclosure, the capacitance setting in the TES impedance matching system 401 sets the capacitance C1 that is applied to all states S1, S0, and S2 of the pulsed TES RF signal. As will be discussed further below, such changes in the capacitance setting of the TES impedance matching system also affect the relationship between the voltage setpoints for states S0 and S2 and the tolerance range of these voltage setpoints. Accordingly, it is desirable to optimize the voltage setpoints for states S0 and S2 in response to changes in the capacitance setting.

[0107] Figure 6 is a graph conceptually illustrating the allowable voltage setpoint range for state S0 or S2 in an implementation of the present disclosure. More specifically, the allowable voltage setpoint range is shown by vertical bars as a function of the capacitor tap position of the variable capacitor 323 in the TES impedance matching system 401. Roughly speaking, as the voltage setpoint of state S1 changes, the capacitor tap position, for example, changes accordingly to minimize reflected power from state S1. However, as described above, states S0 and S2 depend on the voltage of state S1, in that the voltages of states S0 and S2 are realized by the drive actuator power attenuating the output of the power amplifier. This is set by the TES RF signal generator when controlling the voltage setpoint of state S1. The expected voltage setpoint range for states S0 and S2 is determined by the voltage of state S1 and the ability of the drive actuator to attenuate the output of the power amplifier. The maximum or upper limit of the voltage setpoint for S0 / S2 is determined by the voltage setpoint of state S1. This is because the output of the power amplifier used to control state S1 to its completely unattenuated level is the expected maximum output for states S0 / S2. The minimum or lower limit of the voltage setpoint for S0 / S2 is determined by the amount of attenuation possible by the drive actuator of the TES RF signal generator 403. Therefore, the range of allowable voltage setpoints is defined by the output required to control state S1 and the amount by which the drive actuator can attenuate the output of the power amplifier.

[0108] As mentioned above, if the voltage setpoint for state S1 is increased, for example to compensate for edge ring wear, the capacitor tap position of the variable capacitor 323 of the TES impedance matching system 401 is adjusted to minimize reflected power. Accordingly, as shown in Figure 6, the voltage setpoint for state S1 changes in accordance with edge ring wear, so the tolerance range of the voltage setpoints for states S0 / S2 changes along with the change in the capacitor tap position.

[0109] However, such shifts in the acceptable range of voltage setpoints present the challenge of how to adjust the voltage setpoints for states S0 and S2. For example, if the voltage setpoint for state S1 changes and the capacitor tap position also changes, the acceptable range for the voltage setpoint for state S0 may change, potentially resulting in the existing voltage setpoint for state S0 being out of acceptable range, and consequently the system being unable to realize the existing voltage setpoint for state S0. A similar change may occur in the acceptable range for the voltage setpoint for state S2, again potentially resulting in the existing voltage setpoint for state S2 being out of acceptable range, and consequently the system being unable to realize the existing voltage setpoint for state S2. In addition, even if the existing voltage setpoint for either state S0 or S2 is still within acceptable range, it may be at the edge of the acceptable range, thus limiting the degree of freedom to adjust the voltage setpoint to optimize a given recipe as needed.

[0110] For example, continuing to refer to Figure 6, the existing voltage setpoint for S0 / S2 is V1. When the capacitor tap position is at P5, the voltage setpoint V1 is approximately in the middle of the acceptable voltage setpoint tolerance range of 600. This provides tolerance for adjusting the voltage setpoint up or down if required for recipe optimization.

[0111] However, if the voltage setpoint for state S1 is increased, and as a result the capacitor tap position changes to P4, the tolerance range for the voltage setpoints for states S0 / S2 changes to tolerance range 602, which is roughly an increase from the previous tolerance range of 600. At this stage, the existing voltage setpoint V1 for S0 / S2 is still within tolerance range 602. However, V1 is now near the bottom of the current tolerance range 602, and as a result the degree of freedom to further reduce the voltage setpoint if necessary is very limited. This can be a problem for recipe development because a user might try to adjust the voltage setpoint in this way and find that it is not possible.

[0112] If the voltage setpoint for state S1 is further increased, and as a result the capacitor tap position then changes to P3, the tolerance range for the voltage setpoints for states S0 / S2 changes to tolerance range 604, which is roughly an increase from the previous tolerance range 602. This presents an unsatisfactory scenario in that the existing S0 / S2 voltage setpoint V1 is no longer within the current tolerance range 604 of the voltage setpoint. In other words, if the capacitor tap position is P3, the system cannot realize the existing setpoint V1. In such a scenario, as an unrestricted example, the system may generate an error indicating that the voltage setpoint is outside the tolerance range.

[0113] Therefore, it is desirable to adjust the voltage setpoints for states S0 / S2 as the voltage setpoint for state S1 changes and the capacitor tap position changes. For example, if the capacitor tap position changes to P4, it is desirable to change the S0 / S2 voltage setpoint to V2 so that the S0 / S2 voltage setpoint is maintained approximately in the middle or near the middle of the tolerance range 602. Similarly, if the capacitor tap position changes to P3, it is desirable to change the S0 / S2 voltage setpoint to V3 so that the S0 / S2 voltage setpoint is maintained approximately in the middle or near the middle portion of the tolerance range 604.

[0114] It has been unexpectedly discovered that, across the entire range of capacitor tap settings, a voltage setpoint for states S0 / S2 that is approximately midway through the tolerance range for any given capacitor tap setting results in a nearly constant or identical phase adjustment amount (automatically set by the TES RF signal generator 403 for states S0 / S2) across the entire range of capacitor tap settings. In other words, if the capacitor tap setting is changed in response to a change in the voltage setpoint for state S1, and the resulting phase adjustment amount is approximately the same as the phase adjustment amount that existed before the change in the capacitor tap setting, then the voltage setpoint for states S0 / S2 will be approximately midway through the (new) tolerance range. Therefore, when the capacitor tap setting changes, a target phase adjustment amount can be defined and used to determine the appropriate voltage setpoint for states S0 / S2. In this specification, states S0 and S2 are referred to alternately, and it should be understood that the target phase adjustment amount for state S0 may be the same as or different from the target phase adjustment amount for state S2.

[0115] Figure 7 is a graph conceptually illustrating the relationship between phase adjustment for states S0 / S2 and voltage setpoints for states S0 / S2 in an implementation of the present disclosure. In the illustrated implementation, the curve 700 shows the phase adjustment for a given capacitor tap position as described above, as a function of the voltage setpoint for states S0 / S2. The tolerance range 602 of the voltage setpoint is indicated by the width of the curve 700 along the horizontal axis representing the voltage setpoint.

[0116] Point 706 along curve 700 represents the maximum voltage setpoint Vmax, as defined by the voltage in state S1, as previously mentioned. Position 702 along curve 700 represents the minimum voltage setpoint Vmin, which may be based on the amount of power attenuation possible by the drive actuator of the TES RF signal generator 403. The allowable voltage setpoint range 602 also corresponds to the phase adjustment range 710. As shown in the figure, when the voltage setpoint is adjusted to Vc, which is approximately in the middle or midpoint of the allowable voltage setpoint range 602 and corresponds to point 704 along curve 700, the phase adjustment amount is PA Tis. Although this is an unexpected result, when the voltage setpoint is adjusted to approximately the middle of the allowable range of the voltage setpoint, this phase adjustment amount PA T was found to be substantially the same for all capacitor tap settings.

[0117] Accordingly, PA T defines a target phase adjustment amount that can be used to automatically adjust the voltage setpoint for state S0 / S2 so that the voltage setpoint remains approximately in the middle of the allowable range of the voltage setpoint. In response to a change in the voltage setpoint for state S1 and a concomitant change in the capacitor tap setting, the voltage setpoint for state S0 / S2 is adjusted until the phase adjustment amount for state S0 / S2 reaches the target phase adjustment amount or falls within a predetermined range of the target phase adjustment amount (e.g., within x degrees of PA T ). As stated, states S0 and S2 may have the same or different target phase adjustment amounts, each configured to allow the corresponding voltage setpoint to remain approximately in the middle of the allowable range.

[0118] In some implementations, a target phase adjustment range 708 is defined, and the voltage setpoint for state S0 / S2 is adjusted until the phase adjustment amount for state S0 / S2 falls within the target phase adjustment range. It will be appreciated that the target phase adjustment range is configured such that the corresponding voltage setpoint range (the phase adjustment that results in falling within the target phase adjustment range) is approximately in the middle of the allowable voltage setpoint range. It will be appreciated that states S0 and S2 may have the same or different target phase adjustment ranges.

[0119] Figure 8 conceptually illustrates a method for maintaining a voltage setpoint within a schematic intermediate range of allowable voltage setpoints for a given state of a pulsed RF signal, according to an implementation of this disclosure. In method operation 801, a target phase adjustment range (or amount) is defined for a given state of the pulsed RF signal. The target phase adjustment range is configured such that the amount of phase adjustment obtained when the voltage setpoint for a given state is within the intermediate / center range of allowable voltage setpoints. As previously stated, phase adjustment is automatically performed by the TES RF signal generator to minimize the phase difference / delta when the (main) RF signal is applied to electrode 109 for a given state. Therefore, as the voltage setpoint changes, the phase adjustment also automatically changes to minimize the phase difference. Thus, the range of allowable voltage setpoints corresponds to the range of phase adjustment, and it was unexpectedly found that the target phase adjustment range / amount resulting from a voltage setpoint in the middle of that allowable range is approximately constant or the same for different capacitance settings in the TES impedance matching system 401.

[0120] In step 803 of the method, the phase adjustment amount, which is automatically determined by the TES RF signal generator, is monitored for a given state, for example, state S0 or state S2. In step 805 of the method, it is determined whether the phase adjustment amount is within the target phase adjustment range. If yes, the method returns to step 803 for continuous monitoring of the phase adjustment amount.

[0121] If no, in method operation 807, the voltage setpoint for a given state, e.g., state S0 or state S2, is adjusted. The method then returns to method operations 803 and 805 to continue monitoring the phase adjustment amount and to determine again whether the phase adjustment amount is within the target phase adjustment range. If the phase adjustment amount is within the target phase adjustment range, it will be understood that the voltage setpoint will fall within the approximate midpoint / center range of the allowable voltage setpoints for the current situation.

[0122] Figure 9 is a graph conceptually illustrating the change in the voltage setpoint for various states of a pulsed RF signal according to an implementation of the present disclosure. The voltage setpoints for states S1, S0, and S2 are shown as a function of the accumulated RF time of the edge ring. Curve 901 shows the voltage setpoint for state S1. As can be seen from the figure, as the RF time accumulates, the voltage setpoint for state S1 is periodically increased to compensate for edge ring wear and maintain the plasma sheath height and characteristics in the edge region.

[0123] According to the method of this disclosure, the voltage setpoints for state S2 (indicated by curve 903) and state S0 (indicated by curve 905) are also increased in steps in coordination with the stepwise change of the voltage setpoint for state S1. As discussed, the voltage setpoints for states S0 and S2 are adjusted to maintain a target phase adjustment amount or range for each state.

[0124] In some implementations, the target phase adjustment amount or range can be specified via the user interface. For example, a default target phase adjustment amount or range (e.g., 160-180 degrees in some implementations) may exist, which can be adjusted by the user in predetermined increments (e.g., 1-10 degree in some implementations) and within a predetermined range (e.g., 120-220 degrees in some implementations).

[0125] For a given recipe, there may be a target phase adjustment for each state of the pulsed RF signal for each recipe step. Furthermore, the target phase adjustment may be editable via a user interface, for example, via the recipe editor of the user interface. There may be default values ​​for the target phase adjustment that are provided when a new recipe step is constructed. For example, there may be a model (based on empirical data) that predicts what the target phase adjustment should be for each recipe step. When constructing each recipe step, the user may have the option to use this model, or the user may enter their own values.

[0126] It will be understood that any of the methods described herein can be implemented to operate automatically by the control system 120. In some embodiments, as discussed, the capacitor tap positions can be automatically optimized to minimize reflected power in the TES system.

[0127] Figure 10 shows an exemplary schematic diagram of the control system 120 of Figure 2 according to several embodiments. In some embodiments, the control system 120 is configured as a process controller for controlling a semiconductor manufacturing process carried out in the plasma processing system 100. In various embodiments, the control system 120 includes a processor 1401, a memory hardware unit (HU) 1403 (e.g., memory), an input HU 1405, an output HU 1407, an input / output (I / O) interface 1409, an I / O interface 1411, a network interface controller (NIC) 1413, and a data communication bus 1415. The processor 1401, memory HU 1403, input HU 1405, output HU 1407, I / O interface 1409, I / O interface 1411, and NIC 1413 are in data communication state with each other via the data communication bus 1415. The input HU 1405 is configured to receive data communication from multiple external devices. Examples of input HU 1405 include data acquisition systems and data acquisition cards. Output HU 1407 is configured to transmit data to multiple external devices. An example of output HU 1407 is a device controller. Examples of NIC 1413 include network interface cards and network adapters. I / O interfaces 1409 and 1411 are each defined to provide compatibility between various hardware units coupled to the I / O interface. For example, I / O interface 1409 can be defined to convert signals received from input HU 1405 into a format, amplitude, and / or speed compatible with data communication bus 1415. Similarly, I / O interface 1407 can be defined to convert signals received from data communication bus 1415 into a format, amplitude, and / or speed compatible with output HU 1407.Although various operations in this specification are described as being performed by the processor 1401 of the control system 120, it should be understood that in some embodiments, various operations may be performed by multiple processors of the control system 120 and / or by multiple processors of multiple computing systems that are in data communication with the control system 120.

[0128] In some embodiments, the control system 120 is used to control devices in various wafer fabrication systems, partially based on sensed values. For example, the control system 120 may control one or more of the following based on sensed values ​​and other control parameters: valve 1417, filter heater 1419, wafer support structure heater 1421, pump 1423, and other devices 1425. Valve 1417 may include valves associated with the control of the back surface gas supply system 129, process gas supply system 191, and temperature-controlled fluid circulation system 125. The control system 120 receives sensed values ​​from, for example, a pressure manometer 1427, a flow meter 1429, a temperature sensor 1431, and / or other sensors 1433, such as a voltage sensor, a current sensor, etc. The control system 120 may also be used to control processing conditions within the plasma processing system 100 during the performance of plasma processing operations on the wafer W. For example, the control system 120 can control the type and amount of process gas supplied from the process gas supply system 191 to the plasma processing area 182. The control system 120 can also control the operation of the first high-frequency signal generator 147, the second high-frequency signal generator 149, the impedance matching system 143, the TES high-frequency signal generator 403, and the TES impedance matching system 401. Furthermore, the control system 120 can control the operation of the DC supply unit 117 for the clamp electrode 112. The control system 120 can also control the operation of the lifting device 133 for the lift pin 132 and the door 107. The control system 120 also controls the operation of the back gas supply system 129 and the temperature-controlled fluid circulation system 125. The control system 120 also controls the vertical movement of the cantilever arm assembly 115. The control system 120 also controls the operation of the throttle member 196 and the pump that controls suction in the exhaust port 105. The control system 120 also controls the operation of the hold-down control mechanism 913 of the hold-down rod 911 of the TES system 1000. The control system 120 also receives input from the temperature probe of the TES system 1000.It should be understood that the control system 120 is equipped to programmatically control and / or manually control any function within the plasma processing system 100.

[0129] In some embodiments, the control system 120 is configured to run a computer program that includes a set of instructions for controlling process timing, process gas delivery system temperature and pressure difference, valve position, process gas mixing, process gas flow rate, back cooling gas flow rate, chamber pressure, chamber temperature, wafer support structure temperature (wafer temperature), RF power level, RF frequency, RF pulsation, impedance matching system 143 settings, cantilever arm assembly position, bias power, and other parameters of a particular process. In some embodiments, other computer programs stored in a memory device associated with the control system 120 may be used. In some embodiments, there is a user interface associated with the control system 120. The user interface includes a display 1435 (e.g., a display screen and / or graphical software display of the apparatus and / or process conditions) and a user input device 1437 such as a pointing device, keyboard, touchscreen, or microphone.

[0130] The software for instructing the operation of the control system 120 may be designed or configured in many different forms. A computer program for instructing the operation of the control system 120 to execute various wafer manufacturing processes in a process sequence can be written in any conventional computer-readable programming language, such as assembly language, C, C++, Pascal, or Fortran. The compiled object code or script is executed by the processor 1401 to perform the tasks identified in the program. The control system 120 can be programmed to control various process control parameters related to process conditions, such as, for example, the filter pressure difference, process gas composition and flow rate, back-side cooling gas composition and flow rate, plasma conditions such as temperature, pressure, RF power level and RF frequency, bias voltage, cooling gas / fluid pressure, and chamber wall temperature. Examples of sensors that may be monitored during the wafer manufacturing process include, but are not limited to, a mass flow control module, pressure sensors such as the pressure manometer 1427, and a temperature sensor 1431. Appropriately programmed feedback and control algorithms may be used in conjunction with data from these sensors to control / adjust one or more process control parameters to maintain desired process conditions.

[0131] In some implementations, the control system 120 is part of a broader manufacturing control system. Such a manufacturing control system may include semiconductor processing equipment, including processing tools, chambers, and / or wafer processing platforms, and / or specific processing components, such as wafer pedestals, gas flow systems, etc. These manufacturing control systems may be incorporated into electronics for controlling pre-processing, in-processing, and post-processing operations of wafers. The control system 120 may control various components or sub-components of the manufacturing control system. Depending on the wafer processing requirements, the control system 120 may be programmed to control any of the processes disclosed herein, including the supply of processing gases, the supply of back-side cooling gases, temperature settings (e.g., heating and / or cooling), pressure settings, vacuum settings, power settings, high-frequency (RF) generator settings, RF matching circuit settings, frequency settings, flow rate settings, fluid supply settings, position and work settings, loading and unloading of wafers to and from tools and other transfer tools connected to or interfaced with specific systems, and / or load locks.

[0132] Broadly speaking, the control system 120 may be defined as an electronic device having various integrated circuits, logic, memory, and / or software that receives instructions, issues instructions, controls operations, enables wafer processing operations, enables endpoint measurements, and so on. The integrated circuits may include chips in the form of firmware that store program instructions, chips defined as digital signal processors (DSPs), application-specific integrated circuits (ASICs), and / or one or more microprocessors or microcontrollers that execute program instructions (e.g., software). The program instructions are instructions communicated to the control system 120 in the form of various individual settings (or program files) that may define work parameters for performing a particular process on a wafer in the system 100. In some embodiments, the work parameters may be part of a recipe defined by a process engineer to implement one or more processing steps when fabricating one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or wafer dies.

[0133] In some implementations, the control system 120 may be part of or coupled to a computer that is integrated into or coupled to the plasma processing system 100, or is networked to the system 100 in other ways, or a combination thereof. For example, the control system 120 may reside in a “cloud” of all or part of the fab host computer system, thereby enabling remote access to wafer processing. The computer may enable remote access to the system 100 to monitor the current progress of manufacturing operations, investigate the history of past manufacturing operations, investigate trends or performance indicators from multiple manufacturing operations, modify the parameters of the current process, and set up processing steps to continue the current process or start a new process. In some embodiments, a remote computer (e.g., a server) may provide a process recipe to the system 100 via a network that may include a local network or the Internet.

[0134] The remote computer may include a user interface that enables the input or programming of parameters and / or settings, which are then communicated from the remote computer to system 100. In some embodiments, the control system 120 receives instructions in data format that specify parameters for each processing step performed during one or more operations. It should be understood that the parameters may be specific to the type of process performed within the plasma processing system 100. Thus, as described above, the control system 120 may be distributed by comprising, for example, one or more separate controllers networked together and aimed at common purposes such as the processes and controls described herein. An example of a distributed controller for such purposes may be one or more integrated circuits on the plasma processing system 100 that are in communication with one or more integrated circuits located remotely (e.g., at the platform level or as part of a remote computer), and these combined control the processes performed in the plasma processing system 100.

[0135] Exemplary systems that the control system 120 may interface with include, but are not limited to, plasma etching chambers or modules, deposition chambers or modules, spin rinse chambers or modules, metal plating chambers or modules, cleaning chambers or modules, bevel edge etching chambers or modules, physical vapor deposition (PVD) chambers or modules, chemical vapor deposition (CVD) chambers or modules, atomic layer deposition (ALD) chambers or modules, atomic layer etching (ALE) chambers or modules, ion implantation chambers or modules, track chambers or modules, and any other semiconductor processing systems associated with or that may be used in the fabrication and / or manufacture of semiconductor wafers. As described above, depending on the process steps performed by the tool, the control system 120 may communicate with one or more of the following: other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, neighboring tools, tools located throughout the plant, a main computer, another controller, or tools used for material handling to load and unload wafer containers between tool locations and / or load ports within the semiconductor manufacturing plant.

[0136] Embodiments described herein may also be implemented in conjunction with a variety of computer system configurations, including handheld hardware units, microprocessor systems, microprocessor-based or programmable consumer electronics, minicomputers, and mainframe computers. Embodiments described herein may also be implemented in conjunction with a distributed computing environment in which tasks are performed by remote processing hardware units linked over a network. Embodiments described herein, in particular those associated with control system 120, should be understood to be able to utilize a variety of tasks that can be performed by a computer, involving data stored in a computer system. These tasks are tasks that require the physical manipulation of physical quantities. Any tasks described herein that form part of an embodiment are useful mechanical tasks. Embodiments also relate to hardware units or devices for performing these tasks. Devices may be specifically built for a dedicated computer. When defined as a dedicated computer, the computer may also perform other processing, program execution, or routines that are not part of its dedicated purpose, even though it is capable of operating for a dedicated purpose. In some embodiments, tasks may be processed by a general-purpose computer selectively activated or configured by one or more computer programs stored in computer memory, cache, or retrieved over a network. If data is acquired via a network, the data may be processed by other computers on the network, such as a cloud of computing resources.

[0137] Various embodiments described herein can be realized via process control instructions instantiated as computer-readable code on a non-temporary computer-readable medium. A non-temporary computer-readable medium is any data storage hardware unit capable of storing data that can later be read by a computer system. Examples of non-temporary computer-readable mediums include hard drives, network-attached storage (NAS), ROM, RAM, compact disk-ROM (CD-ROM), CD-recordable (CD-R), CD-rewritable (CD-RW), magnetic tape, and other optical and non-optical data storage hardware units. A non-temporary computer-readable medium may include computer-readable tangible media distributed across network-connected computer systems so that computer-readable code is stored and executed in a distributed manner.

[0138] While the foregoing disclosure includes some details for clarity, it will be clear that certain changes and modifications can be made within the scope of the attached claims. For example, it should be understood that one or more features from any embodiment disclosed herein may be combined with one or more features from any embodiment disclosed herein. Therefore, these embodiments should be considered illustrative rather than restrictive, and the claims should not be limited to the details described herein, but may be modified within the scope of the embodiments and equivalents described herein. This disclosure includes the following examples of applications. [Application Example 1] A method for adjusting the voltage setpoint for a multi-state pulsed RF signal in a plasma processing system, wherein the method is: The method involves applying RF power from a first generator to an ESC, wherein the RF power from the first generator defines a first multi-state pulse RF signal. RF power is applied from a second generator to an edge electrode located below the edge ring surrounding the ESC, wherein the RF power from the second generator defines a second multi-state pulsed RF signal having a first state and a second state, and for each state of the second multi-state pulsed RF signal, the second generator automatically introduces a phase adjustment to substantially match the phase to the corresponding state of the first multi-state pulsed RF signal. A method comprising adjusting the voltage setpoint for the second state of the second multi-state pulse RF signal to adjust the phase adjustment to a target phase adjustment setting. [Application Example 2] A method according to Application Example 1, wherein the target phase adjustment setting is captured via a user interface. [Application Example 3] A method according to Application Example 1, wherein the target phase adjustment setting is calculated based on a model. [Application Example 4] A method according to Application Example 1, wherein the target phase adjustment setting defines a predetermined phase adjustment amount used when the phase of the RF power from the second generator is adjusted. [Application Example 5] A method according to Application Example 1, wherein adjusting the voltage setpoint to adjust the phase adjustment includes performing stepwise adjustments to the voltage setpoint until the phase adjustment reaches the target phase adjustment setting. [Application Example 6] A method according to Application Example 5, wherein the stepwise adjustment is based on a specific voltage setpoint associated with the first state of the second multi-state pulse RF signal. [Application Example 7] A method according to Application Example 1, wherein when the phase adjustment reaches the target phase adjustment setting, or when the phase adjustment is within a predetermined range from the target phase adjustment setting, the phase adjustment is adjusted to the target phase adjustment setting. [Application Example 8] A method according to Application Example 1, wherein the voltage setpoint is adjusted to adjust the phase adjustment to the target phase adjustment setting, so that the voltage setpoint is located in the middle of the allowable range of the voltage setpoint. [Application Example 9] A method according to Application Example 6, wherein the target phase adjustment setting, which facilitates the positioning of the voltage setpoint in the intermediate portion of the allowable range of the voltage setpoint, remains substantially the same with respect to changes in the capacitance of the matching circuit through which the RF power from the second generator passes when applied to the edge electrode. [Application Example 10] A method according to Application Example 9, wherein the change in the capacitance of the matching circuit responds to a change in the voltage setpoint of the first state of the second multi-state pulse RF signal. [Application Example 11] A method according to Application Example 10, wherein the change in the voltage setpoint in the first state occurs based on the amount of use of the edge ring. [Application Example 12] A method according to Application Example 11, wherein the amount of use of the edge ring is defined as the amount of time the edge ring is exposed to RF. [Application Example 13] A method for adjusting the voltage setpoint for a multi-state pulsed RF signal in a plasma processing system, wherein the method is: The method involves applying RF power from a first generator to an ESC, wherein the RF power from the first generator defines a first pulse RF signal having a first state and a second state. RF power is applied from a second generator to an edge electrode located below the edge ring surrounding the ESC, wherein the RF power from the second generator defines a second pulsed RF signal having a first state and a second state, the second generator automatically introduces a first phase adjustment to substantially match the phase of the first state of the second pulsed RF signal to the first state of the first pulsed RF signal, the second generator automatically introduces a second phase adjustment to substantially match the phase of the second state of the second pulsed RF signal to the second state of the first pulsed RF signal, and the second phase adjustment is adjusted to a target phase adjustment setting. A method comprising: adjusting the voltage setpoint for the second state of the second pulse RF signal to return the second phase adjustment to the target phase adjustment setting in response to the detection of a change in the second phase adjustment that causes the second phase adjustment to move away from the target phase adjustment setting. [Application Example 14] A method according to Application Example 13, wherein the target phase adjustment setting is captured via a user interface. [Application Example 15] A method according to Application Example 13, wherein the target phase adjustment setting is calculated based on a model. [Application Example 16] A method according to Application Example 13, wherein the target phase adjustment setting defines a predetermined phase adjustment amount used when the phase of the second state of the second pulse RF signal is adjusted. [Application Example 17] A method according to Application Example 13, wherein adjusting the voltage setpoint to return the second phase adjustment includes performing stepwise adjustments to the voltage setpoint until the second phase adjustment reaches the target phase adjustment setting. [Application Example 18] A method according to Application Example 17, wherein the stepwise adjustment is based on a specific voltage setpoint associated with the first state. [Application Example 19] A method according to Application Example 13, wherein when the second phase adjustment reaches the target phase adjustment setting, or when the second phase adjustment is within a predetermined range of the target phase adjustment setting, the second phase adjustment is returned to the target phase adjustment setting. [Application Example 20] A method according to Application Example 13, wherein the voltage setpoint is adjusted to return the second phase adjustment to the target phase adjustment setting, so that the voltage setpoint is located in the middle of the allowable range of the voltage setpoint. [Application Example 21] A method according to Application Example 20, wherein the target phase adjustment setting, which facilitates the positioning of the voltage setpoint in the intermediate portion of the allowable range of the voltage setpoint, remains substantially the same with respect to changes in the capacitance of the matching circuit through which the RF power from the second generator passes when applied to the edge electrode. [Application Example 22] A method according to Application Example 21, wherein the change in the capacitance of the matching circuit responds to a change in the voltage setpoint of the first state of the second pulse RF signal. [Application Example 23] A method according to Application Example 22, wherein the change in the voltage setpoint of the first state of the second pulse RF signal occurs based on the amount of edge ring used. [Application Example 24] A method according to Application Example 23, wherein the amount of use of the edge ring is defined as the amount of time the edge ring is exposed to RF.

Claims

1. A plasma processing system configured to adjust the voltage setpoint for a multi-state pulse RF signal, A chamber having an electrostatic chuck (ESC) located inside, An edge electrode is positioned below the edge ring surrounding the ESC, A first generator that applies RF power to the ESC, wherein the RF power from the first generator defines a first multi-state pulse RF signal, A second generator for applying RF power to the edge electrode, wherein the RF power from the second generator defines a second multi-state pulse RF signal having a first state and a second state, and for each state of the second multi-state pulse RF signal, the second generator automatically introduces a phase adjustment to substantially match the phase to the corresponding state of the first multi-state pulse RF signal, A plasma processing system in which the voltage setpoint for the second state of the second multi-state pulse RF signal is adjusted to adjust the phase adjustment to a target phase adjustment setting.

2. A plasma processing system according to Claim 1, wherein the target phase adjustment setting is captured via a user interface.

3. A plasma processing system according to Claim 1, wherein the target phase adjustment setting is calculated based on a model.

4. A plasma processing system according to Claim 1, wherein the target phase adjustment setting defines a predetermined phase adjustment amount used when the phase of the RF power from the second generator is adjusted.

5. A plasma processing system according to Claim 1, wherein adjusting the voltage setpoint to adjust the phase adjustment includes performing stepwise adjustments to the voltage setpoint until the phase adjustment reaches the target phase adjustment setting.

6. A plasma processing system according to claim 5, wherein the stepwise adjustment is based on a specific voltage setpoint associated with the first state of the second multi-state pulse RF signal.

7. A plasma processing system according to Claim 1, wherein when the phase adjustment reaches the target phase adjustment setting, or when the phase adjustment is within a predetermined range from the target phase adjustment setting, the phase adjustment is adjusted to the target phase adjustment setting.

8. A plasma processing system according to Claim 1, wherein by adjusting the voltage setting point and adjusting the phase adjustment to the target phase adjustment setting, the voltage setting point is located in the middle portion of the allowable range of the voltage setting point.

9. A plasma processing system according to claim 8, wherein the target phase adjustment setting, which facilitates the positioning of the voltage setting point in the intermediate portion of the allowable range of the voltage setting point, remains substantially the same with respect to changes in the capacitance of the matching circuit through which the RF power from the second generator passes when applied to the edge electrode.

10. A plasma processing system according to claim 9, wherein the change in the capacitance of the matching circuit responds to a change in the voltage setpoint of the first state of the second multi-state pulse RF signal.

11. A plasma processing system according to claim 10, wherein the change in the voltage setting point in the first state is generated based on the amount of use of the edge ring.

12. A plasma processing system according to claim 11, wherein the amount of the edge ring used is defined as the amount of time the edge ring is exposed to RF.

13. A plasma processing system configured to adjust the voltage setpoint for a multi-state pulse RF signal, A chamber having an electrostatic chuck (ESC) located inside, An edge electrode is positioned below the edge ring surrounding the ESC, A first generator that applies RF power to the ESC, wherein the RF power from the first generator defines a first pulse RF signal having a first state and a second state, A second generator for applying RF power to the edge electrode, wherein the RF power from the second generator defines a second pulse RF signal having a first state and a second state, the second generator automatically introduces a first phase adjustment to substantially match the phase of the first state of the second pulse RF signal to the first state of the first pulse RF signal, the second generator automatically introduces a second phase adjustment to substantially match the phase of the second state of the second pulse RF signal to the second state of the first pulse RF signal, and the second phase adjustment is adjusted to a target phase adjustment setting. A plasma processing system in which, in response to the detection of a change in the second phase adjustment that deviates from the target phase adjustment setting, the voltage setpoint for the second state of the second pulse RF signal is adjusted to return the second phase adjustment to the target phase adjustment setting.

14. A plasma processing system according to claim 13, wherein the target phase adjustment setting is captured via a user interface.

15. A plasma processing system according to claim 13, wherein the target phase adjustment setting is calculated based on a model.

16. A plasma processing system according to claim 13, wherein the target phase adjustment setting defines a predetermined phase adjustment amount used when the phase of the second state of the second pulse RF signal is adjusted.

17. A plasma processing system according to claim 13, wherein adjusting the voltage setpoint to return the second phase adjustment includes performing stepwise adjustments to the voltage setpoint until the second phase adjustment reaches the target phase adjustment setting.

18. A plasma processing system according to claim 17, wherein the stepwise adjustment is based on a specific voltage setpoint associated with the first state.

19. A plasma processing system according to claim 13, wherein when the second phase adjustment reaches the target phase adjustment setting, or when the second phase adjustment is within a predetermined range of the target phase adjustment setting, the second phase adjustment is returned to the target phase adjustment setting.

20. A plasma processing system according to claim 13, wherein by adjusting the voltage setting point to return the second phase adjustment to the target phase adjustment setting, the voltage setting point is located in the middle portion of the allowable range of the voltage setting point.

Images